TLV62595 [TI]

采用 1.5mm x 1.5mm QFN 封装、具有 1% 输出精度的 2.5V 至 5.5V 输入、4A 降压转换器;


型号：	TLV62595
厂家：	TEXAS INSTRUMENTS
描述：	采用 1.5mm x 1.5mm QFN 封装、具有 1% 输出精度的 2.5V 至 5.5V 输入、4A 降压转换器转换器
文件：	总27页 (文件大小：1815K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLV62595

ZHCSKS8A –DECEMBER 2020 –REVISED JANUARY 2023

采用1.5mm × 1.5mm QFN 封装、具有1% 输出精度的TLV62595 2.5V 至5.5V 输

入、4A 降压转换器

1 特性

3 说明

• 效率高达97%

TLV62595 是一款高频同步降压转换器，经优化具有解

决方案尺寸紧凑和高效率两大优点。该器件集成了可提

供高达 4A 输出电流的开关。在中等负载至重负载情况

下，该转换器将以 2.2MHz 典型开关频率在脉宽调制

(PWM) 模式下运行。在轻负载情况下，该器件自动进

入节能模式 (PSM)，从而在整个负载电流范围内保持

高效率，且静态电流低至10µA。

• 低R_DS(ON)电源开关：26mΩ/25mΩ

• 输入电压范围为2.5V 至5.5V

• 可调输出电压范围为0.6V 至4V

• 反馈电压精度为1%（整个温度范围）

• DCS-Control 拓扑

• 可实现轻负载效率的省电模式

• 100% 占空比，可实现超低压降

• 工作静态电流为10μA

• 典型开关频率为2.2MHz

• 短路保护(HICCUP)

• 有源输出放电

• 电源正常状态输出

• 热关断保护

该器件基于 DCS 控制拓扑，可实现快速瞬态响应。内

部基准在 -40°C 至 125°C 的结温范围内，以 1% 的高

反馈电压精度将输出电压调低至 0.6V。整个解决方案

需要一个小型 470nH 电感器、一个 4.7μF 输入电容

器以及三个10μF 或一个47μF 输出电容器。

该器件采用 6 引脚 1.5mm × 1.5mm QFN 封装，可提

供高功率密度解决方案。

• 使用TLV62595 并借助WEBENCH^®Power

Designer 创建定制设计方案

封装信息

封装⁽¹⁾

封装尺寸（标称值）

2 应用

器件型号

DMQ（VSON-HR，

6）

• 固态硬盘

TLV62595

1.50mm x 1.50mm

• 便携式电子产品

• IP 网络摄像头

• 工业PC

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 多功能打印机

V_IN

2.5 V to 5.5 V

TLV62595

VIN SW

0.47 µH

V_OUT

1.8 V

100

4.7 µF

3x10 µF

120 pF

100 kꢀ

200 kꢀ

V_PG

PG GND FB

100 kꢀ

V_OUT= 0.6V

V_OUT= 1.2V

V_OUT= 1.8V

V_OUT= 2.5V

V_OUT= 3.3V

典型应用原理图

100m

10m

Load (A)

100m

D007

V_IN= 5V 时的效率

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSDR2

TLV62595

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ZHCSKS8A –DECEMBER 2020 –REVISED JANUARY 2023

Table of Contents

7.4 Device Functional Modes............................................9

8 Application and Implementation..................................10

8.1 Application Information............................................. 10

8.2 Typical Application.................................................... 10

8.3 Power Supply Recommendations.............................17

8.4 Layout....................................................................... 17

9 Device and Documentation Support............................19

9.1 Device Support......................................................... 19

9.2 Documentation Support............................................ 19

9.3 接收文档更新通知..................................................... 19

9.4 支持资源....................................................................19

9.5 Trademarks...............................................................19

9.6 静电放电警告............................................................ 19

9.7 术语表....................................................................... 20

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................4

6.5 电气特性......................................................................5

6.6 Typical Characteristics................................................6

7 Detailed Description........................................................7

7.1 Overview.....................................................................7

7.2 Functional Block Diagram...........................................7

7.3 Feature Description.....................................................8

Information.................................................................... 20

4 Revision History

Changes from Revision * (December 2020) to Revision A (January 2023)

Page

• Updated ESD Ratings.........................................................................................................................................6

• Removed duplicate table in Output Filter Design section................................................................................. 11

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5 Pin Configuration and Functions

GND

VIN

图5-1. 6-Pin VSON-HR DMQ Package (Bottom View)

表5-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

Device enable pin. To enable the device, this pin must be pulled high. Pulling this pin low

disables the device. Do not leave floating.

Power-good open-drain output pin. The pullup resistor can be connected to voltages up to

5.5 V. If unused, leave this pin floating.

Feedback pin. For the fixed output voltage versions, this pin must be connected to the

output.

GND

Ground pin

PWR

Switch pin of the power stage

Input voltage pin

VIN

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6 Specifications

6.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–1

MAX

UNIT

Pin voltage⁽²⁾

Temperature

VIN, FB, EN, PG

SW (DC)

V_IN+ 0.3

SW (DC, in current limit)

SW (AC, less than 10ns)⁽³⁾

Operating Junction, T_J

Storage, T_STG

–2.5

–40

150

°C

150

–65

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values are with respect to the network ground terminal

(3) While switching

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC

JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per ABSI/ESDA/JEDEC

JS-002⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating temperature range (unless otherwise noted)

MIN

2.5

0.6

NOM

MAX

5.5

4.0

UNIT

V_IN

Input voltage range

V_OUT

I_OUT

V_PG

Output voltage range

Output curent range

Pull-up resistor voltage

Sink current at PG pin

Operating junction temperature

5.5

I_{SINK_PG}

T_J

°C

125

–40

6.4 Thermal Information

TLV62595

DMQ (JEDEC)

6 PINS

129.5

TLV62595EVM-794

THERMAL METRIC⁽¹⁾

DMQ (EVM)

6 PINS

71.4

UNIT

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

103.9

n/a

33.1

n/a

Junction-to-top characterization parameter

Junction-to-board characterization parameter

3.8

3.9

Y_JB

33.1

38.6

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 电气特性

T_J= 25°C 且V_IN= 5V，除非另有说明。

最小

值

参数

测试条件

典型值最大值

单位

电源

I_Q

µA

EN = 高电平，无负载，器件未开关

静态电流

I_SD

0.05

EN = 低电平，T_J= -40℃至85℃

关断电流

2.1

2.2

160

150

2.3

V_IN下降

V_IN上升

T_J上升

T_J下降

欠压锁定阈值

V_UVLO

°C

欠压锁定迟滞

热关断阈值

T_JSD

热关断迟滞

逻辑接口EN

V_IH

1.0

V_IN= 2.5 V 至5.5 V

高电平阈值电压

V_IL

0.4

低电平阈值电压

软启动，电源正常

t_SS

1.75

从EN 高电平到V_OUT标称值的95% 的时间

V_PG上升，V_FB以V_FB标称值为基准

V_PG下降，V_FB以V_FB标称值为基准

V_PG上升，V_FB以V_FB标称值为基准

V_PG下降，V_FB以V_FB标称值为基准

I_sink= 1 mA

软启动时间

电源正常下限阈值

V_PG

105

110

电源正常上限阈值

V_PG,OL

I_PG,LKG

0.4

低电平输出电压

V_PG= 5.0 V

0.01

100

µA

流入PG 引脚的输入漏电流

PG 上升沿

PG 下降沿

t_PG,DLY

µs

电源正常抗尖峰脉冲延迟

输出

PWM 模式，2.5V ≤V_IN≤5.5V，T_J= -40°C 至

125°C

V_FB

594

600

606

反馈调节电压

I_FB,LKG

I_DIS

V_FB= 0.6V

0.01

400

0.1

µA

%/A

可调输出电压的反馈输入漏电流

输出放电电流

V_SW= 0.4V；EN = 低电平

I_OUT= 0.5A 至3A，V_OUT= 1.8V

负载调整率

电源开关

高侧FET 导通电阻

低侧FET 导通电阻

高侧FET 开关电流限制，DC

PWM 开关频率

mΩ

R_DS(on)

I_LIM

f_SW

4.8

5.6

2.2

I_OUT= 1A，V_OUT= 1.8V

MHz

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6.6 Typical Characteristics

70.0

60.0

50.0

40.0

30.0

70.0

60.0

50.0

40.0

30.0

20.0

10.0

0.0

20.0

T_J= 0 °C

T_J= 25 °C

T_J= 0 °C

T_J= 25 °C

T_J= 85 °C

T_J= 125 °C

10.0

T_J= 85 °C

T_J= 125 °C

0.0

2.5

3.0

3.5

4.0

Input Voltage (V)

4.5

5.0

5.5

2.5

3.0

3.5

4.0

Input Voltage (V)

4.5

5.0

5.5

D010

D011

图6-1. High-Side FET On-Resistance

图6-2. Low-Side FET On-Resistance

0.5

0.4

0.3

0.2

0.1

0.0

8.0

6.0

4.0

2.0

0.0

T_J= -40 °C

T_J= 25 °C

T_J= 85 °C

T_J= 125 °C

T_J= -40 °C

T_J= 25 °C

T_J= 85 °C

T_J= 125 °C

2.5

3.0

3.5

4.0

Input Voltage (V)

4.5

5.0

5.5

2.5

3.0

3.5

4.0

Input Voltage (V)

4.5

5.0

5.5

D000

D001

图6-3. Shutdown Current

图6-4. Quiescent Current

500

450

400

350

300

250

200

150

100

T_J= 0 °C

T_J= 25 °C

T_J= 85 °C

T_J= 125 °C

2.5

3.0

3.5

4.0

Input Voltage (V)

4.5

5.0

5.5

D012

图6-5. Output Discharge Current

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7 Detailed Description

7.1 Overview

The TLV62595 are synchronous step-down converters based on the DCS-Control topology with an adaptive

constant on-time control and a stabilized switching frequency. The devices operate in PWM (pulse width

modulation) mode for medium to heavy loads and in PSM (power save mode) at light load conditions, keeping

the output voltage ripple small. The nominal switching frequency is about 2.2 MHz with a small and controlled

variation over the input voltage range. As the load current decreases, the converter enters PSM, reducing the

switching frequency to keep efficiency high over the entire load current range. Since combining both PWM and

PSM within a single building block, the transition between modes is seamless and without effect on the output

voltage. The devices offer both excellent dc voltage and fast load transient regulation, combined with a very low

output voltage ripple.

7.2 Functional Block Diagram

Control Logic

V_FB

V_REF

Thermal

Shutdown

Soft-Start

UVLO

V_FB

V_IN

V_SW

VIN

Ramp

Peak Current Detect

V_REF

HICCUP

Comp

V_SW

Modulator

Gate Drive

Ton

Output

Discharge

V_IN

V_SW

Zero Current Detect

0.6 V

Fixed Output Voltages

V_REF

GND

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7.3 Feature Description

7.3.1 Pulse Width Modulation (PWM) Operation

At load currents larger than half the inductor ripple current, the device operates in pulse width modulation in

continuous conduction mode (CCM). The PWM operation is based on an adaptive constant on-time control with

stabilized switching frequency. To achieve a stable switching frequency in a steady state condition, the on-time is

calculated as:

V_OUT

T_ON

× 450ns

(1)

7.3.2 Power Save Mode (PSM) Operation

To maintain high efficiency at light loads, the device enters power save mode (PSM) at the boundary to

discontinuous conduction mode (DCM). This happens when the output current becomes smaller than half of the

ripple current of the inductor. The device operates now with a fixed on-time and the switching frequency further

decreases proportionally to the load current. It can be calculated as:

2×I_OUT

f_PSM

V -V

T_O²_N

OUT

V_OUT

(2)

In PSM, the output voltage rises slightly above the nominal target, which can be minimized using larger output

capacitance. At duty cycles larger than 90%, the device may not enter PSM. The device maintains output

regulation in PWM mode.

7.3.3 Minimum Duty Cycle and 100% Mode Operation

There is no limitation for small duty cycles, because even at very low duty cycles, the switching frequency is

reduced as needed to always ensure a proper regulation.

If the output voltage level comes close to the input voltage, the device enters 100% mode. While the high-side

switch is constantly turned on, the low-side switch is switched off. The difference between VIN and VOUT is

determined by the voltage drop across the high-side FET and the dc resistance of the inductor. The minimum

VIN that is needed to maintain a specific VOUT value is estimated as:

= V_OUT+ I_OUT,MAX´(R_DS(on)+ R_L)

IN,MIN

(3)

where

• V_IN,MIN= Minimum input voltage to maintain an output voltage

• I_OUT,MAX= Maximum output current

• R_DS(on)= High-side FET ON-resistance

• R_L= Inductor ohmic resistance (DCR)

7.3.4 Soft Start

About 250 μs after EN goes high, the internal soft-start circuitry controls the output voltage during start-up. This

avoids excessive inrush current and ensures a controlled output voltage ramp. It also prevents unwanted voltage

drops from high-impedance power sources or batteries. The TLV62595 can start into a pre-biased output.

7.3.5 Switch Current Limit and HICCUP Short-Circuit Protection

The switch current limit prevents the device from drawing excessive current in case of externally-caused

overcurrent or short circuit condition. Due to an internal propagation delay (typically 60 ns), the actual ac peak

current can exceed the static current limit during that time.

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If the current limit threshold is reached, the device delivers its maximum output current. Detecting this condition

for 32 switching cycles (about 13 μs), the device turns off the high-side MOSFET for about 100 μs which

allows the inductor current to decrease through the low-side MOSFET body diode and then restart again with a

soft start cycle. As long as the overload condition is present, the device hiccups that way, limiting the output

power.

7.3.6 Undervoltage Lockout

The undervoltage lockout (UVLO) function prevents misoperation of the device, if the input voltage drops below

the UVLO threshold. It is set to about 2.2 V with a hysteresis of typically 160 mV.

7.3.7 Thermal Shutdown

The junction temperature (T_J) of the device is monitored by an internal temperature sensor. If T_Jexceeds 150°C

(typical), the device goes in thermal shutdown with a hysteresis of typically 20°C. After the TJ has decreased

enough, the device resumes normal operation.

7.4 Device Functional Modes

7.4.1 Enable, Disable and Output Discharge

The device starts operation, when Enable (EN) is set High. The input threshold levels are typically 0.9 V for

rising and 0.7 V for falling signals. Do not leave EN floating. Shutdown is forced if EN is pulled low with a

shutdown current of typically 50 nA. During shutdown, the internal power MOSFETs as well as the entire control

circuitry, are turned off and the output voltage is actively discharged through the SW pin by a current sink.

Therefore VIN must remain present for the discharge to function.

7.4.2 Power Good

The TLV62595 has a built-in power good (PG) function. The PG pin goes high impedance, when the output

voltage has reached its nominal value. Otherwise, including when disabled, in UVLO or in thermal shutdown, PG

is low (see 表 7-1). The PG function is formed with a window comparator, which has an upper and lower voltage

threshold. The PG pin is an open-drain output and is specified to sink up to 1 mA. The power good output

requires a pullup resistor connecting to any voltage rail less than 5.5 V.

The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters.

Leave the PG pin unconnected when not used. The PG rising edge has a 100-µs blanking time and the PG

falling edge has a deglitch delay of 20 µs.

表7-1. PG Pin Logic

LOGIC STATUS

DEVICE CONDITIONS

HIGH Z

LOW

EN = High, V_FB≥0.576 V

EN = High, V_FB≤0.552 V

EN = High, V_FB≤0.63 V

EN = High, V_FB≥0.66 V

EN = Low

√

Enable

√

Shutdown

Thermal Shutdown

UVLO

T_J> T_JSD

0.7 V < V_IN< V_UVLO

V_IN< 0.7 V

Power Supply Removal

√

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The following section discusses the design of the external components to complete the power supply design for

several input and output voltage options by using typical applications as a reference.

8.2 Typical Application

V_IN

2.5 V to 5.5 V

TLV62595

VIN SW

0.47 µH

V_OUT

1.8 V

4.7 µF

3x10 µF

120 pF

100 kꢀ

200 kꢀ

V_PG

PG GND FB

100 kꢀ

图8-1. Typical Application of TLV62595

8.2.1 Design Requirements

For this design example, use the parameters listed in 表8-1 as the input parameters.

表8-1. Design Parameters

DESIGN PARAMETER

Input voltage, TLV62595

Output voltage

EXAMPLE VALUE

2.5 V to 5.5 V

1.8 V

< 20 mV

4 A

Output ripple voltage

Maximum output current, TLV62595

表8-2 lists the components used for the example.

表8-2. List of Components

REFERENCE

DESCRIPTION

MANUFACTURER

4.7 µF, Ceramic capacitor, 6.3 V, X7R, size 0603, JMK107BB7475MA

Taiyo Yuden

Murata

Std

3 × 10 µF, Ceramic capacitor, 10 V, X7R, size 0603, GRM188Z71A106MA73D

120 pF, Ceramic capacitor, 50 V, size 0402

0.47 µH, Power Inductor, XFL4015-471MEB

Coilcraft

Std

Depending on the output voltage, 1%, size 0402

100 kΩ, Chip resistor, 1/16 W, 1%, size 0402

Std

100 kΩ, Chip resistor, 1/16 W, 1%, size 0402

1. See the Third-Party Products Disclaimer.

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8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TLV62595 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Setting The Output Voltage

The output voltage is set by an external resistor divider according to 方程式4:

≈

∆

’

V_OUT

V_FB

OUT

≈

’

R1= R2ì

-1 = R2ì

-1

∆

0.6V

◊

(4)

R2 must not be higher than 100 kΩ to achieve high efficiency at light load while providing acceptable noise

sensitivity. 方程式 5 shows how to compute the value of the feedforward capacitor for a given R2 value. For the

recommended 100 k value for R2, a 120-pF feedforward capacitor is used.

12µ

C3 =

(5)

For the fixed output voltage versions, connect the FB pin to the output. R1, R2, and C3 are not needed. The

fixed output voltage devices have an internal feedforward capacitor.

8.2.2.3 Output Filter Design

The inductor and the output capacitor together provide a low-pass filter. To simplify this process, 表 8-3 outlines

possible inductor and capacitor value combinations for most applications. Checked cells represent combinations

that are proven for stability by simulation and lab test. Further combinations must be checked for each individual

application.

表8-3. Matrix of Output Capacitor and Inductor Combinations, TLV62595

NOMINAL C_OUT[µF]⁽³⁾

NOMINAL L [µH]⁽²⁾

3 x 10

100

0.33

0.47

1.0

(1)

(1) This LC combination is the standard value and recommended for most applications.

(2) Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%.

(3) Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by 20% and –35%.

8.2.2.4 Inductor Selection

The main parameter for the inductor selection is the inductor value and then the saturation current of the

inductor. To calculate the maximum inductor current under static load conditions, 方程式6 is given.

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DI_L

I_L,MAX= I_OUT,MAX

V_OUT

DI_L= V_OUT

L ´ f_SW

(6)

where

• I_OUT,MAX= Maximum output current

• ΔI_L= Inductor current ripple

• f_SW= Switching frequency

• L = Inductor value

TI recommends to choose a saturation current for the inductor that is approximately 20% to 30% higher than

I_L,MAX. In addition, DC resistance and size must also be taken into account when selecting an appropriate

inductor. 表8-4 lists recommended inductors.

表8-4. List of Recommended Inductors

MAX. DC

RESISTANCE [mΩ]

INDUCTANCE CURRENT RATING DIMENSIONS [L x W x

MFR PART NUMBER⁽¹⁾

[µH]

[A]

4.8

4.6

4.8

5.1

5.2

6.6

8.0

6.8

H mm]

2.0 × 1.6 × 1.0

2.0 × 1.2 × 1.0

2.0 × 1.6 × 1.0

4.0 × 4.0 × 1.6

3.5 × 3.2 × 2.0

4.5 × 4 × 1.8

HTEN20161T-R47MDR, Cyntec

HTEH20121T-R47MSR, Cyntec

DFE201610E - R47M, MuRata

DFE201210S - R47M, MuRata

TFM201610ALM-R47MTAA, TDK

TFM201610ALC-R47MTAA, TDK

XFL4015-471ME, Coilcraft

0.47

8.36

10.85

11.2

XEL3520-471ME, Coilcraft

WE-LHMI-744373240047, Würth

(1) See Third-party Products Disclaimer.

8.2.2.5 Capacitor Selection

The input capacitor is the low-impedance energy source for the converters which helps to provide stable

operation. A low-ESR multilayer ceramic capacitor is recommended for best filtering and must be placed

between VIN and GND as close as possible to those pins. For most applications, a minimum effective input

capacitance of 3 µF must be present, though a larger value reduces input current ripple.

The architecture of the device allows the use of tiny ceramic output capacitors with low equivalent series

resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low

resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends

using X7R or X5R dielectrics. Considering the DC-bias derating the capacitance, the minimum effective output

capacitance is 20 µF for TLV62595.

A feedforward capacitor is required for the adjustable version, as described in 节 8.2.2.2. This capacitor is not

required for the fixed output voltage versions.

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8.2.3 Application Curves

V_IN= 5.0 V, V_OUT= 1.8 V, T_A= 25°C, BOM = 表8-2, unless otherwise noted.

0.612

0.609

0.606

0.603

0.6

0.597

0.594

0.591

0.588

V_IN= 2.5 V

V_IN= 3.3 V

V_IN= 4.2 V

V_IN= 5.0 V

V_IN= 2.5V

V_IN= 3.3V

V_IN= 4.2V

V_IN= 5.0V

100m

10m

Load (A)

100m

10m

Load (A)

100m

D021

D002

V_OUT= 0.6 V

图8-3. Load Regulation

图8-2. Efficiency

100

1.212

1.209

1.206

1.203

1.2

1.197

1.194

1.191

1.188

V_IN= 2.4 V

V_IN= 3.3 V

V_IN= 4.5 V

V_IN= 5.0 V

V_IN= 2.5V

V_IN= 3.3V

V_IN= 4.2V

V_IN= 5.0V

100m

10m

Load (A)

100m

10m

Load (A)

100m

D031

D003

V_OUT= 1.2 V

图8-5. Load Regulation

图8-4. Efficiency

100

1.818

1.812

1.806

1.8

V_IN= 2.5 V

V_IN= 3.3 V

V_IN= 4.2 V

V_IN= 5.0 V

1.794

1.788

1.782

V_IN= 2.5V

V_IN= 3.3V

V_IN= 4.2V

V_IN= 5.0V

100m

10m

Load (A)

100m

10m

Load (A)

100m

D041

D004

V_OUT= 1.8 V

图8-7. Load Regulation

图8-6. Efficiency

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100

2.525

2.515

2.505

2.495

2.485

2.475

V_IN= 3.3 V

V_IN= 4.2 V

V_IN= 5.0 V

V_IN= 3.3V

V_IN= 4.2V

V_IN= 5.0V

100m

10m

Load (A)

100m

10m

Load (A)

100m

D061

D006

V_OUT= 2.5 V

图8-9. Load Regulation

图8-8. Efficiency

100

3.340

3.320

3.300

3.280

3.260

V_IN= 4.2V

V_IN= 5.0V

V_IN= 4.2V

V_IN= 5.0V

100m

10m

Load (A)

100m

10m

Load (A)

100m

D051

D005

V_OUT= 3.3 V

图8-11. Load Regulation

图8-10. Efficiency

3000

2750

2500

2250

2000

1750

1500

1250

1000

750

3000

2750

2500

2250

2000

1750

1500

1250

1000

750

V_OUT= 0.6V

V_OUT= 1.2V

V_OUT= 1.8V

V_OUT= 2.5V

V_OUT= 3.3V

V_OUT= 0.6V

V_OUT= 1.2V

V_OUT= 1.8V

V_OUT= 2.5V

500

250

0.0

0.5

1.0

1.5

2.0

Load (A)

2.5

3.0

3.5

4.0

2.5

3.0

3.5

4.0

Input Voltage (V)

4.5

5.0

5.5

D013

D014

V_IN= 3.3 V

I_OUT= 1.0 A

图8-12. Switching Frequency

图8-13. Switching Frequency

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V_IN= 2.5 V

V_IN= 3.3 V

V_IN= 5.0 V

V_IN= 2.5 V

V_IN= 3.3 V

V_IN= 5.0 V

Ambient Temperature (°C)

105

115

125

Ambient Temperature (°C)

105

115

125

D020

D015

V_OUT= 1.2 V

V_OUT= 1.8 V

θ_JA= 71.4 °C/W

图8-14. Thermal Derating

图8-15. Thermal Derating

V_IN= 3.3 V

V_IN= 5.0 V

55 65

Ambient Temperature (°C)

105

115

125

Ambient Temperature (°C)

105

115

125

D017

D016

V_OUT= 2.5 V

V_OUT= 3.3 V

θ_JA= 71.4 °C/W

图8-16. Thermal Derating

图8-17. Thermal Derating

I_OUT= 1.0 A

I_OUT= 0.1 A

图8-18. PWM Operation

图8-19. PSM Operation

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Load = 0.6 Ω

图8-21. Startup with No Load

图8-20. Start-up with Load

Load = 1.8 Ω

图8-23. Disable, Active Output Discharge at No

图8-22. Disable, Active Output Discharge

Load

I_OUT= 0.05 A to 1A

I_OUT= 1 A to 2 A

图8-24. Load Transient

图8-25. Load Transient

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V_PG

5V/DIV

I_COIL

2A/DIV

V_OUT

1V/DIV

Time - 200ꢀs/DIV

Time - 2ꢀs/DIV

D018

D019

I_OUT= 1 A

图8-26. HICCUP Short Circuit Protection

图8-27. HICCUP Short Circuit Protection (Zoom In)

8.3 Power Supply Recommendations

The device is designed to operate from an input voltage supply range from 2.4 V to 5.5 V. Ensure that the input

power supply has a sufficient current rating for the application.

8.4 Layout

8.4.1 Layout Guidelines

The printed-circuit-board (PCB) layout is an important step to maintain the high performance of the device. See

图8-28 for the recommended PCB layout.

• The input/output capacitors and the inductor must be placed as close as possible to the IC. This keeps the

power traces short. Routing these power traces direct and wide results in low trace resistance and low

parasitic inductance.

• The low side of the input and output capacitors must be connected properly to the GND pin to avoid a ground

potential shift.

• The sense traces connected to FB is a signal trace. Special care must be taken to avoid noise being induced.

Keep these traces away from SW nodes. The connection of the output voltage trace for the FB resistors must

be made at the output capacitor.

• Refer to 图8-28 for an example of component placement, routing and thermal design.

8.4.2 Layout Example

VOUT

VIN

Solution size = 31mm²

GND

图8-28. PCB Layout Recommendation

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8.4.2.1 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires

special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added

heat sinks and convection surfaces, and the presence of other heat-generating components affect the power

dissipation limits of a given component.

Two basic approaches for enhancing thermal performance are:

• Improving the power dissipation capability of the PCB design

• Introducing airflow in the system

Thermal Information provides the thermal metric of the device on the EVM after considering the PCB design of

real applications. The big copper planes connecting to the pads of the IC on the PCB improve the thermal

performance of the device. For more details on how to use the thermal parameters, see the Thermal

Characteristics application notes, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB

Designs and Semiconductor and IC Package Thermal Metrics.

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9 Device and Documentation Support

9.1 Device Support

9.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

9.1.2 Development Support

9.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TLV62595 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs

application note

• Texas Instruments, Semiconductor and IC Package Thermal Metrics application note

9.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

WEBENCH^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

9.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

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9.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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12-May-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TLV62595DMQR

ACTIVE

VSON-HR

DMQ

3000 RoHS & Green

Call TI | SN

Level-1-260C-UNLIM

-40 to 125

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

22-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV62595DMQR

VSON-

DMQ

3000

180.0

8.4

1.75

1.0

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

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22-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VSON-HR DMQ

SPQ

Length (mm) Width (mm) Height (mm)

210.0 185.0 35.0

TLV62595DMQR

3000

Pack Materials-Page 2

PACKAGE OUTLINE

DMQ0006A

VSON - 1 mm max height

SCALE 6.000

PLASTIC SMALL OUTLINE - NO LEAD

1.55

1.45

PIN 1 INDEX AREA

1.55

1.45

1.0

0.8

SEATING PLANE

0.08 C

(0.2) MIN

(0.2) TYP

0.05

0.00

0.5

0.3

4X 0.5

0.3

0.25

0.15

0.2

0.9

0.1

C A B

0.1

C A B

0.7

0.05

4222645/D 05/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

DMQ0006A

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

3X (1)

3X (0.6)

3X (0.2)

SYMM

3X (0.25)

4X (0.5)

(R0.05) TYP

(0.65)

(0.45)

PKG

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

PADS 4-6

NON SOLDER MASK

DEFINED

PADS 1-3

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222645/D 05/2022

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

DMQ0006A

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

EXPOSED METAL

3X (0.85)

3X (0.6)

3X (0.25)

3X (0.2)

SYMM

4X (0.5)

(R0.05) TYP

SOLDER MASK

OPENING

TYP

(0.65)

(0.525)

METAL UNDER

SOLDER MASK

TYP

PKG

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

PADS 4, 5 & 6:

81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:30X

4222645/D 05/2022

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TLV62595 [TI]

相关型号：

TLV62595DMQR

TLV627432

TLV627432YFPR

TLV6700

TLV6700-Q1

TLV6700DDCR

TLV6700DDCT

TLV6700DSER

TLV6700QDDCRQ1

TLV6700QDSERQ1

TLV6703

TLV6703-Q1