TLV6703QDSERQ1 [TI]
具有集成基准的汽车类 18V 比较器 | DSE | 6 | -40 to 125;
| 型号： | TLV6703QDSERQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成基准的汽车类 18V 比较器 | DSE | 6 | -40 to 125 比较器 |
| 文件： | 总23页 (文件大小：1665K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV6703-Q1
ZHCSMR5 –NOVEMBER 2020
具有400mV 基准电压的TLV6703-Q1 汽车微功耗、18V 比较器
1 特性
3 说明
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性：
TLV6703-Q1 是一款高电压比较器，工作电压范围为
1.8V 至 18V。TLV6703-Q1 具有一个内部基准电压为
400mV 的高精度比较器和一个额定电压为 18V 的开漏
输出，用于实现精确的电压检测。可以使用外部电阻设
置监视电压。
– 器件温度等级1：–40°C 至125°C 环境工作温
度范围
– 器件HBM ESD 分类等级H2
– 器件CDM ESD 分类等级C6
• 宽电源电压范围：1.8 V 至18V
• 可调节阈值：低至400mV
• 高阈值精度：
– 25°C 时最高为0.5%
– 在工作温度范围内最大值为1.0%
• 低静态电流：5.5µA（典型值）
• 开漏输出
当 SENSE 引脚上的电压下降至低于 (VIT–) 时，OUT
引脚被驱动至低电平，而当电压返回到对应阈值 (VIT+
)
之上时，OUT 引脚变为高电平。TLV6703-Q1 中的比
较器具有拒绝短暂干扰的内置迟滞，确保稳定的输出运
行，不会引起误触发。
TLV6703-Q1 采用无引线 WSON-6 封装，额定工作结
温范围为–40°C 至+125°C。
• 内部迟滞：5.5mV（典型值）
• 温度范围：–40°C 至+125°C
• 封装：无引线WSON-6
器件信息(1)
封装尺寸（标称值）
器件型号
TLV6703-Q1
封装
WSON (6)
1.50mm × 1.50mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
• 紧急呼叫(eCall)
• 汽车音响主机
• 仪表组
• 车载充电器(OBC) 和无线充电器
401
VDD = 1.8 V
VDD = 5 V
VDD = 12 V
VDD = 18 V
VMON
0.01 ꢀF
400.6
400.2
VPULLUP
Up to 18 V
VDD
399.8
399.4
399
R1
RP
SENSE
OUT
R2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
上升输入阈值电压(VIT+) 与温度间的关系
VIT
+
GND
简化版方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSDA1
TLV6703-Q1
ZHCSMR5 –NOVEMBER 2020
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Table of Contents
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................11
9 Application and Implementation..................................12
9.1 Application Information............................................. 12
9.2 Typical Application.................................................... 14
9.3 Dos and Don'ts..........................................................15
10 Power-Supply Recommendations............................. 16
11 Layout...........................................................................17
11.1 Layout Guidelines................................................... 17
11.2 Layout Example...................................................... 17
12 Device and Documentation Support..........................18
12.1 Device Support....................................................... 18
12.2 Receiving Notification of Documentation Updates..18
12.3 支持资源..................................................................18
12.4 Trademarks.............................................................18
12.5 静电放电警告.......................................................... 18
12.6 术语表..................................................................... 18
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Timing Requirements..................................................7
7.7 Switching Characteristics............................................7
7.8 Timing Diagrams ........................................................7
7.9 Typical Characteristics................................................8
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
Information.................................................................... 18
4 Revision History
DATE
REVISION
NOTES
November 2020
*
Initial release.
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5 Device Comparison Table
表5-1. TLV67xx Integrated Comparator Family
OPERATING
VOLTAGE RANGE
THRESHOLD ACCURACY OVER
TEMPERATURE
PART NUMBER
CONFIGURATION
TLV6700
TLV6700-Q1
TLV6703
Window
Window
1.8 V to 18 V
1.8 V to 18 V
1.8 V to 18 V
1.8 V to 18 V
1.8 V to 36 V
1.8 V to 36 V
1%
1%
Non-Inverting Single Channel
Non-Inverting Single Channel
Window
1%
TLV6703-Q1
TLV6710
1%
0.75%
0.75%
TLV6713
Non-Inverting Single Channel
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6 Pin Configuration and Functions
GND
VDD
1
2
6
5
4
OUT
GND
GND
3
SENSE
图6-1. DSE Package, 6-Pin WSON, Top View
表6-1. Pin Functions
DESCRIPTION
PIN
I/O
—
O
NAME
GND
DSE
1,3,5
Connect all three pins to ground.
SENSE comparator open-drain output. OUT is driven low when the voltage at this comparator
is below (VIT-). The output goes high when the sense voltage returns above the respective
threshold (VIT+).
OUT
6
This pin is connected to the voltage to be monitored with the use of an external resistor
SENSE
VDD
4
2
I
I
divider. When the voltage at this pin drops below the threshold voltage (VIT-), OUT is driven
low.
Supply voltage input. Connect a 1.8-V to 18-V supply to VDD to power the device. Good
analog design practice is to place a 0.1-µF ceramic capacitor close to this pin.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
20
UNIT
VDD
Voltage(2)
OUT
20
V
SENSE
7
Current
OUT (output sink current)
Operating junction, TJ
Storage, Tstg
40
mA
°C
125
150
–40
–65
Temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltages are with respect to network ground pin.
7.2 ESD Ratings
VALUE
±2500
±1000
UNIT
Human body model (HBM), per AEC Q100-002, all pins(1)
Charged device model (CDM), per AEC Q100-002, all pins
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shal be in accordance with ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
1.8
0
NOM
MAX UNIT
VDD
VI
Supply voltage
Input voltage
Output voltage
18
6.5
18
V
V
V
SENSE
OUT
VO
0
7.4 Thermal Information
DSE (WSON)
6 PADS
194.9
THERMAL METRIC (1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
128.9
153.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
11.9
ψJT
157.4
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor an IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
Over the operating temperature range of TJ = –40°C to +125°C, and 1.8 V < VDD < 18 V (unless otherwise noted).
Typical values are at TJ = 25°C and VDD = 5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
400
MAX UNIT
V(POR) Power-on reset voltage (1)
VOLmax = 0.2 V, output sink current = 15 µA
VDD = 1.8V and 18 V, TJ = 25°C
0.8
402.5
404
397.5
400
12
V
398
396
VIT+
Positive-going input threshold voltage
mV
VDD = 1.8V and 18 V, TJ = –40°C to 125°C
VDD = 1.8V and 18 V, TJ = 25°C
391.6
387
394.5
VIT–
Negative-going input threshold voltage
mV
VDD = 1.8V and 18 V, TJ = –40°C to 125°C
Vhys
I(SENSE) Input current (at the SENSE pin)
5.5
1
mV
nA
Hysteresis voltage (hys = VIT+ –VIT–
)
VDD = 1.8 V and 18 V, VI = 6.5 V
VDD = 1.8 V, output sink current = 3 mA
VDD = 5 V, output sink current = 5 mA
VDD = 1.8 V and 18 V, VO = VDD
VDD = 1.8 V, VO = 18 V
VDD = 1.8 V, no load
25
–25
250
250
300
300
11
VOL
Low-level output voltage
mV
nA
Ilkg(OD) Open-drain output leakage-current
5.5
6
VDD = 5 V
13
IDD
Supply current
µA
V
VDD = 12 V
6
13
VDD = 18 V
7
13
UVLO Undervoltage lockout (2)
VDD falling
1.3
1.7
(1) The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. Below V(POR), the output cannot be determined.
(2) When VDD falls below UVLO, OUT is driven low. The output cannot be determined below V(POR)
.
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7.6 Timing Requirements
over operating temperature range (unless otherwise noted)
MIN
NOM MAX UNIT
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV,
see 图7-1
tpd(HL)
High-to-low propagation delay (1)
18
µs
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV,
see 图7-1
tpd(LH)
td(start)
Low-to-high propagation delay (1)
Start-up delay (2)
29
µs
µs
150
(1) High-to-low and low-to-high refers to the transition at the input pin (SENSE).
(2) During power on, VDD must exceed 1.8 V for at least 150 µs before the output is in a correct state.
7.7 Switching Characteristics
over operating temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VO = (0.1 to 0.9) × VDD
tr
tf
Output rise time
2.2
µs
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VO = (0.1 to 0.9) × VDD
Output fall time
0.22
µs
7.8 Timing Diagrams
VDD
SENSE
OUT
V(POR)
VIT+
VITœ
VHYS
tpd(LH)
tpd(HL)
tpd(LH)
t d(start)
图7-1. Timing Diagram
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7.9 Typical Characteristics
at TJ = 25°C and VDD = 5 V (unless otherwise noted)
10
9
401
400.6
400.2
399.8
399.4
399
VDD = 1.8 V
VDD = 5 V
VDD = 12 V
VDD = 18 V
8
7
6
5
4
3
2
1
0
TJ = -40°C
TJ = 0°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
0
2
4
6
8
10
Supply Voltage (V)
12
14
16
18
图7-3. Rising Input Threshold Voltage (VIT+) vs Temperature
图7-2. Supply Current (IDD) vs Supply Voltage (VDD
)
9
25
VDD = 1.8 V
VDD = 18 V
23
21
19
17
15
13
11
9
8
7
6
5
VDD = 1.8 V
VDD = 5 V
VDD = 12 V
VDD = 18 V
4
3
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
图7-4. Hysteresis (Vhys) vs Temperature
图7-5. Propagation Delay vs Temperature (High-to-Low
Transition at Sense)
30
28
26
24
22
20
18
16
14
16
14
12
10
8
6
4
2
VDD = 1.8 V
VDD = 18 V
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
2.5
4
5.5
7
8.5
10
Positive-Going Input Threshold Overdrive (%)
11.5
13
14.5
SENSE = negative spike below VIT–
图7-6. Propagation Delay vs Temperature (Low-to-High
图7-7. Minimum Pulse Width vs Threshold Overdrive Voltage
Transition at Sense)
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7.9 Typical Characteristics (continued)
at TJ = 25°C and VDD = 5 V (unless otherwise noted)
12
2000
1800
1600
1400
1200
1000
800
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
10
8
6
4
600
TJ = -40°C
TJ = 0°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
400
2
0
200
0
0
4
8
12
16
Output Sink Current (mA)
20
24
28
32
36
40
0
4
8
12
16
Output Sink Current (mA)
20
24
28
32
36
40
图7-8. Supply Current (IDD) vs Output Sink Current
图7-9. Output Voltage Low (VOL) vs Output Sink Current (–
40°C)
2000
2000
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
1800
1800
1600
1600
1400
1200
1000
800
600
400
200
0
1400
1200
1000
800
600
400
200
0
0
4
8
12
16
Output Sink Current (mA)
20
24
28
32
36
40
0
4
8
12
16
Output Sink Current (mA)
20
24
28
32
36
40
图7-10. Output Voltage Low (VOL) vs Output Sink Current (0°C) 图7-11. Output Voltage Low (VOL) vs Output Sink Current (25°C)
2000
1800
1600
1400
1200
1000
800
2000
1800
1600
1400
1200
1000
800
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
600
600
400
400
200
200
0
0
0
4
8
12
16
Output Sink Current (mA)
20
24
28
32
36
40
0
4
8
12
16
Output Sink Current (mA)
20
24
28
32
36
40
图7-12. Output Voltage Low (VOL) vs Output Sink Current (85°C)
图7-13. Output Voltage Low (VOL) vs Output Sink Current
(125°C)
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8 Detailed Description
8.1 Overview
The TLV6703-Q1 provides precision voltage detection. The TLV6703-Q1 is a wide-supply voltage range (1.8 V to
18 V) comparator with a high-accuracy rising input threshold of 400 mV (1% over temperature) and built-in
hysteresis. The output is also rated to 18 V, independant of supply voltage, and can sink up to 40 mA.
The TLV6703-Q1 asserts the output signal, as shown in 表8-1. To monitor any voltage above 0.4 V, set the input
using an external resistor divider network. Each input pin has very low input leakage current, allowing the use of
large resistor dividers without sacrificing system accuracy. Broad voltage thresholds are supported that enable
the device for use in a wide array of applications.
表8-1. TLV6703-Q1 Truth Table
CONDITION
SENSE > VIT+
SENSE < VIT–
OUTPUT
OUT high
OUT low
OUTPUT STATE
Output high impedance
Output sinking
8.2 Functional Block Diagram
VDD
SENSE
OUT
VIT+
GND
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8.3 Feature Description
8.3.1 Input Pin (SENSE)
The TLV6703-Q1 comparator has two inputs: one external input, and one input internally connected to the
internal 400mV reference. The comparator rising threshold is trimmed to be equal to the reference voltage (400
mV). The comparator also has a built-in falling hysteresis that makes the device less sensitive to supply-rail
noise and provides stable operation.
The comparator input (SENSE) is able to swing from ground to 6.5 V, regardless of the device supply voltage.
Although not required in most cases, to reduce sensitivity to transients and layout parasitics for extremely noisy
applications, place a 1-nF to 10-nF bypass capacitor at the comparator input.
OUT is driven to logic low when the input SENSE voltage drops below (VIT-). When the voltage exceeds VIT+, the
output (OUT) goes to a high-impedance state; see 图7-1 .
8.3.2 Output Pin (OUT)
In a typical TLV6703-Q1 application, the output is connected to a GPIO input of the processor (such as a digital
signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or application-
specific integrated circuit [ASIC]).
The TLV6703-Q1 device provides an open-drain output (OUT). Use a pullup resistor to hold this line high when
the output goes to high impedance (not asserted). To connect the output to another device at the correct
interface-voltage level, connect a pullup resistor to the proper voltage rail. The TLV6703-Q1 output can be pulled
up to 18 V, independent of the device supply voltage.
表 8-1 and the 节 8.3.1 section describe how the output is asserted or deasserted. See for a 图 7-1 timing
diagram that describes the relationship between threshold voltage and the respective output.
8.3.3 Immunity to Input-Pin Voltage Transients
The TLV6703-Q1 is relatively immune to short voltage transient spikes on the sense pin. Sensitivity to transients
depends on both transient duration and amplitude; see 图 7-7, Minimum Pulse Width vs Threshold Overdrive
Voltage.
8.4 Device Functional Modes
8.4.1 Normal Operation (VDD > UVLO)
When the voltage on VDD is greater than 1.8 V for at least 150 µs, the OUT signal correspond to the voltage on
SENSE as listed in 表8-1.
8.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
When the voltage on VDD is less than the device UVLO voltage, and greater than the power-on reset voltage,
V(POR), the OUT signal is asserted regardless of the voltage on SENSE.
8.4.3 Power-On Reset (VDD < V(POR)
)
When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND
(V(POR)), SENSE is in a high-impedance state.
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9 Application and Implementation
备注
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TLV6703-Q1 device is a wide-supply voltage comparator that operates over a VDD range of 1.8 V to
18 V. The device has a high-accuracy comparator with an internal 400-mV reference and an open-drain output
rated to 18 V for precision voltage detection. The device can be used as a voltage monitor. The monitored
voltage are set with the use of external resistors.
9.1.1 VPULLUP to a Voltage Other Than VDD
The output is often tied to VDD through a resistor. However, some applications may require the output to be
pulled up to a higher or lower voltage than VDD to correctly interface with the reset and enable pins of other
devices.
VMON
1.8 V to 18 V
0.01 ꢀF
VPULLUP
Up to 18 V
R1
VDD
RP
To a reset or enable
input of the system.
SENSE
OUT
R2
GND
图9-1. Interfacing to a Voltage Other Than VDD
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9.1.2 Monitoring VDD
Many applications monitor the same rail that is powering VDD. In these applications the resistor divider is simply
connected to the VDD rail.
1.8 V to 18 V
0.01 ꢀF
VPULLUP
Up to 18 V
R1
R2
VDD
RP
To a reset or enable
input of the system.
SENSE
OUT
GND
图9-2. Monitoring the Same Voltage as VDD
9.1.3 Monitoring a Voltage Other Than VDD
Some applications monitor rails other than the one that is powering VDD. In these types of applications the
resistor divider used to set the desired threshold is connected to the rail that is being monitored.
VMON
1.8 V to 18 V
0.01 ꢀF
VPULLUP
Up to 18 V
R1
VDD
RP
To a reset or enable
input of the system.
SENSE
OUT
R2
GND
NOTE: The input can monitor a voltage greater than maximum VDD with the use of an external resistor divider network.
图9-3. Monitoring a Voltage Other Than VDD
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9.2 Typical Application
The TLV6703-Q1 device is a wide-supply voltage comparator that operates over a VDD range of 1.8 to 18 V. The
monitored voltage is set with the use of external resistors, so the device can be used either as a precision
voltage monitor.
VMON
1.8 V to 18 V
0.01 ꢀF
VPULLUP
Up to 18 V
R1
2.21 MΩ
RP
VDD
49.9 kΩ
To a reset or enable
input of the system.
SENSE
OUT
R2
83.5 kΩ
GND
图9-4. Wide VIN Voltage Monitor
9.2.1 Design Requirements
For this design example, use the values summarized in 表9-1 as the input parameters.
表9-1. Design Parameters
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
12-V nominal rail with maximum falling
threshold of 10%
Monitored voltage
VMON(UV)= 10.99 V (8.33%)
9.2.2 Detailed Design Procedure
9.2.2.1 Resistor Divider Selection
The resistor divider values and target threshold voltage can be calculated by using 方程式 1 to determine
VMON(UV)
.
R1
R2
≈
’
VMON(UV) = 1 +
∆
× V
IT-
÷
◊
«
(1)
where
• R1 and R2 are the resistor values for the resistor divider on the SENSEx pins
• VMON(UV) is the target voltage at which an undervoltage condition is detected
Choose RTOTAL ( = R1 + R2) so that the current through the divider is approximately 100 times higher than the
input current at the SENSE pin. The resistors can have high values to minimize current consumption as a result
of low input bias current without adding significant error to the resistive divider. For details on sizing input
resistors, refer to application report SLVA450, Optimizing Resistor Dividers at a Comparator Input, available for
download from www.ti.com.
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9.2.2.2 Pullup Resistor Selection
To ensure the proper voltage level, the pullup resistor value is selected by ensuring that the pullup voltage
divided by the resistor does not exceed the sink-current capability of the device. This confirmation is calculated
by verifying that the pullup voltage minus the output-leakage current (Ilkg(OD)) multiplied by the resistor is greater
than the desired logic-high voltage. These values are specified in the 节7.5.
Use 方程式2 to calculate the value of the pullup resistor.
(VHI - VPU)
VPU
IO
³ RPU
³
Ilkg(OD)
(2)
9.2.2.3 Input Supply Capacitor
Although an input capacitor is not required for stability, for good analog design practice, connect a 0.1-μF low
equivalent series resistance (ESR) capacitor across the VDD and GND pins. A higher-value capacitor may be
necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power
source.
9.2.2.4 Sense Capacitor
Although not required in most cases, for extremely noisy applications, place a 1-nF to 10-nF bypass capacitor
from the comparator input (SENSE) to the GND pin for good analog design practice. This capacitor placement
reduces device sensitivity to transients.
9.2.3 Application Curves
401
VDD = 1.8 V
VDD = 5 V
VDD = 12 V
VDD = 18 V
400.6
400.2
399.8
399.4
399
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
图9-5. Rising Input Threshold Voltage (VIT+) vs Temperature
9.3 Dos and Don'ts
Do connect a 0.1-µF decoupling capacitor from VDD to GND for best system performance.
If the monitored rail is noisy, do connect a decoupling capacitor from the comparator input (sense) to GND.
Don't use resistors for the voltage divider that cause the current through them to be less than 100 times the input
current of the comparator without also accounting for the effect to the accuracy.
Don't use a pullup resistor that is too small, because the larger current sunk by the output then exceeds the
desired low-level output voltage (VOL).
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10 Power-Supply Recommendations
These devices operate from an input voltage supply range between 1.8 V and 18 V.
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11 Layout
11.1 Layout Guidelines
Placing a 0.1-µF capacitor close to the VDD pin to reduce the input impedance to the device is good analog
design practice.
11.2 Layout Example
Pullup
Voltage
RP1
Output
Flag
6
5
1
CVDD
Input
Supply
2
3
4
R1
R2
Monitored
Voltage
图11-1. Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
The DIP Adapter Evaluation Module allows conversion of the SOT-23-6 package to a standard DIP-6 pinout for
ease of prototyping and bench evaluation.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV6703QDSERQ1
ACTIVE
WSON
DSE
6
3000 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
K7
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV6703QDSERQ1
WSON
DSE
6
3000
180.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WSON DSE
SPQ
Length (mm) Width (mm) Height (mm)
213.0 191.0 35.0
TLV6703QDSERQ1
6
3000
Pack Materials-Page 2
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