TLV841SADL01YBHR [TI]

具有可调节释放延迟功能且采用 Wafer Chip-Scale Package 封装的超低压纳瓦级功率监控器 | YBH | 4 | -40 to 125;


型号：	TLV841SADL01YBHR
厂家：	TEXAS INSTRUMENTS
描述：	具有可调节释放延迟功能且采用 Wafer Chip-Scale Package 封装的超低压纳瓦级功率监控器 \| YBH \| 4 \| -40 to 125 监控
文件：	总34页 (文件大小：1890K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLV841

ZHCSMZ5D –APRIL 2020 –REVISED JANUARY 2023

采用WCSP 封装的TLV841 小型纳米功率电压监控器

1 特性

3 说明

旨在实现高性能：

TLV841 是一款微功耗精密电压监控器，阈值精度为

±0.5%，采用超小型 DSBGA 封装。TLV841 可提供三

种引脚排列系列（S、M、C），解决方案总尺寸非常

小，可提供许多独特选项。监控电压轨或按钮信号时，

内置迟滞及固定或可编程 (TLV841C) 复位延时可防止

发出错误复位信号。在 TLV841S 的低电平有效输出

端，通过在 SENSE 和 RESET 引脚之间添加外部电阻

器，可增加电压阈值迟滞。TLV841 具有精度高、功耗

低、特性出色、外形紧凑等优点，可为个人和消费类产

品等各种电池供电应用提供理想解决方案。

• 纳米静态电流：125nA（典型值）

• 高阈值精度：±0.5%（典型值）

• 内置精密迟滞(V_HYS)：5%（典型值）

适用于多种应用：

• 工作电压范围：0.7V 至5.5V

• 可调节阈值电压：0.505 V（典型值）

• 固定电压(V_IT-)：0.8 V 至4.9 V（步长为0.1 V）

• 独立SENSE 引脚(TLV841S)

• 低电平有效手动复位(MR) (TLV841M)

• TLV841 的按钮监控（S/M 系列）

• 复位延时时间(t_D)：可基于电容器编程(TLV841C)

– 下限延时时间：40μA（典型值），无电容器

• 复位延时时间(t_D)：固定延时时间选项（TLV841M

和TLV841S）

– 40μs、2ms、10ms、30ms、50ms、80ms、

100ms、150ms、200ms

• 温度范围：–40°C 至+125°C

通过单独的 VDD 和 SENSE (TLV841S) 引脚，可实现

高可靠性系统所需的冗余。SENSE 已从 VDD 去耦，

能监控除 VDD 外的轨电压，也可用作按钮输入。

SENSE 引脚的高阻抗输入支持使用可选的外部电阻

器。TLV841S 无需外部电容器即可提供固定复位延时

计时选项。CT 引脚悬空时，TLV841C 支持包括下限

延时的可编程复位延时时间。TLV841M 提供单独的手

动复位 (MR) 引脚，可通过外部信号强制创造复位条

件，也可用作按钮输入。TLV841M 可设置为 VDD 和

MR 引脚监控，从而创建简易双通道监控器解决方案。

TLV841 的工作温度范围为-40°C 至+125°C (T_A)。

多输出拓扑、封装类型：

• TLV841xxDL：开漏，低电平有效(RESET)

• TLV841xxPL：推挽，低电平有效(RESET)

• TLV841xxDH：开漏，高电平有效(RESET)

• TLV841xxPH：推挽，高电平有效(RESET)

• 封装：0.73mm x 0.73mm DSBGA

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

TLV841

DSBGA (4)

0.73mm × 0.73mm

(1) 如需了解封装详细信息，请参阅数据表末尾的机械制图附录。

2 应用

• 包括可穿戴设备和助听设备在内的个人电子产品

• 家庭影院和娱乐系统

• 电子销售终端

• 电网基础设施

• 数据中心和企业级计算

0.7 V to 5.5 V

-40^oC

25^oC

125^oC

0.8

0.6

0.4

0.2

IN LDO

OUT

*R_pu

VDD

Microcontroller

SENSE RESET

RESET

TLV841SADL01

GND

0.5

1.5

2.5

3 3.5 4 4.5 5 5.5

*R_puonly for TLV841xxDx

VDD (V)

典型电源电流

典型应用电路

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSFO5

TLV841

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ZHCSMZ5D –APRIL 2020 –REVISED JANUARY 2023

Table of Contents

8.4 Device Functional Modes..........................................19

9 Application and Implementation..................................20

9.1 Application Information............................................. 20

9.2 Typical Application.................................................... 20

10 Power Supply Recommendations..............................23

11 Layout...........................................................................24

11.1 Layout Guidelines................................................... 24

11.2 Layout Example...................................................... 24

12 Device and Documentation Support..........................25

12.1 Device Nomenclature..............................................25

12.2 Documentation Support.......................................... 26

12.3 接收文档更新通知................................................... 26

12.4 支持资源..................................................................26

12.5 Trademarks.............................................................26

12.6 静电放电警告.......................................................... 26

12.7 术语表..................................................................... 26

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison.........................................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings ....................................... 5

7.2 ESD Ratings .............................................................. 5

7.3 Recommended Operating Conditions ........................5

7.4 Thermal Information ...................................................6

7.5 Electrical Characteristics ............................................7

7.6 Timing Requirements .................................................9

7.7 Timing Diagrams ......................................................10

7.8 Typical Characteristics..............................................12

8 Detailed Description......................................................13

8.1 Overview...................................................................13

8.2 Functional Block Diagram.........................................13

8.3 Feature Description...................................................13

Information.................................................................... 26

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision C (June 2021) to Revision D (January 2023)

Page

• Removed Table 12-2.........................................................................................................................................25

Changes from Revision B (May 2021) to Revision C (June 2021)

Page

• 器件的RTM........................................................................................................................................................ 1

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5 Device Comparison

图 5-1 shows the device naming nomenclature to compare the different device variants. See 表 12-1 for a more

detailed explanation. Please contact Texas Instruments for availability of variant options.

TLV 841 X X XX XX XXX

Feature Op on

S: SENSE pin

C: Capacitor delay (CT) B: 2 ms

M: Manual reset (MR) C: 10 ms

Delay Op on

A: 40 µs

Output Type

DL: Open-drain,

ac ve-low

PL: Push-pull,

ac ve-low

DH: Open-drain,

ac ve-high

PH: Push-pull,

ac ve-high

Package

YBH: DSBGA (4-pin)

Detect Voltage Threshold

01: 0.505V

08: 0.8V

...

D: 30 ms

E: 50 ms

F: 80 ms

G: 100 ms

H: 150 ms

I: 200 ms

49: 4.9V

图5-1. Device Naming Nomenclature

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6 Pin Configuration and Functions

VDD

RESET / RESET

SENSE

GND

图6-1. YBH 4-Pin DSBGA Package

图6-2. YBH 4-Pin DSBGA Package

(TLV841S)

Top View

(TLV841C)

Top View

VDD

RESET / RESET

GND

图6-3. YBH 4-Pin DSBGA Package

(TLV841M)

Top View

表6-1. Pin Functions

I/O

DESCRIPTION

PIN NO. TLV841S TLV841C TLV841M

Active-Low Output Reset Signal for TLV841xxxL: This pin is driven logic low

when VDD and SENSE voltage falls below the negative voltage threshold (V_IT-) or

when the MR voltage falls below the logic low threshold. RESET remains logic low

(asserted) until MR is above the logic high threshold or for the duration of the delay

time period (t_D) after VDD or SENSE voltage rises above V_IT-+ V_HYS

RESET

Active-High Output Reset Signal for TLV841xxxH: This pin is driven logic high

when VDD or SENSE voltage falls below the negative voltage threshold (V_IT-) or

when the MR voltage falls below the logic low threshold. RESET remains logic high

(asserted) until MR is above the logic high threshold or for the duration of the delay

time period (t_D) after VDD or SENSE voltage rises above V_IT-+ V_HYS

RESET

VDD

RESET

VDD

RESET

VDD

Input Supply Voltage: The VDD pin connects to the power supply to power the

device. TLV841C and TLV841M monitor VDD voltage. TLV841S monitors SENSE

only. Good analog design practice recommends placing a minimum 0.1 µF ceramic

capacitor as near as possible to the VDD pin.

SENSE pin: This pin is connected to the voltage to be monitored. When the voltage

on SENSE falls below the negative threshold voltage V_IT-, reset asserts. When the

voltage on SENSE rises above the positive threshold voltage (V_IT-+ V_HYS), reset

deasserts. For noisy applications, placing a 10 nF to 100 nF ceramic capacitor close

to this pin may be needed for optimum performance.

SENSE

Capacitor Time Delay Pin: The CT pin offers a user-programmable reset deassert

delay time. Connect an external capacitor on this pin to adjust time delay. When not

in use leave pin floating for the smallest fixed time delay.

Manual Reset: Pull this pin to a logic low to assert a reset signal in the RESET

output pin (RESET signal for DL and PL option). After MR pin is left floating or pulls

to logic high, the RESET output deasserts to the nominal state after the reset delay

time (t_D)expires. If unused, the pin can be left floating or connected to VDD.

GND

Ground

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range, unless otherwise noted⁽¹⁾

MIN

MAX

UNIT

Voltage

VDD, SENSE (TLV841S)

–0.3

CT (TLV841C), MR (TLV841M), RESET

(TLV841xxPx), RESET (TLV841xxPx)

V_DD+0.3 ⁽³⁾

–0.3

RESET (TLV841xxDx), RESET (TLV841xxDx)

RESET, RESET

±20

125

150

Current

°C

Temperature⁽²⁾

Operating ambient temperature, T_A

Storage, T_stg

–40

–65

Temperature

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) As a result of the low dissipated power in this device, it is assumed that T_J= T_A.

(3) The absolute maximum rating is (VDD + 0.3) V or 6 V, whichever is smaller

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC

JS-001⁽¹⁾

± 2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification

JESD22-C101⁽²⁾

± 750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

0.7

0.85

NOM

MAX

5.5

V_DD

5.5

UNIT

VDD (TLV841C, TLV841M)

VDD (TLV841S)

VDD (TLV841xxPH)

Voltage

SENSE

MR ⁽¹⁾, CT

RESET(TLV841xxPL), RESET (TLV841xxPH)

RESET(TLV841xxDL), RESET (TLV841xxDH)

RESET, RESET

Current

T_A

°C

–5

–40

Operating free air temperature

CT pin capacitor range

125

C_CT

µF

(1) If the logic signal driving MR is less than V_DD, then additional current flows into VDD and out of MR. MR pin voltage should not be

higher than V_DD.

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UNIT

ZHCSMZ5D –APRIL 2020 –REVISED JANUARY 2023

7.4 Thermal Information

TLV841

YBH (WCSP)

4 PINS

180.8

THERMAL METRIC⁽¹⁾

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

1.8

58.0

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.9

ψ_JT

58.0

ψ_JB

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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7.5 Electrical Characteristics

At V_DDMIN≤V_DD≤5.5 V, CT = MR = Open, RESET/RESET pull-up resistor R_pull-up⁽³⁾= 100 kΩto VDD, output reset load

C_LOAD= 10 pF and over the operating free-air temperature range –40℃to 125℃, unless otherwise noted. Typical values

are at T_A= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

COMMON PARAMETERS

Negative-going input threshold for

TLV841Sxxx01 ADJ version

V_ADJ-VIT–

0.505

Negative-going input threshold range

Fixed threshold version ⁽¹⁾

V_IT–

0.8

4.9

2.5

V_IT–= 0.505 V (TLV841Sxx01) or 0.8 V to 1.7 V

(Fixed threshold)

-2.5

±0.5

V_{IT–_ACC}Negative-going input threshold accuracy

V_IT–= 1.8 V to 4.9 V (Fixed threshold)

V_IT–= 0.505 V and 0.8 V

-2

±0.5

V_HYS

Hysteresis on V_IT–pin

V_IT–= 0.9 V to 4.9 V

V_OL(MAX)= 300 mV

TLV841xxxLxx

700

900

I_RESET(Sink)= 15 µA

V_POR

Power on reset voltage ⁽²⁾

V_OH(MIN)= 0.8VDD

TLV841xxxHxx

I_{RESET(Source)}= 15 µA

V_DD= 0.85 V

I_RESET(Sink)= 15 µA

300 mV

V_DD= 3.3 V

V_OL

Low level output voltage

I_RESET(Sink)= 2 mA

300 mV

V_DD= 5.5 V

I_RESET(Sink)= 2 mA

300 mV

V_DD= 1 V

I_{RESET(Source)}= 15 µA

0.8V_DD

V_DD= 1.8 V

I_{RESET(Source)}= 500 µA

V_OH

High level output voltage

V_DD≥3.3 V

I_{RESET(Source)}= 2 mA

100

T_A= –40℃to 85℃

I_lkg(OD)

Open-Drain output leakage current

Supply current into Supply current

V_DD= V_PULLUP= 5.5 V

350

V_DD= 5.5 V

V_IT–= 1.9 V to 4.9 V

I_DD

0.125

µA

VDD pin

into VDD pin

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7.5 Electrical Characteristics (continued)

At V_DDMIN≤V_DD≤5.5 V, CT = MR = Open, RESET/RESET pull-up resistor R_pull-up⁽³⁾= 100 kΩto VDD, output reset load

C_LOAD= 10 pF and over the operating free-air temperature range –40℃to 125℃, unless otherwise noted. Typical values

are at T_A= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

TLV841S

Current into SENSE pin, fixed threshold V_DD= V_SENSE= 5.5 V

0.025

0.1

µA

variant

V_IT–= 0.8 V to 4.9 V

I_SENSE

V_DD= V_SENSE= 5.5 V

V_IT–= 0.505 V

Current into SENSE pin, ADJ variant

0.05

TLV841M

V_{MR_L}

V_{MR_H}

R_MR

Manual reset logic low input

0.3V_DD

Manual reset logic high input

0.7V_DD

410

Manual reset internal pull-up resistance

100

500

kΩ

TLV841C

R_CT

CT pin internal resistance

590

kΩ

(1) V_IT-threshold voltage range from 0.8 V to 4.9 V (for DL, PL, DH) and 1 V to 4.9 V (for PH) in 100 mV steps, for released versions see

Device Voltage Thresholds table.

(2) V_PORis the minimum V_DDvoltage level for a controlled output state.

(3) Pull up resistance applicable for open drain variants

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7.6 Timing Requirements

At V_DDMIN≤V_DD≤5.5 V, CT = MR = Open, RESET pull-up resistor R_pull-up= 100 kΩto VDD, output load is C_LOAD= 10 pF

and over the operating free-air temperature range –40°C to 125°C, unless otherwise noted. Typical values are at T_A= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Propagation detect delay for V_DDfalling

below V_IT–

V_DD= (V_IT++ 10%) to (V_IT––10%) ⁽²⁾

t_{P_HL}

µs

CT pin = Open or NC

CT pin = 10 nF

CT pin = 1 µF

Variant A ⁽³⁾

6.2

619

µs

t_D

Reset time delay (TLV841C variant)

Variant B ⁽³⁾

µs

Variant C ⁽³⁾

Variant D ⁽³⁾

Reset time delay (TLV841S and TLV841M

variant) ⁽⁵⁾

t_D

Variant E ⁽³⁾

Variant F ⁽³⁾

Variant G ⁽³⁾

100

150

200

Variant H ⁽³⁾

Variant I ⁽³⁾

t_{GI_VIT–}Glitch immunity V_IT–

t_STRT

Startup Delay ⁽¹⁾

t_{MR_RES}Propagation delay from MR low to reset

5% V_IT–overdrive ⁽⁴⁾

300

µs

V_DD= 3.3 V, MR < V_{MR_L}

t_{P_HL}

t_D

µs

V_DD= 3.3 V,

MR = V_{MR_L}to V_{MR_H}

t_{MR_tD}

Delay from release MR to deassert reset

µs

t_{MR_PW}Glitch immunity MR pin

(1) When VDD starts from less than the specified minimum V_DDand then exceeds V_POR, reset is release after the startup delay (t_STRT).

For TLV841C variants a capacitor at CT pin will add t_Ddelay to t_STRTtime

(2) t_{P_HL}measured from threhold trip point (V_IT–) to V_OLfor active low variants and V_OHfor active high variants.

(3) Refer device nomenclature table for variant description. V_DDtransition from V_IT––10% to V_IT++ 10% for TLV841M and TLV841C;

_SENSEtransition from V_IT––10% to V_IT++ 10% for TLV841S

(4) Overdrive % = [(V_DD/ V_IT–) –1] × 100% for TLV841M and TLV841C; Overdrive % = [(V_SENSE/ V_IT–) –1] × 100% for TLV841S

(5) Specified by design and characterization

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7.7 Timing Diagrams

V_DD(MIN)

V_POR

VDD

SENSE

RESET

V_IT-+ V_HYS

V_IT-

_STRT+ t_D

t_{D_HL}

t_D

Unde ned

A. Open-Drain timing diagram assumes the RESET pin is connected via an external pull-up resistor to VDD.

Unde ned

图7-1. Timing Diagram for TLV841SxxL (SENSE) Active Low Output

[Open-Drain and Push-Pull Output Topology]

VDD

V_DD(MIN)

V_POR

V_IT-+ V_HYS

V_IT-

SENSE

t_D-HL

_STRT+ t_D

t_D

RESET

Unde ned

A. Open-Drain timing diagram assumes the RESET pin is connected via an external pull-up resistor to VDD.

Unde ned

图7-2. Timing Diagram for TLV841SxxH (SENSE) Active High Output

[Open-Drain and Push-Pull Output Topology]

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V_IT-+ V_HYS

V_IT-

V_DD(MIN)

V_POR

VDD

_STRT+ t_D

t_{D_HL}

t_D

t_{D_HL}

t_D

RESET

Unde ned

A. Open-Drain timing diagram assumes the RESET / RESET pin is connected via an external pull-up resistor to VDD.

B. t_{D (no cap)}is included in t_STRTtime delay. If t_Ddelay is programmed by an external capacitor connected to CT pin then t_Dprogrammed

time will be added to the startup time, VDD slew rate = 1 V / µs.

C. Be advised that the VDD falling slew rate is (slew rate > 1 V / µs) and resulting RESETin what is shown above figure. The RESET

behavior would be similar to 图7-1 if the slew rate was much slower or if VDD decay time is larger than the prop delay (t_{D_HL}).

图7-3. Timing Diagram for TLV841CxxL (CT) Active Low Output

[Open-Drain and Push-Pull Output Topology]

V_IT+

V_HYS

V_IT-

V_IT+

V_HYS

V_IT-

VDD

t_{P_HL}

t_D

t_{MR_tD}

RESET

(2)

t_{MR_RES}

V_{MR_H}

V_{MR_L}

(1)

t_{MR_PW}

(1) MR pulse width too small to assert RESET

(2) MR voltage not low enough to assert RESET

Time

A. Open-Drain timing diagram assumes the RESET / RESET pin is connected via an external pull-up resistor to VDD.

图7-4. Timing Diagram for TLV841MxxL Active Low Output (MR)

[Open-Drain and Push-Pull Output Topology]

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7.8 Typical Characteristics

Typical characteristics show the typical performance of the TLV841 device. Test conditions are T_A= 25°C,

V_DD= 3.3 V, R_pull-up= 100 kΩ, C_Load= 50 pF, unless otherwise noted.

0.8

0.6

0.4

0.2

-40^oC

25^oC

125^oC

-40^oC

25^oC

125^oC

0.5

1.5

2.5

3.5

4.5

5.5

0.5

1.5

2.5

V_SENSE(V)

3.5

4.5 5 5.5

VDD (V)

图7-5. Supply Current vs Supply Voltage for

图7-6. SENSE Current vs V_SENSE

TLV841S

V_IT-= 0.505 V

1.2

0.4

-0.4

-1.2

-2

-50

-10

110

150

(°C) Temperature

图7-8. SENSE Glitch Immunity (V_IT-) vs Overdrive

图7-7. V_IT-Accuracy vs Temperature

V_IT-= 0.505 V

-50

-10

110

150

(°C) Temperature

图7-10. V_OLvs I_OL

图7-9. SENSE Delay (t_{D_HL}) vs Temperature

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8 Detailed Description

8.1 Overview

The TLV841 is a family of very small, accurate, nano-quiescent current voltage supervisors with fixed threshold

voltages. TLV841S features a separate SENSE pin for adjustable voltage threshold without losing accuracy,

TLV841C features a programable reset time delay using external capacitor, and TLV841M features an active-low

manual reset (MR). The TLV841 family provide ±0.5% typical monitor threshold accuracy with hysteresis and

glitch immunity.

The adjustable variant of TLV841S has an internal reference voltage of 0.505 V and can be used to accurately

monitor any voltage above 0.505 V within the recommended operating conditions. In addition to the adjustable

threshold variant, fixed negative threshold voltages (V_IT-) can be factory set from 0.8 V to 4.9 V in 100 mV steps.

TLV841 is available in a very small (0.73 mm x 0.73 mm) 4-pin BGA package.

8.2 Functional Block Diagram

VDD

R_MR

Push-pull

(TLV841xxPx)

VDD

(TLV841M)

RESET

LOGIC

TIMER

RESET (TLV841xxxL)

RESET (TLV841xxxH)

SENSE

(TLV841S)

–

ADJ

TLV841S

VDD

GND

Reference

VDD

Fixed

(TLV841M,

R_CT

TLV841C)

(TLV841C)

GND

8.3 Feature Description

8.3.1 Input Voltage (VDD)

For TLV841C and TLV841M, the VDD pin is monitored by the internal comparator to indicate when VDD falls

below the fixed threshold voltage. For TLV841S, the SENSE pin is monitored by the internal comparator. VDD

also functions as the supply for the internal bandgap, internal regulator, state machine, buffers and other control

logic blocks. Good design practice involve placing a 0.1 μF to 1 μF bypass capacitor at VDD input for noisy

applications to ensure enough charge is available for the device to power up correctly.

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8.3.1.1 VDD Hysteresis

The internal comparator has built-in hysteresis to avoid erroneous output reset release. If the voltage at the VDD

(TLV841C, TLV841M) pin falls below V_IT-the output reset is asserted. When the monitored voltage goes above

V_IT-plus hysteresis (V_HYS) the output reset is deasserted after t_Ddelay.

Hystersis Width

RESET

V_IT-

V_IT+

VDD

图8-1. Hysteresis Diagram

8.3.1.2 VDD Transient Immunity

The TLV841 is immune to quick voltage transients or excursion on VDD. Sensitivity to transients depends on

both pulse duration (t_{GI_VIT-}), specified in 节 7.6, and overdrive. Overdrive is defined by how much VDD deviates

from the specified threshold. Threshold overdrive is calculated as a percent of the threshold in question, as

shown in 方程式1.

Overdrive = | ((V_DD/ V_IT-) –1) × 100% |

(1)

VDD

V_IT+

V_IT-

Overdrive

Pulse

Duration

图8-2. Overdrive vs Pulse Duration

8.3.2 SENSE Input (TLV841S)

The SENSE input can vary from 0 V to 5.5 V, regardless of the device supply voltage used. The SENSE pin is

used to monitor a critical voltage rail or push-button input. If the voltage on this pin drops below V_IT-, then

RESET/RESET is asserted. When the voltage on the SENSE pin rises above the positive threshold voltage

V_IT-+ V_HYS, RESET/RESET deasserts after the user-defined RESET/RESET delay time. The internal

comparator has built-in hysteresis to ensure well-defined RESET/RESET assertions and deassertions even

when there are small changes on the voltage rail being monitored.

The TLV841 device is relatively immune to short transients on the SENSE pin. Glitch immunity (t_{GI_V}), specified

IT-

in 节 7.6, is dependent on threshold overdrive, as illustrated in 图 7-8. Although not required in most cases, for

noisy applications, good analog design practice is to place a 10 nF to 100 nF bypass capacitor at the SENSE

input to reduce sensitivity to transient voltages on the monitored signal.

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8.3.2.1 SENSE Hysteresis

The internal comparator has built-in hysteresis to avoid erroneous output reset release. If the voltage at the

SENSE (TLV841S) pin falls below V_IT-the output reset is asserted. When the monitored voltage goes above V_IT-

plus hysteresis (V_HYS) the output reset is deasserted after t_Ddelay.

Hystersis Width

RESET

V_IT-

V_IT+

V_SENSE

V_IT-

V_SENSE

图8-3. Hysteresis Diagram

8.3.2.2 Immunity to SENSE Pin Voltage Transients

The TLV841S is immune to short voltage transient spikes or excursion on the SENSE pin. To further improve the

noise immunity on the SENSE pin, placing a 10 nF to 100 nF capacitor between the SENSE pin and GND can

reduce the sensitivity to sensitivity to transient voltages on the monitored signal.

Sensitivity to transients depends on both transient duration and overdrive (amplitude) on the transient voltage.

Overdrive is defined by how much V_SENSEexceeds the specified threshold and is important to know because the

smaller the overdrive, the slower the resonse of the output. Threshold overdrive is calculated as a percent of the

threshold in question, as shown in 方程式2.

Overdrive = | ((V_SENSE/ V_IT-) –1) × 100% |

(2)

V_SENSE

V_{IT- +}V_HYS

V_IT-

Overdrive

Pulse

Duration

图8-4. Overdrive vs Pulse Duration

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8.3.3 User-Programmable Reset Time Delay for TLV841C only

The reset time delay can be set to a typical value of 40 µs by leaving the CT pin floating, or a maximum value of

approximately 6.2 seconds by connecting 10 µF delay capacitor. The reset time delay (t_D) can be programmed

by connecting a capacitor no larger than 10 µF between the CT pin and GND.

The relationship between external capacitor (C_{CT_EXT (typ)}) in µF at CT pin and the time delay (t_{D (typ)}) in seconds

is given by 方程式3.

t_{D (typ)}= -ln (0.29) x R_{CT (typ)}x C_{CT_EXT (typ)}+ t_{D (no cap, typ)}

(3)

(4)

(5)

方程式3 is simplified to 方程式4 by plugging R_{CT (typ)}and t_{D (no cap, typ)}given in 节7.5 and 节7.6:

t_{D (typ)}= 618937 x C_{CT_EXT (typ)}+ 40 µs

方程式5 solves for external capacitor value C_{CT_EXT}in units of µF where t_{D (typ)}is in units of seconds

C_{CT_EXT}= (t_{D (typ)}- 40 µs) ÷ 618937

The reset delay varies according to three variables: the external capacitor C_{CT_EXT}, CT pin internal resistance

_CTprovided in 节7.5, and a constant. The maximum variance due to the constant is show in 方程式6:

t_{D (max)}= -ln (0.25) x R_{CT (max)}x C_{CT_EXT (max)}+ t_{D (no cap, max)}

(6)

The recommended maximum delay capacitor for the TLV841C is limited to 10 μF as this ensures enough time

for the capacitor to fully discharge when a voltage fault occurs. Also, having a too large of a capacitor value can

cause very slow charge up (rise times) and system noise can cause the the internal circuit to trip earlier or later

near the threshold. This leads to variation in time delay where it can make the delay accuracy worse in the

presence of system noise.

When a voltage fault occurs, the previously charged up capacitor discharges and if the monitored voltage returns

from the fault condition before the delay capacitor discharges completely, the delay will be shorter than

expected. The capacitor will begin charging from a voltage above zero and resulting in shorter than expected

time delay. A larger delay capacitor can be used so long as the capacitor has enough time to fully discharge

during the duration of the voltage fault. The amount of time required to discharge the delay capacitor relative to

the reset delay rises as VDD fault undervoltage increases as shown in 图 8-5. From the graph below, to ensure

the C_{CT_EXT}capacitor is fully discharged, the time period or duration of the voltage fault needs to be greater than

10% of the programmed reset time delay.

25°C

0.6

0.8

1.2

1.4

VDD Fault Underoltage (V)

1.6

1.8

CTR_

图8-5. C_{CT_EXT}Discharge Time During Fault Condition (C_{CT_EXT}= 1 µF)

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8.3.4 Manual Reset (MR) Input for TLV841M only

The manual reset (MR) input allows a processor GPIO or other logic circuits to initiate a reset. A logic low on MR

with pulse duration longer than t_{MR_RES}will causes reset output to assert. After MR returns to a logic high

(V_{MR_H}) and VDD is above V_IT+, reset is deasserted after the user programmed reset time delay (t_D) expires.

If MR is not controlled externally, then MR can be left disconnected. If the logic signal controlling MR is less than

VDD, then additional current flows from VDD into MR internally. For minimum current consumption, drive MR to

either VDD or GND. V_MRshould not be higher than VDD voltage.

V_IT+

V_HYS

V_IT-

V_IT+

V_HYS

V_IT-

VDD

t_{P_HL}

t_D

t_{MR_tD}

RESET

(2)

t_{MR_RES}

V_{MR_H}

V_{MR_L}

(1)

t_{MR_PW}

(1) MR pulse width too small to assert RESET

(2) MR voltage not low enough to assert RESET

Time

图8-6. Timing Diagram MR and RESET (TLV841M)

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8.3.5 Output Logic

8.3.5.1 RESET Output, Active-Low

RESET (Active-Low) applies to TLV841xxDL (Open-Drain) and TLV841xxPL (Push-Pull) hence the "L" in the

device name. RESET remains high (deasserted) as long as VDD/SENSE is above the negative threshold (V_IT-)

and the MR pin is floating or above V_{MR_H}. If VDD/SENSE falls below the negative threshold (V_IT-) or if MR is

driven low, then RESET is asserted.

When MR is again logic high or floating and VDD/SENSE rise above V_IT+(V_IT-+ V_HYS), the delay circuit will hold

RESET low for the specified reset time delay (t_D). When the reset time delay has elapsed, the RESET pin goes

back to logic high voltage V_OH

The TLV841xxDL (Open-Drain) version, denoted with "D" in the device name, requires an external pull-up

resistor to hold RESET pin high. Connect the external pull-up resistor to the desired pull-up voltage source and

RESET can be pulled up to any voltage up to 5.5 V independent of the VDD voltage. To ensure proper voltage

levels, give some consideration when choosing the external pull-up resistor values. The external pull-up resistor

value determines the actual V_OL, the output capacitive loading, and the output leakage current (I_lkg(OD)).

The Push-Pull variant (TLV841xxPL), denoted with "P" in the device name, does not require an external pull-up

resistor

8.3.5.2 RESET Output, Active-High

RESET (active-high), denoted with no bar above the pin label, applies only to TLV841xxDH (open-drain) and

TLV841xxPH (push-pull) active-high version, hence the "H" in the device name. RESET remains low

(deasserted) as long as VDD/SENSE is above the threshold (V_IT-) and the manual reset signal ( MR) is floating

or above V_{MR_H}. If VDD/SENSE falls below the negative threshold (V_IT-) or if MR is driven low, then RESET is

asserted driving the RESET pin to high voltage V_OH

When MR is again logic high or floating and VDD/SENSE is above V_IT+(V_IT-+ V_HYS) the delay circuit will hold

RESET high for the specified reset time delay (t_D). When the reset time delay has elapsed, the RESET pin goes

back to low voltage V_OL

The TLV841xxDH (Open-Drain) version, denoted with "D" in the device name, requires an external pull-up

resistor to hold RESET pin high. Connect the external pull-up resistor to the desired pull-up voltage source and

RESET can be pulled up to any voltage up to 5.5 V independent of the VDD voltage. To ensure proper voltage

levels, give some consideration when choosing the external pull-up resistor values. The external pull-up resistor

value determines the actual V_OL, the output capacitive loading, and the output leakage current (I_lkg(OD)).

The Push-Pull variant (TLV841xxPH), denoted with "P" in the device name, does not require an external pull-up

resistor

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8.4 Device Functional Modes

表 8-1 and 表 8-2 summarizes the various functional modes of the device. Logic high is represented by "H" and

logic low is represented by "L".

表8-1. Truth Table for TLV841S

RESET

(ACTIVE-HIGH)

RESET

(ACTIVE-LOW)

VDD

SENSE

VDD < V_POR

V_POR< V_DD< V_DD(MIN)

VDD ≥V_DD(MIN)

Undefined

—

(1)

V_SENSE< V_IT-

V_SENSE> V_IT-+ V_HYS

VDD ≥V_DD(MIN)

(1) When V_DDfalls below V_DD(MIN), undervoltage-lockout (UVLO) takes effect and RESET is held logic low (RESET is held logic high) until

V_DDfalls below V_PORat which the RESET/RESET output is undefined.

表8-2. Truth Table for TLV841M

RESET

(ACTIVE-HIGH)

RESET

(ACTIVE-LOW)

VDD

VDD < V_POR

V_POR< V_DD< V_IT-

VDD ≥V_IT-

Undefined

—

VDD ≥V_IT-

Floating

VDD ≥V_IT-

8.4.1 Normal Operation (V_DD> V_POR

)

When VDD is greater than V_POR, the reset signal is determined by the voltage on the VDD pin with respect to the

trip point (V_IT-)

• MR high: The reset signal corresponds to VDD with respect to the threshold voltage.

• MR low: In this mode, the reset is asserted regardless of the threshold voltage.

8.4.2 Below Power-On-Reset (V_DD< V_POR

)

When the voltage on VDD is lower than V_POR, the device does not have enough bias voltage to internally pull the

asserted output low or high and reset voltage level is undefined.

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The following sections describe in detail how to properly use this device, depending on the requirements of the

final application.

9.2 Typical Application

Design 1: Adjustable Voltage Supervisor with Push-Button Functionality

A typical application for the TLV841S is voltage rail monitoring with push-button functionality. In this design

application, the TLV841SADL01 is being used to monitor a 3.3 V power rail and will trigger a reset when the

voltage drops below 2.90 V or when the push-button is pressed. The reset output connects to an MCU for

system resetting or servicing the push-button.

3.3V

0.1 µF

R_pull-up

47.5 k

30.1 k

VDD

SENSE

TLV841SADL01

GND

RESET

Push-button

input

10k

0.1µF

图9-1. Design 1 - Adjustable Voltage Supervisor with Push-Button Functionality Circuit

9.2.1 Design Requirements

The design requirements, described in 表 9-1, for this design has a defined reset threshold voltage of 2.90 V, a

reset delay of 40 μs and an output current no larger than 150 µA.

表9-1. Design Requirements

PARAMETER

Reset Asserting

DESIGN REQUIREMENTS

DESIGN RESULTS

Reset needs to assert when under the reset

Reset asserted when under the reset condition of a

condition of a button press or VDD ≤2.90 V.

button pressed or VDD ≤2.90 V.

Reset Asserting Timing

Output Current

Reset output needs to assert when the reset

conditions are met for 20 μs, and needs to de-

assert after 40 μs of no reset conditions.

Reset output asserted when the reset conditions

were met for 26.4 μs and deasserted after 46.8 μs

of no reset conditions.

The output current must not exceed 150 µA.

The output current was 110 µA under the reset

condition.

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9.2.2 Detailed Design Procedure

The TLV841SADL01 can monitor any voltage above 0.505 V using an external voltage divider. This device has a

negative going input threshold voltage of 0.505 V; however, the design needs to assert a reset when VDD drops

below 2.90 V. By using a resistor divider (R1 = 47.5 kΩ, R2 = 10 kΩ) the negative going threshold voltage

becomes 2.90 V. The device's positive going voltage threshold is V_IT-+ V_HYS. The typical V_HYSis 25 mV. This in

combination with the resistor divider makes the design's positive going threshold voltage equal to 3.05 V. If VDD

falls below 2.90 V, RESET will assert. If VDD rises above 3.05 V, RESET will deassert. See 图 9-2 for a timing

diagram detailing the voltage levels and reset assertion/deassertion conditions.

3.3 V

V_IT-+ V_HYS= 3.05V

V_IT-= 2.90V

Push-bu on

input

SENSE

t_D

t_D-HL

RESET

图9-2. Design 1 Timing Diagram

This design will also enter a reset condition when the "push-button input" is asserted. The push-button is tied to

ground and when pressed will drop the SENSE voltage to 0 V, making the device assert a reset. As a good

analog practice, a 0.1 µF capacitor was also placed on VDD.

The desired reset timing conditions are sense propagation delay time (t_{P_HL}of 25 μs (how long it takes to assert

RESET) and a reset delay time of 40 μs (how long it takes to deassert RESET). 图 9-3 and 图 9-4 are the

results of the described application where the measured propagation delay and reset delay time are shown

respectively.

For the requirement of a maximum output current, an external pull-up resistor needs to be selected so that the

current through the external pull-up resistor exceeds no more than 150 µA. When the reset output is low, the

voltage drop across the external pull-up resistor is equal to VDD. Ohm’s law is used to calculate the minimum

resistor value. The resistor needs to be greater than 22 kΩ in order to pull less than 150 µA in the reset asserted

low condition. A resistor value of 30.1 kΩ was selected to accomplish this.

Note that this design does not account for tolerances.

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9.2.3 Application Curves: TLV841EVM

These application curves are taken with the TLV841SADL01 part on the TLV841EVM. Please see the TLV841

User Guide for more information.

RESET

Propaga on Detect Delay (t_{P_HL}) = 26.4

Reset Delay (t_D) = 46.8 s

VDD

图9-4. TLV841EVM RESET Time Delay (t_D)

图9-3. TLV841EVM Propagation Delay Time Delay

(t_{D_HL}

)

VDD / SENSE

RESET

Glitch Immunity Overdrive > 5%

Glitch Immunity V_IT-(t_{GI_VIT-}) = 10

图9-5. TLV841EVM SENSE Pin Glitch Immunity (t_{GI_VIT-}

)

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10 Power Supply Recommendations

These devices are designed to operate from an input supply with a voltage range between 0.7 V and 5.5 V. TI

recommends an input supply capacitor of 0.1 μF between the VDD pin and GND pin. This device has a 6 V

absolute maximum rating on the VDD pin. If the voltage supply providing power to VDD is susceptible to any

large voltage transient that can exceed 6 V, additional precautions must be taken.

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11 Layout

11.1 Layout Guidelines

Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends

placing a minimum 0.1 µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected

to the CT pin (TLV841C), then minimize parasitic capacitance on this pin so the rest time delay is not adversely

affected.

• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a

greater than 0.1 µF ceramic capacitor as near as possible to the VDD pin.

• If a C_{CT_EXT}capacitor is used (TLV841C), place the capacitor as close as possible to the CT pin. If the CT pin

is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin to less than 5 pF.

• If a SENSE capacitor (C_SENSE) is used (TLV841S), place the capacitor as close as possible to the SENSE pin

to further improve the noise immunity on the SENSE pin. Placing a 10 nF to 100 nF capacitor between the

SENSE pin and GND can reduce the sensitivity to sensitivity to transient voltages on the monitored signal.

• Place the pull-up resistors on RESET pin as close to the pin as possible.

11.2 Layout Example

The layout example in 图 11-1 shows how the TLV841S is laid out on a printed circuit board (PCB) for every

device variant.

Pull-up resistor required for Open-Drain output

(TLV841xxDx)

R_pull-up

RESET (TLV841xxxL)

RESET (TLV841xxxH)

VDD

C_IN

SENSE (TLV841S)

MR (TLV841M)

GND

CT (TLV841C) or

C_SENSE(TLV841S)

图11-1. TLV841 Recommended Layout

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12 Device and Documentation Support

12.1 Device Nomenclature

图5-1 in 节5 and 表12-1 shows how to decode the function of the device based on its part number.

表12-1. Device Naming Convention

DESCRIPTION

Generic Part number

NOMENCLATURE

VALUE

TLV841

Feature Option

SENSE pin option

CT pin for programmable delay using

external capacitor

Manual Reset (MR) pin option

40 µs (No internal reset time delay)

2 ms reset time delay

Delay Option

10 ms reset time delay

30 ms reset time delay

50 ms reset time delay

80 ms reset time delay

100 ms reset time delay

150 ms reset time delay

200 ms reset time delay

Open-Drain, Active-Low

Push-Pull, Active-Low

Open-Drain, Active-High

Push-Pull, Active-High

Example: 12 stands for 1.2 V threshold

DSBGA (4)

Variant code (Output Topology)

Detect Voltage Option

Package

## (two characters)

YBH

Reel

Large Reel

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12.2 Documentation Support

12.2.1 Related Documentation

The following related documents are available for download at www.ti.com:

• Optimizing Resistor Dividers at a Comparator Input, SLVA450

• Sensitivity Analysis for Power Supply Design, SLVA481

• Getting Started With TMS320C28x Digital Signal Controllers, SPRAAM0

• TLV841EVM-775 Evaluation Module User Guide, SBVU030

• C2000 Delfino Family of Microprocessors

• TMS320F2833x microcontroller, SPRS439

12.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TLV841SADL01YBHR

TLV841SADL41YBHR

ACTIVE

DSBGA

YBH

3000 RoHS & Green

SNAGCU

Level-1-260C-UNLIM

-40 to 125

Samples

SNAGCU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

27-Jan-2023

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

27-Jan-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV841SADL01YBHR

TLV841SADL41YBHR

DSBGA

YBH

3000

180.0

8.4

0.84

0.48

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

27-Jan-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV841SADL01YBHR

TLV841SADL41YBHR

DSBGA

YBH

3000

182.0

20.0

Pack Materials-Page 2

PACKAGE OUTLINE

YBH0004

DSBGA - 0.4 mm max height

SCALE 12.000

DIE SIZE BALL GRID ARRAY

BALL A1

CORNER

0.4 MAX

SEATING PLANE

0.05 C

0.16

0.10

BALL TYP

0.4

TYP

SYMM

D: Max = 0.761 mm, Min =0.701 mm

E: Max = 0.761 mm, Min =0.701 mm

0.4

TYP

0.225

0.185

0.015

SYMM

C A B

4224051/A 11/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

YBH0004

DSBGA - 0.4 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

4X ( 0.2)

SYMM

(0.4) TYP

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 50X

0.05 MIN

0.05 MAX

METAL UNDER

SOLDER MASK

(

0.2)

METAL

(

0.2)

EXPOSED

METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

(PREFERRED)

NON-SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4224051/A 11/2017

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

YBH0004

DSBGA - 0.4 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

(R0.05) TYP

4X ( 0.21)

SYMM

(0.4) TYP

METAL

TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.075 mm THICK STENCIL

SCALE: 50X

4224051/A 11/2017

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TLV841SADL01YBHR [TI]

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