TLVM13630RDHR [TI]
高密度 3V 至 36V 输入、1V 至 6V 输出、3A 降压电源模块 | RDH | 30 | -40 to 125;
| 型号： | TLVM13630RDHR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 高密度 3V 至 36V 输入、1V 至 6V 输出、3A 降压电源模块 | RDH | 30 | -40 to 125 电源电路 |
| 文件： | 总42页 (文件大小：3768K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLVM13630
ZHCSLL8B –MAY 2021 –REVISED JANUARY 2022
TLVM13630 高密度、3V 至36V 输入、1V 至6V 输出、3A 电源模块采用增强型
HotRod™ QFN 封装
1 特性
3 说明
• 多功能同步降压直流/直流模块
TLVM13630 同步降压电源模块是一款高度集成的
36V、3A 直流/直流解决方案， 集成了多个功率
MOSFET、一个屏蔽式电感器和多个无源器件，并采
用增强型 HotRod™ QFN 封装。该模块的 VIN 和
VOUT 引脚位于封装的边角处，可优化输入和输出电
容器在布局中的放置。模块下方具有四个较大的散热焊
盘，可在制造过程中实现简单布局和轻松处理。
– 集成MOSFET、电感器和控制器
– 3 V 至36 V 的宽输入电压范围
– 可调节输出电压范围为1V 至6V，在整个温度
范围具有1% 的设定点精度
– 4mm × 6mm × 1.8mm 超模压塑料封装
– –40°C 至125°C 结温范围
– 可在200kHz 至2.2MHz 范围内调节频率
– 负输出电压应用功能
TLVM13630 具有 1V 到 6V 的输出电压，旨在快速、
轻松实现小尺寸 PCB 的低EMI 设计。总体解决方案仅
需四个外部元件，并且省去了设计流程中的磁性和补偿
元件选择过程。
• 在整个负载范围内具有超高效率
– 12VIN、5VOUT、1MHz 时峰值效率为93%
– 具有用于提升效率的外部偏置选项
– 关断时的静态电流为0.6µA（典型值）
– 3A 负载下的典型压降为0.4V
尽管针对空间受限型应用采用了简易的小尺寸设计，
TLVM13630 模块提供了许多特性，可实现稳健的性
能：具有迟滞功能的精密使能端可实现输入电压 UVLO
调节、集成 VCC、自举和输入电容器以提高可靠性和
密度、全负载电流范围内恒定开关频率以提高负载瞬态
性能、 负输出电压能力以用于反相应用、以及
PGOOD 指示器可实现时序控制、故障保护和输出电压
监控。
• 超低的传导和辐射EMI 信号
– 具有双输入路径和集成电容器的低噪声封装可降
低开关振铃
– 恒定频率FPWM 运行模式
– 符合CISPR 11 和32 B 类发射要求
• 适用于可扩展电源
– 与TLVM13620（36V、2A）引脚兼容
• 固有保护特性，可实现稳健设计
器件信息
器件型号(1)
封装尺寸（标称值）
封装
– 精密使能输入和漏极开路PGOOD 指示器（用
于时序、控制和VIN UVLO）
– 断续模式过流保护
TLVM13630
B0QFN (30)
4.0mm × 6.0mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 具有迟滞功能的热关断保护
• 使用TLVM13630 并借助WEBENCH® Power
空白
Designer 创建定制设计方案
2 应用
• 测试和测量以及航天和国防
• 工厂自动化和控制
• 降压和反相降压/升压电源
100
95
90
85
80
75
VIN = 3 V...36 V
VIN
CIN
PGND
TLVM13630
VOUT = 5 V
VOUT = 5 V
fSW = 1 MHz
70
VLDOIN
EN
IOUT(max) = 3 A
65
VOUT
60
PG
VIN = 12 V
VIN = 24 V
VIN = 36 V
RFBT
55
50
COUT
VCC
RT
FB
0.0
0.5
1.0
1.5
Output Current (A)
2.0
2.5
3.0
RFBB
CVCC
RRT
AGND
典型效率（VOUT = 5V, FSW = 1MHz）
* VOUT enters dropout
if VIN < 5.4 V
典型电路原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSFT6
TLVM13630
ZHCSLL8B –MAY 2021 –REVISED JANUARY 2022
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................22
8 Applications and Implementation................................23
8.1 Application Information............................................. 23
8.2 Typical Applications.................................................. 23
9 Power Supply Recommendations................................33
10 Layout...........................................................................34
10.1 Layout Guidelines................................................... 34
10.2 Layout Example...................................................... 34
11 Device and Documentation Support..........................35
11.1 Device Support........................................................35
11.2 Documentation Support.......................................... 36
11.3 接收文档更新通知................................................... 36
11.4 支持资源..................................................................36
11.5 Trademarks............................................................. 36
11.6 Electrostatic Discharge Caution..............................36
11.7 术语表..................................................................... 36
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................7
6.6 System Characteristics............................................... 9
6.7 Typical Characteristics..............................................10
6.8 Typical Characteristics: VIN = 12 V............................11
6.9 Typical Characteristics: VIN = 24 V........................... 12
6.10 Typical Characteristics: VIN = 36 V......................... 13
7 Detailed Description......................................................14
7.1 Overview...................................................................14
7.2 Functional Block Diagram.........................................14
Information.................................................................... 37
4 Revision History
Changes from Revision * (March 2021) to Revision A (January 2022)
Page
• 将文档状态从“预告信息”更改为“量产数据”................................................................................................ 1
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Device Comparison Table
DEVICE
ORDERABLE PART
MODE
SPREAD
SPECTRUM
OUTPUT
VOLTAGE
EXTERNAL
SYNC
JUNCTION
TEMPERATURE
NUMBER
TLVM13630
TLVM13630RDHR
FPWM
No
Adjustable
No
–40°C to 125°C
5 Pin Configuration and Functions
RT
1
2
21 DNC
20 DNC
27
AGND
EN
VIN
VIN
3
4
5
6
19 VIN
18 VIN
17 PGND
28
PGND
PGND
PGND
29
PGND
16 PGND
15 VOUT
14 VOUT
VOUT
VOUT
7
8
30
VOUT
图5-1. 30-Pin QFN, RDH Package (Top View)
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表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
Frequency setting pin. This analog pin is used to set the switching frequency between 200 kHz and
2.2 MHz by placing an external resistor from this pin to AGND. Do not leave open or connect to
ground.
1
RT
I
I
Precision enable input pin. High = on, low = off. Can be connected to VIN. Precision enable allows
the pin to be used as an adjustable UVLO. Place an external voltage divider between this pin, AGND,
and VIN to create an external UVLO.
2
EN
VIN
Input supply voltage. Connect the input supply to these pins. Connect input capacitors between these
pins and PGND in close proximity to the device. Refer to 节10.2 for input capacitor placement
example.
3, 4, 18, 19
P
G
Power ground. This is the return current path for the power stage of the device. Connect this pad to
the input supply return, the load return, and the capacitors associated with the VIN and VOUT pins.
See 节10.2 for a recommended layout.
5, 6, 16, 17,
28, 29
PGND
Output voltage. These pins are connected to the internal output inductor. Connect these pins to the
output load and connect external output capacitors between these pins and PGND.
7-10, 12–
15, 30
VOUT
SW
P
O
Switch node. Do not place any external component on this pin or connect to any signal. The amount
of copper placed on these pins must be kept to a minimum to prevent issues with noise and EMI.
11
Do Not Connect. Do not connect these pins to ground, to another DNC pin, or to any other voltage.
These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.
20,21
DNC
–
Optional LDO supply input. Connect to VOUT or to other voltage rail to improve efficiency. Connect
an optional high quality 0.1-μF to 1-μF capacitor from this pin to ground for improved noise
immunity. Do not connect to a voltage above 12 V or to a voltage greater than VIN. If unused, connect
this pin to ground..
22
VLDOIN
P
Internal LDO output. Used as supply to internal control circuits. Do not connect to any external loads.
Connect a high-quality 1-μF ceramic capacitor from this pin to PGND.
23
VCC
O
G
Analog ground. Zero voltage reference for internal references and logic. All electrical parameters are
measured with respect to this pin. This pin must be connected to PGND at a single point. See 节
10.2 for a recommended layout.
24, 27
AGND
Feedback input. For the adjustable output version, connect the mid-point of the feedback resistor
divider to this pin. Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired
point of regulation. Connect the lower resistor (RFBB) of the feedback divider to AGND. When
connecting with feedback resistor divider, keep this FB trace short and as small as possible to avoid
noise coupling. See 节10.2 for a feedback resistor placement.
25
26
FB
I
Power-good monitor. Open-drain output that asserts low if the feedback voltage is not within the
specified window thresholds. A 10-kΩto 100-kΩpullup resistor is required to a suitable pullup
voltage. If not used, this pin can be left open or connected to PGND.
PG
O
(1) P = Power, G = Ground, I = Input, O = Output
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6 Specifications
6.1 Absolute Maximum Ratings
Limits apply over TJ = –40°C to 125°C (unless otherwise noted). (1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
0
MAX
40
UNIT
V
VIN to AGND, PGND
VLDOIN to AGND, PGND
EN to AGND, PGND
16
V
40
V
Input voltage
RT to AGND, PGND
FB to AGND, PGND
PG to AGND, PGND
PGND to AGND
5.5
16
V
V
20
V
2
V
–1
VCC to AGND, PGND
SW to AGND, PGND(2)
VOUT to AGND, PGND
PG
5.5
40
V
–0.3
–0.3
–0.3
–
Output voltage
V
6
V
Input current
10
mA
°C
°C
°C
°C
TJ
Junction temperature
Ambient temperature
Storage temperature
125
105
150
260
3
–40
–40
–55
TA
Tstg
Peak reflow case temperature
Maximum number of reflows allowed
Mechanical shock
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
Mil-STD-883D, Method 2007.2, 20 to 2000 Hz
1500
20
G
G
Mechanical vibration
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) A voltage of 2 V below PGND and 2 V above VIN can appear on this pin for ≤200 ns with a duty cycle of ≤0.01%.
6.2 ESD Ratings
VALUE
±2500
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002 (2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
Limits apply over TJ = –40°C to 125°C (unless otherwise noted).
MIN
NOM
MAX
UNIT
V
Input voltage
Input voltage
Output voltage
Output current
Frequency
Input current
Output voltage
TJ
VIN (Input voltage range after start-up)
3
36
12
VLDOIN
V
VOUT(1)
1
0
6
V
IOUT(2)
3
A
FSW set by RT
200
2200
2
kHz
mA
V
PG
PG
0
–40
–40
16
Operating junction temperature
Operating ambient temperature
125
105
°C
°C
TA
(1) Under no conditions should the output voltage be allowed to fall below 0 V.
(2) Maximum continuous DC current may be derated when operating with high switching frequency, high ambient temperature, or both.
Refer to the Typical Characteristics section for details.
6.4 Thermal Information
TLVM13630
THERMAL METRIC(1)
RDH (QFN)
30 PINS
29.1
UNIT
RθJA
RθJA
ψJT
Junction-to-ambient thermal resistance (TPSM63603 EVM)
Junction-to-ambient thermal resistance(2)
°C/W
°C/W
°C/W
°C/W
33.5
Junction-to-top characterization parameter(3)
Junction-to-board characterization parameter(4)
4.1
21.5
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 64-mm x 83-mm four-layer PCB with 2 oz.
copper and natural convection cooling. Additional airflow and PCB copper area reduces RθJA. For more information see the Layout
section.
(3) The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TT is
the temperature of the top of the device.
(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TB is
the temperature of the board 1mm from the device.
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6.5 Electrical Characteristics
Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, VLDOIN = 5 V, FSW = 800 kHz (unless otherwise noted).
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
Needed to start up (over IOUT range)
Once operating (over IOUT range)
3.95
3
36
36
V
V
VIN
Input operating voltage range
VIN_HYS
IQ_VIN
Hysteresis(1)
1.0
4
V
Input operating quiescent current (non-switching)
VIN shutdown quiescent current
TA = 25°C, VEN = 3.3 V, VFB = 1.5 V
VEN = 0 V, TA = 25°C
µA
µA
ISDN_VIN
ENABLE
VEN_RISE
VEN_FALL
VEN_HYS
VEN_WAKE
IEN
3
EN voltage rising threshold
EN voltage falling threshold
EN voltage hysteresis
1.161
1.263
0.91
1.365
0.404
V
V
0.275
0.4
0.353
V
EN wake-up threshold
V
Input current into EN (non-switching)
EN HIGH to start of switching delay(1)
VEN = 3.3 V, VFB = 1.5 V
1.65
0.7
µA
ms
tEN
INTERNAL LDO VCC
3.3
3.1
3.6
3.6
1.1
V
V
V
V
V
3.4 V ≤VLDOIN ≤12.5 V
VLDOIN = 3.1 V, non-switching
VLDOIN < 3.1 V(1)
VCC
Internal LDO VCC output voltage
VCC_UVLO
VCC UVLO rising threshold
VIN < 3.6 V(2)
VCC_UVLO_HYS VCC UVLO hysteresis(2)
Hysteresis below VCC_UVLO
Input current into the VLDOIN pin (non-switching,
IVLDOIN
VEN = 3.3 V, VFB = 1.5 V
25
31.2
6
µA
maximum at TA = 125℃)(3)
FEEDBACK
VOUT
Adjustable output voltage range
Feedback voltage
Over the IOUT range
TA = 25°C, IOUT = 0 A
1
V
V
VFB
1.0
Over the VIN range, VOUT = 1 V, IOUT = 0
A, FSW = 200 kHz
VFB_ACC
VFB
Feedback voltage accuracy
Load regulation
+1%
–1%
0.1%
0.1%
10
TA = 25°C, 0 A ≤IOUT ≤3 A
TA = 25°C, IOUT = 0 A, 4.0 V ≤VIN ≤36
V
VFB
Line regulation
IFB
Input current into the FB pin
VFB = 1.0 V
nA
CURRENT
IOUT
Output current
TA = 25°C
0
3.0
A
A
A
A
A
IOCL
Output overcurrent (DC) limit threshold
High-side switch current limit
Low-side switch current limit
Negative current limit
4.9
6.2
3.4
–3
IL_HS
Duty cycle approaches 0%
5.6
2.9
6.8
3.8
IL_LS
IL_NEG
Ratio of FB voltage to in-regulation FB voltage to
enter hiccup
VHICCUP
tW
Not during soft start
40%
80
Short circuit wait time ("hiccup" time before soft start)
ms
(1)
SOFT START
tSS
Time from first SW pulse to VREF at 90%
3.5
9.5
5
7
ms
ms
VIN ≥4.2 V
VIN ≥4.2 V
Time from first SW pulse to release of FPWM lockout
if output not in regulation(1)
tSS2
13
17
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6.5 Electrical Characteristics (continued)
Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, VLDOIN = 5 V, FSW = 800 kHz (unless otherwise noted).
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD
PGOV
% of VOUT setting
105%
92%
107%
94%
110%
PG upper threshold –rising
PGUV
% of VOUT setting
96.5%
PG lower threshold –falling
PGHYS
PG upper threshold hysteresis (rising and falling)
Input voltage for valid PG output
Low level PG function output voltage
% of VOUT setting
1.3%
VIN_PG_VALID
VPG_LOW
1.0
1.5
V
V
46-μA pullup, VEN = 0 V
2-mA pullup to the PG pin, VEN = 3.3 V
0.4
2.5
Input current into PG pin when open-drain output is
high
IPG
IOV
VPG = 3.3 V
10
nA
Pulldown current at the SW node under overvoltage
condition
0.5
mA
tPG_FLT_RISE
tPG_FLT_FALL
Delay time to PG high signal
2.0
ms
µs
Glitch filter time constant for PG function
120
SWITCHING FREQUENCY
fSW_RANGE Switching frequency range by RT or SYNC
fSW_RT1
200
180
2200
220
kHz
kHz
kHz
Default switching frequency by RT
Default switching frequency by RT
200
RRT = 66.5 kΩ
fSW_RT2
1980
2200
2420
VIN = 12 V, RRT = 5.76 kΩ
SYNCHRONIZATION
tB
Blanking of EN after rising or falling edges(1)
4
28
µs
ns
Enable sync signal hold time after edge for
edge recognition(1)
tSYNC_EDGE
POWER STAGE
VBOOT_UVLO
100
Voltage on CBOOT pin compared to SW which will
turn off the high-side switch
2.1
V
tON_MIN
tON_MAX
tOFF_MIN
Minimum ON pulse width(1)
Maximum ON pulse width(1)
Minimum OFF pulse width
VOUT = 1 V, IOUT = 1 A
VIN = 4 V, IOUT = 1 A
Temperature rising
55
9
70
85
ns
µs
ns
65
THERMAL SHUTDOWN
TSDN
Thermal shutdown threshold (1)
Thermal shutdown hysteresis (1)
158
168
10
180
°C
°C
THYST
(1) Parameter specified by design, statistical analysis and production testing of correlated parameters. Not production tested.
(2) Production tested with VIN = 3 V
(3) This is the current used by the device while not switching, open loop, with FB pulled to +5% of nominal. It does not represent the total
input current to the system while regulating. For additional information, reference the System Characteristics and the Input Supply
Current section.
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6.6 System Characteristics
The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the
typical (TYP) column apply to TJ = 25°C only. These specifications are not ensured by production testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
Input supply current when in
regulation
VIN = 24 V, VOUT = 3.3 V, VEN = VIN, VVLDOIN = VOUT, FSW = 800 kHz,
IOUT = 0 A
IIN
10
mA
OUTPUT VOLTAGE
VFB
VFB
Load regulation
VOUT = 3.3 V, VIN = 24 V, IOUT = 0.1 A to full load
VOUT = 3.3 V, VIN = 4 V to 36 V, IOUT = 3 A
1
6
mV
mV
Line regulation
Load transient
VOUT = 3.3 V, VIN = 24 V, IOUT = 1 A to 2.5 A at 2 A/μs,
COUT(derated) = 49 μF
VOUT
50
mV
EFFICIENCY
VOUT = 3.3 V, VIN = 12 V, IOUT = 2.5 A, VLDOIN = VOUT, FSW = 800 kHz
VOUT = 3.3 V, VIN = 24 V, IOUT = 2.5 A, VLDOIN = VOUT, FSW = 800 kHz
VOUT = 5 V, VIN = 24 V, IOUT = 2.5 A, VLDOIN = VOUT, FSW = 1 MHz
VOUT = 5 V, VIN = 36 V, IOUT = 2.5 A, VLDOIN = VOUT, FSW = 1 MHz
VOUT = 12 V, VIN = 24 V, IOUT = 1.5 A, VLDOIN = VOUT, FSW = 2 MHz
89.5%
87.5%
91%
Efficiency
η
88.1%
94.1%
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6.7 Typical Characteristics
VIN = 24 V, unless otherwise specified.
1.01
1.005
1
4
TJ = -40C
TJ = 25C
TJ = 125C
3
2
1
0
0.995
0.99
-50
-25
0
25
50
75
100
125
Junction Temperature (°C)
0
6
12
18
24
30
36
Input Voltage (V)
VEN = 0 V
图6-2. Feedback Voltage
图6-1. Shutdown Supply Current
70
70
60
50
40
30
20
10
60
50
40
30
20
10
0
High-side MOSFET
Low-side MOSFET
200 400 600 800 1000 1200 1400 1600 1800 2000 2200
Frequency (kHz)
-50
-25
0
25
50
75
100
125
Junction Temperature (°C)
图6-3. Switching Frequency Set by RT Resistor
图6-4. High-Side and Low-Side MOSFET RDS(on)
1.4
115
110
105
100
95
1.2
1
0.8
0.6
90
0.4
OV Tripping
OV Recovery
UV Recovery
UV Tripping
VEN Rising
VEN Falling
VEN_WAKE Rising
VEN_WAKE Falling
85
0.2
80
-50
0
-50
-25
0
25
50
75
100 125
-25
0
25
50
75
100
125
Junction Temperature (°C)
Junction Temperature (°C)
图6-6. Power-Good (PG) Thresholds
图6-5. Enable Thresholds
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6.8 Typical Characteristics: VIN = 12 V
Refer to 节8.2 for circuit designs.
100
95
90
85
80
75
70
65
60
55
1.5
1.2
0.9
0.6
0.3
0.0
VOUT, FSW
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.5 V, 750 kHz
1.8 V, 600 kHz
VOUT, FSW
50
45
40
35
30
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.5 V, 750 kHz
1.8 V, 600 kHz
0
0.5
1
1.5
Output Current (A)
2
2.5
3
0
0.5
1
1.5
Output Current (A)
2
2.5
3
VLDOIN = VOUT
VLDOIN = VOUT
图6-7. Efficiency
图6-8. Power Dissipation
115
105
95
22
VOUT, FSW
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.5 V, 750 kHz
1.8 V, 600 kHz
20
18
16
14
12
10
8
85
75
65
55
45
Airflow
400LFM
200LFM
100LFM
Nat conv
35
25
6
0
0.5
1
1.5
Output Current (A)
2
2.5
3
0
0.5
1
1.5
Output Current (A)
2
2.5
3
Device soldered to a 64-mm × 83-mm, 4-layer PCB
COUT = 2 × 47-µF ceramic, 25-V, 1206 case size
图6-10. Safe Operating Area
VOUT = 1.8 V, FSW = 600 kHz
图6-9. Output Voltage Ripple
115
105
95
115
105
95
85
85
75
75
65
65
55
55
45
Airflow
45
Airflow
400LFM
200LFM
100LFM
Nat conv
400LFM
200LFM
100LFM
Nat conv
35
35
25
25
0
0.5
1
1.5
Output Current (A)
2
2.5
3
0
0.5
1
1.5
Output Current (A)
2
2.5
3
Device soldered to a 64-mm × 83-mm, 4-layer PCB
Device soldered to a 64-mm × 83-mm, 4-layer PCB
图6-11. Safe Operating Area
图6-12. Safe Operating Area
VOUT = 3.3 V, FSW = 800 kHz
VOUT = 5.0 V, FSW = 1 MHz
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6.9 Typical Characteristics: VIN = 24 V
Refer to 节8.2 for circuit designs.
100
95
90
85
80
75
70
65
60
55
50
2.5
2.0
1.5
1.0
0.5
0.0
VOUT, FSW
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.5 V, 750 kHz
VOUT, FSW
45
40
35
30
5 V, 1.0 MHz
3.3 V, 800 kHz
2.5 V, 750 kHz
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
Output Current (A)
Output Current (A)
VLDOIN = VOUT
VLDOIN = VOUT
图6-13. Efficiency
图6-14. Power Dissipation
115
105
95
35
VOUT, FSW
32
29
26
23
20
17
14
11
8
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.5 V, 750 kHz
85
75
65
55
45
Airflow
400LFM
200LFM
100LFM
Nat conv
35
25
0
0.5
1
1.5
Output Current (A)
2
2.5
3
0
0.5
1
1.5
2
2.5
3
Output Current (A)
Device soldered to a 64-mm × 83-mm, 4-layer PCB
COUT = 2 × 47-µF ceramic, 25-V, 1206 case size
图6-16. Safe Operating Area
VOUT = 3.3 V, FSW = 800 kHz
图6-15. Output Voltage Ripple
115
105
95
85
75
65
55
45
35
25
Airflow
400LFM
200LFM
100LFM
Nat conv
0
0.5
1
1.5
Output Current (A)
2
2.5
3
Device soldered to a 64-mm × 83-mm, 4-layer PCB
图6-17. Safe Operating Area
VOUT = 5.0 V, FSW = 1 MHz
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6.10 Typical Characteristics: VIN = 36 V
Refer to 节8.2 for circuit designs.
100
95
90
85
80
75
70
65
60
55
50
45
3.0
2.4
1.8
1.2
0.6
0.0
VOUT, FSW
5.0 V, 1.0 MHz
3.3 V, 800 kHz
VOUT, FSW
5.0 V, 1.0 MHz
3.3 V, 800 kHz
40
35
30
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
Output Current (A)
Output Current (A)
VLDOIN = VOUT
VLDOIN = VOUT
图6-18. Efficiency
图6-19. Power Dissipation
115
105
95
40
VOUT, FSW
5.0 V, 1.0 MHz
3.3 V, 800 kHz
36
32
28
24
20
16
12
8
85
75
65
55
45
Airflow
400LFM
200LFM
100LFM
Nat conv
35
25
0
0.5
1
1.5
Output Current (A)
2
2.5
3
0
0.5
1
1.5
2
2.5
3
Output Current (A)
Device soldered to a 64-mm × 83-mm, 4-layer PCB
COUT = 2 × 47-µF ceramic, 25-V, 1206 case size
图6-21. Safe Operating Area
VOUT = 3.3 V, FSW = 800 kHz
图6-20. Output Voltage Ripple
115
105
95
85
75
65
55
45
35
25
Airflow
400LFM
200LFM
100LFM
Nat conv
0
0.5
1
1.5
Output Current (A)
2
2.5
3
Device soldered to a 64-mm × 83-mm, 4-layer PCB
图6-22. Safe Operating Area
VOUT = 5.0 V, FSW = 1 MHz
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7 Detailed Description
7.1 Overview
The TLVM13630 is an easy-to-use, synchronous buck, DC-DC power module that operates from a 3-V to 36-V
supply voltage. The device is intended for step-down conversions from 5-V, 12-V, and 24-V supply rails. With an
integrated power controller, inductor, and MOSFETs, the TLVM13630 delivers up to 3-A DC load current, with
high efficiency and ultra-low input quiescent current, in a very small solution size. Although designed for simple
implementation, this device offers flexibility to optimize its usage according to the target application. Control-loop
compensation is not required, reducing design time and external component count.
With a programmable switching frequency from 200 kHz to 2.2 MHz using its RT pin, the TLVM13630
incorporates specific features to improve EMI performance in noise-sensitive applications:
• An optimized package and pinout design enables a shielded switch-node layout that mitigates radiated EMI
• Parallel input and output paths with symmetrical capacitor layouts minimize parasitic inductance, switch-
voltage ringing, and radiated field coupling
• Clock synchronization and FPWM mode enable constant switching frequency across the load current range
• Integrated power MOSFETs with enhanced gate drive control enable low-noise PWM switching
• Adjustable switch-node slew rate, which allows optimization of EMI at higher frequency harmonics
The TLVM13630 module also includes inherent protection features for robust system requirements:
• An open-drain PGOOD indicator for power-rail sequencing and fault reporting
• Precision enable input with hysteresis, providing
– Programmable line undervoltage lockout (UVLO)
– Remote ON/OFF capability
• Internally fixed output-voltage soft start with monotonic startup into prebiased loads
• Hiccup-mode overcurrent protection with cycle-by-cycle peak and valley current limits
• Thermal shutdown with automatic recovery.
These features enable a flexible and easy-to-use platform for a wide range of applications. The pin arrangement
is designed for simple layout, requiring few external components. See 节10 for layout example.
7.2 Functional Block Diagram
VLDOIN
VCC
Optional
external bias
(from VOUT)
RT
LDO bias
subregulator
VIN
Oscillator
RRT
CVCC
UVLO
VIN = 3 V to 36 V
OTP
VIN
RENT
Shutdown
logic
Precision
enable for
VIN UVLO
EN
PG
Enable
logic
RENB
OCP
PGOOD
indicator
PGOOD
logic
CIN
SW
Power
stage
and
control
logic
2.2 µH
VOUT = 1 V to 6 V
IOUT(max) = 3 A
COUT
RFBT
VOUT
FB
To VOUT
sense point
UVLO
OTP
OCP
EN
Soft start
+
RFBB
Comp
VREF
PGND
AGND
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7.3 Feature Description
7.3.1 Input Voltage Range
With a steady-state input voltage range from 3 V to 36 V, the TLVM13630 module is intended for step-down
conversions from typical 12-V, 24-V, and 28-V input supply rails. The schematic circuit in 图 7-1 shows all the
necessary components to implement a TLVM13630-based buck regulator using a single input supply.
VIN = 3 to 36 V
Precision
Enable UVLO
VIN
VIN
CIN1
CIN2
PGND
PGND
RENT
TLVM13630
Optional
external bias
VOUT = 1 to 6 V
IOUT(max) = 3 A
EN
VLDOIN
VCC
VOUT
VOUT
RENB
CVCC
COUT
RPG
RFBT
PG
RT
PGOOD
indicator
FB
RRT
RFBB
AGND
PGND
图7-1. TLVM13630 Schematic Diagram with Input Voltage Operating Range of 3 V to 36 V
Take extra care to make sure that the voltage at the VIN pins of the module does not exceed the absolute
maximum voltage rating of 40 V during line or load transient events. Voltage ringing at the VIN pins that exceeds
the absolute maximum ratings can damage the IC.
7.3.2 Adjustable Output Voltage (FB)
The TLVM13630 has an adjustable output voltage range of 1 V to 6 V. Setting the output voltage requires two
resistors, RFBT and RFBB (see 图 7-2). Connect RFBT between VOUT, at the regulation point, and the FB pin.
Connect RFBB between the FB pin and AGND (pin 10). The recommended value of RFBB is 10 kΩ. The value for
RFBT can be calculated using 方程式 1. 表 7-1 lists the standard resistor values for several output voltages and
the recommended switching frequency. The minimum required output capacitance for each output voltage is also
included in 表 7-1. The capacitance values listed represent the effective capacitance, taking into account the
effects of DC bias and temperature variation.
(1)
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VOUT
RFBT
FB
RFBB
10 kΩ
AGND
图7-2. FB Resistor Divider
表7-1. Standard RFBT Values, Recommended FSW and Minimum COUT
RECOMMENDED
FSW (kHz)
COUT(MIN) (µF)
(EFFECTIVE)
RECOMMENDED
FSW (kHz)
COUT(MIN) (µF)
(EFFECTIVE)
RFBT (kΩ) (1)
RFBT (kΩ) (1)
VOUT (V)
VOUT (V)
1.0
1.2
1.5
1.8
2.0
Short
2
400
500
500
600
600
300
200
160
120
100
2.5
3.0
3.3
5.0
6.0
15
750
750
65
50
40
25
22
20
4.99
8.06
10
23.2
40.2
49.9
800
1000
1000
(1) RFBB = 10 kΩ.
Note that higher feedback resistances consume less DC current, which is mandatory if light-load efficiency is
critical. However, RFBT larger than 1 MΩ is not recommended as the feedback path becomes more susceptible
to noise. High feedback resistance generally requires more careful layout of the feedback path. It is important to
keep the feedback trace as short as possible while keeping the feedback trace away from the noisy area of the
PCB. For more layout recommendations, see 节10.
7.3.3 Input Capacitors
Input capacitors are necessary to limit the input ripple voltage to the module due to switching-frequency AC
currents. TI recommends using ceramic capacitors to provide low impedance and high RMS current rating over a
wide temperature range. 方程式 2 gives the input capacitor RMS current. The highest input capacitor RMS
current occurs at D = 0.5, at which point the RMS current rating of the capacitors should be greater than half the
output current.
DIL2
12
≈
’
D∂ IOUT2 ∂ 1-D +
∆
÷
÷
◊
ICIN,rms
=
(
)
∆
«
(2)
where
• D = VOUT / VIN = the module duty cycle
Ideally, the DC and AC components of input current to the buck stage are provided by the input voltage source
and the input capacitors, respectively. Neglecting inductor ripple current, the input capacitors source current of
amplitude (IOUT – IIN) during the D interval and sink IIN during the 1 – D interval. Thus, the input capacitors
conduct a square-wave current of peak-to-peak amplitude equal to the output current. The resultant capacitive
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component of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, 方程
式3 gives the peak-to-peak ripple voltage amplitude:
IOUT ∂D ∂ 1- D
(
)
+ IOUT ∂RESR
DV
=
IN
FSW ∂CIN
(3)
(4)
方程式4 gives the input capacitance required for a particular load current:
D∂ 1-D ∂I
(
)
OUT
CIN
í
FSW ∂ DVIN -RESR ∂IOUT
where
• ΔVIN is the input voltage ripple specification.
The TLVM13630 requires a minimum of 2 × 4.7 µF of ceramic type input capacitance. Only use high-quality
ceramic type capacitors with sufficient voltage and temperature rating. The ceramic input capacitors provide a
low impedance source to the converter in addition to supplying the ripple current and isolating switching noise
from other circuits. Additional capacitance can be required for applications with transient load requirements. The
voltage rating of input capacitors must be greater than the maximum input voltage. To compensate for the
derating of ceramic capacitors, TI recommends a voltage rating of twice the maximum input voltage or placing
multiple capacitors in parallel. 表7-2 includes a preferred list of capacitors by vendor.
表7-2. Recommended Input Capacitors
CAPACITOR CHARACTERISTICS
VENDOR(1)
DIELECTRIC
PART NUMBER
CASE SIZE
CAPACITANCE (2)
(µF)
VOLTAGE RATING (V)
TDK
X7R
X7R
X7R
X7S
C3216X7R1H475K160AC
GRM31CR71H475KA12L
CGA6P3X7R1H475K250AB
GCM31CC71H475KA03L
1206
1206
1210
1206
50
50
50
50
4.7
4.7
4.7
4.7
Murata
TDK
Murata
(1) Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table. See the Third-Party Products Disclaimer.
(2) Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature).
7.3.4 Output Capacitors
表 7-1 lists the TLVM13630 minimum amount of required output capacitance. The effects of DC bias and
temperature variation must be considered when using ceramic capacitance. For ceramic capacitors, the package
size, voltage rating, and dielectric material contribute to differences between the standard rated value and the
actual effective value of the capacitance.
When adding additional capacitance above COUT(MIN), the capacitance can be ceramic type, low-ESR polymer
type, or a combination of the two. See 表7-3 for a preferred list of output capacitors by vendor.
表7-3. Recommended Output Capacitors
CAPACITOR CHARACTERISTICS
TEMPERATURE
COEFFICIENT
VENDOR(1)
TDK
PART NUMBER
CASE SIZE
VOLTAGE (V)
CAPACITANCE(2) (µF)
X7R
X7R
X7R
X7S
X6S
X7R
CGA5L1X7R1C106K160AC
GCM31CR71C106KA64L
C3216X7R1E106K160AB
GCJ31CC71E106KA15L
GRM31CC81E226K
1206
1206
1206
1206
1206
1210
16
16
25
25
25
25
10
10
10
10
22
22
Murata
TDK
Murata
Murata
Murata
GRM32ER71E226M
(1) Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table. See the Third-Party Products Disclaimer.
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(2) Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature).
7.3.5 Switching Frequency (RT)
The switching frequency range of the TLVM13630 is 200 kHz to 2.2 MHz. The switching frequency can easily be
set by connecting a resistor (RRT) between the RT pin and AGND. Use 方程式 5 to calculate the RRT value for a
desired frequency or simply select from 表7-4. Note that a resistor value outside of the recommended range can
cause the device to shut down. This prevents unintended operation if RT pin is shorted to ground or left open.
Do not apply a pulsed signal to this pin to force synchronization.
The switching frequency must be selected based on the output voltage setting of the device. See 表 7-4 for RRT
resistor values and the allowable output voltage range for a given switching frequency for common input
voltages.
(5)
表7-4. Switching Frequency Versus Output Voltage (IOUT = A)
VIN = 5 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
RRT
(kΩ)
FSW (kHz)
VOUT RANGE (V)
VOUT RANGE (V)
VOUT RANGE (V)
VOUT RANGE (V)
MIN
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.2
1.2
MAX
2.0
3.0
3.5
3.5
3.0
3.0
3.0
3.0
3.0
2.5
2.5
MIN
1.0
1.0
1.0
1.0
1.0
1.5
1.5
1.5
2.0
2.0
2.0
MAX
2.0
4.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
MIN
1.0
1.0
1.5
1.5
2.0
2.5
3.0
3.0
3.5
4.0
4.5
MAX
1.5
3.3
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
MIN
1.0
1.2
1.8
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-
MAX
1.5
3.0
5.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
-
200
400
66.5
33.2
22.1
16.5
13.0
10.7
9.09
8.06
6.98
6.34
5.626
600
800
1000
1200
1400
1600
1800
2000
2200
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7.3.6 Output ON/OFF Enable (EN) and VIN UVLO
The EN pin provides precision ON and OFF control for the TLVM13630. Once the EN/SYNC pin voltage exceeds
the threshold voltage and VIN is above the minimum turn-on threshold, the device starts operation. The simplest
way to enable the TLVM13630 is to connect EN directly to VIN. This allows the TLVM13630 to start up when VIN
is within its valid operating range. However, many applications benefit from the employment of an enable divider
network as shown in 图 7-3, which establishes a precision input undervoltage lockout (UVLO). This can be used
for sequencing, to prevent re-triggering the device when used with long input cables, or to reduce the occurrence
of deep discharge of a battery power source. An external logic signal can also be used to drive the enable input
to toggle the output on and off and for system sequencing or protection.
VIN
VIN
RENT
EN
RENB
AGND
图7-3. VIN UVLO Using the EN Pin
RENB can be calculated using 方程式6.
(6)
where
• A typical value for RENT is 100 kΩ.
• VEN is 1.263 V (typical).
• VIN(ON) is the desired start-up input voltage.
7.3.7 Power Good Monitor (PG)
The TLVM13630 provides a PGOOD signal to indicate when the output voltage is within regulation. Use the
PGOOD signal for output monitoring, fault protection, or start-up sequencing of downstream converters. The
PGOOD pin voltage goes low when the feedback voltage is outside of the PGOOD thresholds. This occurs
during the following:
• While the device is disabled
• In current limit
• In thermal shutdown
• During normal start-up, when the output voltage has not reach its regulation value
A glitch filter prevents false flag operation for short excursions (<120 µs typical) of the output voltage, such as
during line and load transients.
PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater than 20 V. The typical
range of pullup resistance is 10 kΩ to 100 kΩ. When EN is pulled low, the flag output is also forced low. With EN
low, power good remains valid as long as the input voltage is above 1 V (typical). Use the PG signal for start-up
sequencing of downstream regulators, as shown in 图7-4, or for fault protection and output monitoring.
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VIN(on) = 13.9 V
VIN(off) = 10 V
VOUT2 = 3.3 V
VOUT1 = 5 V
RUV1
1 M
RFB3
PG 13
PG 13
RPG
RFB1
40.2 k
23.2 k
100 k
14
EN
14
EN
RUV2
FB
10
FB
10
1 V
1 V
100 k
RFB4
10 k
RFB2
10 k
Regulator #1
Regulator #2
Start-up based on
input voltage UVLO
Sequential start-up
based on PG
图7-4. TLVM13630 Sequencing Implementation Using PG and EN
7.3.8 Internal LDO, VCC Output, and VLDOIN Input
The TLVM13630 has an internal LDO to power internal circuitry. The VCC pin is the output of the internal LDO.
This pin must not be used to power external circuitry. Connect a high-quality, 1-μF capacitor from this pin to
AGND, close to the device pins. Do not load the VCC pin or short it to ground.
The VLDOIN pin is an optional input to the internal LDO. Connect an optional high quality 0.1-µF to 1-µF
capacitor from this pin to ground for improved noise immunity.
The LDO generates the VCC voltage from one of the two inputs: VIN or the VLDOIN input. When VLDOIN is tied
to ground or below 3.1 V, the LDO is powered from VIN. When VLDOIN is tied to a voltage higher than 3.1 V, the
LDO input is powered from VLDOIN. VLDOIN voltage must be lower than both VIN and 12.5 V.
The VLDOIN input is designed to reduce the LDO power loss. The LDO power loss is:
PLDO-LOSS = ILDO × (VIN_LDO –VVCC
)
(7)
The higher the difference between the input and output voltages of the LDO, the more loss occurs to supply the
same LDO output current. The VLDOIN input provides an option to supply the LDO with a lower voltage than
VIN, to reduce the difference of the input and output voltages of the LDO and reduce power loss. For example, if
the LDO current is 10 mA at a certain frequency with VIN = 24 V and VOUT = 5 V. The LDO loss with VLDOIN tied
to ground is equal to 10 mA × (24 V – 3.3 V) = 207 mW, while the loss with VLDOIN tied to VOUT (5 V) is equal
to 10 mA × (5 V –3.3 V) = 17 mW.
The efficiency improvement is more significant at light and mid loads because the LDO loss is a higher
percentage of the total loss. The improvement is more significant with higher switching frequency because the
LDO current is higher at higher switching frequency. The improvement is more significant when VIN » VOUT
because the voltage difference is higher.
图7-5 shows typical efficiency waveforms with VLDOIN powered by different input voltages.
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100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
68
66
64
62
60
VLDOIN
3.3V
5V
GND
0
0.5
1
1.5
2
2.5
3
Output Current (A)
VIN = 24 V
VOUT = 5 V
FSW = 1 MHz
ILDO = 10 mA
图7-5. Efficiency improvements with VLDOIN (VOUT = 5 V)
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7.3.9 Overcurrent Protection (OCP)
The TLVM13630 is protected from overcurrent conditions using cycle-by-cycle current limiting of the peak
inductor current. The current is compared every switching cycle to the current limit threshold. During an
overcurrent condition, the output voltage decreases.
The TLVM13630 employs hiccup overcurrent protection if there is an extreme overload. In hiccup mode, the
regulator is shut down and kept off for 80 ms (typical) before the TLVM13630 tries to start again. If an
overcurrent or short-circuit fault condition still exists, hiccup repeats until the fault condition is removed. Hiccup
mode reduces power dissipation under severe overcurrent conditions, and prevents overheating and potential
damage to the device. Once the fault is removed, the module automatically recovers and returns to normal
operation.
7.3.10 Thermal Shutdown
Thermal shutdown is an integrated self-protection used to limit junction temperature and prevent damage related
to overheating. Thermal shutdown turns off the device when the junction temperature exceeds 168°C (typical) to
prevent further power dissipation and temperature rise. Junction temperature decreases after shutdown, and the
TLVM13630 attempts to restart when the junction temperature falls to 158°C (typical).
7.4 Device Functional Modes
7.4.1 Shutdown Mode
The EN/SYNC pin provides ON and OFF control for the TLVM13630. When VEN is below approximately 0.4 V,
the device is in shutdown mode. Both the internal LDO and the switching regulator are off. The input quiescent
current in shutdown mode drops to 0.6 µA (typical). The TLVM13630 also employs internal undervoltage
protection. If the input voltage is below its UV threshold, the regulator remains off.
7.4.2 Standby Mode
The internal LDO has a lower enable threshold than the regulator itself. When VEN is above 1.1 V (maximum)
and below the precision enable threshold of 1.263 V (typical), the internal LDO is on and regulating. The
precision enable circuitry is turned on once the internal VCC is above its UVLO threshold. The switching action
and voltage regulation are not enabled until VEN/SYNC rises above the precision enable threshold.
7.4.3 Active Mode
The TLVM13630 is in active mode when VIN and VEN are above their relevant thresholds and no fault conditions
are present. The simplest way to enable the operation is to connect the EN pin to VIN, which allows self start-up
when the applied input voltage exceeds the minimum start-up voltage.
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8 Applications and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TLVM13630 only requires a few external components to convert from a wide range of supply voltages to a
fixed output voltage. The following section describes the design procedure to configure the TLVM13630 power
module. To expedite and streamline the design process, WEBENCH® online software is available to generate
complete designs, leveraging iterative design procedures and access to comprehensive component databases.
As mentioned previously, the TLVM13630 also integrates several optional features to meet system design
requirements, including the following:
• Precision enable with hysteresis
• External adjustable UVLO
• Adjustable SW node slew rate
• Power-good indicator
The following application circuit detailed shows the TLVM13630 configuration options suitable for several
application use cases.
8.2 Typical Applications
The following are sample typical applications along with design procedure for the implemenation of TLVM13630.
8.2.1 Design 1: 3-A Synchronous Buck Regulator for Industrial Applications
图 8-1 shows the schematic diagram of a 5-V, 3-A buck regulator with a switching frequency of 1 MHz. The
nominal input voltage for the sample design is 24 V. A resistor RRT of 13 kΩ sets the free-running switching
frequency at 1 MHz. An optional SYNC input signal allows adjustment of the switching frequency for this specific
application.
VIN = 24 V
VIN(on) = 6 V
VIN(off) = 4.3 V
VIN
VIN
CIN1
4.7
CIN2
4.7
F
F
PGND
PGND
RENT
374 k
TLVM13630
Optional
external bias
VOUT = 5 V
IOUT(max) = 3 A
EN
VLDOIN
VCC
VOUT
VOUT
RENB
CVCC
1
100 k
COUT
RPG
F
2 ꢀ 47
F
100 k
RFBT
40.2 k
PG
RT
PGOOD
indicator
FB
RRT
13 k
RFBB
10 k
AGND
PGND
图8-1. Circuit Schematic
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8.2.1.1 Design Requirements
For this design example, use the parameters listed in 表 8-1 as the input parameters and follow the design
procedures in 节8.2.1.2.
表8-1. Design Example Parameters
DESIGN PARAMETER
VALUE
Input voltage
24 V
Output voltage
5 V
Output current
0 A to 3 A
1 MHz
Switching Frequency
表 8-2 gives the selected buck module power-stage components with availability from multiple vendors. This
design uses an all-ceramic output capacitor implementation.
表8-2. List of Materials for Application Circuit 1
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURER(1)
PART NUMBER
Taiyo Yuden
TDK
UMK325B7475KN-TR
CGA6P3X7R1H475K250AB
GRM31CC72A475KE11L
GRM32ER71A476ME15L
1210ZC476MAT2A
4.7 µF, 50 V, X7R, 1210, ceramic
CIN1, CIN2
2
4.7 µF, 100 V, X7S, 1206, ceramic
47 µF, 10 V, X7R, 1210, ceramic
Murata
Murata
COUT1, COUT2
2
AVX
1 µF, 16 V, X7R, 0603, ceramic
Murata
GCM188R71C105KA64J
EMK105BJ105KVHF
CVCC
U1
1
1
1 µF, 16 V, X5R, 0402, ceramic
Taiyo Yuden
Texas Instruments
TLVM13630 36-V, 3-A synchronous buck module
TLVM13630RDLR
(1) See the Third-Party Products Disclaimer.
More generally, the TLVM13630 module is designed to operate with a wide range of external components and
system parameters. However, the integrated loop compensation is optimized for a certain range of output
capacitance.
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM63603 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance.
• Run thermal simulations to understand board thermal performance.
• Export customized schematic and layout into popular CAD formats.
• Print PDF reports for the design, and share the design with colleagues.
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Output Voltage Setpoint
The output voltage of the TLVM13630 device is externally adjustable using a resistor divider. The recommended
value of RFBB is 10 kΩ. The value for RFBB can be selected from 表7-1 or calculated using 方程式8:
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(8)
For the desired output voltage of 5 V, the formula yields a value of 40.2 kΩ. Choose the closest available
standard value of 40.2 kΩfor RFBT
.
8.2.1.2.3 Switching Frequency Selection
The recommended switching frequency for standard output voltages can be found in 表 7-1. For a 5-V output,
the recommended switching frequency is 1 MHz. To set the switching frequency to 1 MHz, connect a 13.0-kΩ
resistor between the RT pin and AGND.
8.2.1.2.4 Input Capacitor Selection
The TLVM13630 requires a minimum input capacitance of 2 × 4.7-µF ceramic type. High-quality ceramic type
capacitors with sufficient voltage and temperature rating are required. The voltage rating of input capacitors must
be greater than the maximum input voltage.
For this design, select two 4.7-µF, 50-V, 1210 case size, ceramic capacitors.
8.2.1.2.5 Output Capacitor Selection
For a 5-V output, the TLVM13630 requires a minimum of 25 µF of effective output capacitance for proper
operation (see 表 7-1). High-quality ceramic type capacitors with sufficient voltage and temperature rating are
required. Additional output capacitance can be added to reduce ripple voltage or for applications with transient
load requirements.
For this design example, select two 47-µF, 10-V, 1210 case size, ceramic capacitors, which have a total effective
capacitance of approximately 48 µF at 5 V.
8.2.1.2.6 Other Connections
• Connect VLDOIN to VOUT to improve efficiency.
• Place a 1-µF capacitor between the VCC pin and PGND, located near to the device.
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8.2.1.3 Application Curves
Unless otherwise indicated, VIN = 24 V, VOUT = 5 V, IOUT = 3 A, and FSW = 1 MHz.
VIN (20 V/DIV)
VIN (20 V/DIV)
EN (5 V/DIV)
VOUT (5 V/DIV)
PG (5 V/DIV)
EN (5 V/DIV)
VOUT (5 V/DIV)
PG (5 V/DIV)
2 ms/DIV
500 µs/DIV
VIN = 24 V
VOUT = 5 V
VIN = 24 V
VOUT = 5 V
图8-3. Shutdown Waveforms
图8-2. Start-Up Waveforms
VOUT (200 mV/DIV)
VOUT (200 mV/DIV)
5V
5V
IOUT (2 A/DIV)
IOUT (2 A/DIV)
50 µs/DIV
50 µs/DIV
VIN = 24 V
VOUT = 5 V
FSW = 1 MHz
VIN = 24 V
VOUT = 5 V
FSW = 1 MHz
COUT = 2 × 47µF
COUT = 2 × 47µF
图8-4. Load Transient 0 A to 3 A, 1 A/µs
图8-5. Load Transient 1.5 A to 3 A, 1 A/µs
VOUT (200 mV/DIV)
VOUT (200 mV/DIV)
3.3V
3.3V
IOUT (2 A/DIV)
IOUT (2 A/DIV)
50 µs/DIV
50 µs/DIV
VIN = 24 V
VOUT = 3.3 V
FSW = 1 MHz
VIN = 24 V
VOUT = 3.3 V
F SW = 1 MHz
COUT = 2 × 47µF
COUT = 2 × 47µF
图8-6. Load Transient 0 A to 3 A, 1 A/µs
图8-7. Load Transient 1.5 A to 3 A, 1 A/µs
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图8-9. Thermal Image VIN = 12 V, VOUT = 5 V, FSW
=
图8-8. Thermal Image VIN = 12 V, VOUT = 3.3 V, FSW
1 MHz, IOUT = 3 A
= 1 MHz, IOUT = 3 A
图8-10. Thermal Image VIN = 24 V, VOUT = 3.3 V, FSW
图8-11. Thermal Image VIN = 24 V, VOUT = 5 V, FSW
=
= 1 MHz, IOUT = 3 A
1 MHz, IOUT = 3 A
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8.2.2 Design 2: Inverting Buck-Boost Regulator with a –5-V Output
图 8-12 shows the schematic diagram of a –5-V inverting buck-boost regulator with a switching frequency of 1
MHz. The input voltage range for the sample design is 12 V to 24 V.
VIN+
VIN
VIN
CIN3
VIN(on) = 8.9 V
VIN = 12 V to 24 V
VIN–
CIN1
4.7
CIN2
4.7
10
F
F
F
PGND
PGND
RENT
604 k
–VOUT
–VOUT
TLVM13630
Optional
external bias
EN
VLDOIN
VCC
VOUT
VOUT
RENB
CVCC
1
100 k
COUT
F
VOUT = –5 V
IOUT(max) = –2 A
2 ꢀ 47
F
RFBT
40.2 k
VOUT–
PG
RT
Optional
Schottky
Diode
FB
–VOUT
RRT
13 k
RFBB
10 k
AGND
PGND
–VOUT
图8-12. Circuit Schematic
8.2.2.1 Design Requirements
For this design example, use the parameters listed in 表 8-3 as the input parameters and follow the design
procedures in 节8.2.2.2.
表8-3. Design Example Parameters
DESIGN PARAMETER
VALUE
12 to 24 V
–5 V
Input voltage
Output voltage
Output current
0 A to 2 A
1 MHz
Switching frequency
表 8-4 gives the selected module power-stage components with availability from multiple vendors. This design
uses an all-ceramic output capacitor implementation.
表8-4. List of Materials for Application Circuit 2
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURER(1)
PART NUMBER
Taiyo Yuden
TDK
UMK325B7475KN-TR
CGA6P3X7R1H475K250AB
GCM31CC71H475KA03K
GRM32ER71A476ME15L
1210ZC476MAT2A
4.7 µF, 50 V, X7R, 1210, ceramic
CIN1, CIN2, CIN3
3
4.7 µF, 50 V, X7S, 1206, ceramic
47 µF, 10 V, X7R, 1210, ceramic
Murata
Murata
COUT1, COUT2
2
AVX
CVCC
U1
1
1
1 µF, 16 V, X7R, 0603, ceramic
Murata
GCM188R71C105KA64J
TLVM13630RDLR
TLVM13630 36-V, 3-A synchronous buck module
Texas Instruments
More generally, the TLVM13630 module is designed to operate with a wide range of external components and
system parameters. However, the integrated loop compensation is optimized for a certain range of output
capacitance.
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8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Output Voltage Setpoint
The output voltage of the TLVM13630 device is externally adjustable using a resistor divider. The recommended
value of RFBB is 10 kΩ. Calculate the value for RFBT using 方程式9:
(9)
For the desired output voltage of – 5 V, enter the absolute value of 5 V for the VOUT in 方程式 9. The formula
yields a value of 40.2 kΩ. Choose the closest available standard value of 40.2 kΩfor RFBT
.
8.2.2.2.2 IBB Maximum Output Current
The achievable output current with an IBB topology using the TLVM13630 is IOUT(max) = ILDC(max) × (1 – D),
where ILDC(max) = 3 A is the rated current of the module and D = |VOUT| / (VIN + |VOUT|) is the module duty cycle.
Therefore in the case of VIN = 12 V and the VOUT = –5 V, the maximum output current is 2.1 A.
8.2.2.2.3 Switching Frequency Selection
To set the switching frequency to 1 MHz, connect a 13.0-kΩ resistor between the RT pin and AGND pins of the
module based on 方程式5.
8.2.2.2.4 Input Capacitor Selection
The TLVM13630 requires a minimum input capacitance of 2 × 4.7-µF ceramic type between the VIN pins and
PGND pins as close as possible to the module. High-quality ceramic type capacitors with sufficient voltage and
temperature rating are required. In the inverting buck-boost configuration the maximum voltage between VIN and
PGND pin of the module is equal to VIN + |VOUT|.
For this design, two 4.7-µF, 50-V, 1210 case size, ceramic capacitors are selected.
8.2.2.2.5 Output Capacitor Selection
The TLVM13630 requires a minimum of 25 µF of effective output capacitance for proper operation. High-quality
ceramic type capacitors with sufficient voltage and temperature rating are required. Additional output
capacitance can be added to reduce ripple voltage or for applications with transient load requirements.
For this design example, a two 47-µF, 10-V, 1210 case size, ceramic capacitors are used which have a total
effective capacitance of approximately 48 µF at 5 V.
8.2.2.2.6 Other Connections
Place a 1-µF capacitor between the VCC pin and PGND, located near to the device.
The right-half-plane zero of an IBB topology is at its lowest frequency at minimum input voltage. However, it does
not appear at low frequency for a –5 V output and thus has minimal effect on the loop response for this
application.
In the inverting buck-boost configuration, the input capacitor CIN and output capacitor COUT can formed an AC
capacitive divider during a fast VIN transient or hot-plugged event at the input. This event will resulted in a
positive voltage spike at the output that may disturb the load. In this case, an optional Schottky diode may be
installed between –VOUT and GND as shown in 图8-12 to clamp the output spike.
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8.2.2.3 Application Curves
Unless otherwise indicated, VIN = 12 V, VOUT = –5 V, and FSW = 1 MHz.
95
90
85
80
75
70
65
60
5.1
5.098
5.096
5.094
5.092
5.09
VIN = 12 V
VIN = 18 V
VIN = 24 V
VIN = 12 V
VIN = 18 V
VIN = 24 V
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Load Current (A)
Load Current (A)
图8-13. Efficiency Curves
图8-14. Load Regulation
VOUT (200 mV/DIV)
VOUT (100 mV/DIV)
-5V
0A
-5V
0A
IOUT (1 A/DIV)
200 µs/DIV
IOUT (1 A/DIV)
200 µs/DIV
VIN = 12 V
FSW = 1 MHz
COUT = 2 × 47 µF
VIN = 12 V
FSW = 1 MHz
COUT = 2 × 47 µF
VOUT = –5 V
VOUT = –5 V
图8-15. Load Transient –0.5 A to –1.5 A, 1 A/µs
图8-16. Load Transient 0 A to –2 A, 1 A/µs
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8.2.2.3.1 EMI
The TLVM13630 is compliant with EN55011 radiated emissions. 图 8-17, 图 8-18, and 图 8-19 show typical
examples of radiated emission plots for the TPSM63603 which is in the same family of parts. The graphs include
the plots of the antenna in the horizontal and vertical positions.
8.2.2.3.1.1 EMI Plots
EMI plots were measured using the standard TPSM63603EVM.
图8-17. Radiated Emissions 24-V Input, 5-V Output, 3-A Load
图8-18. Radiated Emissions 24-V Input, 5-V Output, 3-A Load, Spread Spectrum
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图8-19. Radiated Emissions 24-V Input, 3.3-V Output, 3-A Load
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9 Power Supply Recommendations
The TLVM13630 buck module is designed to operate over a wide input voltage range of 3 V to 36 V. The
characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended
Operating Conditions in this data sheet. In addition, the input supply must be capable of delivering the required
input current to the loaded regulator circuit. Estimate the average input current with 方程式10.
VOUT ∂IOUT
IIN
=
V ∂ h
IN
(10)
where
• η= efficiency
If the module is connected to an input supply through long wires or PCB traces with a large impedance, take
special care to achieve stable performance. The parasitic inductance and resistance of the input cables can
have an adverse affect on module operation. More specifically, the parasitic inductance in combination with the
low-ESR ceramic input capacitors form an underdamped resonant circuit, possibly resulting in instability, voltage
transients, or both, each time the input supply is cycled ON and OFF. The parasitic resistance causes the input
voltage to dip during a load transient. If the module is operating close to the minimum input voltage, this dip can
cause false UVLO triggering and a system reset.
The best way to solve such issues is to reduce the distance from the input supply to the module and use an
electrolytic input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitor helps
damp the input resonant circuit and reduce any overshoot or undershoot at the input. A capacitance in the range
of 47 μF to 100 μF is usually sufficient to provide input parallel damping and helps hold the input voltage
steady during large load transients. A typical ESR of 0.1 Ω to 0.4 Ω provides enough damping for most input
circuit configurations.
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10 Layout
The performance of any switching power supply depends as much upon the layout of the PCB as the component
selection. Use the following guidelines to design a PCB with the best power conversion performance, optimal
thermal performance, and minimal generation of unwanted EMI.
10.1 Layout Guidelines
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. 图10-1 and 图10-2
show a typical PCB layout. Some considerations for an optimized layout are:
• Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
• Place ceramic input and output capacitors close to the device pins to minimize high-frequency noise.
• Locate additional output capacitors between the ceramic capacitors and the load.
• Connect AGND to PGND at a single point.
• Place RFBT and RFBB as close as possible to the FB pin.
• Use multiple vias to connect the power planes to internal layers.
10.2 Layout Example
图10-2. Typical Top-Layer
图10-1. Typical Top-Layer Layout
10.2.1 Package Specifications
表10-1. Package Specifications Table
TPSM63603
VALUE
UNIT
Weight
123
mg
Flammability
Meets UL 94 V-0
MTBF calculated reliability
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
84
MHrs
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.1.2 Development Support
With an input operating voltage from 3 V to 36 V and rated output current from 2 A to 6 A, the
TLVM13620/30/40/60 family of synchronous buck power modules specified in 表 11-1 provides flexibility,
scalability and optimized solution size for a range of applications. These modules enable DC/DC solutions with
high density, low EMI and increased flexibility. Available EMI mitigation features include RBOOT-configured
switch-node slew rate control, fixed switching frequency, and integrated input bypass capacitors. All modules are
rated for an ambient temperature up to 105°C.
表11-1. Synchronous Buck DC/DC Power Module Family
DC/DC MODULE
TLVM13620
TLVM13630
TLVM13640
TLVM13660
RATED IOUT PACKAGE
DIMENSIONS
FEATURES
EMI MITIGATION
2 A
B0QFN (30)
3 A
4.0 × 6.0 × 1.8 mm
Integrated BOOT capacitor
RT adjustable FSW
precision enable
,
4 A
Integrated input, VCC and
BOOT capacitors
B3QFN (20)
6 A
5.0 × 5.5 × 4.0 mm
For development support see the following:
• TLVM13630 Quickstart Calculator
• TLVM13630 Simulation Models
• For TI's reference design library, visit the TI Reference Design library.
• For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center.
• To design a low-EMI power supply, review TI's comprehensive EMI Training Series.
• To design an inverting buck-boost (IBB) regulator, visit DC/DC inverting buck-boost modules.
• TI Reference Designs:
– Multiple Output Power Solution For Kintex 7 Application
– Arria V Power Reference Design
– Altera Cyclone V SoC Power Supply Reference Design
– Space-optimized DC/DC Inverting Power Module Reference Design With Minimal BOM Count
– 3- To 11.5-VIN, –5-VOUT, 1.5-A Inverting Power Module Reference Design For Small, Low-noise Systems
• Technical Articles:
– Powering Medical Imaging Applications With DC/DC Buck Converters
– How To Create A Programmable Output Inverting Buck-boost Regulator
• To view a related device of this product, see the LM61460 36-V, 6-A synchronous buck converter.
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM63603 device with WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance.
Copyright © 2022 Texas Instruments Incorporated
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• Run thermal simulations to understand board thermal performance.
• Export customized schematic and layout into popular CAD formats.
• Print PDF reports for the design, and share the design with colleagues.
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Innovative DC/DC Power Modules selection guide
• Texas Instruments, Enabling Small, Cool and Quiet Power Modules with Enhanced HotRod™ QFN Package
Technology white paper
• Texas Instruments, Benefits and Trade-offs of Various Power-Module Package Options white paper
• Texas Instruments, Simplify Low EMI Design with Power Modules white paper
• Texas Instruments, Power Modules for Lab Instrumentation white paper
• Texas Instruments, An Engineer's Guide To EMI In DC/DC Regulators e-book
• Texas Instruments, Soldering Considerations for Power Modules application report
• Texas Instruments, Practical Thermal Design With DC/DC Power Modules application report
• Texas Instruments, Using New Thermal Metrics application report
• Texas Instruments, AN-2020 Thermal Design By Insight, Not Hindsight application report
• Texas Instruments, Using the TPSM53602/3/4 for Negative Output Inverting Buck-Boost Applications
application report
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
HotRod™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2022 Texas Instruments Incorporated
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLVM13630RDHR
ACTIVE
B0QFN
RDH
30
3000
RoHS Exempt
& Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
13630
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
RDH0030A
B0QFN - 1.9 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
6.1
5.9
1.9
1.7
C
SEATING PLANE
0.08 C
0.01
0.00
2X 1.6 0.1
SYMM
0.675
0.575
2X 1.25 0.1
4X
0.6
0.4
(0.125) TYP
2X 0.74 0.1
1.925 0.1
0.8
0.7
(0.2) TYP
10X
4X
8
2X 2.425
14
30
2X 1.775
2X 1.125
2X 0.475
2X 1 0.1
29
28
0.6 0.1
0.000 PKG
2X 0.325
2X 0.975
0.6 0.1
0.75
12X
0.55
27
2X 1.775
1.925 0.1
2X 2.425
PIN 1 ID
21
0.3
0.2
1
22X
26
0.1
C A B
(0.15)
TYP
0.05
C
12X 0.5
2X 3
4226150/B 01/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RDH0030A
B0QFN - 1.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.55)
2X (1.6)
2X (1.25)
SYMM
4X (0.5)
2X (0.5)
26
4X (0.825)
4X (0.95)
1
2X (2.425)
21
2X (0.74)
2X (1)
27
1.925
2X (1.775)
2X (0.975)
2X (0.325)
28
29
2X (0.6)
0.000 PKG
(5.7)
2X (0.475)
2X (1.125)
2X (1.775)
2X (2.425)
2X (0.6)
12X (0.85)
1.925
30
4X (0.05)
8
4X (0.625)
10X (0.7)
14
(
0.2) TYP
(R0.05) TYP
30X (0.25)
2X (3)
12X (0.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
EDGE
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK DETAILS
4226150/B 01/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RDH0030A
B0QFN - 1.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.55)
2X (1.47)
2X (1.17)
4X (0.5)
SYMM
4X (0.825)
26
4X (0.95)
1
2X (0.74)
21
2.425
1.775
27
(1.925)
(0.6)
2X (0.95)
0.975
0.325
28
29
0.000 PKG
(5.7)
0.475
1.125
1.775
2.425
(0.6)
12X (0.85)
(1.925)
30
4X (0.05)
8
4X (0.625)
10X (0.7)
14
(R0.05) TYP
30X (0.25)
2X (3)
12X (0.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 27 & 30:
94% PRINTED SOLDER COVERAGE BY AREA
EXPOSED PAD 28 & 29
87% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
4226150/B 01/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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保。
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
TLVM13640RDLR
采用 5mm x 5.5mm 增强型 HotRod™ QFN 封装的 36V 输入、1V 至 6V 输出、4A 降压电源模块 | RDL | 20 | -40 to 125
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