TM248CBK32U-70 [TI]
2MX32 FAST PAGE DRAM MODULE, 70ns, SMA72, SIMM-72;
| 型号： | TM248CBK32U-70 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2MX32 FAST PAGE DRAM MODULE, 70ns, SMA72, SIMM-72 动态存储器 内存集成电路 |
| 文件： | 总9页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE
TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS649A – DECEMBER 1994 – REVISED JUNE 1995
Organization
Presence Detect
TM124BBK32F . . . 1 048 576 × 32
TM248CBK32F . . . 2 097 152 × 32
Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME
OR
Single 5-V Power Supply (±10% Tolerance)
t
t
t
WRITE
CYCLE
(MIN)
RAC
AA
CAC
72-Pin Single-In-Line Memory Module
(SIMM) for Use With Socket
(MAX)
’124BBK32F-60 60 ns
’124BBK32F-70 70 ns
’124BBK32F-80 80 ns
’248CBK32F-60 60 ns
’248CBK32F-70 70 ns
’248CBK32F-80 80 ns
(MAX)
30 ns
35 ns
40 ns
30 ns
35 ns
40 ns
(MAX)
15 ns
18 ns
20 ns
15 ns
18 ns
20 ns
110 ns
130 ns
150 ns
110 ns
130 ns
150 ns
TM124BBK32F – Utilizes Two 16-Megabit
DRAMs in Plastic Small-Outline J-Lead
(SOJ) Packages
TM248CBK32F – Utilizes Four 16-Megabit
DRAMs in Plastic Small-Outline J-Lead
(SOJ) Packages
Low Power Dissipation
Long Refresh Period
16 ms (1024 Cycles)
Operating Free-Air Temperature Range
0°C to 70°C
All Inputs, Outputs, Clocks Fully TTL
Compatible
†
Gold-Tabbed Versions Available:
– TM124BBK32F
– TM248CBK32F
3-State Output
Common CAS Control for Eight Common
Data-In and Data-Out Lines in Four Blocks
Tin-Lead (Solder) Tabbed Versions
Available:
Enhanced Page-Mode Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
– TM124BBK32U
– TM248CBK32U
description
TM124BBK32F
The TM124BBK32F is a 32-megabit dynamic random-access memory (DRAM) organized as four times
1048576 × 8 in a 72-pin SIMM. The SIMM is composed of two TMS418160DZ, 1 048 576 × 16-bit DRAMs, each
in a 42-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS418160DZ is
described in the TMS418160 data sheet. The TM124BBK32F SIMM is available in the single-sided BK-leadless
module for use with sockets.
TM248CBK32F
The TM248CBK32F is a 64-megabit DRAM organized as four times 2 097 152 × 8 in a 72-pin SIMM. The SIMM
is composed of four TMS418160DZ, 1 048 576 × 16-bit DRAMs, each in a 42-lead plastic SOJ package
mounted on a substrate with decoupling capacitors. The TMS418160DZ is described in the TMS418160 data
sheet. The TM248CBK32F SIMM is available in the double-sided BK-leadless module for use with sockets.
operation
The TM124BBK32F operates as two TMS418160DZs connected as shown in the functional block diagram and
Table 1. The TM248CBK32F operates as four TMS418160DZs connected as shown in the functional block
diagram and Table 1. The common I/O feature dictates the use of early-write cycles to prevent contention on
D and Q.
†
Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE
TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS649A – DECEMBER 1994 – REVISED JUNE 1995
BK SINGLE-IN-LINE MEMORY MODULE
(TOP VIEW)
TM124BBK32F
(SIDE VIEW)
TM248CBK32F
(SIDE VIEW)
V
1
2
3
4
SS
DQ0
DQ16
DQ1
DQ17
DQ2
5
6
DQ18
DQ3
7
8
DQ19
9
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CC
NC
A0
A1
A2
A3
A4
A5
A6
NC
DQ4
DQ20
DQ5
DQ21
DQ6
DQ22
DQ7
DQ23
A7
NC
V
CC
A8
A9
RAS3
RAS2
NC
NC
NC
NC
SS
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
NC
W
NC
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
V
PIN NOMENCLATURE
A0–A9
Address Inputs
CAS0–CAS3
DQ0–DQ31
Column-Address Strobe
Data In/Data Out
No Connection
Presence Detects
Row-Address Strobe
5-V Supply
NC
PD1– PD4
RAS0–RAS3
V
V
CC
Ground
SS
W
Write Enable
PRESENCE DETECT
V
SIGNAL
(PIN)
PD1
(67)
PD2
(68)
PD3
(69)
PD4
(70)
CC
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
80 ns
70 ns
60 ns
80 ns
70 ns
60 ns
V
V
V
V
V
V
NC
V
SS
SS
SS
SS
SS
SS
SS
TM124BBK32F
TM248CBK32F
V
SS
NC
NC
NC
NC
PD1
PD2
PD3
PD4
NC
NC
NC
NC
NC
NC
V
SS
NC
V
SS
NC
NC
NC
V
SS
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE
TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS649A – DECEMBER 1994 – REVISED JUNE 1995
Table 1. Connection Table
RASx
DATA BLOCK
CASx
†
SIDE 1
RAS0
RAS0
RAS2
RAS2
SIDE 2
RAS1
RAS1
RAS3
RAS3
DQ0–DQ7
CAS0
CAS1
CAS2
CAS3
DQ8–DQ15
DQ16–DQ23
DQ24–DQ31
†
Side 2 applies to the TM248CBK32F only.
single-in-line memory module and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM124BBK32F and TM248CBK32F: Nickel plate and gold plate over copper
Contact area for TM124BBK32U and TM248CBK32U: Nickel plate and tin/lead over copper
functional block diagram (TM124BBK32F and TM248CBK32F, side 1)
10
A0–A9
RAS0
W
RAS2
1M × 16
1M × 16
10
10
A0–A9
DQ0–
DQ7
A0–A9
DQ0–
DQ7
D0–D7
D16–D23
D24–D31
RAS
W
RAS
W
CAS0
CAS1
CAS2
CAS3
LCAS
UCAS
DQ8–
DQ15
LCAS
UCAS
DQ8–
DQ15
D8–D15
functional block diagram (TM248CBK32F, side 2)
10
A0–A9
RAS1
W
RAS3
1M × 16
1M × 16
10
10
A0–A9
DQ0–
DQ7
A0–A9
RAS
DQ0–
DQ7
D24–D31
D16–D23
D8–D15
D0–D7
RAS
W
W
CAS1
CAS0
CAS3
CAS2
LCAS
UCAS
DQ8–
DQ15
LCAS
UCAS
DQ8–
DQ15
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE
TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS649A – DECEMBER 1994 – REVISED JUNE 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
CC
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation: TM124BBK32F, TM124BBK32U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 W
TM248CBK32F, TM248CBK32U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
5.5
6.5
0.8
70
UNIT
V
V
V
V
Supply voltage
4.5
2.4
– 1
0
5
CC
IH
IL
High-level input voltage
V
Low-level input voltage (see Note 2)
Operating free-air temperature
V
T
A
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’124BBK32F-60 ’124BBK32F-70 ’124BBK32F-80
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
I
I
= – 5 mA
= 4.2 mA
2.4
2.4
2.4
V
V
OH
OH
0.4
0.4
0.4
OL
OL
V
= 5.5 V, V = 0 V to 6.5 V,
I
CC
All other pins = 0 V to V
I
I
I
Input current (leakage)
± 10
± 10
± 10
µA
I
CC
V
V
= 5.5 V,
CC
= 0 V to V ,
CC
Output current (leakage)
± 10
180
4
± 10
160
4
± 10
140
4
µA
O
O
CAS high
Read- or write-cycle
current
V
V
= 5.5 V, Minimum cycle
mA
mA
CC1
CC
= 2.4 V (TTL),
IH
After 1 memory cycle,
RAS and CAS high
I
Standby current
CC2
V
IH
= V
– 0.2 V (CMOS),
CC
After 1 memory cycle,
RAS and CAS high
2
2
2
mA
V
CC
= 5.5 V, Minimum cycle,
Average refresh current
(RAS only or CBR)
RAS cycling,
I
I
180
180
160
160
140
140
mA
mA
CC3
CAS high (RAS only);
RAS low after CAS low (CBR)
V
= 5.5 V,
t
= MIN,
CC
RAS low,
PC
CAS cycling
Average page current
CC4
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE
TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS649A – DECEMBER 1994 – REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
†
temperature (unless otherwise noted)
’248CBK32F-60 ’248CBK32F-70 ’248CBK32F-80
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
= – 5 mA
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
= 4.2 mA
0.4
± 10
± 20
184
0.4
± 10
± 20
164
0.4
± 10
± 20
144
OL
OL
Input current (leak-
age)
V
= 5.5 V,
V = 0 V to 6.5 V,
I
CC
All other pins = 0 V to V
I
I
I
µA
µA
mA
I
CC
Output current
(leakage)
V
V
= 5.5 V,
CC
= 0 V to V , CAS high
O
O
CC
Read- or write-cycle
current (see Note 3)
V
= 5.5 V,
Minimum cycle
CC1
CC
V
IH
= 2.4 V (TTL),
After 1 memory cycle,
RAS and CAS high
8
4
8
4
8
4
mA
mA
I
Standby current
CC2
V
IH
= V
– 0.2 V (CMOS),
CC
After 1 memory cycle,
RAS and CAS high
V
= 5.5 V,
Minimum cycle,
CC
RAS cycling,
Average refresh
current (RAS only or
CBR) (see Note 3)
I
I
360
184
320
164
280
144
mA
mA
CC3
CAS high (RAS only);
RAS low after CAS low (CBR)
V
= 5.5 V,
t
= MIN,
Average page current
(see Note 4)
CC
RAS low,
PC
CAS cycling
CC4
†
For test conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions.
NOTES: 3. Measured with a maximum of one address change while RAS = V
IL
4. Measured with a maximum of one address change while CAS = V
IH
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
’124BBK32F
’248CBK32F
PARAMETER
UNIT
MIN
MAX
10
7
MIN
MAX
20
7
C
C
C
C
C
Input capacitance, A0–A9
Input capacitance, RAS inputs
Input capacitance, CAS inputs
Input capacitance, W
pF
pF
pF
pF
pF
i(A)
i(R)
7
14
28
14
i(C)
14
7
i(W)
o(DQ)
Output capacitance on DQ0–DQ31
V = 5 V ± 0.5 V, and the bias on pins under test is 0 V.
CC
NOTE 5:
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE
TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS649A – DECEMBER 1994 – REVISED JUNE 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’124BBK32F-60 ’124BBK32F-70 ’124BBK32F-80
’248CBK32F-60 ’248CBK32F-70 ’248CBK32F-80
PARAMETER
UNIT
MIN
MAX
30
MIN
MAX
35
MIN
MAX
40
t
t
t
t
t
t
t
Access time from column address
Access time from CAS low
ns
ns
ns
ns
ns
ns
ns
AA
15
18
20
CAC
RAC
CPA
CLZ
OH
Access time from RAS low
60
70
80
Access time from column precharge
CAS to output in low-impedance state
Output disable time from start of CAS high
Output disable time after CAS high (see Note 6)
35
40
45
0
3
0
0
3
0
0
3
0
15
18
20
OFF
NOTE 6:
t
is specified when the output is no longer driven.
OFF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’124BBK32F-60 ’124BBK32F-70 ’124BBK32F-80
’248CBK32F-60 ’248CBK32F-70 ’248CBK32F-80
UNIT
MIN
110
155
40
MAX
MIN
130
181
45
MAX
MIN
150
205
50
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write (see Note 7)
Cycle time, read-write
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
RWC
PC
Cycle time, page-mode read or write (see Notes 7 and 8)
Pulse duration, page mode, RAS low
Pulse duration, nonpage mode, RAS low
Pulse duration, CAS low
60 100 000
70 100 000
80 100 000
RASP
RAS
CAS
CP
60
15
10
40
10
0
10 000
10 000
70
18
10
50
10
0
10 000
10 000
80
20
10
60
10
0
10 000
10 000
Pulse duration, CAS high
Pulse duration, RAS high (precharge)
Pulse duration, W low
RP
WP
Setup time, column address before CAS low
Setup time, row address before RAS low
Setup time, data before CAS low
ASC
ASR
DS
0
0
0
0
0
0
Setup time, W high before CAS low
Setup time, W low before CAS high
Setup time, W low before RAS high
Setup time, W low before CAS low
Setup time, W high before RAS low (CBR refresh only)
Hold time, column address after CAS low
Hold time, RAS high from CAS precharge
Hold time, data after CAS low
0
0
0
RCS
CWL
RWL
WCS
WRP
CAH
RHCP
DH
15
15
0
18
18
0
20
20
0
10
10
35
10
10
0
10
15
40
15
10
0
10
15
45
15
10
0
Hold time, row address after RAS low
Hold time, W high after CAS high (see Note 9)
Hold time, W high after RAS high (see Note 9)
RAH
RCH
RRH
0
0
0
NOTES: 7. All cycles assume t = 5 ns.
T
8. To assure t
min, t
should be ≥ t .
CP
PC
or t
ASC
must be satisfied for a read cycle.
RCH
9. Either t
RRH
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE
TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS649A – DECEMBER 1994 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’124BBK32F-60 ’124BBK32F-70 ’124BBK32F-80
’248CBK32F-60 ’248CBK32F-70 ’248CBK32F-80
UNIT
MIN
10
10
10
5
MAX
MIN
15
10
10
5
MAX
MIN
15
10
10
5
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Hold time, W low after CAS low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
WCH
WRH
CHR
CRP
CSH
CSR
RAD
RAL
CAL
RCD
RPC
RSH
REF
T
Hold time, W high after RAS low (CBR refresh only)
Delay time, RAS low to CAS high (CBR refresh only)
Delay time, CAS high to RAS low
Delay time, RAS low to CAS high
60
5
70
5
80
5
Delay time, CAS low to RAS low (CBR refresh only)
Delay time, RAS low to column address (see Note 10)
Delay time, column address to RAS high
Delay time, column address to CAS high
Delay time, RAS low to CAS low (see Note 10)
Delay time, RAS high to CAS low (CBR only)
Delay time, CAS low to RAS high
15
30
30
20
0
30
45
15
35
35
20
0
35
52
15
40
40
20
0
40
60
15
18
20
Refresh time interval
16
30
16
30
16
30
Transition time
3
3
3
NOTE 10: The maximum value is specified only to assure access time.
device symbolization (TM124BBK32F illustrated)
TM124BBK32F
-SS
YYMMT
YY = Year Code
MM = Month Code
T = Assembly Site Code
-SS = Speed Code
NOTE: Location of symbolization may vary.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE
TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS649A – DECEMBER 1994 – REVISED JUNE 1995
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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