TMP101NA/250 [TI]
Digital Temperature Sensor with I2C Interface; 数字温度传感器，具有I2C接口
| 型号： | TMP101NA/250 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Digital Temperature Sensor with I2C Interface |
| 文件： | 总14页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMP100
TMP101
SBOS231C – JANUARY 2002 – REVISED JULY 2003
Digital Temperature Sensor
with I2C Interface
FEATURES
DESCRIPTION
● DIGITAL OUTPUT: I2C Serial 2-Wire
The TMP100 and TMP101 are 2-wire, serial output tempera-
ture sensors available in SOT23-6 packages. Requiring no
external components, the TMP100 and TMP101 are capable
of reading temperatures with a resolution of 0.0625°C.
● RESOLUTION: 9- to 12-Bits, User-Selectable
● ACCURACY:
±
2.0
3.0
● LOW QUIESCENT CURRENT: 45
°
C from –25
°
C to +85
C to +125
A, 0.1
°
C (max)
C (max)
µA Standby
±
°
C from –55
°
°
The TMP100 and TMP101 feature SMBus and I2C™ inter-
face compatibility, with the TMP100 allowing up to eight
devices on one bus. The TMP101 offers SMBus alert func-
tion with up to three devices per bus.
µ
● WIDE SUPPLY RANGE: 2.7V to 5.5V
● TINY SOT23-6 PACKAGE
The TMP100 and TMP101 are ideal for extended tempera-
ture measurement in a variety of communication, computer,
consumer, environmental, industrial, and instrumentation
applications.
APPLICATIONS
● POWER-SUPPLY TEMPERATURE MONITORING
● COMPUTER PERIPHERAL THERMAL PROTECTION
● NOTEBOOK COMPUTERS
The TMP100 and TMP101 are specified for operation over a
temperature range of –55°C to +125°C.
I2C is a registered trademark of Philips Incorporated.
● CELL PHONES
● BATTERY MANAGEMENT
● OFFICE MACHINES
● THERMOSTAT CONTROLS
● ENVIRONMENTAL MONITORING and HVAC
● ELECTROMECHANICAL DEVICE TEMPERATURE
Temperature
Diode
Temperature
Diode
1
2
3
Control
Logic
6
5
4
1
2
3
Control
Logic
6
5
4
Temp.
Sensor
Temp.
Sensor
SCL
SDA
ADD0
V+
SCL
SDA
ADD0
V+
∆Σ
A/D
Converter
∆Σ
A/D
Converter
Serial
Interface
Serial
Interface
GND
GND
Config
and Temp
Register
Config
and Temp
Register
ADD1
ALERT
OSC
OSC
TMP100
TMP101
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2002-2003, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Power Supply, V+ ............................................................................... 7.5V
Input Voltage(2) .................................................................... –0.5V to 7.5V
Operating Temperature Range ......................................–55°C to +125°C
Storage Temperature Range .........................................–60°C to +150°C
Junction Temperature (TJ Max) .................................................... +150°C
Lead Temperature (soldering) ....................................................... +300°C
NOTES: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability. (2) Input voltage
rating applies to all TMP100 and TMP101 input voltages.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
SPECIFIED
PACKAGE
DESIGNATOR(1)
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
TMP100
SOT23-6
DBV
"
DBV
"
–55°C to +125°C
T100
TMP100NA/250
TMP100NA/3K
TMP101NA/250
TMP101NA/3K
Tape and Reel, 250
Tape and Reel, 3000
Tape and Reel, 250
Tape and Reel, 3000
"
TMP101
"
"
"
"
T101
"
SOT23-6
–55°C to +125°C
"
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PIN CONFIGURATIONS
Top View
SOT23 Top View
SOT23
1
2
3
1
2
3
SCL
GND
6
5
4
SDA
ADD0
V+
SCL
GND
6
5
4
SDA
ADD0
V+
ADD1
ALERT
TMP100
TMP101
TMP100, 101
2
SBOS231C
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ELECTRICAL CHARACTERISTICS
At TA = –55°C to +125°C, and V+ = 2.7V to 5.5V, unless otherwise noted.
TMP100, TMP101
TYP
PARAMETER
CONDITION
MIN
MAX
UNITS
TEMPERATURE INPUT
Range
Accuracy (Temperature Error)
–55
+125
±2.0
±3.0
°C
°C
°C
°C
–25°C to +85°C
–55°C to +125°C
Selectable
±0.5
±1.0
±0.0625
Resolution
DIGITAL INPUT/OUTPUT
Input Logic Levels:
VIH
0.7(V+)
–0.5
6.0
0.3(V+)
1
V
V
µA
VIL
Input Current, IIN
Output Logic Levels:
VOL SDA
VOL ALERT
Resolution
0V ≤ VIN ≤ 6V
IOL = 3mA
IOL = 4mA
Selectable
9-Bit
10-Bit
11-Bit
12-Bit
9-Bit
10-Bit
11-Bit
0
0
0.15
0.15
9 to 12
40
0.4
0.4
V
V
Bits
ms
ms
ms
ms
s/s
s/s
s/s
s/s
Conversion Time
75
80
150
300
600
160
320
25
12
6
Conversion Rate
12-Bit
3
POWER SUPPLY
Operating Range
Quiescent Current
2.7
5.5
75
V
IQ
Serial Bus Inactive
45
70
150
0.1
20
µA
µA
µA
µA
µA
µA
Serial Bus Active, SCL Freq = 400kHz
Serial Bus Active, SCL Freq = 3.4MHz
Serial Bus Inactive
Serial Bus Active, SCL Freq = 400kHz
Serial Bus Active, SCL Freq = 3.4MHz
Shutdown Current
ISD
1
100
TEMPERATURE RANGE
Specified Range
Storage Range
–55
–60
+125
+150
°C
°C
Thermal Resistance, θJA
SOT23-6 Surface-Mount
150
°C/W
TMP100, 101
3
SBOS231C
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TYPICAL CHARACTERISTICS
At TA = +25°C, V+ = 5.0V, unless otherwise noted.
QUIESCENT CURRENT vs TEMPERATURE
70
SHUTDOWN CURRENT vs TEMPERATURE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
–0.1
60
V+ = 5V
50
V+ = 2.7V
40
Serial Bus Inactive
30
–60 –40 –20
0
20
40
60
80 100 120 140
–60 –40 –20
0
20
40
60
80 100 120 140
Temperature (°C)
Temperature (°C)
CONVERSION TIME vs TEMPERATURE
TEMPERATURE ACCURACY vs TEMPERATURE
400
350
300
250
2.0
1.5
1.0
V+ = 5V
0.5
0.0
–0.5
–1.0
–1.5
–2.0
V+ = 2.7V
NOTE: 12-bit resolution.
3 Typical Units
NOTE: 12-bit resolution.
–60 –40 –20
0
20
40
60
80 100 120 140
–60 –40 –20
0
20
40
60
80 100 120 140
Temperature (°C)
Temperature (°C)
QUIESCENT CURRENT WITH
BUS ACTIVITY vs TEMPERATURE
180
160
140
120
100
80
125°C
25°C
125°C
25°C
–55°C
60
40
–55°C
20
FAST MODE
10k
Hs MODE
0
100k
1M
10M
SCL Frequency (Hz)
TMP100, 101
4
SBOS231C
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POINTER REGISTER
APPLICATIONS INFORMATION
Figure 3 shows the internal register structure of the TMP100
and TMP101. The 8-bit Pointer Register of the TMP100 and
TMP101 is used to address a given data register. The Pointer
Register uses the two LSBs to identify which of the data
registers should respond to a read or write command. Table
I identifies the bits of the Pointer Register byte. Table II
describes the pointer address of the registers available in the
TMP100 and TMP101. Power-up Reset value of P1/P0 is 00.
The TMP100 and TMP101 are digital temperature sensors
optimal for thermal management and thermal protection
applications. The TMP100 and TMP101 are I2C and SMBus
interface compatible and are specified over a temperature
range of –55°C to +125°C.
The TMP100 and TMP101 require no external components
for operation except for pull-up resistors on SCL, SDA, and
ALERT, although a 0.1µF bypass capacitor is recommended,
as shown in Figure 1 and Figure 2.
Pointer
Register
V+
Temperature
Register
0.1µF
4
3
5
ALERT
(Output)
SCL
SDA
1
6
SCL
Configuration
Register
To I2C
Controller
TMP101
I/O
Control
Interface
ADD0
(Input)
2
TLOW
Register
SDA
NOTE: (1) SCL, SDA and ALERT
require pull-up resistors for
I2C bus applications.
THIGH
Register
GND
FIGURE 1. Typical Connections of the TMP101.
FIGURE 3. Internal Register Structure of TMP100 and TMP101.
V+
P7
P6
P5
P4
P3
P2
P1
P0
0
0
0
0
0
0
Register Bits
TABLE I. Pointer Register Byte.
0.1µF
4
3
5
ADD1
(Input)
P1
P0
REGISTER
SCL
SDA
1
6
To I2C
Controller
0
0
1
1
0
1
0
1
Temperature Register (READ Only)
Configuration Register (READ/WRITE)
TLOW Register (READ/WRITE)
TMP100
ADD0
(Input)
THIGH Register (READ/WRITE)
2
TABLE II. Pointer Addresses of the TMP100 and TMP101
Registers.
NOTE: (1) SCL and SDA
require pull-up resistors for
I2C bus applications.
TEMPERATURE REGISTER
GND
The Temperature Register of the TMP100 or TMP101 is a 12-
bit read-only register that stores the output of the most recent
conversion. Two bytes must be read to obtain data and are
described in Table III and Table IV. The first 12 bits are used
to indicate temperature with all remaining bits equal to zero.
Data format for temperature is summarized in Table V.
Following power-up or reset, the Temperature Register will
read 0°C until the first conversion is complete.
FIGURE 2. Typical Connections of the TMP100.
The die flag of the lead frame is connected to pin 2. The
sensing device of the TMP100 and TMP101 is the chip itself.
Thermal paths run through the package leads as well as the
plastic package. The lower thermal resistance of metal causes
the leads to provide the primary thermal path. The GND pin
of the TMP100 or TMP101 is directly connected to the metal
lead frame, and is the best choice for thermal input.
D7
D6
D5
D4
D3
D2
D1
D0
To maintain the accuracy in applications requiring air or
surface temperature measurement, care should be taken to
isolate the package and leads from ambient air temperature.
A thermally conductive adhesive will assist in achieving
accurate surface temperature measurement.
T11
T10
T9
T8
T7
T6
T5
T4
TABLE III. Byte 1 of Temperature Register.
D7
D6
D5
D4
D3
D2
D1
D0
T3
T2
T1
T0
0
0
0
0
TABLE IV. Byte 2 of Temperature Register.
TMP100, 101
5
SBOS231C
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TEMPERATURE
DIGITAL OUTPUT
(BINARY)
(°C)
HEX
128
127.9375
100
0111 1111 1111
0111 1111 1111
0110 0100 0000
0101 0000 0000
0100 1011 0000
0011 0010 0000
0001 1001 0000
0000 0000 0100
0000 0000 0000
1111 1111 1100
1110 0111 0000
1100 1001 0000
1000 0000 0000
7FF
7FF
640
500
4B0
320
190
004
000
FFC
E70
C90
800
THIGH
Measured
Temperature
80
75
50
25
0.25
0.0
–0.25
–25
–55
–128
TLOW
TMP101 ALERT PIN
(Comparator Mode)
POL = 0
TMP101 ALERT PIN
(Interrupt Mode)
POL = 0
TABLE V. Temperature Data Format.
TMP101 ALERT PIN
(Comparator Mode)
POL = 1
The user can obtain 9, 10, 11, or 12 bits of resolution by
addressing the Configuration Register and setting the reso-
lution bits accordingly. For 9, 10, or 11 bit resolution, the most
significant bits in the Temperature Register are used with the
unused LSBs set to zero.
TMP101 ALERT PIN
(Interrupt Mode)
POL = 1
Read
Read
Time
Read
CONFIGURATION REGISTER
FIGURE 4. Output Transfer Function Diagrams.
The Configuration Register is an 8-bit read/write register
used to store bits that control the operational modes of the
temperature sensor. Read/write operations are performed
MSB first. The format of the Configuration Register for the
TMP100 and TMP101 is shown in Table VI, followed by a
breakdown of the register bits. The power-up/reset value of
the Configuration Register is all bits equal to 0. The OS/
ALERT bit will read as 1 after power-up/reset.
FAULT QUEUE (F1/F0)
A fault condition occurs when the measured temperature
exceeds the limits set in the THIGH and TLOW Registers. The
Fault Queue is provided to prevent a false alert due to
environmental noise and requires consecutive fault mea-
surements to trigger the alert function of the TMP101. Table
VII defines the number of measured faults that may be
programmed to trigger an alert condition.
Byte
D7
D6
D5
D4
D3
D2
D1
D0
1
OS/ALERT
R1
R0
F1
F0
POL
TM
SD
F1
F0
CONSECUTIVE FAULTS
0
0
1
1
0
1
0
1
1
2
4
6
TABLE VI. Configuration Register Format.
SHUTDOWN MODE (SD)
The Shutdown Mode of the TMP100 and TMP101 allows the
user to save maximum power by shutting down all device
circuitry other than the serial interface, which reduces current
consumption to less than 1µA. For the TMP100 and TMP101,
Shutdown Mode is enabled when the SD bit is 1. The device will
shutdown once the current conversion is completed. For SD
equal to 0, the device will maintain continuous conversion.
TABLE VII. Fault Settings of the TMP100 and TMP101.
CONVERTER RESOLUTION (R1/R0)
The Converter Resolution Bits control the resolution of the
internal Analog-to-Digital (A/D) converter. This allows the
user to maximize efficiency by programming for higher reso-
lution or faster conversion time. Table VIII identifies the
Resolution Bits and relationship between resolution and con-
version time.
THERMOSTAT MODE (TM)
The Thermostat Mode bit of the TMP101 indicates to the device
whether to operate in Comparator Mode (TM = 0) or Interrupt
Mode (TM = 1). For more information on comparator and
interrupt modes, see text “HIGH and LOW Limit Registers.”
CONVERSION TIME
R1
R0
RESOLUTION
(typical)
0
0
1
1
0
1
0
1
9 Bits (0.5°C)
10 Bits (0.25°C)
11 Bits (0.125°C)
12 Bits (0.0625°C)
40ms
80ms
160ms
320ms
POLARITY (POL)
The Polarity Bit of the TMP101 allows the user to adjust the
polarity of the ALERT pin output. If POL = 0, the ALERT pin
will be active LOW, as shown in Figure 4. For POL = 1 the
ALERT Pin will be active HIGH, and the state of the ALERT
Pin is inverted.
TABLE VIII. Resolution of the TMP100 and TMP101.
TMP100, 101
6
SBOS231C
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OS/ALERT (OS)
Byte
D7
D6
D5
D4
D3
D2
D1
D0
1
H11
H10
H9
H8
H7
H6
H5
H4
The TMP100 and TMP101 feature a One-Shot Temperature
Measurement Mode. When the device is in Shutdown Mode,
writing a 1 to the OS/ALERT bit will start a single temperature
conversion. The device will return to the shutdown state at
the completion of the single conversion. This is useful to
reduce power consumption in the TMP100 and TMP101
when continuous monitoring of temperature is not required.
Byte
D7
D6
D5
D4
D3
D2
D1
D0
2
H3
H2
H1
H0
0
0
0
0
TABLE IX. Bytes 1 and 2 of THIGH Register.
Byte
D7
D6
D5
D4
D3
D2
D1
D0
Reading the OS/ALERT bit will provide information about the
Comparator Mode status. The state of the POL bit will invert the
polarity of data returned from the OS/ALERT bit. For POL = 0,
the OS/ALERT will read as 0 until the temperature equals or
exceeds THIGH for the programmed number of consecutive
faults, causing the OS/ALERT bit to read as 1. The OS/ALERT
bit will continue to read as 1 until the temperature falls below
1
L11
L10
L9
L8
L7
L6
L5
L4
Byte
D7
D6
D5
D4
D3
D2
D1
D0
2
L3
L2
L1
L0
0
0
0
0
TABLE X. Bytes 1 and 2 of TLOW Register.
SERIAL INTERFACE
TLOW for the programmed number of consecutive faults when it
The TMP100 and TMP101 operate only as slave devices on
the I2C bus and SMBus. Connections to the bus are made via
the open-drain I/O lines SDA and SCL. The TMP100 and
TMP101 support the transmission protocol for fast (up to
400kHz) and high-speed (up to 3.4MHz) modes. All data
bytes are transmitted most significant bit first.
will again read as 0. The status of the TM bit does not affect the
status of the OS/ALERT bit.
HIGH AND LOW LIMIT REGISTERS
In Comparator Mode (TM = 0), the ALERT Pin of the TMP101
becomes active when the temperature equals or exceeds the
value in THIGH and generates a consecutive number of faults
according to fault bits F1 and F0. The ALERT pin will remain
active until the temperature falls below the indicated TLOW
value for the same number of faults.
SERIAL BUS ADDRESS
To program the TMP100 and TMP101, the master must first
address slave devices via a slave address byte. The slave
address byte consists of seven address bits, and a direction
bit indicating the intent of executing a read or write operation.
In Interrupt Mode (TM = 1) the ALERT Pin becomes active
when the temperature equals or exceeds THIGH for a con-
secutive number of fault conditions. The ALERT pin remains
active until a read operation of any register occurs or the
device successfully responds to the SMBus Alert Response
Address. The ALERT pin will also be cleared if the device is
placed in Shutdown Mode. Once the ALERT pin is cleared,
it will only become active again by the temperature falling
below TLOW. When the temperature falls below TLOW, the
ALERT pin will become active and remain active until cleared
by a read operation of any register or a successful response
to the SMBus Alert Response Address. Once the ALERT pin
is cleared, the above cycle will repeat with the ALERT pin
becoming active when the temperature equals or exceeds
The TMP100 features two address pins to allow up to eight
devices to be addressed on a single I2C interface. Table XI
describes the pin logic levels used to properly connect up to eight
devices. ‘Float’ indicates the pin is left unconnected. The state of
pins ADD0 and ADD1 is sampled on the first I2C bus communi-
cation and should be set prior to any activity on the interface.
ADD1
ADD0
SLAVE ADDRESS
0
0
0
1
1
1
Float
Float
0
Float
1
0
Float
1
0
1
1001000
1001001
1001010
1001100
1001101
1001110
1001011
1001111
T
HIGH. The ALERT pin can also be cleared by resetting the
device with the General Call Reset command. This will also
clear the state of the internal registers in the device returning
the device to Comparator Mode (TM = 0).
TABLE XI. Address Pins and Slave Addresses for TMP100.
Both operational modes are represented in the Figure 4. Tables
IX and X describe the format for the THIGH and TLOW registers.
Power-up Reset values for THIGH and TLOW are: THIGH = 80°C
and TLOW = 75°C. The format of the data for THIGH and TLOW
is the same as for the Temperature Register.
The TMP101 features one address pin and an ALERT pin,
allowing up to three devices to be connected per bus. Pin logic
levels are described in Table XII. The address pins of the
TMP100 and TMP101 are read after reset or in response to an
I2C address acquire request. Following reading, the state of
the address pins is latched to minimize power dissipation
associated with detection.
All 12 bits for the Temperature, THIGH, and TLOW registers are
used in the comparisons for the ALERT function for all con-
verter resolutions. The three LSBs in THIGH and TLOW can
affect the ALERT output even if the converter is configured for
9-bit resolution.
ADD0
SLAVE ADDRESS
0
Float
1
1001000
1001001
1001010
TABLE XII. Address Pins and Slave Address for TMP101.
TMP100, 101
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SBOS231C
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BUS OVERVIEW
byte or bytes are written to the register addressed by the Pointer
register. The TMP100 and TMP101 will acknowledge recep-
tion of each data byte. The master may terminate data
transfer by generating a START or STOP condition.
The device that initiates the transfer is called a “master,” and
the devices controlled by the master are “slaves.” The bus
must be controlled by a master device that generates the
serial clock (SCL), controls the bus access, and generates
the START and STOP conditions.
Slave Transmitter Mode:
The first byte is transmitted by the master and is the slave
address, with the R/W bit HIGH. The slave acknowledges
reception of a valid slave address. The next byte is transmit-
ted by the slave and is the most significant byte of the
register indicated by the Pointer Register. The master ac-
knowledges reception of the data byte. The next byte trans-
mitted by the slave is the least significant byte. The master
acknowledges reception of the data byte. The master may
terminate data transfer by generating a Not-Acknowledge on
reception of any data byte, or generating a START or STOP
condition.
To address a specific device, a START condition is initiated,
indicated by pulling the data-line (SDA) from a HIGH to LOW
logic level while SCL is HIGH. All slaves on the bus shift in the
slave address byte, with the last bit indicating whether a read
or write operation is intended. During the ninth clock pulse,
the slave being addressed responds to the master by gener-
ating an Acknowledge and pulling SDA LOW.
Data transfer is then initiated and sent over eight clock pulses
followed by an Acknowledge Bit. During data transfer SDA
must remain stable while SCL is HIGH, as any change in SDA
while SCL is HIGH will be interpreted as a control signal.
SMBus ALERT FUNCTION
Once all data has been transferred, the master generates a
STOP condition indicated by pulling SDA from LOW to HIGH,
while SCL is HIGH.
The TMP101 supports the SMBus Alert function. When the
TMP101 is operating in Interrupt Mode (TM = 1), the ALERT
pin of the TMP101 may be connected as an SMBus Alert
signal. When a master senses that an ALERT condition is
present on the ALERT line, the master sends an SMBus Alert
command (00011001) on the bus. If the ALERT pin of the
TMP101 is active, the TMP101 will acknowledge the SMBus
Alert command and respond by returning its slave address
on the SDA line. The eighth bit (LSB) of the slave address
byte will indicate if the temperature exceeding THIGH or falling
below TLOW caused the ALERT condition. This bit will be
WRITING/READING TO THE TMP100 AND TMP101
Accessing a particular register on the TMP100 and TMP101
is accomplished by writing the appropriate value to the
Pointer Register. The value for the Pointer Register is the
first byte transferred after the I2C slave address byte with the
R/W bit LOW. Every write operation to the TMP100 and
TMP101 requires a value for the Pointer Register. (Refer to
Figure 6.)
HIGH if the temperature is greater than or equal to THIGH
This bit will be LOW if the temperature is less than TLOW
Refer to Figure 8 for details of this sequence.
.
.
When reading from the TMP100 and TMP101, the last value
stored in the Pointer Register by a write operation is used to
determine which register is read by a read operation. To
change the register pointer for a read operation, a new value
must be written to the Pointer Register. This is accomplished
by issuing an I2C slave address byte with the R/W bit LOW,
followed by the Pointer Register Byte. No additional data is
required. The master can then generate a START condition
and send the I2C slave address byte with the R/W bit HIGH
to initiatnlthe read command. See Figure 7 for details of this
sequence. If repeated reads from the same register are
desired, it is not necessary to continually send the Pointer
Register bytes as the TMP100 and TMP101 will remember
the Pointer Register value until it is changed by the next write
operation.
If multiple devices on the bus respond to the SMBus Alert
command, arbitration during the slave address portion of the
SMBus alert command will determine which device will clear
its ALERT status. If the TMP101 wins the arbitration, its
ALERT pin will become inactive at the completion of the
SMBus Alert command. If the TMP101 loses the arbitration,
its ALERT pin will remain active.
The TMP100 will also respond to the SMBus ALERT com-
mand if its TM bit is set to 1. Since it does not have an ALERT
pin, the master needs to periodically poll the device by
issuing an SMBus Alert command. If the TMP100 has gen-
erated an ALERT, it will acknowledge the SMBus Alert
command and return its slave address in the next byte.
SLAVE MODE OPERATIONS
GENERAL CALL
The TMP100 and TMP101 can operate as slave receivers or
slave transmitters.
The TMP100 and TMP101 respond to the I2C General Call
address (0000000) if the eighth bit is 0. The device will
acknowledge the General Call address and respond to com-
mands in the second byte. If the second byte is 00000100,
the TMP100 and TMP101 will latch the status of their
address pins, but will not reset. If the second byte is 00000110,
the TMP100 and TMP101 will latch the status of their
address pins and reset their internal registers.
Slave Receiver Mode:
The first byte transmitted by the master is the slave address, with
the R/W bit LOW. The TMP100 or TMP101 then acknowledges
reception of a valid address. The next byte transmitted by the
master is the Pointer Register. The TMP100 or TMP101 then
acknowledges reception of the Pointer Register byte. The next
TMP100, 101
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SBOS231C
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Start Data Transfer: A change in the state of the SDA line,
from HIGH to LOW, while the SCL line is HIGH, defines a
START condition. Each data transfer is initiated with a
START condition.
HIGH-SPEED MODE
In order for the I2C bus to operate at frequencies above
400kHz, the master device must issue an Hs-mode master
code (00001XXX) as the first byte after a START condition to
switch the bus to high-speed operation. The TMP100 and
TMP101 will not acknowledge this byte as required by the I2C
specification, but will switch their input filters on SDA and
SCL and their output filters on SDA to operate in Hs-mode,
allowing transfers at up to 3.4MHz. After the Hs-mode master
code has been issued, the master will transmit an I2C slave
address to initiate a data transfer operation. The bus will
continue to operate in Hs-mode until a STOP condition
occurs on the bus. Upon receiving the STOP condition, the
TMP100 and TMP101 will switch their input and output filters
back to fast-mode operation.
Stop Data Transfer: A change in the state of the SDA line
from LOW to HIGH while the SCL line is HIGH defines a
STOP condition. Each data transfer is terminated with a
repeated START or STOP condition.
Data Transfer: The number of data bytes transferred be-
tween a START and a STOP condition is not limited and is
determined by the master device. The receiver acknowl-
edges the transfer of data.
Acknowledge: Each receiving device, when addressed, is
obliged to generate an Acknowledge bit. A device that
acknowledges must pull down the SDA line during the
Acknowledge clock pulse in such a way that the SDA line is
stable LOW during the HIGH period of the Acknowledge
clock pulse. Setup and hold times must be taken into ac-
count. On a master receive, the termination of the data
transfer can be signaled by the master generating a Not-
Acknowledge on the last byte that has been transmitted by
the slave.
TIMING DIAGRAMS
The TMP100 and TMP101 are I2C and SMBus compatible.
Figures 5 to 8 describe the various operations on the TMP100
and TMP101. Bus definitions are given below. Parameters
for Figure 5 are defined in Table XIII.
Bus Idle: Both SDA and SCL lines remain HIGH.
FAST MODE
HIGH-SPEED MODE
PARAMETER
MIN
MAX
MIN
MAX
UNITS
MHz
ns
SCLK Operating Frequency
f(SCLK)
0.4
3.4
Bus Free Time Between STOP and START Condition t(BUF)
600
600
160
160
Hold Time After Repeated START Condition.
After this period, the first clock is generated.
t(HDSTA)
ns
Repeated START Condition Setup Time
STOP Condition Setup Time
Data Hold Time
t(SUSTA)
t(SUSTO)
t(HDDAT)
t(SUDAT)
t(LOW)
t(HIGH)
tF
600
600
0
160
160
0
ns
ns
ns
ns
ns
ns
ns
ns
Data Setup Time
100
1300
600
10
SCLK Clock LOW Period
SCLK Clock HIGH Period
Clock/Data Fall Time
160
60
300
300
160
160
Clock/Data Rise Time
tR
TABLE XIII. Timing Diagram Definitions.
TMP100, 101
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SBOS231C
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I2C TIMING DIAGRAMS
t(LOW)
tF
tR
t(HDSTA)
SCL
t(SUSTO)
t(HDSTA)
t(HIGH) t(SUSTA)
t(HDDAT)
t(SUDAT)
SDA
t(BUF)
P
S
S
P
FIGURE 5. I2C Timing Diagram.
1
9
1
9
SCL
…
…
SDA
1
1
0
0
1
A2
A1
A0 R/W
0
0
0
0
0
0
P1
P0
ACK By
Start By
Master
ACK By
TMP100 or TMP101
TMP100 or TMP101
Frame 1 I2C Slave Address Byte
Frame 2 Pointer Register Byte
9
1
9
SCL
(Continued)
SDA
(Continued)
D7 D6
D5
D4 D3
D2 D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
ACK By
ACK By
Stop By
TMP100 or TMP101
TMP100 or TMP101 Master
Frame 3 Data Byte 1
Frame 4 Data Byte 2
FIGURE 6. I2C Timing Diagram for Write Word Format.
TMP100, 101
10
SBOS231C
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1
9
1
9
…
…
SCL
SDA
1
0
0
1
A2
A1
A0
R/W
0
0
0
0
0
0
P1
P0
Start By
Master
ACK By
TMP100 or TMP101
ACK By
TMP100 or TMP101
Frame 1 I2C Slave Address Byte
Frame 2 Pointer Register Byte
1
9
1
9
SCL
(Continued)
…
SDA
(Continued)
…
1
0
0
1
A2
A1
A0 R/W
D7
D6
D5
D4 D3
D2
D1
D0
Start By
Master
ACK By
TMP100 or TMP101
From
TMP100 or TMP101
ACK By
Master
Frame 3 I2C Slave Address Byte
Frame 4 Data Byte 1 Read Register
1
9
SCL
(Continued)
SDA
(Continued)
D7 D6
D5
D4
D3
D2
D1
D0
From
TMP100 or TMP101
ACK By
Master
Stop By
Master
Frame 5 Data Byte 2 Read Register
FIGURE 7. I2C Timing Diagram for Read Word Format.
ALERT
1
9
1
9
SCL
SDA
0
0
0
1
1
0
0
R/W
1
0
0
1
A2
A1
A0 Status
Start By
Master
ACK By
TMP100 or TMP101
From
NACK By Stop By
Master
TMP100 or TMP101 Master
Frame 1 SMBus ALERT Response Address Byte
Frame 2 Slave Address From TMP100
FIGURE 8. Timing Diagram for SMBus ALERT.
TMP100, 101
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SBOS231C
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
TMP100NA/250
TMP100NA/3K
TMP101NA/250
TMP101NA/3K
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOP
SOP
SOP
SOP
DBV
DBV
DBV
DBV
6
6
6
6
250
3000
250
3000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Copyright 2003, Texas Instruments Incorporated
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