TMS320F28022PTQ_技术文档

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

Piccolo Microcontrollers

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Samples: TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200

1 TMS320F2802x, TMS320F2802xx ( Piccolo™) MCUs

1.1 Features

123

– Integrated Power-on and Brown-out Resets

– Small Packaging, as Low as 38-Pin Available

– Low Power

• Highlights

– High-Efficiency 32-Bit CPU ( TMS320C28x™)

– 60-MHz, 50-MHz, and 40-MHz Devices

– Single 3.3-V Supply

– No Analog Support Pins

• Clocking:

– Integrated Power-on and Brown-out Resets

– Two Internal Zero-pin Oscillators

– Up to 22 Multiplexed GPIO Pins

– Three 32-Bit CPU Timers

– On-Chip Flash, SARAM, OTP Memory

– Code-security Module

– Two Internal Zero-pin Oscillators

– On-Chip Crystal Oscillator/External Clock

Input

– Dynamic PLL Ratio Changes Supported

– Watchdog Timer Module

– Missing Clock Detection Circuitry

– Serial Port Peripherals (SCI/SPI/I2C)

– Enhanced Control Peripherals

• Up to 22 Individually Programmable,

Multiplexed GPIO Pins With Input Filtering

• Peripheral Interrupt Expansion (PIE) Block That

Supports All Peripheral Interrupts

• Three 32-Bit CPU Timers

• Independent 16-Bit Timer in Each ePWM

Module

•

Enhanced Pulse Width Modulator (ePWM)

High-Resolution PWM (HRPWM)

Enhanced Capture (eCAP)

Analog-to-Digital Converter (ADC)

On-Chip Temperature Sensor

Comparator

• On-Chip Memory

– 38-Pin and 48-Pin Packages

• High-Efficiency 32-Bit CPU ( TMS320C28x™)

– 60 MHz (16.67-ns Cycle Time)

– 50 MHz (20-ns Cycle Time)

– Flash, SARAM, OTP, Boot ROM Available

• 128-Bit Security Key/Lock

– Protects Secure Memory Blocks

– Prevents Firmware Reverse Engineering

• Serial Port Peripherals

– 40 MHz (25-ns Cycle Time)

– 16 x 16 and 32 x 32 MAC Operations

– 16 x 16 Dual MAC

– Harvard Bus Architecture

– Atomic Operations

– One SCI (UART) Module

– One SPI Module

– One Inter-Integrated-Circuit (I2C) Bus

• Advanced Emulation Features

– Analysis and Breakpoint Functions

– Real-Time Debug via Hardware

• 2802x, 2802xx Packages

– Fast Interrupt Response and Processing

– Unified Memory Programming Model

– Code-Efficient (in C/C++ and Assembly)

• Low Device and System Cost:

– Single 3.3-V Supply

– 38-Pin DA Plastic Small-Outline Package

(PSOP)

– No Power Sequencing Requirement

– 48-Pin PT Plastic Quad Flatpack (PQFP)

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Piccolo, TMS320C28x, C28x, TMS320C2000, Code Composer Studio, XDS510, XDS560 are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

2

3

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

www.ti.com

1.2 Description

The F2802x Piccolo™ family of microcontrollers provides the power of the C28x™ core coupled with

highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous

C28x-based code, as well as providing a high level of analog integration.

An internal voltage regulator allows for single rail operation. Enhancements have been made to the

HRPWM module to allow for dual-edge control (frequency modulation). Analog comparators with internal

10-bit references have been added and can be routed directly to control the PWM outputs. The ADC

converts from 0 to 3.3-V fixed full scale range and supports ratio-metric V_REFHI/V_REFLOreferences. The

ADC interface has been optimized for low overhead/latency.

1.3 Getting Started

This section gives a brief overview of the steps to take when first developing for a C28x device. For more

detail on each of these steps, see the following:

•

Getting Started With TMS320C28x Digital Signal Controllers (literature number SPRAAM0).

C2000 Getting Started Website (http://www.ti.com/c2000getstarted)

TMS320F28x MCU Development and Experimenter's Kits (http://www.ti.com/f28xkits)

2

TMS320F2802x, TMS320F2802xx ( Piccolo™) MCUs

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TMS320F28020 TMS320F280200

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

1

TMS320F2802x, TMS320F2802xx ( Piccolo™)

MCUs ...................................................... 1

1.1 Features .............................................. 1

1.2 Description ........................................... 2

1.3 Getting Started ....................................... 2

Introduction .............................................. 4

2.1 Pin Assignments ..................................... 6

4.7 Enhanced Capture Module (eCAP1) ............... 66

4.8 JTAG Port .......................................... 68

4.9 GPIO MUX .......................................... 69

5

6

Device Support ......................................... 74

5.1

Device and Development Support Tool

2

3

Nomenclature ....................................... 74

5.2 Related Documentation ............................. 76

5.3 Community Resources ............................. 77

Electrical Specifications ............................. 78

2.2 Signal Descriptions .................................. 8

Functional Overview .................................. 13

3.1 Block Diagram ...................................... 13

3.2 Memory Maps ...................................... 14

3.3 Brief Descriptions ................................... 22

6.1 Absolute Maximum Ratings ........................ 78

6.2 Recommended Operating Conditions .............. 78

6.3 Electrical Characteristics ........................... 79

6.4 Current Consumption ............................... 80

3.4 Register Map ....................................... 30

3.5 Device Emulation Registers ........................ 31

3.6 Interrupts ............................................ 32

3.7 VREG/BOR/POR ................................... 36

3.8 System Control ..................................... 38

6.5 Thermal Design Considerations .................... 85

6.6

Emulator Connection Without Signal Buffering for

the MCU ............................................ 85

6.7 Timing Parameter Symbology ...................... 86

6.8

Clock Requirements and Characteristics ........... 90

3.9 Low-power Modes Block ........................... 46

Peripherals .............................................. 47

4.1 Analog Block ........................................ 47

4

6.9 Power Sequencing ................................. 91

6.10 General-Purpose Input/Output (GPIO) ............. 93

6.11 Enhanced Control Peripherals .................... 100

6.12 Detailed Descriptions .............................. 118

6.13 Flash Timing ....................................... 119

4.2

Serial Peripheral Interface (SPI) Module ........... 53

Serial Communications Interface (SCI) Module .... 56

4.3

4.4 Inter-Integrated Circuit (I2C) ........................ 59

Enhanced PWM Modules (ePWM1/2/3/4) .......... 61

4.6 High-Resolution PWM (HRPWM) .................. 65

7

8

Revision History ...................................... 121

Thermal/Mechanical Data .......................... 123

4.5

Contents

3

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TMS320F28020 TMS320F280200

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

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2 Introduction

Table 2-1 lists the features of the TMS320F2802x devices.

4

Introduction

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TMS320F28020 TMS320F280200

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

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2.1 Pin Assignments

Figure 2-1 shows the 48-pin PT plastic quad flatpack (PQFP) pin assignments. Figure 2-2 shows the

38-pin DA plastic small outline package (PSOP) pin assignments.

GPIO2/EPWM2A 37

GPIO3/EPWM2B/COMP2OUT 38

GPIO4/EPWM3A 39

24 GPIO18/SPICLKA/SCITXDA/XCLKOUT

23 GPIO38/XCLKIN (TCK)

22 GPIO37 (TDO)

GPIO5/EPWM3B/ECAP1 40

21 GPIO36 (TMS)

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO 41

GPIO7/EPWM4B/SCIRXDA 42

20 GPIO35 (TDI)

19 GPIO34/COMP2OUT

18 ADCINB7

V_DD

V_SS

43

44

17 ADCINB6/AIO14

16 ADCINB4/COMP2B/AIO12

15 ADCINB3

X1 45

X2 46

GPIO12/TZ1/SCITXDA 47

GPIO28/SCIRXDA/SDAA/TZ2 48

14 ADCINB2/COMP1B/AIO10

13 ADCINB1

Figure 2-1. 2802x 48-Pin PT PQFP (Top View)

6

Introduction

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TMS320F28020 TMS320F280200

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

V_DD

V_SS

1

38 TEST

2

37 GPIO0/EPWM1A

VREGENZ

V_DDIO

3

36 GPIO1/EPWM1B/COMP1OUT

35 GPIO16/SPISIMOA/TZ2

34 GPIO17/SPISOMIA/TZ3

33 GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1

32 GPIO18/SPICLKA/SCITXDA/XCLKOUT

31 GPIO38/XCLKIN (TCK)

30 GPIO37 (TDO)

4

GPIO2/EPWM2A

GPIO3/EPWM2B

5

6

GPIO4/EPWM3A

7

GPIO5/EPWM3B/ECAP1

8

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO

GPIO7/EPWM4B/SCIRXDA

V_DD

9

10

11

12

13

14

15

16

17

18

19

29 GPIO36 (TMS)

28 GPIO35 (TDI)

V_SS

27 GPIO34

GPIO12/TZ1/SCITXDA

GPIO28/SCIRXDA/SDAA/TZ2

GPIO29/SCITXDA/SCLA/TZ3

26 ADCINB6/AIO14

25 ADCINB4/AIO12

24 ADCINB2/COMP1B/AIO10

/V_REFLO

23 V_SSA

22 V_DDA

TRST

XRS

ADCINA6/AIO6

ADCINA4/AIO4

21 ADCINA0/V_REFHI

20 ADCINA2/COMP1A/AIO2

Figure 2-2. 2802x 38-Pin DA PSOP (Top View)

Introduction

7

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TMS320F28020 TMS320F280200

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

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2.2 Signal Descriptions

Table 2-2 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at

reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate

functions. Some peripheral functions may not be available in all devices. See Table 2-1 for details. Inputs

are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively

enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM

pins are not enabled at reset. The pullups on other GPIO pins are enabled upon reset. The AIO pins do

not have an internal pullup.

NOTE: When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38

pins could glitch during power up. If this is unacceptable in an application, 1.8 V could be supplied

externally. There is no power-sequencing requirement when using an external 1.8-V supply. However, if

the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered prior to the 1.9-V

transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power

up. To avoid this behavior, power the V_DDpins prior to or simultaneously with the V_DDIOpins, ensuring that

the V_DDpins have reached 0.7 V before the V_DDIOpins reach 0.7 V.

Table 2-2. TERMINAL FUNCTIONS⁽¹⁾

TERMINAL

I/O/Z

DESCRIPTION

PT

PIN #

DA

PIN #

NAME

JTAG

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan

system control of the operations of the device. If this signal is not connected or driven

low, the device operates in its functional mode, and the test reset signals are ignored.

NOTE: TRST is an active high test pin and must be maintained low at all times during

normal device operation. An external pulldown resistor is required on this pin. The

value of this resistor should be based on drive strength of the debugger pods

applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since

this is application-specific, it is recommended that each target board be validated for

proper operation of the debugger and the application. (↓)

TRST

2

16

I

TCK

TMS

See GPIO38

See GPIO36

I

See GPIO38. JTAG test clock with internal pullup (↑)

See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control

input is clocked into the TAP controller on the rising edge of TCK. (↑)

See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the

selected register (instruction or data) on a rising edge of TCK. (↑)

TDI

See GPIO35

See GPIO37

I

See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected

register (instruction or data) are shifted out of TDO on the falling edge of TCK.

(8-mA drive)

TDO

O/Z

FLASH

TEST

30

38

I/O

Test Pin. Reserved for TI. Must be left unconnected.

CLOCK

See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same

frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This

is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT =

SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV

to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to

propogate to the pin.

XCLKOUT

See GPIO18

O/Z

See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is

controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default

selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1

pin, if available, must be tied to GND and the on-chip crystal oscillator must be

disabled via bit 14 in the CLKCTL register. If a crystal/resonator is used, the XCLKIN

path must be disabled by bit 13 in the CLKCTL register.

NOTE: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock for

normal device operation may need to incorporate some hooks to disable this path

during debug using the JTAG connector. This is to prevent contention with the TCK

signal, which is active during JTAG debug sessions. The zero-pin internal oscillators

may be used during this time to clock the device.

See GPIO19 and

GPIO38

XCLKIN

I

(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown

Introduction

8

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TMS320F28021, TMS320F28020, TMS320F280200

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

Table 2-2. TERMINAL FUNCTIONS (continued)

TERMINAL

I/O/Z

DESCRIPTION

PT

PIN #

DA

PIN #

NAME

On-chip crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic

resonator must be connected across X1 and X2. In this case, the XCLKIN path must

be disabled by bit 13 in the CLKCTL register. If this pin is not used, it must be tied to

GND. (I)

X1

X2

45

46

–

I

On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be

connected across X1 and X2. If X2 is not used, it must be left unconnected. (O)

O

RESET

Device Reset (in) and Watchdog Reset (out). Piccolo devices have a built-in

power-on-reset (POR) and brown-out-reset (BOR) circuitry. As such, no external

circuitry is needed to generate a reset pulse. During a power-on or brown-out

condition, this pin is driven low by the device. See Section 6.3, Electrical

Characteristics, for thresholds of the POR/BOR block. This pin is also driven low by

the MCU when a watchdog reset occurs. During watchdog reset, the XRS pin is driven

low for the watchdog reset duration of 512 OSCCLK cycles. If need be, an external

circuitry may also drive this pin to assert a device reset. In this case, it is

recommended that this pin be driven by an open-drain device. An R-C circuit must be

connected to this pin for noise immunity reasons. Regardless of the source, a device

reset causes the device to terminate execution. The program counter points to the

address contained at the location 0x3FFFC0. When reset is deactivated, execution

begins at the location designated by the program counter. The output buffer of this pin

is an open-drain with an internal pullup. (I/OD)

XRS

3

17

I/OD

ADC, COMPARATOR, ANALOG I/O

ADCINA7

6

4

–

I

ADC Group A, Channel 7 input

ADCINA6

AIO6

I

ADC Group A, Channel 6 input

Digital AIO 6

18

I/O

ADCINA4

COMP2A

AIO4

I

ADC Group A, Channel 4 input

Comparator Input 2A (available in 48-pin device only)

Digital AIO 4

5

7

19

–

I/O

ADCINA3

I

ADC Group A, Channel 3 input

ADCINA2

COMP1A

AIO2

I

ADC Group A, Channel 2 input

Comparator Input 1A

Digital AIO 2

9

20

–

I/O

ADCINA1

8

I

ADC Group A, Channel 1 input

ADC Group A, Channel 0 input

ADC External Reference – only used when in ADC external reference mode. See

Section 4.1.1, ADC.

ADCINA0

V_REFHI

I

10

21

ADCINB7

18

17

–

I

ADC Group B, Channel 7 input

ADCINB6

AIO14

I

ADC Group B, Channel 6 input

Digital AIO 14

26

I/O

ADCINB4

COMP2B

AIO12

I

ADC Group B, Channel 4 input

Comparator Input 2B (available in 48-pin device only)

Digital AIO12

16

15

14

13

25

–

I/O

ADCINB3

I

ADC Group B, Channel 3 input

ADCINB2

COMP1B

AIO10

I

ADC Group B, Channel 2 input

Comparator Input 1B

Digital AIO 10

24

–

I/O

ADCINB1

I

ADC Group B, Channel 1 input

Introduction

9

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TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

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Table 2-2. TERMINAL FUNCTIONS (continued)

TERMINAL

I/O/Z

DESCRIPTION

PT

PIN #

DA

PIN #

NAME

CPU AND I/O POWER

V_DDA

11

12

32

22

23

1

Analog Power Pin. Tie with a 2.2-µF capacitor (typical) close to the pin.

V_SSA

V_REFLO

Analog Ground Pin

ADC Low Reference (always tied to ground)

I

V_DD

CPU and Logic Digital Power Pins – no supply source needed when using internal

VREG. Tie with 1.2 µF (minimum) ceramic capacitor (10% tolerance) to ground when

using internal VREG. Higher value capacitors may be used, but could impact

supply-rail ramp-up time.

V_DD

43

35

11

4

Digital I/O and Flash Power Pin – Single Supply source when VREG is enabled. Tie

with a 2.2-µF capacitor (typical) close to the pin.

V_DDIO

V_SS

33

44

2

Digital Ground Pins

12

VOLTAGE REGULATOR CONTROL SIGNAL

Internal VREG Enable/Disable. Pull low to enable the internal voltage regulator

(VREG), pull high to disable VREG.

VREGENZ

34

29

3

I

(1)

GPIO AND PERIPHERAL SIGNALS

GPIO0

EPWM1A

–

37

I/O/Z

O

General purpose input/output 0

Enhanced PWM1 Output A and HRPWM channel

–

GPIO1

EPWM1B

–

28

37

38

39

40

41

36

5

I/O/Z

O

General purpose input/output 1

Enhanced PWM1 Output B

–

COMP1OUT

GPIO2

EPWM2A

–

O

Direct output of Comparator 1

I/O/Z

O

General purpose input/output 2

Enhanced PWM2 Output A and HRPWM channel

–

GPIO3

EPWM2B

–

6

I/O/Z

O

General purpose input/output 3

Enhanced PWM2 Output B

–

COMP2OUT

GPIO4

EPWM3A

–

O

I/O/Z

O

Direct output of Comparator 2 (available in 48-pin device only)

General purpose input/output 4

Enhanced PWM3 output A and HRPWM channel

–

7

–

GPIO5

EPWM3B

–

8

I/O/Z

O

General purpose input/output 5

Enhanced PWM3 output B

–

ECAP1

GPIO6

EPWM4A

EPWMSYNCI

EPWMSYNCO

I/O

I/O/Z

O

Enhanced Capture input/output 1

General purpose input/output 6

Enhanced PWM4 output A and HRPWM channel

External ePWM sync pulse input

External ePWM sync pulse output

9

I

O

(1) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions.

For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the

GPIO block and the path to the JTAG block from a pin is enabled/disabled based on the condition of the TRST signal. See the

TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference Guide (literature number SPRUFN3) for details.

10

Introduction

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TMS320F28021, TMS320F28020, TMS320F280200

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

Table 2-2. TERMINAL FUNCTIONS (continued)

TERMINAL

I/O/Z

DESCRIPTION

PT

PIN #

DA

PIN #

NAME

GPIO7

EPWM4B

SCIRXDA

–

42

47

27

26

24

10

13

35

34

32

I/O/Z

General purpose input/output 7

Enhanced PWM4 output B

SCI-A receive data

–

O

I

GPIO12

TZ1

I/O/Z

General purpose input/output 12

Trip Zone input 1

I

SCITXDA

–

O

SCI-A transmit data

–

GPIO16

SPISIMOA

–

I/O/Z

I/O

General purpose input/output 16

SPI slave in, master out

–

TZ2

I

Trip Zone input 2

GPIO17

SPISOMIA

–

I/O/Z

I/O

General purpose input/output 17

SPI-A slave out, master in

–

TZ3

I

Trip zone input 3

GPIO18

SPICLKA

SCITXDA

I/O/Z

I/O

O

General purpose input/output 18

SPI-A clock input/output

SCI-A transmit

Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency,

one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled

by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT =

SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV

to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to

propogate to the pin.

XCLKOUT

O/Z

GPIO19

25

33

I/O/Z

General purpose input/output 19

External Oscillator Input. The path from this pin to the clock block is not gated by the

mux function of this pin. Care must be taken not to enable this path for clocking if it is

being used for the other periperhal functions

XCLKIN

SPISTEA

SCIRXDA

ECAP1

I/O

SPI-A slave transmit enable input/output

SCI-A receive

I

I/O

I/O/Z

I

Enhanced Capture input/output 1

General purpose input/output 28

SCI receive data

GPIO28

SCIRXDA

SDAA

48

1

14

15

–

I/OD

I

I2C data open-drain bidirectional port

Trip zone input 2

TZ2

GPIO29

SCITXDA

SCLA

I/O/Z

O

General purpose input/output 29.

SCI transmit data

I/OD

I

I2C clock open-drain bidirectional port

Trip zone input 3

TZ3

GPIO32

SDAA

31

I/O/Z

I/OD

I

General purpose input/output 32

I2C data open-drain bidirectional port

Enhanced PWM external sync pulse input

ADC start-of-conversion A

EPWMSYNCI

ADCSOCAO

O

Introduction

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Table 2-2. TERMINAL FUNCTIONS (continued)

TERMINAL

I/O/Z

DESCRIPTION

PT

PIN #

DA

PIN #

NAME

GPIO33

36

–

I/O/Z

I/OD

O

General-Purpose Input/Output 33

SCLA

I2C clock open-drain bidirectional port

Enhanced PWM external synch pulse output

ADC start-of-conversion B

EPWMSYNCO

ADCSOCBO

GPIO34

COMP2OUT

–

O

19

27

I/O/Z

O

General-Purpose Input/Output 34

Direct output of Comparator 2. COMP2OUT signal is not available in the DA package.

–

GPIO35

20

21

22

23

28

29

30

31

I/O/Z

I

General-Purpose Input/Output 35

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register

(instruction or data) on a rising edge of TCK

TDI

GPIO36

TMS

I/O/Z

I

General-Purpose Input/Output 36

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked

into the TAP controller on the rising edge of TCK.

GPIO37

TDO

I/O/Z

O/Z

General-Purpose Input/Output 37

JTAG scan out, test data output (TDO). The contents of the selected register

(instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive)

GPIO38

TCK

I/O/Z

I

General-Purpose Input/Output 38

JTAG test clock with internal pullup

External Oscillator Input. The path from this pin to the clock block is not gated by the

mux function of this pin. Care must be taken to not enable this path for clocking if it is

being used for the other functions.

XCLKIN

I

12

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

3 Functional Overview

3.1 Block Diagram

M0

SARAM 1K x 16

(0-wait)

OTP 1K x 16

Secure

SARAM

M1

SARAM 1K x 16

(0-wait)

1K/3K/4K x 16

(0-wait)

Secure

Code

Security

Module

FLASH

8K/16K/32K x 16

Secure

Boot-ROM

8K x 16

(0-wait)

OTP/Flash

Wrapper

PSWD

Memory Bus

TRST

TCK

TDI

TMS

TDO

COMP1OUT

GPIO

C28x

32-bit CPU

COMP2OUT

MUX

GPIO

Mux

COMP1A

COMP1B

COMP2A

COMP2B

COMP

3 External Interrupts

XCLKIN

PIE

OSC1,

OSC2,

Ext,

CPU Timer 0

X1

X2

AIO

CPU Timer 1

CPU Timer 2

Memory Bus

MUX

PLL,

LPM,

WD

LPM Wakeup

XRS

ADC

A7:0

B7:0

POR/

BOR

VREG

32-bit Peripheral Bus

16-bit Peripheral Bus

32-Bit Peripheral Bus

ePWM

SCI

(4L FIFO)

SPI

(4L FIFO)

I2C

eCAP

(4L FIFO)

HRPWM

From

COMP1OUT,

COMP2OUT

GPIO MUX

A. Not all peripheral pins are available at the same time due to multiplexing.

Figure 3-1. Functional Block Diagram

Functional Overview

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3.2 Memory Maps

In Figure 3-2, Figure 3-3, Figure 3-4, Figure 3-5, and Figure 3-6, the following apply:

•

Memory blocks are not to scale.

Peripheral Frame 0, Peripheral Frame 1 and Peripheral Frame 2 memory maps are restricted to data

memory only. A user program cannot access these memory maps in program space.

•

Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline

order.

•

Certain memory ranges are EALLOW protected against spurious writes after configuration.

Locations 0x3D7C80 – 0x3D7CC0 contain the internal oscillator and ADC calibration routines. These

locations are not programmable by the user.

14

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

Data Space

Prog Space

0x00 0000

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K x 16, 0-Wait)

M1 SARAM (1K x 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 2000

0x00 6000

Peripheral Frame 0

Reserved

Peripheral Frame 1

(4K x 16, Protected)

Reserved

0x00 7000

0x00 8000

Peripheral Frame 2

(4K x 16, Protected)

L0 SARAM (4K x 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x00 9000

0x3D 7800

0x3D 7C00

Reserved

User OTP (1K x 16, Secure Zone + ECSL)

Reserved

0x3D 7C80

0x3D 7CC0

0x3D 7CE0

0x3D 7E80

Calibration Data

Get_mode function

Reserved

Calibration Data

Reserved

0x3D 7EB0

0x3D 7FFF

PARTID

0x3D 8000

0x3F 0000

Reserved

FLASH

(32K x 16, 4 Sectors, Secure Zone + ECSL)

0x3F 7FF8

0x3F 8000

128-Bit Password

L0 SARAM (4K x 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x3F 9000

0x3F E000

0x3F FFC0

Reserved

Boot ROM (8K x 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.

Figure 3-2. 28023/28027 Memory Map

Functional Overview

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Data Space

Prog Space

0x00 0000

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K x 16, 0-Wait)

M1 SARAM (1K x 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 2000

0x00 6000

Peripheral Frame 0

Reserved

Peripheral Frame 1

(4K x 16, Protected)

Reserved

0x00 7000

0x00 8000

Peripheral Frame 2

(4K x 16, Protected)

L0 SARAM (4K x 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x00 9000

0x3D 7800

0x3D 7C00

Reserved

User OTP (1K x 16, Secure Zone + ECSL)

Reserved

0x3D 7C80

0x3D 7CC0

Calibration Data

Get_mode function

Reserved

0x3D 7CE0

0x3D 7E80

Calibration Data

Reserved

0x3D 7EB0

0x3D 7FFF

PARTID

0x3D 8000

0x3F 4000

Reserved

FLASH

(16K x 16, 4 Sectors, Secure Zone + ECSL)

0x3F 7FF8

0x3F 8000

128-Bit Password

L0 SARAM (4K x 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x3F 9000

0x3F E000

0x3F FFC0

Reserved

Boot ROM (8K x 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.

Figure 3-3. 28022/28026 Memory Map

16

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

Data Space

Prog Space

0x00 0000

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K x 16, 0-Wait)

M1 SARAM (1K x 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 2000

0x00 6000

Peripheral Frame 0

Reserved

Peripheral Frame 1

(4K x 16, Protected)

Reserved

0x00 7000

0x00 8000

Peripheral Frame 2

(4K x 16, Protected)

L0 SARAM (3K x 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x00 8C00

0x3D 7800

0x3D 7C00

Reserved

User OTP (1K x 16, Secure Zone + ECSL)

Reserved

0x3D 7C80

0x3D 7CC0

Calibration Data

Get_mode function

Reserved

0x3D 7CE0

0x3D 7E80

Calibration Data

Reserved

0x3D 7EB0

0x3D 7FFF

PARTID

0x3D 8000

0x3F 0000

Reserved

FLASH

(32K x 16, 4 Sectors, Secure Zone + ECSL)

0x3F 7FF8

0x3F 8000

128-Bit Password

L0 SARAM (3K x 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x3F 8C00

0x3F E000

0x3F FFC0

Reserved

Boot ROM (8K x 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.

Figure 3-4. 28021 Memory Map

Functional Overview

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Data Space

Prog Space

0x00 0000

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K x 16, 0-Wait)

M1 SARAM (1K x 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 2000

0x00 6000

Peripheral Frame 0

Reserved

Peripheral Frame 1

(4K x 16, Protected)

Reserved

0x00 7000

0x00 8000

Peripheral Frame 2

(4K x 16, Protected)

L0 SARAM (1K x 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x00 8400

0x3D 7800

0x3D 7C00

Reserved

User OTP (1K x 16, Secure Zone + ECSL)

Reserved

0x3D 7C80

0x3D 7CC0

0x3D 7CE0

0x3D 7E80

Calibration Data

Get_mode function

Reserved

Calibration Data

Reserved

0x3D 7EB0

0x3D 7FFF

PARTID

0x3D 8000

0x3F 4000

Reserved

FLASH

(16K x 16, 4 Sectors, Secure Zone + ECSL)

0x3F 7FF8

0x3F 8000

128-Bit Password

L0 SARAM (1K x 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x3F 8400

0x3F E000

0x3F FFC0

Reserved

Boot ROM (8K x 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.

Figure 3-5. 28020 Memory Map

18

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Data Space

Prog Space

0x00 0000

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K x 16, 0-Wait)

M1 SARAM (1K x 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 2000

0x00 6000

Peripheral Frame 0

Reserved

Peripheral Frame 1

(4K x 16, Protected)

Reserved

0x00 7000

0x00 8000

Peripheral Frame 2

(4K x 16, Protected)

L0 SARAM (1K x 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x00 8400

0x3D 7800

0x3D 7C00

Reserved

User OTP (1K x 16, Secure Zone + ECSL)

Reserved

0x3D 7C80

0x3D 7CC0

Calibration Data

Get_mode function

Reserved

0x3D 7CE0

0x3D 7E80

Calibration Data

Reserved

0x3D 7EB0

0x3D 7FFF

PARTID

0x3D 8000

0x3F 6000

Reserved

FLASH

(8K x 16, 2 Sectors, Secure Zone + ECSL)

0x3F 7FF8

0x3F 8000

128-Bit Password

L0 SARAM (1K x 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x3F 8400

0x3F E000

0x3F FFC0

Reserved

Boot ROM (8K x 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.

Figure 3-6. 280200 Memory Map

Functional Overview

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Table 3-1. Addresses of Flash Sectors in F28021/28023/28027

ADDRESS RANGE

0x3F 0000 – 0x3F 1FFF

0x3F 2000 – 0x3F 3FFF

0x3F 4000 – 0x3F 5FFF

0x3F 6000 – 0x3F 7F7F

PROGRAM AND DATA SPACE

Sector D (8K x 16)

Sector C (8K x 16)

Sector B (8K x 16)

Sector A (8K x 16)

Program to 0x0000 when using the

Code Security Module

0x3F 7F80 – 0x3F 7FF5

0x3F 7FF6 – 0x3F 7FF7

0x3F 7FF8 – 0x3F 7FFF

Boot-to-Flash Entry Point

(program branch instruction here)

Security Password (128-Bit)

(Do not program to all zeros)

Table 3-2. Addresses of Flash Sectors in F28020/28022/28026

ADDRESS RANGE

0x3F 4000 – 0x3F 4FFF

0x3F 5000 – 0x3F 5FFF

0x3F 6000 – 0x3F 6FFF

0x3F 7000 – 0x3F 7F7F

PROGRAM AND DATA SPACE

Sector D (4K x 16)

Sector C (4K x 16)

Sector B (4K x 16)

Sector A (4K x 16)

Program to 0x0000 when using the

Code Security Module

0x3F 7F80 – 0x3F 7FF5

0x3F 7FF6 – 0x3F 7FF7

0x3F 7FF8 – 0x3F 7FFF

Boot-to-Flash Entry Point

(program branch instruction here)

Security Password (128-Bit)

(Do not program to all zeros)

Table 3-3. Addresses of Flash Sectors in F280200

ADDRESS RANGE

0x3F 6000 – 0x3F 6FFF

0x3F 7000 – 0x3F 7F7F

PROGRAM AND DATA SPACE

Sector B (4K x 16)

Sector A (4K x 16)

Program to 0x0000 when using the

Code Security Module

0x3F 7F80 – 0x3F 7FF5

0x3F 7FF6 – 0x3F 7FF7

0x3F 7FF8 – 0x3F 7FFF

Boot-to-Flash Entry Point

(program branch instruction here)

Security Password (128-Bit)

(Do not program to all zeros)

NOTE

•

When the code-security passwords are programmed, all addresses between 0x3F 7F80

and 0x3F 7FF5 cannot be used as program code or data. These locations must be

programmed to 0x0000.

If the code security feature is not used, addresses 0x3F 7F80 through 0x3F 7FEF may

be used for code or data. Addresses 0x3F 7FF0 – 0x3F 7FF5 are reserved for data and

should not contain program code.

Table 3-4 shows how to handle these memory locations.

20

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

Table 3-4. Impact of Using the Code Security Module

FLASH

ADDRESS

CODE SECURITY ENABLED

CODE SECURITY DISABLED

Application code and data

0x3F 7F80 – 0x3F 7FEF

0x3F 7FF0 – 0x3F 7FF5

Fill with 0x0000

Reserved for data only

Peripheral Frame 1 and Peripheral Frame 2 are grouped together to enable these blocks to be write/read

peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as

written. Because of the pipeline, a write immediately followed by a read to different memory locations, will

appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral

applications where the user expected the write to occur first (as written). The CPU supports a block

protection mode where a region of memory can be protected so that operations occur as written (the

penalty is extra cycles are added to align the operations). This mode is programmable and by default, it

protects the selected zones.

The wait-states for the various spaces in the memory map area are listed in Table 3-5 .

Table 3-5. Wait-states

AREA

WAIT-STATES (CPU)

0-wait

COMMENTS

M0 and M1 SARAMs

Peripheral Frame 0

Peripheral Frame 1

Fixed

0-wait

0-wait (writes)

2-wait (reads)

Cycles can be extended by peripheral generated ready.

Back-to-back write operations to Peripheral Frame 1 registers will incur

a 1-cycle stall (1-cycle delay).

Peripheral Frame 2

0-wait (writes)

2-wait (reads)

Fixed. Cycles cannot be extended by the peripheral.

L0 SARAM

OTP

0-wait data and program

Programmable

Assumes no CPU conflicts

Programmed via the Flash registers.

1-wait is minimum number of wait states allowed.

Programmed via the Flash registers.

1-wait minimum

Programmable

FLASH

0-wait Paged min

1-wait Random min

Random ≥ Paged

FLASH Password

Boot-ROM

16-wait fixed

0-wait

Wait states of password locations are fixed.

Functional Overview

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3.3 Brief Descriptions

3.3.1 CPU

www.ti.com

The 2802x (C28x) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The

C28x-based controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. It is a very

efficient C/C++ engine, enabling users to develop not only their system control software in a high-level

language, but also enabling development of math algorithms using C/C++. The device is as efficient at

MCU math tasks as it is at system control tasks that typically are handled by microcontroller devices. This

efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC 64-bit

processing capabilities enable the controller to handle higher numerical resolution problems efficiently.

Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device

that is capable of servicing many asynchronous events with minimal latency. The device has an

8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables it to execute at

high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware

minimizes the latency for conditional discontinuities. Special store conditional operations further improve

performance.

3.3.2 Memory Bus (Harvard Bus Architecture)

As with many MCU-type devices, multiple busses are used to move data between the memories and

peripherals and the CPU. The memory bus architecture contains a program read bus, data read bus, and

data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and

write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable

single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the

C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and

memories attached to the memory bus prioritize memory accesses. Generally, the priority of memory bus

accesses can be summarized as follows:

Highest:

Data Writes

(Simultaneous data and program writes cannot occur on the

memory bus.)

Program Writes

(Simultaneous data and program writes cannot occur on the

memory bus.)

Data Reads

Program Reads

(Simultaneous program reads and fetches cannot occur on the

memory bus.)

Lowest:

Fetches

(Simultaneous program reads and fetches cannot occur on the

memory bus.)

3.3.3 Peripheral Bus

To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the

devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes

the various busses that make up the processor Memory Bus into a single bus consisting of 16 address

lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus are

supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version

supports both 16- and 32-bit accesses (called peripheral frame 1).

3.3.4 Real-Time JTAG and Analysis

The devices implement the standard IEEE 1149.1 JTAG⁽¹⁾interface for in-circuit based debug.

Additionally, the devices support real-time mode of operation allowing modification of the contents of

memory, peripheral, and register locations while the processor is running and executing code and

servicing interrupts. The user can also single step through non-time-critical code while enabling

time-critical interrupts to be serviced without interference. The device implements the real-time mode in

(1) IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture

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hardware within the CPU. This is a feature unique to the 28x family of devices, requiring no software

monitor. Additionally, special analysis hardware is provided that allows setting of hardware breakpoint or

data/address watch-points and generating various user-selectable break events when a match occurs.

These devices do not support boundary scan; however, IDCODE and BYPASS features are available if

the following considerations are taken into account. The IDCODE does not come by default. The user

needs to go through a sequence of SHIFT IR and SHIFT DR state of JTAG to get the IDCODE. For

BYPASS instruction, the first shifted DR value would be 1.

3.3.5 Flash

The F280200 device contains 8K x 16 of embedded flash memory, segregated into two 4K x 16 sectors.

The F28021/23/27 devices contain 32K x 16 of embedded flash memory, segregated into four 8K x 16

sectors. The F28020/22/26 devices contain 16K x 16 of embedded flash memory, segregated into four

4K x 16 sectors. All devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800 –

0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other

sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash

algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash

module to achieve higher performance. The flash/OTP is mapped to both program and data space;

therefore, it can be used to execute code or store data information. Addresses 0x3F 7FF0 – 0x3F 7FF5

are reserved for data variables and should not contain program code.

NOTE

The Flash and OTP wait-states can be configured by the application. This allows applications

running at slower frequencies to configure the flash to use fewer wait-states.

Flash effective performance can be improved by enabling the flash pipeline mode in the

Flash options register. With this mode enabled, effective performance of linear code

execution will be much faster than the raw performance indicated by the wait-state

configuration alone. The exact performance gain when using the Flash pipeline mode is

application-dependent.

For more information on the Flash options, Flash wait-state, and OTP wait-state registers,

see the TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference

Guide (literature number SPRUFN3).

3.3.6 M0, M1 SARAMs

All devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer

points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x

devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute

code or for data variables. The partitioning is performed within the linker. The C28x device presents a

unified memory map to the programmer. This makes for easier programming in high-level languages.

3.3.7 L0 SARAM

The device contains up to 4K x 16 of single-access RAM. Refer to the device-specific memory map figures

in Section 3.2 to ascertain the exact size for a given device. This block is mapped to both program and

data space.

3.3.8 Boot ROM

The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell

the bootloader software what boot mode to use on power up. The user can select to boot normally or to

download new software from an external connection or to select boot software that is programmed in the

internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use

in math-related algorithms.

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Table 3-6. Boot Mode Selection

MODE

GPIO37/TDO

GPIO34/COMP2OUT

TRST

MODE

3

2

1

0

x

1

0

1

0

x

0

1

GetMode

Wait (see Section 3.3.9 for description)

1

SCI

0

Parallel IO

Emulation Boot

EMU

3.3.8.1 Emulation Boot

When the emulator is connected, the GPIO37/TDO pin cannot be used for boot mode selection. In this

case, the boot ROM detects that an emulator is connected and uses the contents of two reserved SARAM

locations in the PIE vector table to determine the boot mode. If the content of either location is invalid,

then the Wait boot option is used. All boot mode options can be accessed in emulation boot.

3.3.8.2 GetMode

The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another

boot option by programming two locations in the OTP. If the content of either OTP location is invalid, then

boot to flash is used. One of the following loaders can be specified: SCI, SPI, I2C, or OTP.

3.3.8.3 Peripheral Pins Used by the Bootloader

Table 3-7 shows which GPIO pins are used by each peripheral bootloader. Refer to the GPIO mux table

to see if these conflict with any of the peripherals you would like to use in your application.

Table 3-7. Peripheral Bootload Pins

BOOTLOADER

PERIPHERAL LOADER PINS

SCIRXDA (GPIO28)

SCI

SCITXDA (GPIO29)

Parallel Boot

SPI

Data (GPIO[7:0])

28x Control (GPIO16)

Host Control (GPIO12)

SPISIMOA (GPIO16)

SPISOMIA (GPIO17)

SPICLKA (GPIO18)

SPISTEA (GPIO19)

I2C

SDAA (GPIO32)⁽¹⁾

SCLA (GPIO33)⁽¹⁾

(1) GPIO pins 32 and 33 may not be available on your device package. On these devices, this bootload

option is unavailable.

3.3.9 Security

The devices support high levels of security to protect the user firmware from being reverse engineered.

The security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the

flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks.

The security feature prevents unauthorized users from examining the memory contents via the JTAG port,

executing code from external memory or trying to boot-load some undesirable software that would export

the secure memory contents. To enable access to the secure blocks, the user must write the correct

128-bit KEY value that matches the value stored in the password locations within the Flash.

In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent

unauthorized users from stepping through secure code. Any code or data access to flash, user OTP, or L0

memory while the emulator is connected will trip the ECSL and break the emulation connection. To allow

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emulation of secure code, while maintaining the CSM protection against secure memory reads, the user

must write the correct value into the lower 64 bits of the KEY register, which matches the value stored in

the lower 64 bits of the password locations within the flash. Note that dummy reads of all 128 bits of the

password in the flash must still be performed. If the lower 64 bits of the password locations are all ones

(unprogrammed), then the KEY value does not need to match.

When initially debugging a device with the password locations in flash programmed (i.e., secured), the

CPU will start running and may execute an instruction that performs an access to a protected ECSL area.

If this happens, the ECSL will trip and cause the emulator connection to be cut.

The solution is to use the Wait boot option. This will sit in a loop around a software breakpoint to allow an

emulator to be connected without tripping security. The user can then exit this mode once the emulator is

connected by using one of the emulation boot options as described in the TMS320x2802x Piccolo Boot

ROM Reference Guide (literature number SPRUFN6). Piccolo devices do not support a hardware

wait-in-reset mode.

NOTE

•

When the code-security passwords are programmed, all addresses between 0x3F7F80

and 0x3F7FF5 cannot be used as program code or data. These locations must be

programmed to 0x0000.

If the code security feature is not used, addresses 0x3F7F80 through 0x3F7FEF may be

used for code or data. Addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data and

should not contain program code.

The 128-bit password (at 0x3F 7FF8 – 0x3F 7FFF) must not be programmed to zeros. Doing

so would permanently lock the device.

Disclaimer

Code Security Module Disclaimer

THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED

TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY

(EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN

ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO

TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR

THIS DEVICE.

TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE

COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED

MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT

AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS

CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED

WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,

INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY

OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN

ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE,

BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR

INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.

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3.3.10 Peripheral Interrupt Expansion (PIE) Block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The

PIE block can support up to 96 peripheral interrupts. On the F2802x , 33 of the possible 96 interrupts are

used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of

12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a

dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU

on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.

Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in

hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.

3.3.11 External Interrupts (XINT1–XINT3)

The devices support three masked external interrupts (XINT1–XINT3). Each of the interrupts can be

selected for negative, positive, or both negative and positive edge triggering and can also be

enabled/disabled. These interrupts also contain a 16-bit free running up counter, which is reset to zero

when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt.

There are no dedicated pins for the external interrupts. XINT1, XINT2, and XINT3 interrupts can accept

inputs from GPIO0–GPIO31 pins.

3.3.12 Internal Zero Pin Oscillators, Oscillator, and PLL

The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a

crystal attached to the on-chip oscillator circuit (48-pin devices only). A PLL is provided supporting up to

12 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to

scale back on operating frequency if lower power operation is desired. Refer to Section 6, Electrical

Specifications, for timing details. The PLL block can be set in bypass mode.

3.3.13 Watchdog

Each device contains two watchdogs: CPU-Watchdog that monitors the core and NMI-Watchdog that is a

missing clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a

certain time frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog

can be disabled if necessary. The NMI-Watchdog engages only in case of a clock failure and can either

generate an interrupt or a device reset.

3.3.14 Peripheral Clocking

The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a

peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled

relative to the CPU clock.

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3.3.15 Low-power Modes

The devices are full static CMOS devices. Three low-power modes are provided:

IDLE:

Place CPU in low-power mode. Peripheral clocks may be turned off selectively and

only those peripherals that need to function during IDLE are left operating. An

enabled interrupt from an active peripheral or the watchdog timer will wake the

processor from IDLE mode.

STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL

functional. An external interrupt event will wake the processor and the peripherals.

Execution begins on the next valid cycle after detection of the interrupt event

HALT:

This mode basically shuts down the device and places it in the lowest possible power

consumption mode. If the internal zero-pin oscillators are used as the clock source,

the HALT mode turns them off, by default. To keep these oscillators from shutting

down, the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin

oscillators may thus be used to clock the CPU-watchdog in this mode. If the on-chip

crystal oscillator is used as the clock source, it is shut down in this mode. A reset or

an external signal (through a GPIO pin) or the CPU-watchdog can wake the device

from this mode.

The CPU clock (OSCCLK) and WDCLK should be from the same clock source before attempting to put

the device into HALT or STANDBY.

3.3.16 Peripheral Frames 0, 1, 2 (PFn)

The device segregates peripherals into three sections. The mapping of peripherals is as follows:

PF0: PIE:

Flash:

PIE Interrupt Enable and Control Registers Plus PIE Vector Table

Flash Waitstate Registers

Timers:

CSM:

CPU-Timers 0, 1, 2 Registers

Code Security Module KEY Registers

ADC Result Registers

ADC:

PF1: GPIO:

ePWM:

GPIO MUX Configuration and Control Registers

Enhanced Pulse Width Modulator Module and Registers

Enhanced Capture Module and Registers

eCAP:

Comparators: Comparator Modules

PF2: SYS:

SCI:

System Control Registers

Serial Communications Interface (SCI) Control and RX/TX Registers

Serial Port Interface (SPI) Control and RX/TX Registers

ADC Status, Control, and Configuration Registers

Inter-Integrated Circuit Module and Registers

External Interrupt Registers

SPI:

ADC:

I2C:

XINT:

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3.3.17 General-Purpose Input/Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This

enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins

are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal

mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter

unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power

modes.

3.3.18 32-Bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock

prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter

reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.

When the counter reaches zero, it is automatically reloaded with a 32-bit period value.

CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use

and can be connected to INT13 of the CPU. CPU-Timer 2 is reserved for DSP/BIOS. It is connected to

INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use.

CPU-Timer 2 can be clocked by any one of the following:

•

SYSCLKOUT (default)

Internal zero-pin oscillator 1 (INTOSC1)

Internal zero-pin oscillator 2 (INTSOC2)

External clock source

3.3.19 Control Peripherals

The devices support the following peripherals that are used for embedded control and communication:

ePWM:

The enhanced PWM peripheral supports independent/complementary PWM

generation, adjustable dead-band generation for leading/trailing edges,

latched/cycle-by-cycle trip mechanism. Some of the PWM pins support the

HRPWM high resolution duty and period features. The type 1 module found on

2802x devices also supports increased dead-band resolution, enhanced SOC and

interrupt generation, and advanced triggering including trip functions based on

comparator outputs.

eCAP:

ADC:

The enhanced capture peripheral uses a 32-bit time base and registers up to four

programmable events in continuous/one-shot capture modes.

This peripheral can also be configured to generate an auxiliary PWM signal.

The ADC block is a 12-bit converter. It has up to 13 single-ended channels pinned

out, depending on the device. It contains two sample-and-hold units for

simultaneous sampling.

Comparator: Each comparator block consists of one analog comparator along with an internal

10-bit reference for supplying one input of the comparator.

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3.3.20 Serial Port Peripherals

The devices support the following serial communication peripherals:

SPI:

The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream

of programmed length (one to sixteen bits) to be shifted into and out of the device

at a programmable bit-transfer rate. Normally, the SPI is used for communications

between the MCU and external peripherals or another processor. Typical

applications include external I/O or peripheral expansion through devices such as

shift registers, display drivers, and ADCs. Multi-device communications are

supported by the master/slave operation of the SPI. The SPI contains a 4-level

receive and transmit FIFO for reducing interrupt servicing overhead.

SCI:

I2C:

The serial communications interface is a two-wire asynchronous serial port,

commonly known as UART. The SCI contains a 4-level receive and transmit FIFO

for reducing interrupt servicing overhead.

The inter-integrated circuit (I2C) module provides an interface between a MCU

and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus)

specification version 2.1 and connected by way of an I2C-bus. External

components attached to this 2-wire serial bus can transmit/receive up to 8-bit data

to/from the MCU through the I2C module. The I2C contains a 4-level receive and

transmit FIFO for reducing interrupt servicing overhead.

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3.4 Register Map

The devices contain three peripheral register spaces. The spaces are categorized as follows:

Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.

See Table 3-8.

Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See

Table 3-9.

Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See

Table 3-10.

Table 3-8. Peripheral Frame 0 Registers⁽¹⁾

NAME

Device Emulation Registers

System Power Control Registers

FLASH Registers⁽³⁾

ADDRESS RANGE

0x00 0880 – 0x00 0984

0x00 0985 – 0x00 0987

0x00 0A80 – 0x00 0ADF

0x00 0AE0 – 0x00 0AEF

0x00 0B00 – 0x00 0B0F

SIZE (×16)

EALLOW PROTECTED⁽²⁾

261

3

Yes

No

96

16

Code Security Module Registers

ADC registers

(0 wait read only)

CPU–TIMER0/1/2 Registers

PIE Registers

0x00 0C00 – 0x00 0C3F

0x00 0CE0 – 0x00 0CFF

0x00 0D00 – 0x00 0DFF

64

32

No

PIE Vector Table

256

(1) Registers in Frame 0 support 16-bit and 32-bit accesses.

(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction

disables writes to prevent stray code or pointers from corrupting register contents.

(3) The Flash Registers are also protected by the Code Security Module (CSM).

Table 3-9. Peripheral Frame 1 Registers

NAME

Comparator 1 registers

ADDRESS RANGE

0x00 6400 – 0x00 641F

0x00 6420 – 0x00 643F

0x00 6800 – 0x00 683F

0x00 6840 – 0x00 687F

0x00 6880 – 0x00 68BF

0x00 68C0 – 0x00 68FF

0x00 6A00 – 0x00 6A1F

0x00 6F80 – 0x00 6FFF

SIZE (×16)

EALLOW PROTECTED

(1)

32

64

32

128

(1)

Comparator 2 registers

ePWM1 + HRPWM1 registers

ePWM2 + HRPWM2 registers

ePWM3 + HRPWM3 registers

ePWM4 + HRPWM4 registers

eCAP1 registers

No

(1)

GPIO registers

(1) Some registers are EALLOW protected. See the module reference guide for more information.

Table 3-10. Peripheral Frame 2 Registers

NAME

System Control Registers

ADDRESS RANGE

0x00 7010 – 0x00 702F

0x00 7040 – 0x00 704F

0x00 7050 – 0x00 705F

0x00 7060 – 0x00 706F

0x00 7070 – 0x00 707F

0x00 7100 – 0x00 717F

0x00 7900 – 0x00 793F

SIZE (×16)

EALLOW PROTECTED

32

16

Yes

No

SPI-A Registers

SCI-A Registers

16

No

NMI Watchdog Interrupt Registers

External Interrupt Registers

ADC Registers

16

Yes

16

Yes

(1)

128

64

(1)

I2C-A Registers

(1) Some registers are EALLOW protected. See the module reference guide for more information.

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3.5 Device Emulation Registers

These registers are used to control the protection mode of the C28x CPU and to monitor some critical

device signals. The registers are defined in Table 3-11 .

Table 3-11. Device Emulation Registers

ADDRESS

RANGE

EALLOW

PROTECTED

NAME

SIZE (x16)

DESCRIPTION

Device Configuration Register

Part ID Register

0x0880

0x0881

DEVICECNF

PARTID

2

1

Yes

0x3D 7FFF

TMS320F280200PT

TMS320F280200DA

TMS320F28027PT

TMS320F28027DA

TMS320F28026PT

TMS320F28026DA

TMS320F28023PT

TMS320F28023DA

TMS320F28022PT

TMS320F28022DA

TMS320F28021PT

TMS320F28021DA

TMS320F28020PT

TMS320F28020DA

TMS320F280200PT/DA

TMS320F28027PT/DA

TMS320F28026PT/DA

TMS320F28023PT/DA

TMS320F28022PT/DA

TMS320F28021PT/DA

TMS320F28020PT/DA

0x00C1

0x00C0

0x00CF

0x00CE

0x00C7

0x00C6

0x00CD

0x00CC

0x00C5

0x00C4

0x00CB

0x00CA

0x00C3

0x00C2

0x00C7

0x00CF

0x00C7

0x00CF

0x00C7

0x00CF

0x00C7

No

CLASSID

0x0882

1

Class ID Register

No

REVID

0x0883

1

Revision ID

Register

0x0000 - Silicon Rev. 0 - TMS

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3.6 Interrupts

Figure 3-7 shows how the various interrupt sources are multiplexed.

Peripherals

(SPI, SCI, ePWM, I2C,

HRPWM, eCAP, ADC)

WDINT

Watchdog

Low-Power Modes

WAKEINT

Sync

LPMINT

SYSCLKOUT

Interrupt Control

XINT1CR(15:0)

XINT2CTR(15:0)

XINT1

GPIOXINT1SEL(4:0)

XINT2SOC

ADC

INT1

to

INT12

XINT2

Interrupt Control

XINT2CR(15:0)

XINT3CTR(15:0)

C28

Core

GPIOXINT2SEL(4:0)

GPIO0.int

XINT3

TINT0

XINT3

GPIO

MUX

Interrupt Control

XINT3CR(15:0)

XINT3CTR(15:0)

GPIO31.int

GPIOXINT3SEL(4:0)

CPU TIMER 0

CPU TIMER 1

CPU TIMER 2

TINT1

TINT2

INT13

INT14

CPUTMR2CLK

CLOCKFAIL

NMIRS

System Control

(See the System

Control section.)

NMI interrupt with watchdog function

(See the NMI Watchdog section.)

NMI

Figure 3-7. External and PIE Interrupt Sources

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Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with

8 interrupts per group equals 96 possible interrupts. Table 3-12 shows the interrupts used by 2802x

devices.

The TRAP #VectorNumber instruction transfers program control to the interrupt service routine

corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address

pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore,

TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.

When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service

routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector

from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth.

IFR[12:1]

IER[12:1]

INTM

INT1

INT2

1

CPU

MUX

0

INT11

INT12

Global

Enable

(Flag)

(Enable)

INTx.1

INTx.2

INTx.3

INTx.4

INTx.5

From

Peripherals

or

External

Interrupts

INTx

MUX

INTx.6

INTx.7

INTx.8

PIEACKx

(Enable/Flag)

(Enable)

(Flag)

PIEIERx[8:1]

PIEIFRx[8:1]

Figure 3-8. Multiplexing of Interrupts Using the PIE Block

Functional Overview

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Table 3-12. PIE MUXed Peripheral Interrupt Vector Table⁽¹⁾

INTx.8

WAKEINT

(LPM/WD)

0xD4E

Reserved

–

INTx.7

TINT0

(TIMER 0)

0xD4C

Reserved

–

INTx.6

ADCINT9

(ADC)

0xD4A

Reserved

–

INTx.5

XINT2

Ext. int. 2

0xD48

Reserved

–

INTx.4

XINT1

Ext. int. 1

0xD46

EPWM4_TZINT

(ePWM4)

0xD56

EPWM4_INT

(ePWM4)

0xD66

Reserved

–

INTx.3

Reserved

–

INTx.2

ADCINT2

(ADC)

INTx.1

ADCINT1

(ADC)

INT1.y

INT2.y

INT3.y

INT4.y

INT5.y

INT6.y

INT7.y

INT8.y

INT9.y

INT10.y

INT11.y

INT12.y

0xD44

EPWM3_TZINT

(ePWM3)

0xD54

EPWM3_INT

(ePWM3)

0xD64

Reserved

–

0xD42

0xD40

EPWM2_TZINT

(ePWM2)

0xD52

EPWM1_TZINT

(ePWM1)

0xD50

0xD5E

Reserved

–

0xD5C

Reserved

–

0xD5A

Reserved

–

0xD58

Reserved

–

EPWM2_INT

(ePWM2)

0xD62

EPWM1_INT

(ePWM1)

0xD60

0xD6E

Reserved

–

0xD6C

Reserved

–

0xD6A

Reserved

–

0xD68

Reserved

–

Reserved

–

ECAP1_INT

(eCAP1)

0xD70

0xD7E

Reserved

–

0xD7C

Reserved

–

0xD7A

Reserved

–

0xD78

Reserved

–

0xD76

Reserved

–

0xD74

Reserved

–

0xD72

Reserved

–

Reserved

–

0xD8E

Reserved

–

0xD8C

Reserved

–

0xD8A

Reserved

–

0xD88

Reserved

–

0xD86

Reserved

–

0xD84

Reserved

–

0xD82

0xD80

SPITXINTA

(SPI-A)

0xD92

SPIRXINTA

(SPI-A)

0xD90

0xD9E

Reserved

–

0xD9C

Reserved

–

0xD9A

Reserved

–

0xD98

Reserved

–

0xD96

Reserved

–

0xD94

Reserved

–

Reserved

–

Reserved

–

0xDAE

Reserved

–

0xDAC

Reserved

–

0xDAA

Reserved

–

0xDA8

Reserved

–

0xDA6

Reserved

–

0xDA4

Reserved

–

0xDA2

0xDA0

I2CINT2A

(I2C-A)

0xDB2

I2CINT1A

(I2C-A)

0xDBE

Reserved

–

0xDBC

Reserved

–

0xDBA

Reserved

–

0xDB8

Reserved

–

0xDB6

Reserved

–

0xDB4

Reserved

–

0xDB0

SCITXINTA

(SCI-A)

0xDC2

SCIRXINTA

(SCI-A)

0xDC0

0xDCE

ADCINT8

(ADC)

0xDDE

Reserved

–

0xDCC

ADCINT7

(ADC)

0xDDC

Reserved

–

0xDCA

ADCINT6

(ADC)

0xDDA

Reserved

–

0xDC8

ADCINT5

(ADC)

0xDD8

Reserved

–

0xDC6

ADCINT4

(ADC)

0xDC4

ADCINT3

(ADC)

0xDD4

Reserved

–

ADCINT2

(ADC)

ADCINT1

(ADC)

0xDD6

Reserved

–

0xDD2

0xDD0

Reserved

–

Reserved

–

0xDEE

Reserved

–

0xDEC

Reserved

–

0xDEA

Reserved

–

0xDE8

Reserved

–

0xDE6

Reserved

–

0xDE4

Reserved

–

0xDE2

0xDE0

Reserved

–

XINT3

Ext. Int. 3

0xDF0

0xDFE

0xDFC

0xDFA

0xDF8

0xDF6

0xDF4

0xDF2

(1) Out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be

used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a

peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR.

To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:

•

No peripheral within the group is asserting interrupts.

No peripheral interrupts are assigned to the group (e.g., PIE groups 5, 7, or 11) .

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Table 3-13. PIE Configuration and Control Registers

NAME

PIECTRL

PIEACK

PIEIER1

PIEIFR1

PIEIER2

PIEIFR2

PIEIER3

PIEIFR3

PIEIER4

PIEIFR4

PIEIER5

PIEIFR5

PIEIER6

PIEIFR6

PIEIER7

PIEIFR7

PIEIER8

PIEIFR8

PIEIER9

PIEIFR9

PIEIER10

PIEIFR10

PIEIER11

PIEIFR11

PIEIER12

PIEIFR12

Reserved

ADDRESS

0x0CE0

0x0CE1

0x0CE2

0x0CE3

0x0CE4

0x0CE5

0x0CE6

0x0CE7

0x0CE8

0x0CE9

0x0CEA

0x0CEB

0x0CEC

0x0CED

0x0CEE

0x0CEF

0x0CF0

0x0CF1

0x0CF2

0x0CF3

0x0CF4

0x0CF5

0x0CF6

0x0CF7

0x0CF8

0x0CF9

SIZE (x16)

DESCRIPTION⁽¹⁾

PIE, Control Register

1

6

PIE, Acknowledge Register

PIE, INT1 Group Enable Register

PIE, INT1 Group Flag Register

PIE, INT2 Group Enable Register

PIE, INT2 Group Flag Register

PIE, INT3 Group Enable Register

PIE, INT3 Group Flag Register

PIE, INT4 Group Enable Register

PIE, INT4 Group Flag Register

PIE, INT5 Group Enable Register

PIE, INT5 Group Flag Register

PIE, INT6 Group Enable Register

PIE, INT6 Group Flag Register

PIE, INT7 Group Enable Register

PIE, INT7 Group Flag Register

PIE, INT8 Group Enable Register

PIE, INT8 Group Flag Register

PIE, INT9 Group Enable Register

PIE, INT9 Group Flag Register

PIE, INT10 Group Enable Register

PIE, INT10 Group Flag Register

PIE, INT11 Group Enable Register

PIE, INT11 Group Flag Register

PIE, INT12 Group Enable Register

PIE, INT12 Group Flag Register

Reserved

0x0CFA –

0x0CFF

(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table

is protected.

3.6.1 External Interrupts

Table 3-14. External Interrupt Registers

NAME

XINT1CR

XINT2CR

XINT3CR

XINT1CTR

XINT2CTR

XINT3CTR

ADDRESS

SIZE (x16)

DESCRIPTION

0x00 7070

0x00 7071

0x00 7072

0x00 7078

0x00 7079

0x00 707A

1

XINT1 configuration register

XINT2 configuration register

XINT3 configuration register

XINT1 counter register

XINT2 counter register

XINT3 counter register

Functional Overview

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Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and

negative edge. For more information, see the TMS320x2802x/TMS320F2802xx Piccolo System Control

and Interrupts Reference Guide (literature number SPRUFN3).

3.7 VREG/BOR/POR

Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip

voltage regulator (VREG) to generate the V_DDvoltage from the V_DDIOsupply. This eliminates the cost and

space of a second external regulator on an application board. Additionally, internal power-on reset (POR)

and brown-out reset (BOR) circuits monitor both the V_DDand V_DDIOrails during power-up and run mode.

3.7.1 On-chip Voltage Regulator (VREG)

A linear regulator generates the core voltage (V_DD) from the V_DDIOsupply. Therefore, although capacitors

are required on each V_DDpin to stabilize the generated voltage, power need not be supplied to these pins

to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the

primary concern of the application.

3.7.1.1 Using the On-chip VREG

To utilize the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended

operating voltage should be supplied to the V_DDIOand V_DDApins. In this case, the V_DDvoltage needed by

the core logic will be generated by the VREG. Each V_DDpin requires on the order of 1.2 mF (minimum)

capacitance for proper regulation of the VREG. These capacitors should be located as close as possible

to the V_DDpins.

3.7.1.2 Disabling the On-chip VREG

To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to

the V_DDpins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied

high.

3.7.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit

Two on-chip supervisory circuits, the power-on reset (POR) and the brown-out reset (BOR) remove the

burden of monitoring the V_DDand V_DDIOsupply rails from the application board. The purpose of the POR is

to create a clean reset throughout the device during the entire power-up procedure. The trip point is a

looser, lower trip point than the BOR, which watches for dips in the V_DDor V_DDIOrail during device

operation. The POR function is present on both V_DDand V_DDIOrails at all times. After initial device

power-up, the BOR function is present on V_DDIOat all times, and on V_DDwhen the internal VREG is

enabled (VREGENZ pin is tied low). Both functions tie the XRS pin low when one of the voltages is below

their respective trip point. Additionally, when the internal voltage regulator is enabled, an over-voltage

protection circuit will tie XRS low if the V_DDrail rises above its trip point. See Section 6 for the various trip

points as well as the delay time for the device to release the XRS pin after the under/over-voltage

condition is removed. Figure 3-9 shows the VREG, POR, and BOR. To disable both the V_DDand V_DDIO

BOR functions, a bit is provided in the BORCFG register. Refer to the TMS320x2802x/TMS320F2802xx

Piccolo System Control and Interrupts Reference Guide (literature number SPRUFN3) for details.

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In

I/O Pin

Out

(Force Hi-Z When High)

DIR (0 = Input, 1 = Output)

SYSRS

Internal

Weak PU

SYSCLKOUT

Deglitch

XRS

Filter

Sync

RS

C28

Core

MCLKRS

PLL

JTAG

TCK

Detect

Logic

XRS

+

Clocking

Logic

VREGHALT

WDRST^(A)

PBRS^(B)

POR/BOR

Generating

Module

On-Chip

Voltage

Regulator

(VREG)

VREGENZ

A. WDRST is the reset signal from the CPU-watchdog.

B. PBRS is the reset signal from the POR/BOR module.

Figure 3-9. VREG + POR + BOR + Reset Signal Connectivity

Functional Overview

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3.8 System Control

This section describes the oscillator and clocking mechanisms, the watchdog function and the low power

modes.

Table 3-15. PLL, Clocking, Watchdog, and Low-Power Mode Registers

NAME

BORCFG

ADDRESS

0x00 0985

0x00 7010

0x00 7011

0x00 7012

0x00 7013

0x00 7014

0x00 7016

0x00 701B

0x00 701C

0x00 701D

0x00 701E

0x00 7020

0x00 7021

0x00 7022

0x00 7023

0x00 7025

0x00 7029

SIZE (x16)

DESCRIPTION⁽¹⁾

BOR Configuration Register

1

XCLK

XCLKOUT Control

PLLSTS

PLL Status Register

CLKCTL

Clock Control Register

PLLLOCKPRD

INTOSC1TRIM

INTOSC2TRIM

LOSPCP

PCLKCR0

PCLKCR1

LPMCR0

PCLKCR3

PLLCR

PLL Lock Period

Internal Oscillator 1 Trim Register

Internal Oscillator 2 Trim Register

Low-Speed Peripheral Clock Prescaler Register

Peripheral Clock Control Register 0

Peripheral Clock Control Register 1

Low Power Mode Control Register 0

Peripheral Clock Control Register 3

PLL Control Register

SCSR

System Control and Status Register

Watchdog Counter Register

Watchdog Reset Key Register

Watchdog Control Register

WDCNTR

WDKEY

WDCR

(1) All registers in this table are EALLOW protected.

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Figure 3-10 shows the various clock domains that are discussed. Figure 3-11 shows the various clock

sources (both internal and external) that can provide a clock for device operation.

SYSCLKOUT

PCLKCR0/1/3

(System Ctrl Regs)

LOSPCP

(System Ctrl Regs)

C28x Core

CLKIN

Clock Enables

LSPCLK

Peripheral

Registers

SPI-A, SCI-A

I/O

PF2

Clock Enables

eCAP1

Peripheral

Registers

PF1

PF2

GPIO

Mux

Clock Enables

ePWM1/.../4

Clock Enables

I2C-A

Peripheral

Registers

Peripheral

Registers

Clock Enables

ADC

Registers

PF2

PF0

16 Ch

12-Bit ADC

Analog

GPIO

Mux

Clock Enables

COMP1/2

COMP

Registers

6

PF1

A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency

as SYSCLKOUT).

Figure 3-10. Clock and Reset Domains

Functional Overview

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CLKCTL[WDCLKSRCSEL]

Internal

OSC 1

(10 MHz)

0

OSC1CLK

OSCCLKSRC1

INTOSC1TRIM Reg^(A)

WDCLK

CPU-Watchdog

(OSC1CLK on XRS reset)

OSCE

1

CLKCTL[INTOSC1OFF]

1 = Turn OSC Off

CLKCTL[OSCCLKSRCSEL]

OSCCLK

CLKCTL[INTOSC1HALT]

1 = Ignore HALT

WAKEOSC

OSC2CLK

0

1

Internal

OSC 2

(10 MHz)

INTOSC2TRIM Reg^(A)

PLL

Missing-Clock-Detect Circuit^(B)

(OSC1CLK on XRS reset)

OSCE

CLKCTL[TRM2CLKPRESCALE]

CLKCTL[TMR2CLKSRCSEL]

1 = Turn OSC Off

10

11

CLKCTL[INTOSC2OFF]

Prescale

/1, /2, /4,

/8, /16

SYNC

Edge

Detect

01, 10, 11

CPUTMR2CLK

1 = Ignore HALT

01

1

0

00

CLKCTL[INTOSC2HALT]

SYSCLKOUT

OSCCLKSRC2

CLKCTL[OSCCLKSRC2SEL]

0 = GPIO38

1 = GPIO19

XCLK[XCLKINSEL]

CLKCTL[XCLKINOFF]

0

1

0

GPIO19

or

XCLKIN

GPIO38

XCLKIN

X1

X2

EXTCLK

(Crystal)

OSC

XTAL

WAKEOSC

(Oscillators enabled when this signal is high)

0 = OSC on (default on reset)

1 = Turn OSC off

CLKCTL[XTALOSCOFF]

A. Register loaded from TI OTP-based calibration function.

B. See Section 3.8.4 for details on missing clock detection.

Figure 3-11. Clock Tree

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3.8.1 Internal Zero Pin Oscillators

The F2802x devices contain two independent internal zero pin oscillators. By default both oscillators are

turned on at power up, and internal oscillator 1 is the default clock source at this time. For power savings,

unused oscillators may be powered down by the user. The center frequency of these oscillators is

determined by their respective oscillator trim registers, written to in the calibration routine as part of the

boot ROM execution. See Section 6, Electrical Specifications, for more information on these oscillators.

3.8.2 Crystal Oscillator Option

The typical specifications for the external quartz crystal (fundamental mode, parallel resonant) are listed in

Table 3-16. Furthermore, ESR range = 30 to 150 Ω.

Table 3-16. Typical Specifications for External Quartz Crystal⁽¹⁾

FREQUENCY (MHz)

R_d(Ω)

2200

470

0

C_L1(pF)

18

C_L2(pF)

18

5

10

15

20

15

0

12

(1) C_shuntshould be less than or equal to 5 pF.

XCLKIN/GPIO19/38

X1

X2

R_d

Turn off

XCLKIN path

in CLKCTL

register

C_L1

Crystal

C_L2

A. X1/X2 pins are available in 48-pin package only.

Figure 3-12. Using the On-chip Crystal Oscillator

NOTE

1. C_L1and C_L2are the total capacitance of the circuit board and components excluding the

IC and crystal. The value is usually approximately twice the value of the crystal's load

capacitance.

2. The load capacitance of the crystal is described in the crystal specifications of the

manufacturers.

3. TI recommends that customers have the resonator/crystal vendor characterize the

operation of their device with the MCU chip. The resonator/crystal vendor has the

equipment and expertise to tune the tank circuit. The vendor can also advise the

customer regarding the proper tank component values that will produce proper start up

and stability over the entire operating range.

XCLKIN/GPIO19/38

X1

X2

NC

External Clock Signal

(Toggling 0−V

)

DDIO

Figure 3-13. Using a 3.3-V External Oscillator

Functional Overview

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3.8.3 PLL-Based Clock Module

The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking

signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control

PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing

to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes

1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of

the PLL (VCOCLK) is at least 50 MHz.

Table 3-17. PLL Settings

SYSCLKOUT (CLKIN)

PLLCR[DIV] VALUE^{(1) (2)}

PLLSTS[DIVSEL] = 0 or 1⁽³⁾

OSCCLK/4 (Default)⁽¹⁾

(OSCCLK * 1)/4

PLLSTS[DIVSEL] = 2

OSCCLK/2

PLLSTS[DIVSEL] = 3

OSCCLK

0000 (PLL bypass)

0001

(OSCCLK * 1)/2

(OSCCLK * 2)/2

(OSCCLK * 3)/2

(OSCCLK * 4)/2

(OSCCLK * 5)/2

(OSCCLK * 6)/2

(OSCCLK * 7)/2

(OSCCLK * 8)/2

(OSCCLK * 9)/2

(OSCCLK * 10)/2

(OSCCLK * 11)/2

(OSCCLK * 12)/2

(OSCCLK * 1)/1

(OSCCLK * 2)/1

(OSCCLK * 3)/1

(OSCCLK * 4)/1

(OSCCLK * 5)/1

(OSCCLK * 6)/1

(OSCCLK * 7)/1

(OSCCLK * 8)/1

(OSCCLK * 9)/1

(OSCCLK * 10)/1

(OSCCLK * 11)/1

(OSCCLK * 12)/1

0010

(OSCCLK * 2)/4

0011

(OSCCLK * 3)/4

0100

(OSCCLK * 4)/4

0101

(OSCCLK * 5)/4

0110

(OSCCLK * 6)/4

0111

(OSCCLK * 7)/4

1000

(OSCCLK * 8)/4

1001

(OSCCLK * 9)/4

1010

(OSCCLK * 10)/4

(OSCCLK * 11)/4

(OSCCLK * 12)/4

1011

1100

(1) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog

reset only. A reset issued by the debugger or the missing clock detect logic has no effect.

(2) This register is EALLOW protected. See the TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference Guide

(literature number SPRUFN3) for more information.

(3) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /1.) PLLSTS[DIVSEL] must be 0 before writing to the

PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.

Table 3-18. CLKIN Divide Options

PLLSTS [DIVSEL]

CLKIN DIVIDE

0

1

2

3

/4

/2

/1

The PLL-based clock module provides four modes of operation:

•

INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can provide

the clock for the Watchdog block, core and CPU-Timer 2

•

INTOSC2 (Internal Zero-pin Oscillator 2): This is the on-chip internal oscillator 2. This can provide

the clock for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be

independently chosen for the Watchdog block, core and CPU-Timer 2.

•

Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external

crystal/resonator attached to the device to provide the time base. The crystal/resonator is connected to

the X1/X2 pins. Some devices may not have the X1/X2 pins. See Table 2-2 for details.

External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows it to

be bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin.

Note that the XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected

as GPIO19 or GPIO38 via the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit

42

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disables this clock input (forced low). If the clock source is not used or the respective pins are used as

GPIOs, the user should disable at boot time.

Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that

clock source must be disabled (using the CLKCTL register) before switching clocks.

Table 3-19. Possible PLL Configuration Modes

CLKIN AND

SYSCLKOUT

PLL MODE

REMARKS

PLLSTS[DIVSEL]

Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block

is disabled in this mode. This can be useful to reduce system noise and for low

power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)

before entering this mode. The CPU clock (CLKIN) is derived directly from the

input clock on either X1/X2, X1 or XCLKIN.

0, 1

2

3

OSCCLK/4

OSCCLK/2

OSCCLK/1

PLL Off

PLL Bypass is the default PLL configuration upon power-up or after an external

reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or

while the PLL locks to a new frequency after the PLLCR register has been

modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.

0, 1

2

3

OSCCLK/4

OSCCLK/2

OSCCLK/1

PLL Bypass

PLL Enable

0, 1

2

3

OSCCLK * n/4

OSCCLK * n/2

OSCCLK * n/1

Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the

PLLCR the device will switch to PLL Bypass mode until the PLL locks.

3.8.4 Loss of Input Clock (NMI Watchdog Function)

The 2802x devices may be clocked from either one of the internal zero-pin oscillators

(INTOSC1/INTOSC2), the on-chip crystal oscillator, or from an external clock input. Regardless of the

clock source, in PLL-enabled and PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will

issue a limp-mode clock at its output. This limp-mode clock continues to clock the CPU and peripherals at

a typical frequency of 1–5 MHz.

When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt.

Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired

immediately or the NMI watchdog counter can issue a reset when it overflows. In addition to this, the

Missing Clock Status (MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect

the input clock failure and initiate necessary corrective action such as switching over to an alternative

clock source (if available) or initiate a shut-down procedure for the system.

If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a

preprogrammed time interval. Figure 3-14 shows the interrupt mechanisms involved.

Functional Overview

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NMIFLG[NMINT]

NMIFLGCLR[NMINT]

Clear

Latch

Set

Clear

XRS

Generate

Interrupt

Pulse

When

Input = 1

NMIFLG[CLOCKFAIL]

Clear

Latch

1

0

NMIFLGCLR[CLOCKFAIL]

CLOCKFAIL

NMINT

SYNC?

Set

Clear

SYSCLKOUT

NMICFG[CLOCKFAIL]

NMIFLGFRC[CLOCKFAIL]

XRS

SYSCLKOUT

SYSRS

NMIWDPRD[15:0]

NMIWDCNT[15:0]

See System

Control Section

NMI Watchdog

NMIRS

Figure 3-14. NMI-watchdog

3.8.5 CPU-Watchdog Module

The CPU-watchdog module on the 2802x device is similar to the one used on the 281x/280x/283xx

devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit

watchdog up counter has reached its maximum value. To prevent this, the user must disable the counter

or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register that resets

the watchdog counter. Figure 3-15 shows the various functional blocks within the watchdog module.

Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a

CPU-watchdog reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog

counter stops decrementing (i.e., the watchdog counter does not change with the limp-mode clock).

NOTE

The CPU-watchdog is different from the NMI watchdog. It is the legacy watchdog that is

present in all 28x devices.

NOTE

Applications in which the correct CPU operating frequency is absolutely critical should

implement a mechanism by which the MCU will be held in reset, should the input clocks ever

fail. For example, an R-C circuit may be used to trigger the XRS pin of the MCU, should the

capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a

periodic basis to prevent it from getting fully charged. Such a circuit would also help in

detecting failure of the flash memory.

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WDCR (WDPS[2:0])

WDCR (WDDIS)

WDCNTR(7:0)

WDCLK

8-Bit

Watchdog

Counter

CLR

Watchdog

Prescaler

/512

Clear Counter

Internal

Pullup

WDKEY(7:0)

WDRST

WDINT

Generate

Watchdog

55 + AA

Key Detector

Output Pulse

(512 OSCCLKs)

Good Key

XRS

Bad

WDCHK

Key

Core-reset

SCSR (WDENINT)

WDCR (WDCHK[2:0])

1

0

1

(A)

WDRST

A. The WDRST signal is driven low for 512 OSCCLK cycles.

Figure 3-15. CPU-watchdog Module

The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.

In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains

functional is the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM

block so that it can wake the device from STANDBY (if enabled). See Section 3.9, Low-power Modes

Block, for more details.

In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of

IDLE mode.

In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset.

Functional Overview

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3.9 Low-power Modes Block

Table 3-20 summarizes the various modes.

Table 3-20. Low-power Modes

MODE

LPMCR0(1:0)

OSCCLK

CLKIN

SYSCLKOUT

EXIT⁽¹⁾

XRS, CPU-watchdog interrupt, any

enabled interrupt

IDLE

00

On

XRS, CPU-watchdog interrupt, GPIO

Port A signal, debugger⁽²⁾

STANDBY

HALT⁽³⁾

01

Off

(CPU-watchdog still running)

Off

(on-chip crystal oscillator and

PLL turned off, zero-pin oscillator

and CPU-watchdog state

dependent on user code.)

XRS, GPIO Port A signal, debugger⁽²⁾

CPU-watchdog

,

1X

Off

(1) The Exit column lists which signals or under what conditions the low power mode is exited. A low signal, on any of the signals, exits the

low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-power

mode will not be exited and the device will go back into the indicated low power mode.

(2) The JTAG port can still function even if the CPU clock (CLKIN) is turned off.

(3) The WDCLK must be active for the device to go into HALT mode.

The various low-power modes operate as follows:

IDLE Mode:

This mode is exited by any enabled interrupt that is recognized by the

processor. The LPM block performs no tasks during this mode as long as

the LPMCR0(LPM) bits are set to 0,0.

STANDBY Mode:

Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY

mode. The user must select which signal(s) will wake the device in the

GPIOLPMSEL register. The selected signal(s) are also qualified by the

OSCCLK before waking the device. The number of OSCCLKs is specified in

the LPMCR0 register.

HALT Mode:

CPU-watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake

the device from HALT mode. The user selects the signal in the

GPIOLPMSEL register.

NOTE

The low-power modes do not affect the state of the output pins (PWM pins included). They

will be in whatever state the code left them in when the IDLE instruction was executed. See

the TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference

Guide (literature number SPRUFN3) for more details.

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4 Peripherals

4.1 Analog Block

A 12-bit ADC core is implemented that has different timings than the 12-bit ADC used on F280x/F2833x.

The ADC wrapper is modified to incorporate the new timings and also other enhancements to improve the

timing control of start of conversions. Figure 4-1 shows the interaction of the analog module with the rest

of the F2802x system.

(3.3 V) VDDA

(Agnd) VSSA

VREFLO

38-Pin

VDDA

48-Pin

VDDA

VREFLO VREFLO

Tied To Tied To

Interface Reference

Diff

VSSA

VREFHI VREFHI

Tied To Tied To

VREFHI

A0

B0

A0

A2

A4

A6

A0

A1

A2

A3

A4

A1

B1

COMP1OUT

A2

AIO2

AIO10

10-Bit

DAC

Comp1

Comp2

B2

A6

A7

A3

B3

ADC

COMP2OUT

(See Note A)

A4

B4

B1

B2

B3

B4

AIO4

AIO12

10-Bit

DAC

B2

B4

B6

B5

B6

B7

Temperature Sensor

A5

A6

Signal Pinout

AIO6

AIO14

B6

A7

B7

A. Comparator 2 is only available on the 48-pin PT package.

Figure 4-1. Analog Pin Configurations

Peripherals

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4.1.1 ADC

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4.1.1.1 Features

The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The

sample-and-hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total

of up to 13 analog input channels. The converter can be configured to run with an internal bandgap

reference to create true-voltage based conversions or with a pair of external voltage references

(V_REFHI/V_REFLO) to create ratiometric-based conversions.

Contrary to previous ADC types, this ADC is not sequencer-based. It is easy for the user to create a

series of conversions from a single trigger. However, the basic principle of operation is centered around

the configurations of individual conversions, called SOCs, or Start-Of-Conversions.

Functions of the ADC module include:

•

12-bit ADC core with built-in dual sample-and-hold (S/H)

Simultaneous sampling or sequential sampling modes

Full range analog input: 0 V to 3.3 V fixed, or V_REFHI/V_REFLOratiometric. The digital value of the input

analog voltage is derived by:

–

Internal Reference (V_REFLO= V_SSA. V_REFHImust not exceed V_DDAwhen using either internal or

external reference modes.)

Digital Value = 0,

when input £ 0 V

Input Analog Voltage -

V_REFLO

Digital Value = 4096 ´

when 0 V < input < 3.3 V

3.3

Digital Value = 4095,

when input ³ 3.3 V

–

External Reference (V_REFHI/V_REFLOconnected to external references. V_REFHImust not exceed V_DDA

when using either internal or external reference modes.)

Digital Value = 0,

when input £ 0 V

Input Analog Voltage -

V_REFLO

Digital Value = 4096 ´

when 0 V < input <

V_REFHI

-

V_REFHIV_REFLO

Digital Value = 4095,

when input ³

V_REFHI

•

Runs at full system clock, no prescaling required

Up to 16-channel, multiplexed inputs

16 SOCs, configurable for trigger, sample window, and channel

16 result registers (individually addressable) to store conversion values

Multiple trigger sources

–

S/W – software immediate start

ePWM 1–7

GPIO XINT2

CPU Timers 0/1/2

ADCINT1/2

•

9 flexible PIE interrupts, can configure interrupt request after any conversion

48

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Table 4-1. ADC Configuration and Control Registers

SIZE

(x16)

EALLOW

PROTECTED

REGISTER NAME

ADDRESS

DESCRIPTION

ADCCTL1

0x7100

0x7104

0x7105

0x7106

0x7107

0x7108

0x7109

0x710A

0x710B

0x710C

0x7110

0x7112

0x7114

0x7115

0x7118

0x711A

0x711C

0x711E

1

Yes

No

Control 1 Register

ADCINTFLG

Interrupt Flag Register

ADCINTFLGCLR

ADCINTOVF

No

Interrupt Flag Clear Register

No

Interrupt Overflow Register

ADCINTOVFCLR

ADCINTSEL1AND2

ADCINTSEL3AND4

ADCINTSEL5AND6

ADCINTSEL7AND8

ADCINTSEL9AND10

ADCSOCPRIORITYCTL

ADCSAMPLEMODE

ADCINTSOCSEL1

ADCINTSOCSEL2

ADCSOCFLG1

No

Interrupt Overflow Clear Register

Yes

No

Interrupt 1 and 2 Selection Register

Interrupt 3 and 4 Selection Register

Interrupt 5 and 6 Selection Register

Interrupt 7 and 8 Selection Register

Interrupt 9 Selection Register (reserved Interrupt 10 Selection)

SOC Priority Control Register

Sampling Mode Register

Interrupt SOC Selection 1 Register (for 8 channels)

Interrupt SOC Selection 2 Register (for 8 channels)

SOC Flag 1 Register (for 16 channels)

SOC Force 1 Register (for 16 channels)

SOC Overflow 1 Register (for 16 channels)

SOC Overflow Clear 1 Register (for 16 channels)

SOC0 Control Register to SOC15 Control Register

ADCSOCFRC1

No

ADCSOCOVF1

No

ADCSOCOVFCLR1

No

ADCSOC0CTL to

ADCSOC15CTL

0x7120 –

0x712F

Yes

ADCREFTRIM

ADCOFFTRIM

ADCREV

0x7140

0x7141

0x714F

1

Yes

No

Reference Trim Register

Offset Trim Register

Revision Register

Table 4-2. ADC Result Registers (Mapped to PF0)

SIZE

(x16)

EALLOW

PROTECTED

REGISTER NAME

ADDRESS

DESCRIPTION

ADCRESULT0 to

ADCRESULT15

0xB00 –

0xB0F

1

No

ADC Result 0 Register to ADC Result 15 Register

Peripherals

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0-Wait

Result

Registers

PF0 (CPU)

PF2 (CPU)

SYSCLKOUT

ADCENCLK

ADCINT 1

PIE

ADCINT 9

TINT 0

TINT 1

TINT 2

ADC

Core

12-Bit

CPUTIMER 0

CPUTIMER 1

CPUTIMER 2

AIO

MUX

ADC

Channels

ADCTRIG 1

ADCTRIG 2

ADCTRIG 3

XINT 2SOC

XINT 2

ePWM 1

ePWM 2

ePWM 3

ePWM 4

ADCTRIG 4

SOCA 1

SOCB 1

SOCA 2

SOCB 2

SOCA 3

SOCB 3

SOCA 4

SOCB 4

ADCTRIG 5

ADCTRIG 6

ADCTRIG 7

ADCTRIG 8

ADCTRIG 9

ADCTRIG 10

ADCTRIG 11

ADCTRIG 12

Figure 4-2. ADC Connections

ADC Connections if the ADC is Not Used

It is recommended that the connections for the analog power pins be kept, even if the ADC is not used.

Following is a summary of how the ADC pins should be connected, if the ADC is not used in an

application:

•

V_DDA– Connect to V_DDIO

V_SSA– Connect to V_SS

V_REFLO– Connect to V_SS

ADCINAn, ADCINBn, V_REFHI– Connect to V_SSA

When the ADC module is used in an application, unused ADC input pins should be connected to analog

ground (V_SSA).

NOTE: Unused ADCIN pins that are multiplexed with AIO function should not be directly connected to

analog ground. They should be grounded through a 1-kΩ resistor. This is to prevent an errant code from

configuring these pins as AIO outputs and driving grounded pins to a logic-high state.

When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power

savings.

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4.1.2 ADC MUX

To COMPy A or B input

To ADC Channel X

Logic implemented in GPIO MUX block

AIOx Pin

SYSCLK

AIOxIN

1

AIOxINE

AIODAT Reg

(Read)

SYNC

0

AIODAT Reg

(Latch)

AIOMUX 1 Reg

AIOSET,

AIOCLEAR,

AIOTOGGLE

Regs

AIODIR Reg

(Latch)

1

(0 = Input, 1 = Output)

0

Figure 4-3. AIOx Pin Multiplexing

The ADC channel and Comparator functions are always available. The digital I/O function is available only

when the respective bit in the AIOMUX1 register is 0. In this mode, reading the AIODAT register reflects

the actual pin state.

The digital I/O function is disabled when the respective bit in the AIOMUX1 register is 1. In this mode,

reading the AIODAT register reflects the output latch of the AIODAT register and the input digital I/O buffer

is disabled to prevent analog signals from generating noise.

On reset, the digital function is disabled. If the pin is used as an analog input, users should keep the AIO

function disabled for that pin.

Peripherals

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4.1.3 Comparator Block

Figure 4-4 shows the interaction of the Comparator modules with the rest of the system.

COMP x A

+

COMP x B

COMP

TZ1/2/3

-

GPIO

MUX

COMP x

+

DAC x

Wrapper

ePWM

AIO

MUX

COMPxOUT

DAC

Core

10-Bit

Figure 4-4. Comparator Block Diagram

Table 4-3. Comparator Control Registers

REGISTER

NAME

COMP1

ADDRESS

COMP2

SIZE (x16)

EALLOW PROTECTED

DESCRIPTION

ADDRESS⁽¹⁾

0x6420

COMPCTL

COMPSTS

DACVAL

0x6400

0x6402

0x6406

1

Yes

No

Comparator Control Register

Comparator Status Register

DAC Value Register

0x6422

0x6426

Yes

(1) Comparator 2 is only available on the 48-pin PT package.

52

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4.2 Serial Peripheral Interface (SPI) Module

The device includes the four-pin serial peripheral interface (SPI) module. One SPI module (SPI-A) is

available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of

programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable

bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals

or another processor. Typical applications include external I/O or peripheral expansion through devices

such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the

master/slave operation of the SPI.

The SPI module features include:

•

Four external pins:

–

SPISOMI: SPI slave-output/master-input pin

SPISIMO: SPI slave-input/master-output pin

SPISTE: SPI slave transmit-enable pin

SPICLK: SPI serial-clock pin

NOTE: All four pins can be used as GPIO if the SPI module is not used.

•

Two operational modes: master and slave

Baud rate: 125 different programmable rates.

LSPCLK

Baud rate =

when SPIBRR = 3 to127

when SPIBRR = 0,1, 2

(SPIBRR + 1)

LSPCLK

Baud rate =

4

•

Data word length: one to sixteen data bits

Four clocking schemes (controlled by clock polarity and clock phase bits) include:

–

Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the

SPICLK signal and receives data on the rising edge of the SPICLK signal.

Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.

Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the

SPICLK signal and receives data on the falling edge of the SPICLK signal.

Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.

•

Simultaneous receive and transmit operation (transmit function can be disabled in software)

Transmitter and receiver operations are accomplished through either interrupt-driven or polled

algorithms.

•

Nine SPI module control registers: Located in control register frame beginning at address 7040h.

NOTE

All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.

When a register is accessed, the register data is in the lower byte (7–0), and the upper byte

(15–8) is read as zeros. Writing to the upper byte has no effect.

Enhanced feature:

•

4-level transmit/receive FIFO

Delayed transmit control

Bi-directional 3 wire SPI mode support

Peripherals

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The SPI port operation is configured and controlled by the registers listed in Table 4-4.

Table 4-4. SPI-A Registers

NAME

SPICCR

SPICTL

ADDRESS

0x7040

0x7041

0x7042

0x7044

0x7046

0x7047

0x7048

0x7049

0x704A

0x704B

0x704C

0x704F

SIZE (x16) EALLOW PROTECTED

DESCRIPTION⁽¹⁾

SPI-A Configuration Control Register

SPI-A Operation Control Register

SPI-A Status Register

1

No

SPISTS

SPIBRR

SPIRXEMU

SPIRXBUF

SPITXBUF

SPIDAT

SPI-A Baud Rate Register

SPI-A Receive Emulation Buffer Register

SPI-A Serial Input Buffer Register

SPI-A Serial Output Buffer Register

SPI-A Serial Data Register

SPIFFTX

SPIFFRX

SPIFFCT

SPIPRI

SPI-A FIFO Transmit Register

SPI-A FIFO Receive Register

SPI-A FIFO Control Register

SPI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

Figure 4-5 is a block diagram of the SPI in slave mode.

SPIFFENA

Overrun

INT ENA

Receiver

Overrun Flag

SPIFFTX.14

SPISTS.7

RX FIFO Registers

SPICTL.4

SPIRXBUF

RX FIFO _0

RX FIFO _1

-----

SPIINT

RX FIFO Interrupt

RX Interrupt

Logic

RX FIFO _3

16

SPIRXBUF

Buffer Register

SPIFFOVF

FLAG

SPIFFRX.15

To CPU

TX FIFO Registers

SPITXBUF

TX FIFO _3

TX Interrupt

Logic

TX FIFO Interrupt

-----

TX FIFO _1

SPITX

TX FIFO _0

16

SPI INT

ENA

16

SPI INT FLAG

SPITXBUF

Buffer Register

SPISTS.6

SPICTL.0

TRIWIRE

SPIPRI.0

16

M

S

M

SPIDAT

Data Register

TW

S

SW1

SW2

SPISIMO

M

S

TW

SPIDAT.15 - 0

M

TW

S

SPISOMI

SPISTE

Talk

SPICTL.1

State Control

Master/Slave

SPICTL.2

SPI Char

LSPCLK

SPICCR.3 - 0

S

SW3

3

2

1

0

Clock

Polarity

Clock

Phase

M

S

SPI Bit Rate

SPIBRR.6 - 0

SPICCR.6

SPICTL.3

SPICLK

M

6

5

4

3

2

1

0

A. SPISTE is driven low by the master for a slave device.

Figure 4-5. SPI Module Block Diagram (Slave Mode)

Peripherals

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4.3 Serial Communications Interface (SCI) Module

The devices include one serial communications interface (SCI) module (SCI-A). The SCI module supports

digital communications between the CPU and other asynchronous peripherals that use the standard

non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its

own separate enable and interrupt bits. Both can be operated independently or simultaneously in the

full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity,

overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit

baud-select register.

Features of each SCI module include:

•

Two external pins:

–

SCITXD: SCI transmit-output pin

SCIRXD: SCI receive-input pin

NOTE: Both pins can be used as GPIO if not used for SCI.

Baud rate programmable to 64K different rates:

–

LSPCLK

Baud rate =

when BRR ¹ 0

when BRR = 0

(BRR + 1) * 8

LSPCLK

16

•

Data-word format

–

One start bit

Data-word length programmable from one to eight bits

Optional even/odd/no parity bit

One or two stop bits

•

Four error-detection flags: parity, overrun, framing, and break detection

Two wake-up multiprocessor modes: idle-line and address bit

Half- or full-duplex operation

Double-buffered receive and transmit functions

Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms

with status flags.

–

Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX

EMPTY flag (transmitter-shift register is empty)

–

Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag

(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)

•

Separate enable bits for transmitter and receiver interrupts (except BRKDT)

NRZ (non-return-to-zero) format

NOTE

All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.

When a register is accessed, the register data is in the lower byte (7–0), and the upper byte

(15–8) is read as zeros. Writing to the upper byte has no effect.

Enhanced features:

•

Auto baud-detect hardware logic

4-level transmit/receive FIFO

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

The SCI port operation is configured and controlled by the registers listed in Table 4-5.

Table 4-5. SCI-A Registers⁽¹⁾

EALLOW

PROTECTED

NAME

ADDRESS

SIZE (x16)

DESCRIPTION

SCICCRA

SCICTL1A

0x7050

0x7051

0x7052

0x7053

0x7054

0x7055

0x7056

0x7057

0x7059

0x705A

0x705B

0x705C

0x705F

1

No

SCI-A Communications Control Register

SCI-A Control Register 1

SCIHBAUDA

SCILBAUDA

SCICTL2A

SCI-A Baud Register, High Bits

SCI-A Baud Register, Low Bits

SCI-A Control Register 2

SCIRXSTA

SCIRXEMUA

SCIRXBUFA

SCITXBUFA

SCIFFTXA⁽²⁾

SCIFFRXA⁽²⁾

SCIFFCTA⁽²⁾

SCIPRIA

SCI-A Receive Status Register

SCI-A Receive Emulation Data Buffer Register

SCI-A Receive Data Buffer Register

SCI-A Transmit Data Buffer Register

SCI-A FIFO Transmit Register

SCI-A FIFO Receive Register

SCI-A FIFO Control Register

SCI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce

undefined results.

(2) These registers are new registers for the FIFO mode.

Peripherals

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Figure 4-6 shows the SCI module block diagram.

SCICTL1.1

SCITXD

Frame Format and Mode

SCITXD

TXSHF

TXENA

Register

Parity

Even/Odd Enable

TX EMPTY

SCICTL2.6

8

SCICCR.6 SCICCR.5

TXRDY

TX INT ENA

SCICTL2.0

Transmitter-Data

Buffer Register

SCICTL2.7

TXWAKE

SCICTL1.3

1

8

TX FIFO _0

TX FIFO

Interrupts

TXINT

TX Interrupt

Logic

TX FIFO _1

-----

To CPU

TX FIFO _3

SCI TX Interrupt select logic

SCITXBUF.7-0

WUT

TX FIFO registers

SCIFFENA

AutoBaud Detect logic

SCIFFTX.14

SCIHBAUD. 15 - 8

SCIRXD

RXSHF

Register

Baud Rate

MSbyte

Register

SCIRXD

RXWAKE

LSPCLK

SCIRXST.1

SCILBAUD. 7 - 0

RXENA

SCICTL1.0

8

Baud Rate

LSbyte

Register

SCICTL2.1

Receive Data

Buffer register

SCIRXBUF.7-0

RXRDY

RX/BK INT ENA

SCIRXST.6

8

RX FIFO _3

BRKDT

SCIRXST.5

-----

RX FIFO

Interrupts

RX FIFO_1

RX FIFO _0

RXINT

RX Interrupt

Logic

SCIRXBUF.7-0

RX FIFO registers

To CPU

RXFFOVF

SCIRXST.7 SCIRXST.4 - 2

SCIFFRX.15

RX Error

FE OE PE

RX Error

RX ERR INT ENA

SCICTL1.6

SCI RX Interrupt select logic

Figure 4-6. Serial Communications Interface (SCI) Module Block Diagram

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

4.4 Inter-Integrated Circuit (I2C)

The device contains one I2C Serial Port. Figure 4-7 shows how the I2C peripheral module interfaces

within the device.

The I2C module has the following features:

•

Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):

–

Support for 1-bit to 8-bit format transfers

7-bit and 10-bit addressing modes

General call

START byte mode

Support for multiple master-transmitters and slave-receivers

Support for multiple slave-transmitters and master-receivers

Combined master transmit/receive and receive/transmit mode

Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)

•

One 4-word receive FIFO and one 4-word transmit FIFO

One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the

following conditions:

–

Transmit-data ready

Receive-data ready

Register-access ready

No-acknowledgment received

Arbitration lost

Stop condition detected

Addressed as slave

•

An additional interrupt that can be used by the CPU when in FIFO mode

Module enable/disable capability

Free data format mode

Peripherals

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I2C Module

I2CXSR

I2CDXR

TX FIFO

RX FIFO

FIFO Interrupt to

CPU/PIE

SDA

Peripheral Bus

I2CRSR

I2CDRR

Control/Status

Registers

CPU

Clock

Synchronizer

SCL

Prescaler

Noise Filters

Arbitrator

Interrupt to

CPU/PIE

I2C INT

A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are

also at the SYSCLKOUT rate.

B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power

operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.

Figure 4-7. I2C Peripheral Module Interfaces

The registers in Table 4-6 configure and control the I2C port operation.

Table 4-6. I2C-A Registers

EALLOW

PROTECTED

NAME

ADDRESS

DESCRIPTION

I2C own address register

I2COAR

I2CIER

0x7900

0x7901

0x7902

0x7903

0x7904

0x7905

0x7906

0x7907

0x7908

0x7909

0x790A

0x790C

0x7920

0x7921

–

No

I2C interrupt enable register

I2C status register

I2CSTR

I2CCLKL

I2CCLKH

I2CCNT

I2CDRR

I2CSAR

I2CDXR

I2CMDR

I2CISRC

I2CPSC

I2CFFTX

I2CFFRX

I2CRSR

I2CXSR

I2C clock low-time divider register

I2C clock high-time divider register

I2C data count register

I2C data receive register

I2C slave address register

I2C data transmit register

I2C mode register

I2C interrupt source register

I2C prescaler register

I2C FIFO transmit register

I2C FIFO receive register

I2C receive shift register (not accessible to the CPU)

I2C transmit shift register (not accessible to the CPU)

–

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4.5 Enhanced PWM Modules (ePWM1/2/3/4)

The devices contain up to four enhanced PWM Modules (ePWM). Figure 4-8 shows a block diagram of

multiple ePWM modules. Figure 4-9 shows the signal interconnections with the ePWM. See the

TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module Reference Guide

(literature number SPRUGE9) for more details.

Table 4-7 shows the complete ePWM register set per module.

EPWMSYNCI

EPWM1SYNCI

EPWM1B

EPWM1TZINT

ePWM1

Module

TZ1 to TZ3

EPWM1INT

EPWM2TZINT

PIE

CLOCKFAIL

EMUSTOP

EPWM2INT

EPWMxTZINT

EPWMxINT

TZ5

TZ6

EPWM1ENCLK

TBCLKSYNC

eCAPI

EPWM1SYNCO

EPWM2SYNCI

EPWM1SYNCO

TZ1 to TZ3

COMPOUT1

COMPOUT2

EPWM2B

ePWM2

Module

COMP

CLOCKFAIL

EMUSTOP

EPWM1A

EPWM2A

TZ5

TZ6

H

R

P

W

M

EPWM2ENCLK

TBCLKSYNC

EPWMxA

G

P

I

EPWM2SYNCO

O

M

U

X

SOCA1

SOCB1

SOCA2

SOCB2

SOCAx

SOCBx

ADC

EPWMxSYNCI

EPWMxB

TZ1 to TZ3

ePWMx

Module

CLOCKFAIL

EMUSTOP

TZ5

TZ6

EPWMxENCLK

TBCLKSYNC

System Control

C28x CPU

SOCA1

SOCA2

SPCAx

ADCSOCAO

Pulse Stretch

(32 SYSCLKOUT Cycles, Active-Low Output)

SOCB1

SOCB2

SPCBx

ADCSOCBO

Pulse Stretch

(32 SYSCLKOUT Cycles, Active-Low Output)

Figure 4-8. ePWM

Peripherals

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Time-Base (TB)

CTR=ZERO

Sync

In/Out

Select

Mux

TBPRD Shadow (24)

CTR=CMPB

TBPRDHR (8)

EPWMxSYNCO

Disabled

TBPRD Active (24)

8

CTR=PRD

TBCTL[SYNCOSEL]

TBCTL[PHSEN]

EPWMxSYNCI

DCAEVT1.sync

DCBEVT1.sync

Counter

Up/Down

(16 Bit)

TBCTL[SWFSYNC]

(Software Forced

Sync)

CTR=ZERO

CTR_Dir

TCBNT

Active (16)

CTR=PRD

CTR=ZERO

TBPHSHR (8)

EPWMxINT

CTR=PRD or ZERO

CTR=CMPA

Event

Trigger

and

Interrupt

(ET)

16

8

EPWMxSOCA

Phase

Control

CTR=CMPB

CTR_Dir

(A)

DCAEVT1.soc

(A)

TBPHS Active (24)

EPWMxSOCB

EPWMxSOCA

ADC

DCBEVT1.soc

EPWMxSOCB

Action

Qualifier

(AQ)

CTR=CMPA

CMPAHR (8)

16

High-resolution PWM (HRPWM)

CMPA Active (24)

CMPA Shadow (24)

EPWMxA

EPWMA

PWM

Chopper

(PC)

Trip

Zone

(TZ)

Dead

Band

(DB)

CTR=CMPB

16

CMPB Active (16)

EPWMB

EPWMxB

EPWMxTZINT

TZ1 to TZ3

CMPB Shadow (16)

EMUSTOP

CTR=ZERO

CLOCKFAIL

DCAEVT1.inter

DCBEVT1.inter

(A)

DCAEVT1.force

DCAEVT2.force

DCBEVT1.force

DCBEVT2.force

DCAEVT2.inter

DCBEVT2.inter

A. These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of

the COMPxOUT and TZ signals.

Figure 4-9. ePWM Sub-Modules Showing Critical Internal Signal Interconnections

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4.6 High-Resolution PWM (HRPWM)

This module combines multiple delay lines in a single module and a simplified calibration system by using

a dedicated calibration delay line. For each ePWM module there is one HR delay line.

The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be

achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:

•

Significantly extends the time resolution capabilities of conventionally derived digital PWM

This capability can be utilized in both single edge (duty cycle and phase-shift control) as well as dual

edge control for frequency/period modulation.

•

Finer time granularity control or edge positioning is controlled via extensions to the Compare A and

Phase registers of the ePWM module.

HRPWM capabilities, when available on a particular device, are offered only on the A signal path of an

ePWM module (i.e., on the EPWMxA output). EPWMxB output has conventional PWM capabilities.

NOTE

The minimum SYSCLKOUT frequency allowed for HRPWM is 50 MHz.

NOTE

When dual-edge high-resolution is enabled (high-resolution period mode), the PWMxB output

is not available for use.

Peripherals

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4.7 Enhanced Capture Module (eCAP1)

The device contains an enhanced capture (eCAP) module. Figure 4-10 shows a functional block diagram

of a module.

CTRPHS

(phase register−32 bit)

APWM mode

SYNCIn

CTR_OVF

OVF

CTR [0−31]

PRD [0−31]

CMP [0−31]

TSCTR

(counter−32 bit)

SYNCOut

PWM

compare

logic

Delta−mode

RST

32

CTR=PRD

CTR=CMP

CTR [0−31]

PRD [0−31]

32

eCAPx

32

LD1

CAP1

(APRD active)

Polarity

select

LD

APRD

shadow

32

CMP [0−31]

32

LD2

CAP2

(ACMP active)

Polarity

select

LD

Event

qualifier

Event

Pre-scale

32

ACMP

shadow

Polarity

select

32

LD3

LD4

CAP3

(APRD shadow)

LD

CAP4

(ACMP shadow)

Polarity

select

LD

4

Capture events

4

CEVT[1:4]

Interrupt

Trigger

and

Flag

control

Continuous /

Oneshot

Capture Control

to PIE

CTR_OVF

CTR=PRD

CTR=CMP

Figure 4-10. eCAP Functional Block Diagram

The eCAP module is clocked at the SYSCLKOUT rate.

The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for

low power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

Table 4-8. eCAP Control and Status Registers

NAME

TSCTR

CTRPHS

CAP1

eCAP1

0x6A00

SIZE (x16) EALLOW PROTECTED

DESCRIPTION

Time-Stamp Counter

2

8

1

6

0x6A02

Counter Phase Offset Value Register

Capture 1 Register

0x6A04

CAP2

0x6A06

Capture 2 Register

CAP3

0x6A08

Capture 3 Register

CAP4

0x6A0A

Capture 4 Register

Reserved

ECCTL1

ECCTL2

ECEINT

ECFLG

ECCLR

ECFRC

Reserved

0x6A0C – 0x6A12

0x6A14

Reserved

Capture Control Register 1

Capture Control Register 2

Capture Interrupt Enable Register

Capture Interrupt Flag Register

Capture Interrupt Clear Register

Capture Interrupt Force Register

Reserved

0x6A15

0x6A16

0x6A17

0x6A18

0x6A19

0x6A1A – 0x6A1F

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4.8 JTAG Port

On the 2802x device, the JTAG port is reduced to 5 pins (TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS

and TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the

pins in Figure 4-11. During emulation/debug, the GPIO function of these pins are not available. If the

GPIO38/TCK/XCLKIN pin is used to provide an external clock, an alternate clock source should be used

to clock the device during emulation/debug since this pin will be needed for the TCK function.

NOTE

In 2802x devices, the JTAG pins may also be used as GPIO pins. Care should be taken in

the board design to ensure that the circuitry connected to these pins do not affect the

emulation capabilities of the JTAG pin function. Any circuitry connected to these pins should

not prevent the emulator from driving (or being driven by) the JTAG pins for successful

debug.

TRST = 0: JTAG Disabled (GPIO Mode)

TRST = 1: JTAG Mode

TRST

XCLKIN

GPIO38_in

TCK

TCK/GPIO38

GPIO38_out

C28x

Core

GPIO37_in

TDO

TDO/GPIO37

1

0

GPIO37_out

GPIO36_in

1

0

TMS

TMS/GPIO36

TDI/GPIO35

1

GPIO36_out

GPIO35_in

1

0

TDI

1

GPIO35_out

Figure 4-11. JTAG/GPIO Multiplexing

68

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TMS320F28021, TMS320F28020, TMS320F280200

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

4.9 GPIO MUX

The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition

to providing individual pin bit-banging I/O capability.

The device supports 22 GPIO pins. The GPIO control and data registers are mapped to Peripheral

Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-9 shows the

GPIO register mapping.

Table 4-9. GPIO Registers

NAME

ADDRESS

GPIO CONTROL REGISTERS (EALLOW PROTECTED)

0x6F80 GPIO A Control Register (GPIO0 to 31)

SIZE (x16)

DESCRIPTION

GPACTRL

GPAQSEL1

GPAQSEL2

GPAMUX1

GPAMUX2

GPADIR

2

0x6F82

0x6F84

0x6F86

0x6F88

0x6F8A

0x6F8C

0x6F90

0x6F92

0x6F96

0x6F9A

0x6F9C

0x6FB6

0x6FBA

GPIO A Qualifier Select 1 Register (GPIO0 to 15)

GPIO A Qualifier Select 2 Register (GPIO16 to 31)

GPIO A MUX 1 Register (GPIO0 to 15)

GPIO A MUX 2 Register (GPIO16 to 31)

GPIO A Direction Register (GPIO0 to 31)

GPIO A Pull Up Disable Register (GPIO0 to 31)

GPIO B Control Register (GPIO32 to 38 )

GPIO B Qualifier Select 1 Register (GPIO32 to 38 )

GPIO B MUX 1 Register (GPIO32 to 38 )

GPIO B Direction Register (GPIO32 to 38 )

GPIO B Pull Up Disable Register (GPIO32 to 38 )

Analog, I/O mux 1 register (AIO0 to AIO15)

Analog, I/O Direction Register (AIO0 to AIO15)

GPAPUD

GPBCTRL

GPBQSEL1

GPBMUX1

GPBDIR

GPBPUD

AIOMUX1

AIODIR

GPIO DATA REGISTERS (NOT EALLOW PROTECTED)

GPADAT

GPASET

0x6FC0

0x6FC2

0x6FC4

0x6FC6

0x6FC8

0x6FCA

0x6FCC

0x6FCE

0x6FD8

0x6FDA

0x6FDC

0x6FDE

2

GPIO A Data Register (GPIO0 to 31)

GPIO A Data Set Register (GPIO0 to 31)

GPIO A Data Clear Register (GPIO0 to 31)

GPIO A Data Toggle Register (GPIO0 to 31)

GPIO B Data Register (GPIO32 to 38 )

GPACLEAR

GPATOGGLE

GPBDAT

GPBSET

GPIO B Data Set Register (GPIO32 to 38 )

GPIO B Data Clear Register (GPIO32 to 38 )

GPIO B Data Toggle Register (GPIO32 to 38 )

Analog I/O Data Register (AIO0 to AIO15)

Analog I/O Data Set Register (AIO0 to AIO15)

Analog I/O Data Clear Register (AIO0 to AIO15)

Analog I/O Data Toggle Register (AIO0 to AIO15)

GPBCLEAR

GPBTOGGLE

AIODAT

AIOSET

AIOCLEAR

AIOTOGGLE

GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)

GPIOXINT1SEL

GPIOXINT2SEL

GPIOXINT3SEL

GPIOLPMSEL

0x6FE0

0x6FE1

0x6FE2

0x6FE8

1

2

XINT1 GPIO Input Select Register (GPIO0 to 31)

XINT2 GPIO Input Select Register (GPIO0 to 31)

XINT3 GPIO Input Select Register (GPIO0 to 31)

LPM GPIO Select Register (GPIO0 to 31)

NOTE

There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn/AIOMUXn

and GPxQSELn registers occurs to when the action is valid.

Peripherals

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Table 4-10. GPIOA MUX⁽¹⁾⁽²⁾

DEFAULT AT RESET

PERIPHERAL

PRIMARY I/O

PERIPHERAL

SELECTION 2

PERIPHERAL

SELECTION 3

SELECTION 1

FUNCTION

GPAMUX1 REGISTER

(GPAMUX1 BITS = 00) (GPAMUX1 BITS = 01)

(GPAMUX1 BITS = 10)

(GPAMUX1 BITS = 11)

BITS

1-0

GPIO0

GPIO1

EPWM1A (O)

EPWM1B (O)

EPWM2A (O)

EPWM2B (O)

EPWM3A (O)

EPWM3B (O)

EPWM4A (O)

EPWM4B (O)

Reserved

COMP1OUT (O)

Reserved

3-2

5-4

GPIO2

Reserved

7-6

GPIO3

Reserved

COMP2OUT⁽³⁾(O)

9-8

GPIO4

Reserved

11-10

13-12

15-14

17-16

19-18

21-20

23-22

25-24

27-26

29-28

31-30

GPIO5

Reserved

ECAP1 (I/O)

EPWMSYNCO (O)

Reserved

GPIO6

EPWMSYNCI (I)

SCIRXDA (I)

Reserved

GPIO7

Reserved

GPIO12

Reserved

TZ1 (I)

SCITXDA (O)

Reserved

GPAMUX2 REGISTER

BITS

(GPAMUX2 BITS = 00) (GPAMUX2 BITS = 01)

(GPAMUX2 BITS = 10)

(GPAMUX2 BITS = 11)

1-0

GPIO16

GPIO17

SPISIMOA (I/O)

SPISOMIA (I/O)

SPICLKA (I/O)

SPISTEA (I/O)

Reserved

TZ2 (I)

TZ3 (I)

3-2

5-4

GPIO18

SCITXDA (O)

SCIRXDA (I)

Reserved

XCLKOUT (O)

ECAP1 (I/O)

Reserved

TZ2 (I)

7-6

GPIO19/XCLKIN

Reserved

GPIO28

9-8

11-10

13-12

15-14

17-16

19-18

21-20

23-22

25-24

27-26

29-28

31-30

Reserved

SCIRXDA (I)

SCITXDA (O)

Reserved

SDAA (I/OD)

SCLA (I/OD)

Reserved

GPIO29

TZ3 (I)

Reserved

(1) The word reserved means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of the

pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.

(2) I = Input, O = Output, OD = Open Drain

(3) These functions are not available in the 38-pin package.

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TMS320F28021, TMS320F28020, TMS320F280200

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

Table 4-11. GPIOB MUX⁽¹⁾

DEFAULT AT RESET

PRIMARY I/O FUNCTION

PERIPHERAL

SELECTION 1

PERIPHERAL

SELECTION 2

PERIPHERAL

SELECTION 3

GPBMUX1 REGISTER

BITS

(GPBMUX1 BITS = 00)

(GPBMUX1 BITS = 01)

(GPBMUX1 BITS = 10)

(GPBMUX1 BITS = 11)

1-0

GPIO32⁽²⁾

GPIO33⁽²⁾

SDAA⁽²⁾(I/OD)

SCLA⁽²⁾(I/OD)

COMP2OUT (O)

Reserved

EPWMSYNCI⁽²⁾(I)

EPWMSYNCO⁽²⁾(O)

Reserved

ADCSOCAO ⁽²⁾(O)

ADCSOCBO ⁽²⁾(O)

Reserved

3-2

5-4

GPIO34

7-6

GPIO35 (TDI)

GPIO36 (TMS)

GPIO37 (TDO)

GPIO38/XCLKIN (TCK)

Reserved

9-8

Reserved

11-10

13-12

15-14

17-16

19-18

21-20

23-22

25-24

27-26

29-28

31-30

Reserved

(1) I = Input, O = Output, OD = Open Drain

(2) These pins are not available in the 38-pin package.

Table 4-12. Analog MUX⁽¹⁾

DEFAULT AT RESET

PERIPHERAL SELECTION 2 AND

PERIPHERAL SELECTION 3

AIOx AND PERIPHERAL SELECTION 1

AIOMUX1 REGISTER BITS

AIOMUX1 BITS = 0,x

ADCINA0 (I)

ADCINA1 ⁽²⁾(I)

AIO2 (I/O)

AIOMUX1 BITS = 1,x

1-0

ADCINA0 (I)

ADCINA1 ⁽²⁾(I)

3-2

5-4

ADCINA2 (I), COMP1A (I)

ADCINA3 ⁽²⁾(I)

7-6

ADCINA3 ⁽²⁾(I)

9-8

AIO4 (I/O)

ADCINA4 (I), COMP2A ⁽³⁾(I)

11-10

13-12

15-14

17-16

19-18

21-20

23-22

25-24

27-26

29-28

31-30

ADCINA5 (I)

AIO6 (I/O)

ADCINA7 ⁽²⁾(I)

ADCINB0 (I)

ADCINB1 ⁽²⁾(I)

AIO10 (I/O)

ADCINA5 (I)

ADCINA6 (I)

ADCINA7 ⁽²⁾(I)

ADCINB0 (I)

ADCINB1 ⁽²⁾(I)

ADCINB2 (I), COMP1B (I)

ADCINB3 ⁽²⁾(I)

ADCINB4 (I), COMP2B ⁽³⁾(I)

ADCINB3 ⁽²⁾(I)

AIO12 (I/O)

ADCINB5 (I)

AIO14 (I/O)

ADCINB7 ⁽²⁾(I)

ADCINB5 (I)

ADCINB6 (I)

ADCINB7 ⁽²⁾(I)

(1) I = Input, O = Output

(2) These pins are not available in the 38-pin package.

(3) These functions are not available in the 38-pin package.

Peripherals

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TMS320F28021, TMS320F28020, TMS320F280200

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The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from

four choices:

•

Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins

at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).

•

Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal,

after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles

before the input is allowed to change.

•

The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in

groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The

sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL

samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode).

No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is

not required (synchronization is performed within the peripheral).

Due to the multi-level multiplexing that is required on the device, there may be cases where a peripheral

input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the

input signal will default to either a 0 or 1 state, depending on the peripheral.

72

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TMS320F28021, TMS320F28020, TMS320F280200

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

GPIOXINT1SEL

GPIOLMPSEL

GPIOXINT2SEL

GPIOXINT3SEL

LPMCR0

External Interrupt

MUX

Low Power

Modes Block

PIE

Asynchronous

path

GPxDAT (read)

GPxQSEL1/2

GPxCTRL

GPxPUD

N/C

00

01

Peripheral 1 Input

Peripheral 2 Input

Input

Internal

Pullup

Qualification

10

11

Peripheral 3 Input

GPxTOGGLE

Asynchronous path

GPIOx pin

GPxCLEAR

GPxSET

00

01

GPxDAT (latch)

Peripheral 1 Output

10

11

Peripheral 2 Output

Peripheral 3 Output

High Impedance

Output Control

GPxDIR (latch)

00

01

Peripheral 1 Output Enable

Peripheral 2 Output Enable

0 = Input, 1 = Output

XRS

10

11

Peripheral 3 Output Enable

= Default at Reset

GPxMUX1/2

A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register

depending on the particular GPIO pin selected.

B. GPxDAT latch/read are accessed at the same memory location.

C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the

TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference Guide (literature number

SPRUFN3) for pin-specific variations.

Figure 4-12. GPIO Multiplexing

Peripherals

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TMS320F28020 TMS320F280200

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

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5 Device Support

Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of MCUs,

including tools to evaluate the performance of the processors, generate code, develop algorithm

implementations, and fully integrate and debug software and hardware modules.

The following products support development of 2802x-based applications:

Software Development Tools

•

Code Composer Studio™ Integrated Development Environment (IDE)

–

C/C++ Compiler

Code generation tools

Assembler/Linker

Cycle Accurate Simulator

•

Application algorithms

Sample applications code

Hardware Development Tools

•

Development and evaluation boards

JTAG-based emulators - XDS510™ class, XDS560™ emulator, XDS100

Flash programming tools

Power supply

Documentation and cables

5.1 Device and Development Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

TMS320™ MCU devices and support tools. Each TMS320™ MCU commercial family member has one of

three prefixes: TMX, TMP, or TMS (e.g., TMS320F28023). Texas Instruments recommends two of three

possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary

stages of product development from engineering prototypes (TMX/TMDX) through fully qualified

production devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX

TMP

TMS

Experimental device that is not necessarily representative of the final device's electrical

specifications

Final silicon die that conforms to the device's electrical specifications but has not

completed quality and reliability verification

Fully qualified production device

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal

qualification testing

TMDS Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following

disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies.

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TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

www.ti.com

SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard

production devices. Texas Instruments recommends that these devices not be used in any production

system because their expected end-use failure rate still is undefined. Only qualified production devices are

to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the

package type (for example, PT) and temperature range (for example, S). Figure 5-1 provides a legend for

reading the complete device name for any family member.

TMS 320

F

28023

PT

S

PREFIX

TEMPERATURE RANGE

experimental device

prototype device

qualified device

TMX =

TMP =

TMS =

T

−40°C to 105°C

−40°C to 125°C

=

S

Q

−40°C to 125°C

(Q refers to Q100 qualification for automotive applications.)

DEVICE FAMILY

PACKAGE TYPE

320 = TMS320 MCU Family

48-Pin PT Plastic Quad Flatpack

38-Pin DA Plastic Small-outline Package

DEVICE

28027

28026

28023

28022

28021

28020

280200

TECHNOLOGY

F = Flash

Figure 5-1. Device Nomenclature

Device Support

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TMS320F28021, TMS320F28020, TMS320F280200

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5.2 Related Documentation

Extensive documentation supports all of the TMS320™ MCU family generations of devices from product

announcement through applications development. The types of documentation available include: data

sheets and data manuals, with design specifications; and hardware and software applications.

Table 5-1 shows the peripheral reference guides appropriate for use with the devices in this data manual.

See the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) for more

information on types of peripherals.

Table 5-1. TMS320F2802x, TMS320F2802xx Peripheral Selection Guide

28027, 28026,

28023, 28022,

28021, 28020

PERIPHERAL

LIT. NO.

SPRUFN3

SPRUGE5

TYPE⁽¹⁾

–

280200

TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts

Reference Guide

X

TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and

Comparator

3/0⁽²⁾

X

TMS320x2802x, 2803x Piccolo Serial Communications Interface (SCI)

TMS320x2802x, 2803x Piccolo Serial Peripheral Interface (SPI)

TMS320x2802x Piccolo Boot ROM

SPRUGH1

SPRUG71

SPRUFN6

SPRUGE9

0

1

–

1

X

TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM)

Module

TMS320x2802x, 2803x Piccolo Enhanced Capture (eCAP) Module

TMS320x2802x, 2803x Piccolo Inter-Integrated Circuit (I2C)

SPRUFZ8

SPRUFZ9

SPRUGE8

0

1

X

–

X

–

TMS320x2802x, 2803x Piccolo High-Resolution Pulse-Width Modulator

(HRPWM)

(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor

differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the

peripheral reference guides.

(2) The ADC module is Type 3 and the comparator module is Type 0.

The following documents can be downloaded from the TI website (www.ti.com):

Errata

SPRZ292

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022, TMS320F28021,

TMS320F28020, TMS320F280200 Piccolo MCU Silicon Errata describes known advisories

on silicon and provides workarounds.

CPU User's Guides

SPRU430 TMS320C28x CPU and Instruction Set Reference Guide describes the central processing

unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital

signal processors (DSPs). It also describes emulation features available on these DSPs.

Peripheral Guides

SPRUFN3 TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference

Guide describes the various interrupts and system control features of the 2802x

microcontrollers (MCUs).

SPRU566

TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference

guides of the 28x digital signal processors (DSPs).

SPRUFN6 TMS320x2802x Piccolo Boot ROM Reference Guide describes the purpose and features

of the boot loader (factory-programmed boot-loading software) and provides examples of

code. It also describes other contents of the device on-chip boot ROM and identifies where

all of the information is located within that memory.

76

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TMS320F28021, TMS320F28020, TMS320F280200

www.ti.com

SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

SPRUGE5 TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator

Reference Guide describes how to configure and use the on-chip ADC module, which is a

12-bit pipelined ADC.

SPRUGE9 TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module

Reference Guide describes the main areas of the enhanced pulse width modulator that

include digital motor control, switch mode power supply control, UPS (uninterruptible power

supplies), and other forms of power conversion.

SPRUGE8 TMS320x2802x, 2803x Piccolo High-Resolution Pulse Width Modulator (HRPWM)

describes the operation of the high-resolution extension to the pulse width modulator

(HRPWM).

SPRUGH1 TMS320x2802x, 2803x Piccolo Serial Communications Interface (SCI) Reference Guide

describes how to use the SCI.

SPRUFZ8 TMS320x2802x, 2803x Piccolo Enhanced Capture (eCAP) Module Reference Guide

describes the enhanced capture module. It includes the module description and registers.

SPRUG71 TMS320x2802x, 2803x Piccolo Serial Peripheral Interface (SPI) Reference Guide

describes the SPI - a high-speed synchronous serial input/output (I/O) port - that allows a

serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the

device at a programmed bit-transfer rate.

SPRUFZ9 TMS320x2802x, 2803x Piccolo Inter-Integrated Circuit (I2C) Reference Guide describes

the features and operation of the inter-integrated circuit (I2C) module.

Tools Guides

SPRU513

TMS320C28x Assembly Language Tools v5.0.0 User's Guide describes the assembly

language tools (assembler and other tools used to develop assembly language code),

assembler directives, macros, common object file format, and symbolic debugging directives

for the TMS320C28x device.

SPRU514

SPRU608

TMS320C28x Optimizing C/C++ Compiler v5.0.0 User's Guide describes the

TMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code

and produces TMS320 DSP assembly language source code for the TMS320C28x device.

TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,

available within the Code Composer Studio for TMS320C2000 IDE, that simulates the

instruction set of the C28x™ core.

5.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the

respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;

see TI's Terms of Use.

TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and

help solve problems with fellow engineers.

TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help

developers get started with Embedded Processors from Texas Instruments and to foster

innovation and growth of general knowledge about the hardware and software surrounding

these devices.

Device Support

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TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

www.ti.com

6 Electrical Specifications

6.1 Absolute Maximum Ratings^{(1) (2)}

Supply voltage range, V_DDIO(I/O and Flash)

Supply voltage range, V_DD

with respect to V_SS

with respect to V_SSA

–0.3 V to 4.6 V

–0.3 V to 2.5 V

–0.3 V to 4.6 V

±20 mA

Analog voltage range, V_DDA

Input voltage range, V_IN(3.3 V)

Output voltage range, V_O

(3)

Input clamp current, I_IK(V_IN< 0 or V_IN> V_DDIO

)

Output clamp current, I_OK(V_O< 0 or V_O> V_DDIO

)

±20 mA

(4)

Junction temperature range, T_J

–40°C to 150°C

–65°C to 150°C

(4)

Storage temperature range, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS, unless otherwise noted.

(3) Continuous clamp current per pin is ± 2 mA.

(4) Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device

life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for

TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963).

6.2 Recommended Operating Conditions

MIN

2.97

1.71

NOM

3.3

MAX

3.63

UNIT

(1)(2)

Device supply voltage, I/O, V_DDIO

V

Device supply voltage CPU, V_DD(When internal

VREG is disabled and 1.8 V is supplied externally)

1.8

1.995

V

Supply ground, V_SS

0

3.3

0

V

(1)

Analog supply voltage, V_DDA

2.97

3.63

Analog ground, V_SSA

Device clock frequency (system clock)

28020, 28021, 280200

28022, 28023

2

40

2

50

60

MHz

28026, 28027

2

High-level input voltage, V_IH(3.3 V)

V_DDIO+ 0.3

0.8

V

Low-level input voltage, V_IL(3.3 V)

V_SS– 0.3

V

High-level output source current, V_OH= V_OH(MIN), I_OH

All GPIO/AIO pins

Group 2⁽³⁾

–4

–8

4

mA

Low-level output sink current, V_OL= V_OL(MAX), I_OL

All GPIO/AIO pins

Group 2⁽³⁾

8

(4)

Junction temperature, T_J

T version

–40

105

125

S version

°C

Q version

(Q100 Qualification)

(1) V_DDIOand V_DDAshould be maintained within ~0.3 V of each other.

(2) A tolerance of ±10% may be used for V_DDIOif the BOR is not used. See the TMS320F28027, TMS320F28026, TMS320F28023,

TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200 Piccolo MCU Silicon Errata (literature number SPRZ292) for more

information. V_DDIOtolerance is ±5% if the BOR is enabled.

(3) Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO19, GPIO28, GPIO29, GPIO36, GPIO37

(4) T_A(Ambient temperature) is product- and application-dependent and can go up to the specified T_Jmax of the device. See Section 6.5,

Thermal Design Considerations.

78

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

6.3 Electrical Characteristics⁽¹⁾

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

2.4

TYP

MAX UNIT

I_OH= I_OHMAX

I_OH= 50 mA

V_OH

V_OL

High-level output voltage

Low-level output voltage

V

V_DDIO– 0.2

I_OL= I_OLMAX

0.4

–205

–360

V

All GPIO/AIO

XRS pin

–80

–140

–290

Pin with pullup

V_DDIO= 3.3 V, V_IN= 0 V

enabled

Input current

(low level)

–225

I_IL

mA

Pin with pulldown

enabled

V_DDIO= 3.3 V, V_IN= 0 V

V_DDIO= 3.3 V, V_IN= V_DDIO

V_O= V_DDIOor 0 V

±2

80

Pin with pullup

enabled

Input current

(high level)

I_IH

mA

Pin with pulldown

enabled

28

50

Output current, pullup or

pulldown disabled

I_OZ

C_I

±2 mA

Input capacitance

2

2.65

35

pF

V_DDIOBOR trip point

V_DDIOBOR hysteresis

Falling V_DDIO

2.42

400

3.135

V

mV

Supervisor reset release delay

time

Time after BOR/POR/OVR event is removed to XRS

release

800 ms

VREG V_DDoutput

Internal VREG on

1.9

V

(1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage

(V_DD) go out of range.

Electrical Specifications

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TMS320F28021, TMS320F28020, TMS320F280200

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6.4 Current Consumption

Table 6-1. TMS320F2802x/F280200⁽¹⁾Current Consumption at 40-MHz SYSCLKOUT

VREG ENABLED

VREG DISABLED

(2)

(3)

(2)

(3)

MODE

TEST CONDITIONS

I_DDIO

TYP⁽⁴⁾

I_DDA

TYP⁽⁴⁾

I_DD

I_DDIO

TYP⁽⁴⁾

I_DDA

TYP⁽⁴⁾

MAX

TYP⁽⁴⁾

MAX

The following peripheral clocks are

enabled:

•

ePWM1/2/3/4

eCAP1

SCI-A

SPI-A

ADC

Operational

(Flash)

70 mA 80 mA 13 mA 18 mA

62 mA

70 mA

15 mA

18 mA 13 mA

18 mA

I2C

COMP1/2

CPU Timer0/1/2

All PWM pins are toggled at 40 kHz.

All I/O pins are left unconnected.⁽⁵⁾

Code is running out of flash with

1 wait-state.

XCLKOUT is turned off.

Flash is powered down.

XCLKOUT is turned off.

All peripheral clocks are off.

IDLE

13 mA 16 mA

53 mA

10 mA

58 mA

15 mA

3 mA

17 mA

6 mA

120 mA

25 mA

400 mA 53 mA

400 mA 10 mA

10 mA

58 mA

15 mA

Flash is powered down.

Peripheral clocks are off.

STANDBY

HALT

3 mA

6 mA

Flash is powered down.

Peripheral clocks are off.

Input clock is disabled.⁽⁶⁾

50 mA

15 mA

(1) For the TMS320F280200 device, subtract the I_DDcurrent number for eCAP (see Table 6-4) from I_DD(VREG disabled)/I_DDIO(VREG

enabled) current numbers shown in Table 6-1 for operational mode.

(2) I_DDIOcurrent is dependent on the electrical loading on the I/O pins.

(3) In order to realize the I_DDAcurrents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by

writing to the PCLKCR0 register.

(4) The TYP numbers are applicable over room temperature and nominal voltage.

(5) The following is done in a loop:

•

Data is continuously transmitted out of SPI-A and SCI-A ports.

The hardware multiplier is exercised.

Watchdog is reset.

ADC is performing continuous conversion.

COMP1/2 are continuously switching voltages.

GPIO17 is toggled.

(6) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.

80

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Table 6-2. TMS320F2802x Current Consumption at 50-MHz SYSCLKOUT

VREG ENABLED

VREG DISABLED

(1)

(2)

(1)

(2)

MODE

TEST CONDITIONS

I_DDIO

TYP⁽³⁾

I_DDA

TYP⁽³⁾

I_DD

I_DDIO

TYP⁽³⁾

I_DDA

TYP⁽³⁾

MAX

TYP⁽³⁾

MAX

The following peripheral clocks are

enabled:

•

ePWM1/2/3/4

eCAP1

SCI-A

SPI-A

ADC

Operational

(Flash)

80 mA 90 mA 13 mA 18 mA

71 mA

80 mA

15 mA

18 mA 13 mA

18 mA

I2C

COMP1/2

CPU Timer0/1/2

All PWM pins are toggled at 40 kHz.

All I/O pins are left unconnected.⁽⁴⁾

Code is running out of flash with

1 wait-state.

XCLKOUT is turned off.

Flash is powered down.

XCLKOUT is turned off.

All peripheral clocks are off.

IDLE

16 mA 19 mA

64 mA

10 mA

69 mA

15 mA

17 mA

4 mA

20 mA

7 mA

120 mA

25 mA

400 mA 64 mA

400 mA 10 mA

10 mA

69 mA

15 mA

Flash is powered down.

Peripheral clocks are off.

STANDBY

HALT

4 mA

7 mA

Flash is powered down.

Peripheral clocks are off.

Input clock is disabled.⁽⁵⁾

50 mA

15 mA

(1) I_DDIOcurrent is dependent on the electrical loading on the I/O pins.

(2) In order to realize the I_DDAcurrents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by

writing to the PCLKCR0 register.

(3) The TYP numbers are applicable over room temperature and nominal voltage.

(4) The following is done in a loop:

•

Data is continuously transmitted out of SPI-A and SCI-A ports.

The hardware multiplier is exercised.

Watchdog is reset.

ADC is performing continuous conversion.

COMP1/2 are continuously switching voltages.

GPIO17 is toggled.

(5) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.

Electrical Specifications

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TMS320F28021, TMS320F28020, TMS320F280200

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Table 6-3. TMS320F2802x Current Consumption at 60-MHz SYSCLKOUT

VREG ENABLED

VREG DISABLED

(1)

(2)

(1)

(2)

MODE

TEST CONDITIONS

I_DDIO

TYP⁽³⁾

I_DDA

TYP⁽³⁾

I_DD

I_DDIO

TYP⁽³⁾

I_DDA

TYP⁽³⁾

MAX

TYP⁽³⁾

MAX

The following peripheral clocks

are enabled:

•

ePWM1/2/3/4

eCAP1

SCI-A

SPI-A

ADC

Operational

(Flash)

I2C

90 mA

100 mA

13 mA

18 mA

80 mA

90 mA

15 mA

18 mA 13 mA

18 mA

COMP1/2

CPU-TIMER0/1/2

All PWM pins are toggled at

60 kHz.

All I/O pins are left

unconnected.⁽⁴⁾

Code is running out of flash

with 2 wait-states.

XCLKOUT is turned off.

Flash is powered down.

XCLKOUT is turned off.

All peripheral clocks are turned

off.

IDLE

18 mA

23 mA

7 mA

75 mA

80 mA

19 mA

24 mA

7 mA

120 mA 400 mA 75 mA

120 mA 400 mA 10 mA

80 mA

Flash is powered down.

Peripheral clocks are off.

STANDBY

HALT

4 mA

10 mA

15 mA

4 mA

15 mA

Flash is powered down.

Peripheral clocks are off.

Input clock is disabled.⁽⁵⁾

50 mA

15 mA

25 mA

10 mA

(1) I_DDIOcurrent is dependent on the electrical loading on the I/O pins.

(2) In order to realize the I_DDAcurrents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by

writing to the PCLKCR0 register.

(3) The TYP numbers are applicable over room temperature and nominal voltage.

(4) The following is done in a loop:

•

Data is continuously transmitted out of SPI-A and SCI-A ports.

The hardware multiplier is exercised.

Watchdog is reset.

ADC is performing continuous conversion.

COMP1/2 are continuously switching voltages.

GPIO17 is toggled.

(5) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.

NOTE

The peripheral - I/O multiplexing implemented in the device prevents all available peripherals

from being used at the same time. This is because more than one peripheral function may

share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the

same time, although such a configuration is not useful. If this is done, the current drawn by

the device will be more than the numbers specified in the current consumption tables.

82

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6.4.1 Reducing Current Consumption

The 2802x/280200 devices incorporate a method to reduce the device current consumption. Since each

peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be

achieved by turning off the clock to any peripheral module that is not used in a given application.

Furthermore, any one of the three low-power modes could be taken advantage of to reduce the current

consumption even further. Table 6-4 indicates the typical reduction in current consumption achieved by

turning off the clocks.

Table 6-4. Typical Current Consumption by Various

Peripherals (at 60 MHz)⁽¹⁾

PERIPHERAL

MODULE⁽²⁾

I_DDCURRENT

REDUCTION (mA)

ADC

2⁽³⁾

I2C

ePWM

3

2

eCAP

2

SCI

2

SPI

2

COMP/DAC

HRPWM

1

3

CPU-TIMER

Internal zero-pin oscillator

1

0.5

(1) All peripheral clocks (except CPU Timer clocks) are disabled upon

reset. Writing to/reading from peripheral registers is possible only

after the peripheral clocks are turned on.

(2) For peripherals with multiple instances, the current quoted is per

module. For example, the 2 mA value quoted for ePWM is for one

ePWM module.

(3) This number represents the current drawn by the digital portion of

the ADC module. Turning off the clock to the ADC module results in

the elimination of the current drawn by the analog portion of the ADC

(I_DDA) as well.

NOTE

I_DDIOcurrent consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.

NOTE

The baseline I_DDcurrent (current when the core is executing a dummy loop with no

peripherals enabled) is 45 mA, typical. To arrive at the I_DDcurrent for a given application, the

current-drawn by the peripherals (enabled by that application) must be added to the baseline

I_DDcurrent.

Following are other methods to reduce power consumption further:

•

The flash module may be powered down if code is run off SARAM. This results in a current reduction

of 18 mA (typical) in the V_DDrail and 13 mA (typical) in the V_DDIOrail.

•

Savings in I_DDIOmay be realized by disabling the pullups on pins that assume an output function.

Electrical Specifications

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6.4.2 Current Consumption Graphs (VREG Enabled)

Operational Current vs Frequency

100

90

80

70

60

50

40

30

20

10

0

10

15

20

25

30

35

40

45

50

55

60

SYSCLKOUT (MHz)

IDDIO (mA)

IDDA

Figure 6-1. Typical Operational Current Versus Frequency (F2802x/F280200)

Operational Power vs Frequency

450

400

350

300

250

200

10

15

20

25

30

35

40

45

50

55

60

SYSCLKOUT (MHz)

Figure 6-2. Typical Operational Power Versus Frequency (F2802x/F280200)

84

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TMS320F28021, TMS320F28020, TMS320F280200

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6.5 Thermal Design Considerations

Based on the end application design and operational profile, the I_DDand I_DDIOcurrents could vary.

Systems that exceed the recommended maximum power dissipation in the end product may require

additional thermal enhancements. Ambient temperature (T_A) varies with the end application and product

design. The critical factor that affects reliability and functionality is T_J, the junction temperature, not the

ambient temperature. Hence, care should be taken to keep T_Jwithin the specified limits. T_caseshould be

measured to estimate the operating junction temperature T_J. T_caseis normally measured at the center of

the package top-side surface. The thermal application reports IC Package Thermal Metrics (literature

number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices (literature number

SPRA963) help to understand the thermal metrics and definitions.

6.6 Emulator Connection Without Signal Buffering for the MCU

Figure 6-3 shows the connection between the MCU and JTAG header for a single-processor configuration.

If the distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals

must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-3 shows

the simpler, no-buffering situation. For the pullup/pulldown resistor values, see Section 2.2, Signal

Descriptions.

6 inches or less

V_DDIO

13

14

2

5

EMU0

EMU1

TRST

TMS

PD

4

6

8

TRST

TMS

TDI

GND

1

GND

3

TDI

7

10

12

TDO

TCK

TDO

11

9

TCK

TCK_RET

MCU

JTAG Header

A. See Figure 4-11 for JTAG/GPIO multiplexing.

Figure 6-3. Emulator Connection Without Signal Buffering for the MCU

NOTE

The 2802x devices do not have EMU0/EMU1 pins. For designs that have a JTAG Header

on-board, the EMU0/EMU1 pins on the header must be tied to V_DDIOthrough a 4.7-kΩ

(typical) resistor.

Electrical Specifications

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6.7 Timing Parameter Symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the

symbols, some of the pin names and other related terminology have been abbreviated as follows:

Lowercase subscripts and their

meanings:

Letters and symbols and their

meanings:

a

c

d

access time

H

L

High

Low

cycle time (period)

delay time

V

Valid

Unknown, changing, or don't care

level

f

fall time

X

Z

h

r

hold time

High impedance

rise time

su

t

setup time

transition time

valid time

v

w

pulse duration (width)

6.7.1 General Notes on Timing Parameters

All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that

all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.

The signal combinations shown in the following timing diagrams may not necessarily represent actual

cycles. For actual cycle examples, see the appropriate cycle description section of this document.

6.7.2 Test Load Circuit

This test load circuit is used to measure all switching characteristics provided in this document.

Tester Pin Electronics

Data Sheet Timing Reference Point

W

3.5 nH

Output

Under

Test

42

Transmission Line

(A)

Z0 = 50 W

Device Pin^(B)

4.0 pF

1.85 pF

A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the

device pin.

B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to

produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to

add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.

Figure 6-4. 3.3-V Test Load Circuit

86

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6.7.3 Device Clock Table

This section provides the timing requirements and switching characteristics for the various clock options

available on the 2802x MCUs. Table 6-5, Table 6-6, and Table 6-7 list the cycle times of various clocks.

Table 6-5. 2802x Clock Table and Nomenclature (40-MHz Devices)

MIN

25

2

NOM

MAX UNIT

t_c(SCO), Cycle time

Frequency

500

40

ns

MHz

ns

SYSCLKOUT

LSPCLK⁽¹⁾

ADC clock

t_c(LCO), Cycle time

Frequency

25

100⁽²⁾

10⁽²⁾

40

MHz

ns

t_c(ADCCLK), Cycle time

Frequency

25

MHz

(1) Lower LSPCLK will reduce device power consumption.

(2) This is the default reset value if SYSCLKOUT = 40 MHz.

Table 6-6. 2802x Clock Table and Nomenclature (50-MHz Devices)

MIN

20

2

NOM

MAX UNIT

t_c(SCO), Cycle time

Frequency

500

50

ns

MHz

ns

SYSCLKOUT

LSPCLK⁽¹⁾

ADC clock

t_c(LCO), Cycle time

Frequency

20

80⁽²⁾

12.5⁽²⁾

50

MHz

ns

t_c(ADCCLK), Cycle time

Frequency

20

MHz

(1) Lower LSPCLK will reduce device power consumption.

(2) This is the default reset value if SYSCLKOUT = 50 MHz.

Table 6-7. 2802x Clock Table and Nomenclature (60-MHz Devices)

MIN

16.67

2

NOM

MAX UNIT

t_c(SCO), Cycle time

Frequency

500

60

ns

MHz

ns

SYSCLKOUT

LSPCLK⁽¹⁾

ADC clock

t_c(LCO), Cycle time

Frequency

16.67

66.67⁽²⁾

15⁽²⁾

60

MHz

ns

t_c(ADCCLK), Cycle time

Frequency

16.67

MHz

(1) Lower LSPCLK will reduce device power consumption.

(2) This is the default reset value if SYSCLKOUT = 60 MHz.

Electrical Specifications

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TMS320F28021, TMS320F28020, TMS320F280200

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Table 6-8. Device Clocking Requirements/Characteristics

MIN

NOM

MAX UNIT

t_c(OSC), Cycle time

Frequency

50

5

200

20

ns

MHz

ns

On-chip oscillator (X1/X2 pins)

(Crystal/Resonator)

t_c(CI), Cycle time (C8)

Frequency

33.3

5

200

30

External oscillator/clock source

(XCLKIN pin) — PLL Enabled

MHz

ns

t_c(CI), Cycle time (C8)

Frequency

33.33

4

250

30

External oscillator/clock source

(XCLKIN pin) — PLL Disabled

MHz

Limp mode SYSCLKOUT

(with /2 enabled)

Frequency range

1 to 5

MHz

t_c(XCO), Cycle time (C1)

66.67

0.5

2000

15

ns

MHz

ms

XCLKOUT

Frequency

t_p

PLL lock time⁽¹⁾

1

(1) The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are

used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum).

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Table 6-9. Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics

PARAMETER

MIN

TYP

10

MAX UNIT

MHz

Internal zero-pin oscillator 1 (INTOSC1)⁽¹⁾⁽²⁾

Internal zero-pin oscillator 2 (INTOSC2)⁽¹⁾⁽²⁾

Step size (coarse trim)

Frequency

10

MHz

55

kHz

Step size (fine trim)

14

kHz

Temperature drift⁽³⁾

Voltage (V_DD) drift⁽³⁾

3.03

175

4.85 kHz/°C

Hz/mV

(1) In order to achieve better oscillator accuracy (10 MHz ± 1% or better) than shown, refer to the oscillator calibration example in

2802x C/C++ Header Files and Peripheral Examples (literature number SPRC832). Refer to Figure 6-5 for MIN/MAX values.

(2) Frequency range ensured only when VREG is enabled, VREGENZ = V_SS

.

(3) Output frequency of the internal oscillators follows the direction of both the temperature gradient and voltage (V_DD) gradient. For

example:

•

Increase in temperature will cause the output frequency to increase per the temperature coefficient.

Decrease in voltage (V_DD) will cause the output frequency to decrease per the voltage coefficient.

Zero-Pin Oscillator Frequency Movement With Temperature

10.6

10.5

10.4

10.3

10.2

10.1

10

9.9

9.8

9.7

9.6

–40

–30

–20

–10

0

10

20

30

40

50

60

70

80

90

100

110

120

Typical

Max

Temperature (°C)

Figure 6-5. Zero-Pin Oscillator Frequency Movement With Temperature

Electrical Specifications

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6.8 Clock Requirements and Characteristics

Table 6-10. XCLKIN Timing Requirements - PLL Enabled

NO.

MIN

MAX UNIT

C9

t_f(CI)

Fall time, XCLKIN

6

ns

%

C10 t_r(CI)

Rise time, XCLKIN

C11 t_w(CIL)

C12 t_w(CIH)

Pulse duration, XCLKIN low as a percentage of t_c(OSCCLK)

Pulse duration, XCLKIN high as a percentage of t_c(OSCCLK)

45

55

Table 6-11. XCLKIN Timing Requirements - PLL Disabled

NO.

MIN

MAX UNIT

C9

t_f(CI)

Fall time, XCLKIN

Rise time, XCLKIN

Up to 20 MHz

6

2

ns

20 MHz to 30 MHz

Up to 20 MHz

C10 t_r(CI)

6

ns

20 MHz to 30 MHz

2

C11 t_w(CIL)

C12 t_w(CIH)

Pulse duration, XCLKIN low as a percentage of t_c(OSCCLK)

Pulse duration, XCLKIN high as a percentage of t_c(OSCCLK)

45

55

%

The possible configuration modes are shown in Table 3-19.

Table 6-12. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)^{(1) (2)}

NO.

C3

C4

C5

C6

PARAMETER

MIN

TYP

MAX

11

UNIT

ns

t_f(XCO)

Fall time, XCLKOUT

Rise time, XCLKOUT

t_r(XCO)

11

ns

t_w(XCOL)

t_w(XCOH)

Pulse duration, XCLKOUT low

Pulse duration, XCLKOUT high

H – 2

H + 2

ns

(1) A load of 40 pF is assumed for these parameters.

(2) H = 0.5t_c(XCO)

C10

C9

C8

(A)

XCLKIN

C6

C3

C1

C4

C5

(B)

XCLKOUT

A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is

intended to illustrate the timing parameters only and may differ based on actual configuration.

B. XCLKOUT configured to reflect SYSCLKOUT.

Figure 6-6. Clock Timing

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6.9 Power Sequencing

There is no power sequencing requirement needed to ensure the device is in the proper state after reset

or to prevent the I/Os from glitching during power up/down. However, it is recommended that no voltage

larger than a diode drop (0.7 V) should be applied to any pin prior to powering up the device. Voltages

applied to pins on an unpowered device can bias internal p-n junctions in unintended ways and produce

unpredictable results.

V_DDIO, V_DDA

(3.3 V)

V_DD(1.8 V)

INTOSC1

t_INTOSCST

X1/X2

t_OSCST

(B)

(A)

XCLKOUT

User-code dependent

t

w(RSL1)

XRS^(D)

Address/data valid, internal boot-ROM code execution phase

Address/Data/

Control

(Internal)

User-code execution phase

User-code dependent

t

d(EX)

(C)

h(boot-mode)

t

Boot-Mode

Pins

GPIO pins as input

Boot-ROM execution starts

Peripheral/GPIO function

Based on boot code

GPIO pins as input (state depends on internal PU/PD)

User-code dependent

I/O Pins

A. Upon power up, SYSCLKOUT is OSCCLK/4. Since the XCLKOUTDIV bits in the XCLK register come up with a reset

state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. XCLKOUT = OSCCLK/16 during this

phase.

B. Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. Note that

XCLKOUT will not be visible at the pin until explicitly configured by user code.

C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code

branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in

debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT

will be based on user environment and could be with or without PLL enabled.

D. Using the XRS pin is optional due to the on-chip power-on reset (POR) circuitry.

Figure 6-7. Power-on Reset

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Table 6-13. Reset (XRS) Timing Requirements

MIN

1000t_c(SCO)

32t_c(OSCCLK)

NOM

MAX UNIT

cycles

t_h(boot-mode)

t_w(RSL2)

Hold time for boot-mode pins

Pulse duration, XRS low on warm reset

cycles

Table 6-14. Reset (XRS) Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_w(RSL1)

Pulse duration, XRS driven by device

600

ms

Pulse duration, reset pulse generated by

watchdog

t_w(WDRS)

512t_c(OSCCLK)

cycles

t_d(EX)

Delay time, address/data valid after XRS high

Start up time, internal zero-pin oscillator

On-chip crystal-oscillator start-up time

32t_c(OSCCLK)

cycles

ms

t_INTOSCST

3

(1)

t_OSCST

1

10

ms

(1) Dependent on crystal/resonator and board design.

INTOSC1

X1/X2

XCLKOUT

User-Code Dependent

t

w(RSL2)

XRS

User-Code Execution Phase

t

d(EX)

Address/Data/

User-Code Execution

Control

(Internal)

(A)

t

Boot-ROM Execution Starts

GPIO Pins as Input

h(boot-mode)

Boot-Mode

Pins

Peripheral/GPIO Function

User-Code Dependent

Peripheral/GPIO Function

User-Code Execution Starts

I/O Pins

GPIO Pins as Input (State Depends on Internal PU/PD)

User-Code Dependent

A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code

branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in

debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The

SYSCLKOUT will be based on user environment and could be with or without PLL enabled.

Figure 6-8. Warm Reset

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Figure 6-9 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =

0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR

register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the

PLL lock-up is complete, SYSCLKOUT reflects the new operating frequency, OSCCLK x 4.

OSCCLK

Write to PLLCR

SYSCLKOUT

OSCCLK * 2

OSCCLK/2

OSCCLK * 4

(CPU frequency while PLL is stabilizing

with the desired frequency. This period

(PLL lock-up time t_p) is 1 ms long.)

(Current CPU

Frequency)

(Changed CPU frequency)

Figure 6-9. Example of Effect of Writing Into PLLCR Register

6.10 General-Purpose Input/Output (GPIO)

6.10.1 GPIO - Output Timing

Table 6-15. General-Purpose Output Switching Characteristics

PARAMETER

Rise time, GPIO switching low to high

Fall time, GPIO switching high to low

Toggling frequency

MIN

MAX

13⁽¹⁾

15

UNIT

ns

t_r(GPO)

t_f(GPO)

t_fGPO

All GPIOs

ns

MHz

(1) Rise time and fall time vary with electrical loading on I/O pins. Values given in Table 6-15 are applicable for a 40-pF load on I/O pins.

GPIO

t

r(GPO)

t

f(GPO)

Figure 6-10. General-Purpose Output Timing

Electrical Specifications

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6.10.2 GPIO - Input Timing

(A)

GPIO Signal

GPxQSELn = 1,0 (6 samples)

1

0

1

0

1

t_w(SP)

Sampling Period determined

by GPxCTRL[QUALPRD]^(B)

t_w(IQSW)

[(SYSCLKOUT cycle * 2 * QUALPRD) * 5^(C)

]

Sampling Window

SYSCLKOUT

QUALPRD = 1

(SYSCLKOUT/2)

(D)

Output From

Qualifier

A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It

can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value

"n", the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin

will be sampled).

B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.

C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is

used.

D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or

greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure

5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide

pulse ensures reliable recognition.

Figure 6-11. Sampling Mode

Table 6-16. General-Purpose Input Timing Requirements

MIN

1t_c(SCO)

MAX

UNIT

cycles

QUALPRD = 0

t_w(SP)

Sampling period

QUALPRD ≠ 0

2t_c(SCO)* QUALPRD

t_w(SP)* (n⁽¹⁾– 1)

2t_c(SCO)

t_w(IQSW)

Input qualifier sampling window

Pulse duration, GPIO low/high

Synchronous mode

With input qualifier

(2)

t_w(GPI)

t_w(IQSW)+ t_w(SP)+ 1t_c(SCO)

(1) "n" represents the number of qualification samples as defined by GPxQSELn register.

(2) For t_w(GPI), pulse width is measured from V_ILto V_ILfor an active low signal and V_IHto V_IHfor an active high signal.

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6.10.3 Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier

configurations.

Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.

Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0

Sampling frequency = SYSCLKOUT, if QUALPRD = 0

Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0

In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.

Sampling period = SYSCLKOUT cycle, if QUALPRD = 0

In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of

the signal. This is determined by the value written to GPxQSELn register.

Case 1:

Qualification using 3 samples

Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0

Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0

Case 2:

Qualification using 6 samples

Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0

Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0

XCLKOUT

GPIOxn

t

w(GPI)

Figure 6-12. General-Purpose Input Timing

Electrical Specifications

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6.10.4 Low-Power Mode Wakeup Timing

Table 6-17 shows the timing requirements, Table 6-18 shows the switching characteristics, and

Figure 6-13 shows the timing diagram for IDLE mode.

Table 6-17. IDLE Mode Timing Requirements⁽¹⁾

MIN NOM

2t_c(SCO)

5t_c(SCO)+ t_w(IQSW)

MAX

UNIT

Without input qualifier

With input qualifier

t_w(WAKE-INT)Pulse duration, external wake-up signal

cycles

(1) For an explanation of the input qualifier parameters, see Table 6-16.

Table 6-18. IDLE Mode Switching Characteristics⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

cycles

(2)

Delay time, external wake signal to program execution resume

Without input qualifier

20t_c(SCO)

20t_c(SCO)+ t_w(IQSW)

1050t_c(SCO)

•

Wake-up from Flash

–

Flash module in active state

Wake-up from Flash

Flash module in sleep state

Wake-up from SARAM

With input qualifier

Without input qualifier

With input qualifier

Without input qualifier

With input qualifier

t_d(WAKE-IDLE)

cycles

–

1050t_c(SCO)+ t_w(IQSW)

20t_c(SCO)

20t_c(SCO)+ t_w(IQSW)

(1) For an explanation of the input qualifier parameters, see Table 6-16.

(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered

by the wake-up) signal involves additional latency.

t

d(WAKE−IDLE)

Address/Data

(internal)

XCLKOUT

t

w(WAKE−INT)

WAKE INT^(A)(B)

A. WAKE INT can be any enabled interrupt, WDINT or XRS.

B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be

initiated until at least 4 OSCCLK cycles have elapsed.

Figure 6-13. IDLE Entry and Exit Timing

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Table 6-19. STANDBY Mode Timing Requirements

TEST CONDITIONS

Without input qualification

With input qualification⁽¹⁾

MIN

3t_c(OSCCLK)

NOM

MAX

UNIT

Pulse duration, external

wake-up signal

t_w(WAKE-INT)

cycles

(2 + QUALSTDBY) * t_c(OSCCLK)

(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.

Table 6-20. STANDBY Mode Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

45t_c(SCO)

UNIT

Delay time, IDLE instruction

executed to XCLKOUT low

t_d(IDLE-XCOL)

32t_c(SCO)

cycles

Delay time, external wake signal to program execution

resume⁽¹⁾

cycles

Without input qualifier

100t_c(SCO)

100t_c(SCO)+ t_w(WAKE-INT)

1125t_c(SCO)

•

Wake up from flash

–

Flash module in active

state

With input qualifier

Without input qualifier

With input qualifier

t_d(WAKE-STBY)

•

Wake up from flash

–

cycles

Flash module in sleep

state

1125t_c(SCO)+ t_w(WAKE-INT)

Without input qualifier

With input qualifier

100t_c(SCO)

•

Wake up from SARAM

100t_c(SCO)+ t_w(WAKE-INT)

(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered

by the wake up signal) involves additional latency.

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(C)

(F)

(A)

(B)

(D)(E)

(G)

Normal Execution

Device

Status

STANDBY

Flushing Pipeline

Wake-up

Signal^(H)

t

w(WAKE-INT)

t

d(WAKE-STBY)

X1/X2 or

XCLKIN

XCLKOUT

t

d(IDLE−XCOL)

A. IDLE instruction is executed to put the device into STANDBY mode.

B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below

before being turned off:

•

16 cycles, when DIVSEL = 00 or 01

32 cycles, when DIVSEL = 10

64 cycles, when DIVSEL = 11

This delay enables the CPU pipeline and any other pending operations to flush properly.

C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in

STANDBY mode.

D. The external wake-up signal is driven active.

E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.

Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the

device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.

F. After a latency period, the STANDBY mode is exited.

G. Normal execution resumes. The device will respond to the interrupt (if enabled).

H. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be

initiated until at least 4 OSCCLK cycles have elapsed.

Figure 6-14. STANDBY Entry and Exit Timing Diagram

Table 6-21. HALT Mode Timing Requirements

MIN NOM

t_oscst+ 2t_c(OSCCLK)

MAX

UNIT

cycles

t_w(WAKE-GPIO)

t_w(WAKE-XRS)

Pulse duration, GPIO wake-up signal

Pulse duration, XRS wakeup signal

t_oscst+ 8t_c(OSCCLK)

Table 6-22. HALT Mode Switching Characteristics

PARAMETER

MIN

TYP

MAX

45t_c(SCO)

1

UNIT

cycles

ms

t_d(IDLE-XCOL)

t_p

Delay time, IDLE instruction executed to XCLKOUT low

PLL lock-up time

32t_c(SCO)

Delay time, PLL lock to program execution resume

1125t_c(SCO)

35t_c(SCO)

cycles

•

Wake up from flash

Flash module in sleep state

t_d(WAKE-HALT)

–

Wake up from SARAM

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(C)

(F)

(A)

(H)

(B)

(G)

(D)(E)

Device

Status

HALT

Flushing Pipeline

PLL Lock-up Time

Normal

Execution

Wake-up Latency

GPIOn^(I)

t

)

d(WAKE−HALT

t

w(WAKE-GPIO)

t_p

X1/X2 or

XCLKIN

Oscillator Start-up Time

XCLKOUT

t

d(IDLE−XCOL)

A. IDLE instruction is executed to put the device into HALT mode.

B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before

oscillator is turned off and the CLKIN to the core is stopped:

•

16 cycles, when DIVSEL = 00 or 01

32 cycles, when DIVSEL = 10

64 cycles, when DIVSEL = 11

This delay enables the CPU pipeline and any other pending operations to flush properly.

C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as

the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes

absolute minimum power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the

watchdog alive in HALT mode. This is done by writing to the appropriate bits in the CLKCTL register.

D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator

wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This

enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin

asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to

entering and during HALT mode.

E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.

Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the

device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.

F. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 1 ms.

G. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT

mode is now exited.

H. Normal operation resumes.

I.

From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be

initiated until at least 4 OSCCLK cycles have elapsed.

Figure 6-15. HALT Wake-Up Using GPIOn

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6.11 Enhanced Control Peripherals

6.11.1 Enhanced Pulse Width Modulator (ePWM) Timing

PWM refers to PWM outputs on ePWM1–4 . Table 6-23 shows the PWM timing requirements and

Table 6-24, switching characteristics.

Table 6-23. ePWM Timing Requirements⁽¹⁾

TEST CONDITIONS

Asynchronous

MIN

2t_c(SCO)

MAX

UNIT

cycles

t_w(SYCIN)

Sync input pulse width

Synchronous

2t_c(SCO)

With input qualifier

1t_c(SCO)+ t_w(IQSW)

(1) For an explanation of the input qualifier parameters, see Table 6-16.

Table 6-24. ePWM Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

33.33

MAX

UNIT

ns

t_w(PWM)

Pulse duration, PWMx output high/low

Sync output pulse width

t_w(SYNCOUT)

t_d(PWM)tza

8t_c(SCO)

cycles

ns

Delay time, trip input active to PWM forced high

Delay time, trip input active to PWM forced low

no pin load

25

20

t_d(TZ-PWM)HZ

Delay time, trip input active to PWM Hi-Z

ns

6.11.2 Trip-Zone Input Timing

(A)

XCLKOUT

t

w(TZ)

TZ

t

d(TZ-PWM)HZ

(B)

PWM

A. TZ - TZ1, TZ2, TZ3

B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM

recovery software.

Figure 6-16. PWM Hi-Z Characteristics

Table 6-25. Trip-Zone Input Timing Requirements⁽¹⁾

MIN

1t_c(SCO)

MAX UNIT

cycles

t_w(TZ)

Pulse duration, TZx input low

Asynchronous

Synchronous

2t_c(SCO)

cycles

With input qualifier

1t_c(SCO)+ t_w(IQSW)

cycles

(1) For an explanation of the input qualifier parameters, see Table 6-16.

100

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Table 6-26 shows the high-resolution PWM switching characteristics.

Table 6-26. High-Resolution PWM Characteristics at SYSCLKOUT = 50 MHz⁽¹⁾–60 MHz

MIN

TYP

MAX UNIT

310 ps

Micro Edge Positioning (MEP) step size⁽²⁾

150

(1) The HRPWM operates at a minimum SYSCLKOUT frequency of 50 MHz. Below 50 MHz, with device process variation, the MEP step

size may decrease under cold temperature and high core voltage conditions to such a point that 255 MEP steps will not span an entire

SYSCLKOUT cycle.

(2) Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase

with low voltage and high temperature and decrease with voltage and cold temperature.

Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI

software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per

SYSCLKOUT period dynamically while the HRPWM is in operation.

6.11.3 Enhanced Capture (eCAP) Timing

Table 6-27 shows the eCAP timing requirement and Table 6-28 shows the eCAP switching characteristics.

Table 6-27. Enhanced Capture (eCAP) Timing Requirement⁽¹⁾

TEST CONDITIONS

Asynchronous

MIN

2t_c(SCO)

MAX UNIT

cycles

t_w(CAP)

Capture input pulse width

Synchronous

2t_c(SCO)

cycles

With input qualifier

1t_c(SCO)+ t_w(IQSW)

cycles

(1) For an explanation of the input qualifier parameters, see Table 6-16.

Table 6-28. eCAP Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

t_w(APWM)

Pulse duration, APWMx output high/low

20

ns

6.11.4 ADC Start-of-Conversion Timing

Table 6-29. External ADC Start-of-Conversion Switching Characteristics

PARAMETER

MIN

MAX

UNIT

t_w(ADCSOCL)

Pulse duration, ADCSOCxO low

32t_{c(HCO )}

cycles

t_w(ADCSOCL)

ADCSOCAO

or

ADCSOCBO

Figure 6-17. ADCSOCAO or ADCSOCBO Timing

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6.11.5 External Interrupt Timing

t

w(INT)

XINT1, XINT2, XINT3

t

d(INT)

Address bus

(internal)

Interrupt Vector

Figure 6-18. External Interrupt Timing

Table 6-30. External Interrupt Timing Requirements⁽¹⁾

TEST CONDITIONS

MIN

1t_c(SCO)

MAX

UNIT

cycles

(2)

t_w(INT)

Pulse duration, INT input low/high

Synchronous

With qualifier

1t_c(SCO)+ t_w(IQSW)

(1) For an explanation of the input qualifier parameters, see Table 6-16.

(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.

Table 6-31. External Interrupt Switching Characteristics⁽¹⁾

PARAMETER

MIN

MAX

UNIT

t_d(INT)

Delay time, INT low/high to interrupt-vector fetch

t_w(IQSW)+ 12t_c(SCO)

cycles

(1) For an explanation of the input qualifier parameters, see Table 6-16.

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6.11.6 I2C Electrical Specification and Timing

Table 6-32. I2C Timing

TEST CONDITIONS

MIN

MAX

UNIT

f_SCL

SCL clock frequency

I2C clock module frequency is between

7 MHz and 12 MHz and I2C prescaler and

clock divider registers are configured

appropriately

400

kHz

v_il

Low level input voltage

High level input voltage

Input hysteresis

0.3 V_DDIO

V

V_ih

0.7 V_DDIO

V_hys

V_ol

0.05 V_DDIO

V

Low level output voltage

Low period of SCL clock

3 mA sink current

0

0.4

V

t_LOW

I2C clock module frequency is between

7 MHz and 12 MHz and I2C prescaler and

clock divider registers are configured

appropriately

1.3

ms

t_HIGH

High period of SCL clock

I2C clock module frequency is between

7 MHz and 12 MHz and I2C prescaler and

clock divider registers are configured

appropriately

0.6

ms

l_I

Input current with an input voltage

–10

10

mA

between 0.1 V_DDIOand 0.9 V_DDIOMAX

6.11.7 Serial Peripheral Interface (SPI) Master Mode Timing

Table 6-33 lists the master mode timing (clock phase = 0) and Table 6-34 lists the timing (clock

phase = 1). Figure 6-19 and Figure 6-20 show the timing waveforms.

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

SPISIMO

Master Out Data Is Valid

8

9

Master In Data

Must Be Valid

SPISOMI

SPISTE^(A)

A. In the master mode, SPISTE goes active 0.5t_c(SPC)(minimum) before valid SPI clock edge. On the trailing

end of the word, the SPISTE will go inactive 0.5t_c(SPC)after the receiving edge (SPICLK) of the last data bit,

except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.

Figure 6-19. SPI Master Mode External Timing (Clock Phase = 0)

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

6

7

Master out data Is valid

10

SPISIMO

SPISOMI

Data Valid

11

Master in data

must be valid

(A)

SPISTE

B. In the master mode, SPISTE goes active 0.5t_c(SPC)(minimum) before valid SPI clock edge. On the trailing

end of the word, the SPISTE will go inactive 0.5t_c(SPC)after the receiving edge (SPICLK) of the last data bit,

except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.

Figure 6-20. SPI Master Mode External Timing (Clock Phase = 1)

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6.11.8 SPI Slave Mode Timing

Table 6-35 lists the slave mode external timing (clock phase = 0) and Table 6-36 (clock phase = 1).

Figure 6-21 and Figure 6-22 show the timing waveforms.

Table 6-35. SPI Slave Mode External Timing (Clock Phase = 0)^{(1)(2)(3)(4)(5)}

NO.

MIN

MAX UNIT

12 t_c(SPC)S

13 t_w(SPCH)S

t_w(SPCL)S

Cycle time, SPICLK

4t_c(LCO)

ns

Pulse duration, SPICLK high (clock polarity = 0)

0.5t_c(SPC)S– 10 0.5t_c(SPC)S

ns

Pulse duration, SPICLK low (clock polarity = 1)

0.5t_c(SPC)S– 10 0.5t_c(SPC)S

14 t_w(SPCL)S

t_w(SPCH)S

Pulse duration, SPICLK low (clock polarity = 0)

0.5t_c(SPC)S– 10 0.5t_c(SPC)S

Pulse duration, SPICLK high (clock polarity = 1)

0.5t_c(SPC)S– 10 0.5t_c(SPC)S

15 t_{d(SPCH-SOMI)S}

t_{d(SPCL-SOMI)S}

16 t_{v(SPCL-SOMI)S}

t_{v(SPCH-SOMI)S}

19 t_{su(SIMO-SPCL)S}

t_{su(SIMO-SPCH)S}

20 t_{v(SPCL-SIMO)S}

t_{v(SPCH-SIMO)S}

Delay time, SPICLK high to SPISOMI valid (clock polarity = 0)

Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)

Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0)

Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1)

Setup time, SPISIMO before SPICLK low (clock polarity = 0)

Setup time, SPISIMO before SPICLK high (clock polarity = 1)

Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0)

Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1)

35

0.75t_c(SPC)S

35

0.5t_c(SPC)S– 10

(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.

(2) t_c(SPC)= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:

Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX

Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.

(4) t_c(LCO)= LSPCLK cycle time

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

12

SPICLK

(clock polarity = 0)

13

14

SPICLK

(clock polarity = 1)

15

16

SPISOMI data Is valid

19

SPISOMI

SPISIMO

20

SPISIMO data

must be valid

(A)

SPISTE

C. In the slave mode, the SPISTE signal should be asserted low at least 0.5t_c(SPC)(minimum) before the valid SPI clock

edge and remain low for at least 0.5t_c(SPC)after the receiving edge (SPICLK) of the last data bit.

Figure 6-21. SPI Slave Mode External Timing (Clock Phase = 0)

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Table 6-36. SPI Slave Mode External Timing (Clock Phase = 1)^(1)(2)(3)(4)

NO.

MIN

8t_c(LCO)

MAX UNIT

12 t_c(SPC)S

13 t_w(SPCH)S

t_w(SPCL)S

Cycle time, SPICLK

ns

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

Setup time, SPISOMI before SPICLK high (clock polarity = 0)

Setup time, SPISOMI before SPICLK low (clock polarity = 1)

0.5t_c(SPC)S– 10

0.125t_c(SPC)S

0.5t_c(SPC)S

ns

0.5t_{c(SPC) S}

0.5t_c(SPC)S

14 t_w(SPCL)S

t_w(SPCH)S

17 t_{su(SOMI-SPCH)S}

t_{su(SOMI-SPCL)S}

18 t_{v(SPCL-SOMI)S}

0.125t_c(SPC)S

Valid time, SPISOMI data valid after SPICLK low

(clock polarity = 1)

0.75t_c(SPC)S

t_{v(SPCH-SOMI)S}

Valid time, SPISOMI data valid after SPICLK high

(clock polarity = 0)

0.75t_{c(SPC) S}

21 t_{su(SIMO-SPCH)S}

t_{su(SIMO-SPCL)S}

Setup time, SPISIMO before SPICLK high (clock polarity = 0)

Setup time, SPISIMO before SPICLK low (clock polarity = 1)

35

ns

22 t_{v(SPCH-SIMO)S}

Valid time, SPISIMO data valid after SPICLK high

(clock polarity = 0)

0.5t_c(SPC)S– 10

t_{v(SPCL-SIMO)S}

Valid time, SPISIMO data valid after SPICLK low

(clock polarity = 1)

0.5t_c(SPC)S– 10

(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.

(2) t_c(SPC)= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:

Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX

Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

12

SPICLK

(clock polarity = 0)

13

14

SPICLK

(clock polarity = 1)

17

18

SPISOMI data is valid

SPISOMI

SPISIMO

Data Valid

21

22

SPISIMO data

must be valid

(A)

SPISTE

A. In the slave mode, the SPISTE signal should be asserted low at least 0.5t_c(SPC)before the valid SPI clock edge and

remain low for at least 0.5t_c(SPC)after the receiving edge (SPICLK) of the last data bit.

Figure 6-22. SPI Slave Mode External Timing (Clock Phase = 1)

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6.11.9 On-Chip Comparator/DAC

Table 6-37. Electrical Characteristics of the Comparator/DAC

CHARACTERISTIC

MIN

TYP

MAX

UNITS

Comparator

Comparator Input Range

V_SSA– V_DDA

V

Comparator response time to PWM Trip Zone (Async)

30

±5

35

ns

Input Offset

Input Hysteresis⁽¹⁾

mV

DAC

DAC Output Range

DAC resolution

V_SSA– V_DDA

10

V

bits

DAC settling time

See

Figure 6-23

DAC Gain

DAC Offset

Monotonic

INL

–1.5

10

%

mV

Yes

±3

LSB

(1) Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration. This results in an effective 100-kΩ feedback

resistance between the output of the comparator and the non-inverting input of the comparator. There is an option to disable the

hysteresis and, with it, the feedback resistance; see the TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and

Comparator Reference Guide (literature number SPRUGE5) for more information on this option if needed in your system.

1100

1000

900

800

700

600

500

400

300

200

100

0

50

100

150

200

250

300

350

400

450

500

DAC Step Size (Codes)

DAC Accuracy

15 Codes

7 Codes

3 Codes

1 Code

Figure 6-23. DAC Settling Time

110

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6.11.10 On-Chip Analog-to-Digital Converter

Table 6-38. ADC Electrical Characteristics

PARAMETER

MIN

TYP

MAX

UNIT

DC SPECIFICATIONS

Resolution

12

0.001

7

Bits

ADC clock

60-MHz device

28027/26/23/22

28021/20/200

60

64

MHz

Sample Window

ADC

Clocks

14

ACCURACY

INL (Integral nonlinearity)⁽¹⁾

60-MHz clock

(4.62 MSPS)

±2

LSB

DNL (Differential nonlinearity)

±1

0

LSB

(2)

Offset error

Executing Device_Cal

function

–20

–4

20

4

Executing periodic

self-recalibration⁽³⁾

0

Overall gain error with internal reference

Overall gain error with external reference

Channel-to-channel offset variation

Channel-to-channel gain variation

ADC temperature coefficient with internal reference

ADC temperature coefficient with external reference

ANALOG INPUT

–60

–40

–4

60

40

4

LSB

–4

4

LSB

–50

–20

ppm/°C

Analog input voltage with internal reference

Analog input voltage with external reference

V_REFLOinput voltage⁽⁴⁾

0

V_REFLO

V_SSA

3.3

V_REFHI

V_SSA

V

V_REFHIinput voltage⁽⁵⁾

with V_REFLO= V_SSA

1.98

V_DDA

V

Input capacitance

5

pF

mA

Input leakage current

±5

(1) INL will degrade when the ADC input voltage goes above V_DDA

.

(2) 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and V_REFHI- V_REFLOfor external

reference.

(3) Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error. This can be performed

as needed in the application without sacrificing an ADC channel by using the procedure listed in the "ADC Zero Offset Calibration"

section of the TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator Reference Guide (literature number

SPRUGE5).

(4) V_REFLOis always connected to V_SSA

(5) V_REFHImust not exceed V_DDAwhen using either internal or external reference modes. Since V_REFHIis tied to ADCINA0, the input signal

on ADCINA0 must not exceed V_DDA

.

Electrical Specifications

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Table 6-39. ADC Power Modes

ADC OPERATING MODE

Mode A – Operating Mode

CONDITIONS

I_DDA

UNITS

ADC Clock Enabled

13

mA

Bandgap On (ADCBGPWD = 1)

Reference On (ADCREFPWD = 1)

ADC Powered Up (ADCPWRDN = 1)

Mode B – Quick Wake Mode

Mode C – Comparator-Only Mode

Mode D – Off Mode

ADC Clock Enabled

4

mA

Bandgap On (ADCBGPWD = 1)

Reference On (ADCREFPWD = 1)

ADC Powered Up (ADCPWRDN = 0)

ADC Clock Enabled

1.5

Bandgap On (ADCBGPWD = 1)

Reference On (ADCREFPWD = 0)

ADC Powered Up (ADCPWRDN = 0)

ADC Clock Enabled

0.075

Bandgap On (ADCBGPWD = 0)

Reference On (ADCREFPWD = 0)

ADC Powered Up (ADCPWRDN = 0)

6.11.10.1 Internal Temperature Sensor

Table 6-40. Temperature Sensor Coefficient

PARAMETER⁽¹⁾

MIN

TYP

MAX

UNIT

T_SLOPE

Degrees C of temperature movement per measured ADC LSB change

of the temperature sensor

0.18⁽²⁾⁽³⁾

°C/LSB

T_OFFSET

ADC output at 0°C of the temperature sensor

1750

LSB

(1) The temperature sensor slope and offset are given in terms of ADC LSBs using the internal reference of the ADC. Values must be

adjusted accordingly in external reference mode to the external reference voltage.

(2) ADC temperature coeffieicient is accounted for in this specification

(3) Output of the temperature sensor (in terms of LSBs) is sign-consistent with the direction of the temperature movement. Increasing

temperatures will give increasing ADC values relative to an initial value; decreasing temperatures will give decreasing ADC values

relative to an initial value.

6.11.10.2 ADC Power-Up Control Bit Timing

Table 6-41. ADC Power-Up Delays

PARAMETER⁽¹⁾

MIN

TYP

MAX

UNIT

t_d(PWD)

Delay time for the ADC to be stable after power up

1

ms

(1) Timings maintain compatibility to the ADC module. The 2802x ADC supports driving all 3 bits at the same time t_d(PWD)ms before first

conversion.

ADCPWDN/

ADCBGPWD/

ADCREFPWD/

ADCENABLE

t_d(PWD)

Request for ADC

Conversion

Figure 6-24. ADC Conversion Timing

112

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R_on

3.4 kW

Switch

R_s

ADCIN

C_p

C_h

Source

Signal

ac

5 pF

1.6 pF

28x DSP

Typical Values of the Input Circuit Components:

Switch Resistance (R_on): 3.4 kW

Sampling Capacitor (C_h): 1.6 pF

Parasitic Capacitance (C_p): 5 pF

Source Resistance (R_s): 50 W

Figure 6-25. ADC Input Impedance Model

Electrical Specifications

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6.11.10.3 ADC Sequential and Simultaneous Timings

Analog Input

SOC0 Sample

Window

SOC1 Sample

Window

SOC2 Sample

Window

0

2

9

15

22 24

37

ADCCLK

ADCCTL 1.INTPULSEPOS

ADCSOCFLG 1.SOC0

ADCSOCFLG 1.SOC1

ADCSOCFLG 1.SOC2

S/H Window Pulse to Core

ADCRESULT 0

SOC0

SOC1

SOC2

Result 0 Latched

2 ADCCLKs

ADCRESULT 1

EOC0 Pulse

EOC1 Pulse

ADCINTFLG.ADCINTx

Minimum

7 ADCCLKs

Conversion 0

13 ADC Clocks

1 ADCCLK

6

Minimum

ADCCLKs 7 ADCCLKs

Conversion 1

13 ADC Clocks

Figure 6-26. Timing Example for Sequential Mode / Late Interrupt Pulse

114

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

Analog Input

SOC0 Sample

Window

SOC1 Sample

Window

SOC2 Sample

Window

0

2

9

15

22 24

37

ADCCLK

ADCCTL1.INTPULSEPOS

ADCSOCFLG 1.SOC0

ADCSOCFLG 1.SOC1

ADCSOCFLG 1.SOC2

S/H Window Pulse to Core

ADCRESULT 0

SOC0

SOC1

SOC2

Result 0 Latched

ADCRESULT 1

EOC0 Pulse

EOC1 Pulse

EOC2 Pulse

ADCINTFLG.ADCINTx

Minimum

7 ADCCLKs

Conversion 0

13 ADC Clocks

2 ADCCLKs

6

Minimum

ADCCLKs 7 ADCCLKs

Conversion 1

13 ADC Clocks

Figure 6-27. Timing Example for Sequential Mode / Early Interrupt Pulse

Electrical Specifications

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Analog Input A

SOC0 Sample

A Window

SOC2 Sample

A Window

Analog Input B

SOC0 Sample

B Window

SOC2 Sample

B Window

0

2

9

22 24

37

50

ADCCLK

ADCCTL1.INTPULSEPOS

ADCSOCFLG 1.SOC0

ADCSOCFLG 1.SOC1

ADCSOCFLG 1.SOC2

S/H Window Pulse to Core

ADCRESULT 0

SOC0 (A/B)

SOC2 (A/B)

2 ADCCLKs

Result 0 (A) Latched

ADCRESULT 1

Result 0 (B) Latched

ADCRESULT 2

EOC0 Pulse

EOC1 Pulse

1 ADCCLK

EOC2 Pulse

ADCINTFLG .ADCINTx

Minimum

7 ADCCLKs

Conversion 0 (A)

13 ADC Clocks

Conversion 0 (B)

13 ADC Clocks

2 ADCCLKs

19

ADCCLKs

Minimum

7 ADCCLKs

Conversion 1 (A)

13 ADC Clocks

Figure 6-28. Timing Example for Simultaneous Mode / Late Interrupt Pulse

116

Electrical Specifications

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

Analog Input A

Analog Input B

SOC0 Sample

A Window

SOC2 Sample

A Window

SOC0 Sample

B Window

SOC2 Sample

B Window

0

2

9

22 24

37

50

ADCCLK

ADCCTL1.INTPULSEPOS

ADCSOCFLG 1.SOC0

ADCSOCFLG 1.SOC1

ADCSOCFLG 1.SOC2

S/H Window Pulse to Core

ADCRESULT 0

SOC0 (A/B)

SOC2 (A/B)

2 ADCCLKs

Result 0 (A) Latched

ADCRESULT 1

Result 0 (B) Latched

ADCRESULT 2

EOC0 Pulse

EOC1 Pulse

EOC2 Pulse

ADCINTFLG .ADCINTx

Minimum

7 ADCCLKs

Conversion 0 (A)

13 ADC Clocks

Conversion 0 (B)

13 ADC Clocks

2 ADCCLKs

19

ADCCLKs

Minimum

7 ADCCLKs

Conversion 1 (A)

13 ADC Clocks

Figure 6-29. Timing Example for Simultaneous Mode / Early Interrupt Pulse

Electrical Specifications

117

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6.12 Detailed Descriptions

Integral Nonlinearity

Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full

scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is

defined as level one-half LSB beyond the last code transition. The deviation is measured from the center

of each particular code to the true straight line between these two points.

Differential Nonlinearity

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal

value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes.

Zero Offset

The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the

deviation of the actual transition from that point.

Gain Error

The first code transition should occur at an analog value one-half LSB above negative full scale. The last

transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is

the deviation of the actual difference between first and last code transitions and the ideal difference

between first and last code transitions.

Signal-to-Noise Ratio + Distortion (SINAD)

SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral

components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is

expressed in decibels.

Effective Number of Bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,

(SINAD -1.76)

N =

6.02

it is possible to get a measure of performance expressed as N, the effective number of

bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be

calculated directly from its measured SINAD.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured

input signal and is expressed as a percentage or in decibels.

Spurious Free Dynamic Range (SFDR)

SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.

118

Electrical Specifications

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

6.13 Flash Timing

Table 6-42. Flash/OTP Endurance for T Temperature Material⁽¹⁾

ERASE/PROGRAM

TEMPERATURE

MIN

TYP

MAX

UNIT

N_f

Flash endurance for the array (write/erase cycles)

OTP endurance for the array (write cycles)

0°C to 105°C (ambient)

0°C to 30°C (ambient)

20000

50000

cycles

write

N_OTP

1

(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.

Table 6-43. Flash/OTP Endurance for S Temperature Material⁽¹⁾

ERASE/PROGRAM

MIN

TYP

MAX

UNIT

TEMPERATURE

0°C to 125°C (ambient)

0°C to 30°C (ambient)

N_f

Flash endurance for the array (write/erase cycles)

OTP endurance for the array (write cycles)

20000

50000

cycles

write

N_OTP

1

(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.

Table 6-44. Flash/OTP Endurance for Q Temperature Material⁽¹⁾

ERASE/PROGRAM

TEMPERATURE

MIN

TYP

MAX

UNIT

N_f

Flash endurance for the array (write/erase cycles)

OTP endurance for the array (write cycles)

–40°C to 125°C (ambient)

–40°C to 30°C (ambient)

20000

50000

cycles

write

N_OTP

1

(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.

Table 6-45. Flash Parameters at 60-MHz SYSCLKOUT

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX

UNIT

(1)

I_DDP

I_DDIOP

V_DDcurrent consumption during Erase/Program cycle

V_DDIOcurrent consumption during Erase/Program cycle

VREG

disabled

80

60

mA

(1)

V_DDIOcurrent consumption during Erase/Program cycle VREG enabled

120

mA

(1) Typical parameters as seen at room temperature including function call overhead, with all peripherals off.

Table 6-46. Flash Parameters at 50-MHz SYSCLKOUT

TEST

CONDITIONS

PARAMETER

MIN

TYP

UNIT

(1)

I_DDP

I_DDIOP

V_DDcurrent consumption during Erase/Program cycle

V_DDIOcurrent consumption during Erase/Program cycle

VREG

disabled

70

60

mA

(1)

I_DDIOP

V_DDIOcurrent consumption during Erase/Program cycle VREG enabled

110

mA

(1) Typical parameters as seen at room temperature including function call overhead, with all peripherals off.

Table 6-47. Flash Parameters at 40-MHz SYSCLKOUT

TEST

CONDITIONS

PARAMETER

MIN

TYP

UNIT

(1)

I_DDP

I_DDIOP

V_DDcurrent consumption during Erase/Program cycle

V_DDIOcurrent consumption during Erase/Program cycle

VREG

disabled

60

mA

(1)

I_DDIOP

V_DDIOcurrent consumption during Erase/Program cycle VREG enabled

100

mA

(1) Typical parameters as seen at room temperature including function call overhead, with all peripherals off.

Electrical Specifications

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UNIT

Table 6-48. Flash Program/Erase Time

TEST

PARAMETER

CONDITIONS

MIN

TYP

MAX

Program Time 16-Bit Word

8K Sector

50

250

125

2

ms

s

4K Sector

Erase Time

8K Sector

4K Sector

2

s

Table 6-49. Flash/OTP Access Timing

PARAMETER

MIN

MAX UNIT

t_a(fp)

Paged Flash access time

Random Flash access time

OTP access time

40

60

ns

t_a(fr)

t_a(OTP)

Table 6-50. Minimum Required Flash/OTP Wait-States at Different Frequencies

SYSCLKOUT

(ns)

PAGE

RANDOM

OTP

WAIT-STATE

(MHz)

WAIT-STATE⁽¹⁾

60

16.67

18.18

20

2

1

2

1

3

2

1

55

50

45

22.22

25

40

35

28.57

33.33

30

(1) Page and random wait-state must be ≥ 1.

The equations to compute the Flash page wait-state and random wait-state in Table 6-50 are as follows:

é

ê

ù

æ

ç

è

ö

÷

t_{a(f ×p)}

Flash Page Wait State =

-1 round up to the next highest integer, or 1, whichever is larger

ú

÷

^c(SCO)ø

t

ê

ë

ú

û

é

ù

æ

ö

÷

t_{a(f ×r)}

ç

Flash Random Wait State =

-1 round up to the next highest integer, or 1, whichever is larger

ú

ê

ç

ê

÷

^c(SCO)ø

t

ú

è

ë

û

The equation to compute the OTP wait-state in Table 6-50 is as follows:

é

ê

ù

æ

ç

è

ö

÷

t_a(OTP)

OTP Wait State =

-1 round up to the next highest integer, or 1, whichever is larger

ú

÷

^c(SCO)ø

t

ê

ë

ú

û

120

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

7 Revision History

This data sheet revision history highlights the technical changes made to the SPRS523E device-specific

data sheet to make it an SPRS523F revision.

Scope: See table below.

LOCATION

Section 2

Table 2-1

ADDITIONS, DELETIONS, AND MODIFICATIONS

Changed section title from "Hardware Features" to "Introduction"

Hardware Features:

12-Bit ADC:

Added row for "Dual Sample-and-Hold"

Signal Descriptions:

Added NOTE about using the on-chip VREG

Register Map:

Changed "The devices contain four peripheral register spaces" to "The devices contain three peripheral

register spaces"

Typical Specifications for External Quartz Crystal:

•

–

Section 2.2

Section 3.4

•

Table 3-16

•

Changed C_L1for 15 MHz from 12 pF to 15 pF

Removed "C_L(pF)" column

Added footnote about C_shunt

Section 4.1.1

ADC:

Section 4.1.1.1, Features:

•

–

Updated Internal Reference list item and equations

Updated External Reference list item and equations

Section 4.1.1

Section 5

ADC:

"ADC Connections if the ADC is Not Used" section:

Changed "ADCINAn, ADCINBn – Connect to V_SSA" to "ADCINAn, ADCINBn, V_REFHI– Connect to V_SSA

Device Support:

•

–

"

•

Added "XDS560 emulator" under Hardware Development Tools

Section 5.3

Section 6.3

Added "Community Resources" section

Electrical Characteristics:

•

Removed "V_DDBOR trip point" parameter

Removed "V_DDover-voltage trip point" parameter

VREG V_DDoutput:

–

Removed MIN value of 1.865 V

Removed MAX value of 1.955 V

•

Updated footnote

Table 6-9

Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics:

•

Internal zero-pin oscillator 1 (INTOSC1):

–

Removed "t_c(ZPOSC1), Cycle time" row

Removed MIN Frequency of 9.7 MHz

Removed MAX Frequency of 10.3 MHz

•

Internal zero-pin oscillator 2 (INTOSC2):

–

Removed "t_c(ZPOSC2), Cycle time" row

Removed MIN Frequency of 9.7 MHz

Removed MAX Frequency of 10.3 MHz

•

Temperature drift:

–

Changed TYP value from 3 kHz/°C to 3.03 kHz/°C

Added MAX value of 4.85 kHz/°C

Updated "In order to achieve better oscillator accuracy ..." footnote

Figure 6-5

Added "Zero-Pin Oscillator Frequency Movement With Temperature" graph

SPI Master Mode External Timing (Clock Phase = 0):

Figure 6-19

•

Replaced drawing

Revision History

121

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

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LOCATION

ADDITIONS, DELETIONS, AND MODIFICATIONS

Electrical Characteristics of the Comparator/DAC:

Table 6-37

•

Input Hysteresis: Added reference to new footnote

DAC settling time: Replaced TYP value of 2 µs with reference to Figure 6-23

Added footnote

Figure 6-23

Table 6-48

Added "DAC Settling Time" figure

Flash Program/Erase Time:

•

Erase time (8K Sector): Changed TYP value from 10 s to 2 s

Erase time (4K Sector): Changed TYP value from 10 s to 2 s

122

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SPRS523F–NOVEMBER 2008–REVISED DECEMBER 2010

8 Thermal/Mechanical Data

Table 8-1 and Table 8-2 show the thermal data. See Section 6.5 for more information on thermal design

considerations.

The mechanical package diagrams that follow the tables reflect the most current released mechanical data

available for the designated devices.

Table 8-1. Thermal Model 38-Pin DA Results

AIR FLOW

PARAMETER

0 lfm

70.1

0.34

32.5

12.8

33

150 lfm

56.4

250 lfm

53.9

500 lfm

50.2

q_JA[°C/W] High k PCB

Ψ_JT[°C/W]

Ψ_JB

0.61

0.74

0.98

32.1

31.7

31.1

q_JC

q_JB

Table 8-2. Thermal Model 48-Pin PT Results

AIR FLOW

PARAMETER

0 lfm

64

150 lfm

50.4

250 lfm

48.2

500 lfm

45

q_JA[°C/W] High k PCB

Ψ_JT[°C/W]

Ψ_JB

0.56

30.1

13.6

30.6

0.94

1.1

1.38

28

28.7

28.4

q_JC

q_JB

Thermal/Mechanical Data

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MECHANICAL DATA

MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996

PT (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

M

0,08

0,50

36

25

37

24

48

13

0,13 NOM

1

12

5,50 TYP

7,20

SQ

6,80

Gage Plane

9,20

SQ

8,80

0,25

0,05 MIN

0°–7°

1,45

1,35

0,75

0,45

Seating Plane

0,10

1,60 MAX

4040052/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. This may also be a thermally enhanced plastic package with leads conected to the die pads.

1

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型号：	TMS320F28022PTQ
厂家：	TEXAS INSTRUMENTS
描述：	Piccolo Microcontrollers Piccolo微处理器微处理器微控制器
文件：	总130页 (文件大小：1343K)
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