TMS320UC5405ZQW [TI]
Fixed-Point Digital Signal Processor; 定点数字信号处理器
| 型号： | TMS320UC5405ZQW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Fixed-Point Digital Signal Processor |
| 文件： | 总77页 (文件大小：1030K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320UC5405 Fixed-Point
Digital Signal Processor
Data Manual
Literature Number: SPRS199B
October 2002 − Revised October 2004
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
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Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
Revision History
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS199A device-specific data
sheet to make it an SPRS199B revision.
Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of the
specified release date with the following changes.
PAGE(S)
ADDITIONS/CHANGES/DELETIONS
NO.
Global:
Added “ZQW” mechanical data package device-specific information.
Moved “Package Thermal Resistance Characteristics” section (was page 42 in SPRS199A) to the Mechanical Data section
18
Signal Descriptions table, TEST PINS:
Added “EMU0 should be pulled up to DV with a separate 4.7-kΩ resistor” to the EMU0 pin DESCRIPTION column
DD
Added “EMU1/OFF should be pulled up to DV with a separate 4.7-kΩ resistor” to the EMU1/OFF pin DESCRIPTION
DD
column
39
74
Device Support section:
Added new section
Added associated figure
Mechanical Data section:
Deleted the “GQW (S−PBGA−N143)” mechanical data package diagram; now an automated merge process
Added lead-in sentences for the thermal resistance characteristics table(s) and the “merged” mechanical data packages
Added “for GQW” to the Thermal Resistance Characteristics table
Added Thermal Resistance Characteristics table for the “ZQW” package
3
October 2002 − Revised October 2004
SPRS199B
Revision History
This page intentionally left blank
4
SPRS199B
October 2002 − Revised October 2004
Contents
Contents
Section
Page
1
2
TMS320UC5405 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
12
13
15
2.1
2.2
2.3
2.4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Assignments for the GQW and ZQW Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
19
19
20
21
21
22
23
23
26
28
28
30
33
33
34
35
35
37
38
3.1
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
On-Chip Dual-Access RAM (DARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip ROM With Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Implications of 6-Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Relocatable Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
Software-Programmable Wait-State Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
3.4
Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1
3.3.2
3.3.3
3.3.4
CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Control Registers and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 IFR and IMR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
39
5
6
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
42
42
43
44
45
45
46
47
6.1
6.2
6.3
6.4
6.5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Over Recommended Operating Case Temperature Range . . . . . . .
Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.1
6.5.2
6.5.3
Internal Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Divide-By-Two Clock Option (PLL disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option (PLL Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
October 2002 − Revised October 2004
SPRS199B
Contents
Section
Page
6.6
Memory and Parallel I/O Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
48
50
52
53
54
57
58
60
61
62
62
65
66
70
6.6.1
6.6.2
6.6.3
6.6.4
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7
6.8
6.9
6.10
6.11
6.12
Ready Timing for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset, BIO, Interrupt, and MP/MC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Acknowledge (IACK) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Flag (XF) and TOUT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.1
6.12.2
6.12.3
McBSP Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP as SPI Master or Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13
Host-Port Interface Timing (HPI8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
6
SPRS199B
October 2002 − Revised October 2004
Figures
List of Figures
Figure
Page
2−1
143-Terminal GQW and ZQW Ball Grid Array (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
3−9
Block Diagram of the TMS320UC5405 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320UC5405 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320UC5405 External Memory Paging Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Mode Status (PMST) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] . . .
Software Wait-State Control Register (SWCR) [MMR Address 002Bh] . . . . . . . . . . . . . . . . . . . . . . .
Bank-Switching Control Register (BSCR) [MMR Address 0029h] . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI8 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
21
22
22
23
24
25
26
30
38
3−10 IFR and IMR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1
TMS320UC5405 DSP Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
6−1
6−2
6−3
6−4
6−5
6−6
6−7
6−8
6−9
1.8-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Divide-by-Two Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Multiply-by-One Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Port Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Port Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
45
46
47
49
51
52
53
54
55
55
56
57
58
59
59
60
61
61
64
64
65
66
67
6−10 Memory Write With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−11 I/O Read With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−12 I/O Write With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−13 HOLD and HOLDA Timings (HM = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−14 Reset and BIO Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−15 Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−16 MP/MC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−17 IACK Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−18 XF Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−19 TOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−20 McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−21 McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−22 McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−23 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . .
6−24 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . .
7
October 2002 − Revised October 2004
SPRS199B
Figures
Figure
Page
6−25 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . .
6−26 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . .
6−27 Using HDS to Control Accesses (HCS Always Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−28 Using HCS to Control Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−29 HINT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−30 GPIOx Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
69
72
73
73
73
8
SPRS199B
October 2002 − Revised October 2004
Tables
Page
List of Tables
Table
2−1
2−2
Terminal Assignments (143-Terminal GQW and ZQW Packages) . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
15
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
Standard On-Chip ROM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Wait-State Register (SWWSR) Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Wait-State Control Register (SWCR) Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank-Switching Control Register (BSCR) Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mode Settings at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Channel Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Control Registers and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IFR and IMR Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
24
24
25
29
32
32
32
33
34
35
36
37
38
3−9
3−10
3−11
3−12
3−13
3−14
6−1
6−2
6−3
6−4
6−5
6−6
6−7
6−8
Divide-By-2 and Divide-by-4 Clock Options Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .
Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ready Timing Requirements for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset, BIO, Interrupt, and MP/MC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Acknowledge (IACK) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Flag (XF) and TOUT Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Transmit and Receive Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Transmit and Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . .
46
46
47
47
48
48
50
52
52
53
54
57
57
58
60
61
62
63
65
65
66
66
67
67
68
68
69
69
6−9
6−10
6−11
6−12
6−13
6−14
6−15
6−16
6−17
6−18
6−19
6−20
6−21
6−22
6−23
6−24
6−25
6−26
6−27
6−28
9
October 2002 − Revised October 2004
SPRS199B
Tables
Table
Page
6−29
6−30
HPI8 Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI8 Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
71
7−1
7−2
Thermal Resistance Characteristics for GQW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance Characteristics for ZQW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
74
10
SPRS199B
October 2002 − Revised October 2004
Features
1
TMS320UC5405 Features
D
D
D
Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
D
Arithmetic Instructions With Parallel Store
and Parallel Load
D
D
D
Conditional Store Instructions
Fast Return From Interrupt
40-Bit Arithmetic Logic Unit (ALU),
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
On-Chip Peripherals
− Software-Programmable Wait-State
Generator and Programmable Bank
Switching
− On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
− Two Multichannel Buffered Serial Ports
(McBSPs)
− Enhanced 8-Bit Parallel Host-Port
Interface (HPI8)
17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
D
D
D
D
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
− Two 16-Bit Timers
− Six-Channel Direct Memory Access
(DMA) Controller
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
D
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
Simplified External Memory Interface
(6-Bit Address Available, A0−A5)
D
D
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
D
D
D
Data Bus With a Bus-Holder Feature
4K x 16-Bit On-Chip ROM
†
IEEE Std 1149.1 (JTAG) Boundary Scan
16K x 16-Bit On-Chip Dual-Access RAM
(DARAM)
Logic
D
12.5-ns Single-Cycle Fixed-Point
Instruction Execution Time (80 MIPS)
D
D
D
D
Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
D
D
1.8-V Core Power Supply
Block-Memory-Move Instructions for
Efficient Program and Data Management
1.8-V to 3.6-V I/O Power Supply Enables
Operation With a Single 1.8-V Supply or
With Dual Supplies
Instructions With a 32-Bit-Long Word
Operand
D
Available in a 143-Ball MicroStar Junior
Ball Grid Array (BGA) (GQW/ZQW Suffixes)
Instructions With Two- or Three-Operand
Reads
MicroStar Junior is a trademark of Texas Instruments.
Other trademarks are the property of their respective owners.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
11
October 2002 − Revised October 2004
SPRS199B
Introduction
2
Introduction
This section describes the main features of the TMS320UC5405, lists the pin assignments, and describes the
function of each pin. This data manual also provides a detailed description section, electrical specifications,
parameter measurement information, and mechanical data about the available packaging.
NOTE: This data manual is designed to be used in conjunction with theTMS320C54x DSP Functional
Overview (literature number SPRU307).
2.1 Description
The TMS320UC5405 fixed-point, digital signal processor (DSP) (hereafter referred to as the UC5405 unless
otherwise specified) is ideal for low-power, high-performance applications. This processor offers very low
power consumption and the flexibility to support various system voltage configurations. The wide range of I/O
voltage enables it to operate with a single 1.8-V power supply or with dual power supplies for mixed-voltage
systems. This feature eliminates the need for external level-shifting and reduces power consumption in
emerging sub-3V systems.
The TMS320UC5405 is essentially similar to a TMS320UC5402 DSP. The main differences are listed below:
•
Simplified external memory interface. There are six address lines (A0−A5) and 16 data lines (D0−D15)
available.
•
•
MSC and IAQ signals are not available.
Significantly reduced package size.
Texas Instrument (TI) DSPs do not require specific power sequencing between the core supply and the I/O
supply. However, systems should be designed to ensure that neither supply is powered up for extended
periods of time if the other supply is below the proper operating voltage. Excessive exposure to these
conditions can adversely affect the long-term reliability of the device.
System-level concerns such as bus contention may require supply sequencing to be implemented. In this
case, the core supply should be powered up at the same time as, or prior to, the I/O buffers and powered down
after the I/O buffers.
The UC5405 is based on an advanced modified Harvard architecture that has one program memory bus and
three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of
parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The
basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.
2.2 Pin Assignments
Figure 2−1 illustrates the ball locations for the 143-terminal GQW and ZQW ball grid array (BGA) packages
and is used in conjunction with Table 2−1 to locate signal names and ball grid numbers. DV is the power
DD
supply for the I/O pins while CV is the power supply for the core CPU. V is the ground for both the I/O
DD
SS
pins and the core CPU.
TMS320C54x is a trademark of Texas Instruments.
12
SPRS199B
October 2002 − Revised October 2004
Introduction
2.3 Terminal Assignments for the GQW and ZQW Packages
M
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10 11 12
Figure 2−1. 143-Terminal GQW and ZQW Ball Grid Array (Bottom View)
13
October 2002 − Revised October 2004
SPRS199B
Introduction
†
Table 2−1. Terminal Assignments (143-Terminal GQW and ZQW Packages)
SIGNAL
NAME
SIGNAL
NAME
SIGNAL
NAME
SIGNAL
NAME
BGA BALL #
BGA BALL #
BGA BALL #
BGA BALL #
A1
A2
V
V
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
BDR1
BFSR1
BFSR0
NC
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
DV
K1
K2
INT1
INT0
INT3
EMU0
TDI
SS
SS
DD
V
SS
A3
MP/MC
HOLDA
IOSTRB
IS
HRDY
NC
K3
A4
K4
A5
NC
NC
K5
A6
NC
NC
K6
TMS
A7
READY
NC
NC
K7
CV
DD
A8
CV
NC
NC
K8
X1
DD
A9
V
SS
NC
NC
K9
D0
D3
A10
A11
A12
B1
HD7
A1
D14
HD4
D13
BDX0
HD0
BDX1
INT2
NC
K10
K11
K12
L1
V
SS
DV
DV
DD
DD
CV
A0
D6
CV
DD
BCLKR1
HCNTL0
BIO
V
SS
DD
B2
E2
BCLKX1
HINT/TOUT1
HCNTL1
NC
L2
HD1
CLKMD2
HD2
B3
E3
L3
B4
XF
E4
L4
B5
MSTRB
DS
E5
L5
EMU1/OFF
TRST
B6
E6
NC
NC
L6
B7
HR/W
NC
E7
NC
NC
L7
V
SS
B8
E8
NC
NC
L8
CLKOUT
‡
B9
HAS
E9
NC
NC
L9
X2/CLKIN
D1
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
DV
E10
E11
E12
F1
HDS2
HDS1
D12
D10
D11
HBIL
IACK
NMI
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
DD
A5
D5
A4
V
SS
V
SS
V
SS
V
SS
BDR0
BFSX0
CV
BCLKR0
F2
J2
DD
DV
F3
BFSX1
BCLKX0
NC
J3
CLKMD3
TOUT0
TDO
DD
HOLD
NC
F4
J4
DV
DD
F5
J5
CLKMD1
NC
R/W
PS
F6
NC
J6
TCK
F7
NC
J7
NC
HPIENA
HD3
HCS
NC
F8
NC
J8
NC
F9
NC
J9
NC
RS
HD6
A2
F10
F11
F12
D15
J10
J11
J12
D9
D2
CV
D7
D4
DD
C12
A3
HD5
D8
V
SS
†
DV is the power supply for the I/O pins while CV is the power supply for the core CPU. V is the ground for both the I/O pins and the core
DD
DD
SS
CPU.
‡
If an external clock source is used, the CLKIN signal level should not exceed CV + 0.3 V.
DD
NOTE: NC = No connection
14
SPRS199B
October 2002 − Revised October 2004
Introduction
2.4 Signal Descriptions
Table 2−2 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for exact
pin locations based on package type.
Table 2−2. Signal Descriptions
TERMINAL
NAME
†
TYPE
DESCRIPTION
DATA SIGNALS
A5
A4
A3
A2
A1
A0
(MSB)
O/Z
Parallel address bus A5 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. These pins are placed
in the high-impedance state when the hold mode is enabled, or when EMU1/OFF is low.
(LSB)
D15 (MSB)
D14
D13
D12
D11
D10
D9
I/O/Z
Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D0 to D15) are multiplexed to transfer
data between the core CPU and external data/program memory or I/O devices. The data bus is placed in the
high-impedance state when not outputting or when RS or HOLD is asserted. The data bus also goes into the
high-impedance state when EMU1/OFF is low.
The data bus has bus holders to reduce the static power dissipation caused by floating, unused pins. These bus
holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven
by the UC5405, the bus holders keep the pins at the previous logic level. The data bus holders on the UC5405
are disabled at reset and can be enabled/disabled via the BH bit of the bank-switching control register (BSCR).
D8
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
Interrupt acknowledge signal. IACK Indicates receipt of an interrupt and that the program counter is fetching the
interrupt vector location designated by A5−A0. IACK also goes into the high-impedance state when EMU1/OFF
is low.
IACK
O/Z
I
INT0
INT1
INT2
INT3
External user interrupts. INT0−INT3 are prioritized and are maskable by the interrupt mask register (IMR) and
the interrupt mode bit. INT0 −INT3 can be polled and reset by way of the interrupt flag register (IFR).
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM bit (in the ST1
register) or the IMR. When NMI is activated, the processor traps to the appropriate vector location.
NMI
I
I
Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the
CPU and peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program
memory. RS affects various registers and status bits.
RS
Microprocessor/microcomputer mode select. If active (low) at reset, microcomputer mode is selected, and the
internal program ROM is mapped into the upper 4K words of program memory space. If the pin is driven high
during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin
is only sampled at reset, and the MP/MC bit of the processor mode status (PMST) register can override the mode
that is selected at reset.
MP/MC
I
†
I = input, O = output, Z = high impedance, S = supply
If an external clock source is used, the CLKIN signal level should not exceed CV + 0.3 V.
‡
DD
15
October 2002 − Revised October 2004
SPRS199B
Introduction
Table 2−2. Signal Descriptions (Continued)
DESCRIPTION
TERMINAL
NAME
†
TYPE
MULTIPROCESSING SIGNALS
Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the
conditional instruction. For the XC instruction, the BIO condition is sampled during the decode phase of the
pipeline; all other instructions sample BIO during the read phase of the pipeline.
BIO
XF
I
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low
by the RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor
configurations or used as a general-purpose output pin. XF goes into the high-impedance state when EMU1/OFF
is low, and is set high at reset.
O/Z
MEMORY CONTROL SIGNALS
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for accessing
a particular external memory space. Active period corresponds to valid address information. DS, PS, and IS are
placed in the high-impedance state in the hold mode; the signals also go into the high-impedance state when
EMU1/OFF is low.
DS
PS
IS
O/Z
O/Z
I
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to
data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the
high-impedance state when EMU1/OFF is low.
MSTRB
READY
R/W
Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the
device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready detection if at least two software wait states are programmed. The READY signal is
not sampled until the completion of the software wait states.
Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally
in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in the
high-impedance state in hold mode; it also goes into the high-impedance state when EMU1/OFF is low.
O/Z
I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O
device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance
state when EMU1/OFF is low.
IOSTRB
HOLD
O/Z
I
Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the
C54x, these lines go into the high-impedance state.
Hold acknowledge. HOLDA indicates that the UC5405 is in a hold state and that the address, data, and control
lines are in the high-impedance state, allowing the external memory interface to be accessed by other devices.
HOLDA also goes into the high-impedance state when EMU1/OFF is low.
HOLDA
O/Z
PLL/TIMER SIGNALS
Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle
is bounded by the rising edges of this signal. CLKOUT also goes into the high-impedance state when EMU1/OFF
is low.
CLKOUT
O/Z
I
Clock mode-select signals. These inputs select the mode that the clock generator is initialized to after reset. The
logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized
to the selected mode. After reset, the clock mode can be changed through software, but the clock mode-select
signals have no effect until the device is reset again.
CLKMD1
CLKMD2
CLKMD3
‡
X2/CLKIN
X1
I
Clock/PLL input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input.
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
unconnected. X1 does not go into the high-impedance state when EMU1/OFF is low.
O
Timer0 output. TOUT0 signals a pulse when the on-chip timer 0 counts down past zero. The pulse is a CLKOUT
cycle wide. TOUT0 also goes into the high-impedance state when EMU1/OFF is low.
TOUT0
O/Z
O/Z
Timer1 output. TOUT1 signals a pulse when the on-chip timer 1 counts down past zero. The pulse is one
CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT pin of the HPI and is only available when
the HPI is disabled. TOUT1 also goes into the high-impedance state when EMU1/OFF is low.
HINT/TOUT1
†
I = input, O = output, Z = high impedance, S = supply
If an external clock source is used, the CLKIN signal level should not exceed CV + 0.3 V.
‡
DD
C54x is a trademark of Texas Instruments.
16
SPRS199B
October 2002 − Revised October 2004
Introduction
Table 2−2. Signal Descriptions (Continued)
DESCRIPTION
TERMINAL
NAME
†
TYPE
MULTICHANNEL BUFFERED SERIAL PORT SIGNALS
Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver.
BCLKR0
BCLKR1
I/O/Z
I
BDR0
BDR1
Serial data receive input
BFSR0
BFSR1
I/O/Z
Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over BDR.
Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as
an input or an output; it is configured as an input following reset. BCLKX enters the high-impedance state when
EMU1/OFF goes low.
BCLKX0
BCLKX1
I/O/Z
O/Z
BDX0
BDX1
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
asserted, or when EMU1/OFF is low.
Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the transmit data process. BFSX
can be configured as an input or an output; it is configured as an input following reset. BFSX goes into the
high-impedance state when EMU1/OFF is low.
BFSX0
BFSX1
I/O/Z
HOST-PORT INTERFACE SIGNALS
Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the
HPI registers. These pins can also be used as general-purpose I/O pins. HD0−HD7 is placed in the
high-impedance state when not outputting data or when EMU1/OFF is low. The HPI data bus includes bus
holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not
being driven by the UC5405, the bus holders keep the pins at the previous logic level. The HPI data bus holders
are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR.
HD0−HD7
I/O/Z
HCNTL0
HCNTL1
Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have
internal pullup resistors that are only enabled when HPIENA = 0.
I
Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup
resistor that is only enabled when HPIENA = 0.
HBIL
HCS
I
Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-select input
has an internal pullup resistor that is only enabled when HPIENA = 0.
I
HDS1
HDS2
Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers. The strobe inputs
have internal pullup resistors that are only enabled when HPIENA = 0.
I
Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA
register. HAS has an internal pullup resistor that is only enabled when HPIENA = 0.
HAS
I
I
Read/write. HR/W controls the direction of an HPI transfer. HR/W has an internal pullup resistor that is only
enabled when HPIENA = 0.
HR/W
HRDY
Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into the
high-impedance state when EMU1/OFF is low.
O/Z
Interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT can also
be configured as the timer 1 output (TOUT1) when the HPI is disabled. The signal goes into the high-impedance
state when EMU1/OFF is low.
HINT/TOUT1
HPIENA
O/Z
I
HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal pulldown resistor
is always active and the HPIENA pin is sampled on the rising edge of RS. If HPIENA is left open or is driven low
during reset, the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the UC5405
is reset.
SUPPLY PINS
CV
DV
S
S
S
+V . Dedicated power supply for the core CPU
DD
DD
+V . Dedicated power supply for the I/O pins
DD
DD
V
SS
Ground
†
‡
I = input, O = output, Z = high impedance, S = supply
If an external clock source is used, the CLKIN signal level should not exceed CV + 0.3 V.
DD
17
October 2002 − Revised October 2004
SPRS199B
Introduction
Table 2−2. Signal Descriptions (Continued)
DESCRIPTION
TERMINAL
NAME
†
TYPE
MISCELLANEOUS SIGNAL
NC
No connection
TEST PINS
IEEE standard 1149.1 (JTAG) test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The
changes on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller,
instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal
(TDO) occur on the falling edge of TCK.
TCK
I
IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
TDI
I
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out
of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in
progress. TDO also goes into the high-impedance state when EMU1/OFF is low.
TDO
TMS
TRST
O/Z
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
I
I
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
operations of the device. If TRST is not connected or is driven low, the device operates in its functional mode,
and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.
Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST
is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way
EMU0
I/O/Z
of the IEEE standard 1149.1 scan system. EMU0 should be pulled up to DV with a separate 4.7-kΩ resistor.
DD
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the
emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. When TRST
is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active (low), puts all output drivers
into the high-impedance state. EMU1/OFF should be pulled up to DV with a separate 4.7-kΩ resistor. Note
that OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications). Therefore,
DD
EMU1/OFF
I/O/Z
for the OFF feature, the following apply:
TRST = low
EMU0 = high
EMU1/OFF = low
†
I = input, O = output, Z = high impedance, S = supply
If an external clock source is used, the CLKIN signal level should not exceed CV + 0.3 V.
‡
DD
18
SPRS199B
October 2002 − Revised October 2004
Functional Overview
3
Functional Overview
The following functional overview is based on the block diagram in Figure 3−1.
P, C, D, E Buses and Control Signals
54x Core
4K ROM Program/Data
16K Dual-Access RAM
Program/Data
JTAG
Peripheral Bus
GPIO
Limited External
Memory Interface
McBSP0
McBSP1
HPI8 Module
DMA Controller
6 Channels
Timer0
Timer1
APLL
DMA Bus
Figure 3−1. Block Diagram of the TMS320UC5405
3.1 Memory
The UC5405 device provides both on-chip ROM and RAM to aid in system performance and integration.
3.1.1 On-Chip Dual-Access RAM (DARAM)
The UC5405 device contains 16K × 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed
of two blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and
a write in one cycle. The DARAM is located in the address range 0080h−3FFFh in data space, and can be
mapped into program/data space by setting the OVLY bit to 1.
19
October 2002 − Revised October 2004
SPRS199B
Functional Overview
3.1.2 On-Chip ROM With Bootloader
The UC5405 features 4K × 16-bit of on-chip maskable ROM. Customers can arrange to have the ROM of the
UC5405 programmed with contents unique to any particular application. A security option is available to
protect a custom ROM. This security option is described in the TMS320C54x DSP Reference Set, Volume 1:
CPU and Peripherals (literature number SPRU131). Note that only the ROM security option, and not the
ROM/RAM option, is available on the UC5405 .
A bootloader is available in the standard UC5405 on-chip ROM. This bootloader can be used to automatically
transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC
pin is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This
location contains a branch instruction to the start of the bootloader program. The standard UC5405 bootloader
provides different ways to download the code to accomodate various system requirements:
•
•
Serial boot from serial ports 8-bit or 16-bit mode
Host-port interface boot
The standard on-chip ROM layout is shown in Table 3−1.
Table 3−1. Standard On-Chip ROM Layout
†
ADDRESS RANGE
DESCRIPTION
F000h − F7FFh
Reserved
F800h − FBFFh
FC00h − FCFFh
FD00h − FDFFh
FE00h − FEFFh
FF00h − FF7Fh
FF80h − FFFFh
Bootloader
µ-law expansion table
A-law expansion table
Sine look-up table
Reserved
Interrupt vector table
†
In the UC5405 ROM, 128 words are reserved for factory device-testing purposes. Application
code to be implemented in on-chip ROM must reserve these 128 words at addresses
FF00h–FF7Fh in program space.
20
SPRS199B
October 2002 − Revised October 2004
Functional Overview
3.1.3 Memory Map
Page 0 Program
Page 0 Program
Data
Hex
0000
Hex
Hex
0000
0000
Memory
Mapped
Registers
Reserved
(OVLY = 1)
External
(OVLY = 0)
Reserved
(OVLY = 1)
External
(OVLY = 0)
005F
0060
Scratch-Pad
RAM
007F
0080
007F
0080
007F
0080
On-Chip DARAM
(OVLY = 1)
On-Chip DARAM
(OVLY = 1)
On-Chip DARAM
(16K x 16-bit)
External
(OVLY = 0)
External
(OVLY = 0)
3FFF
4000
3FFF
4000
3FFF
4000
†
†
External
External
EFFF
F000
EFFF
F000
†
ROM (DROM=1)
External
On-Chip ROM
(4K x 16-bit)
†
or External
(DROM=0)
FEFF
FF00
FEFF
FF00
Reserved
FF7F
FF80
Reserved
(DROM=1)
or External
(DROM=0)
FF7F
FF80
Interrupts
(On-Chip)
Reserved
MP/MC= 1
FFFF
FFFF
FFFF
MP/MC= 0
(Microcomputer Mode)
(Microprocessor Mode)
†
Only six of the 16 total TMS320UC5405 address bits are available to the external interface; therefore, only 64 unique external addresses are
available, regardless of the actual 16-bit address generated internally. These 64 addresses are those resulting from the truncation of the upper
address bits (A6 and above). This results in these 64 addresses being repeated throughout all of the external address space.
Figure 3−2. TMS320UC5405 Memory Map
3.1.4 Implications of 6-Bit Addressing
TMS320UC5405 provides only six of the 16 total address bits to the external interface. Therefore, only
64 unique external addresses are available, regardless of the actual 16-bit address generated internally.
These 64 addresses are those resulting from the truncation of the upper address bits (A6 through A15). This
results in these 64 addresses being repeated throughout all of the external address space.
If more than 64 external locations need to be addressed, a paging scheme can be used to expand the
addressing capability as necessary. In this paging scheme, an external register is used to supply the upper
addresses (A6 through A15) for the memory reach greater than six bits. The external register is loaded by
having the 5405 write to a location in I/O space whose data lines are the higher address bits as shown in
Figure 3−3. This scheme can be implemented using either a simple external latch, or can be included in a
FPGA. This paging scheme can be implemented without any decoding required and shares the same bus
with the SRAM and the DSP.
21
October 2002 − Revised October 2004
SPRS199B
Functional Overview
Register
EN
Q0 − Q9
D0 − D9
TMS320UC5405
IS
SRAM
A6 − A15
D15 − D0
A5 − A0
D15 − D0
A5 − A0
CS
PS or DS
Figure 3−3. TMS320UC5405 External Memory Paging Scheme
3.1.5 Relocatable Interrupt Vector Table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch
instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate
interrupt service routine with minimal overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.
However, these vectors can be remapped to the beginning of any 128-word page in program space after
device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register (see
Figure 3−4) with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or
trap vector is mapped to the new 128-word page.
NOTE: The hardware reset (RS) vector cannot be remapped because a hardware reset loads the IPTR
with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.
15
8
IPTR
R/W
7
6
5
4
AVIS
R
3
DROM
R
2
CLKOFF
R
1
0
IPTR
R/W
MP/MC
R/W
OVLY
R/W
SMUL
R/W
SST
R/W
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3−4. Processor Mode Status (PMST) Register
22
SPRS199B
October 2002 − Revised October 2004
Functional Overview
3.2 On-Chip Peripherals
The UC5405 device supports the following on-chip peripherals:
•
•
•
•
•
•
Software-programmable wait-state generator with programmable bank-switching wait states
An enhanced 8-bit host-port interface (HPI8)
Two multichannel buffered serial ports (McBSPs)
Two hardware timers
A clock generator with a phase-locked loop (PLL)
A direct memory access (DMA) controller
3.2.1 Software-Programmable Wait-State Generator
The software wait-state generator of the UC5405 can extend external bus cycles by up to 14 machine cycles.
Devices that require more than 14 wait states can be interfaced using the hardware READY line. When all
external accesses are configured for zero wait states, the internal clocks to the wait-state generator are
automatically disabled. Disabling the wait-state generator clocks reduces the power consumption of the
UC5405.
The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 15 LSBs
of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to
5 separate address ranges. This allows a different number of wait states for each of the five address ranges.
Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)
defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is
initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown
in Figure 3−5 and described in Table 3−2.
15
14
12
11
9
8
XPA
I/O
DATA
DATA
R/W-111
R/W-0
R/W-111
R/W-111
7
6
5
3
2
0
DATA
PROGRAM
R/W-111
PROGRAM
R/W-111
R/W-111
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3−5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
23
October 2002 − Revised October 2004
SPRS199B
Functional Overview
Table 3−2. Software Wait-State Register (SWWSR) Bit Fields
BIT
RESET
VALUE
FUNCTION
NO.
NAME
Extended program address control bit. XPA is used in conjunction with the program space fields
(bits 0 through 5) to select the address range for the program space wait states.
15
XPA
0
I/O space. The field value (0−7) corresponds to the base number of wait states for I/O space accesses
within addresses 0000−FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for
the base number of wait states.
14−12
11−9
8−6
I/O
1
1
1
Upper data space. The field value (0−7) corresponds to the base number of wait states for external
data space accesses within addresses 8000−FFFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
Data
Data
Lower data space. The field value (0−7) corresponds to the base number of wait states for external
data space accesses within addresses 0000−7FFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
Upper program space. The field value (0−7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
-
-
XPA = 0: x8000 − xFFFFh
5−3
2−0
Program
Program
1
1
XPA = 1: The upper program space bit field has no effect on wait states.
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
Program space. The field value (0−7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
-
-
XPA = 0: x0000−x7FFFh
XPA = 1: 00000−FFFFFh
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
The software wait-state multiplier bit (SWSM) of the software wait-state control register (SWCR) is used to
extend the base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 3−6
and described in Table 3−3.
15
8
Reserved
R/W-0
7
1
0
Reserved
R/W-0
LEGEND: R = Read, W = Write, n = value present after reset
SWSM
R/W-0
Figure 3−6. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]
Table 3−3. Software Wait-State Control Register (SWCR) Bit Fields
BIT
NAME
RESET
VALUE
FUNCTION
NO.
15−1
Reserved
0
These bits are reserved and are unaffected by writes.
Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor
of 1 or 2.
0
SWSM
0
-
-
SWSM = 0: wait-state base values are unchanged (multiplied by 1).
SWSM = 1: wait-state base values are mulitplied by 2 for a maximum of 14 wait states.
24
SPRS199B
October 2002 − Revised October 2004
Functional Overview
3.2.1.1 Programmable Bank-Switching Wait States
The programmable bank-switching logic of the UC5405 is functionally equivalent to that of the 548/549
devices. This feature automatically inserts one cycle when accesses cross memory-bank boundaries within
program or data memory space. A bank-switching wait state can also be automatically inserted when
accesses cross the data space boundary into program space.
The bank-switching control register (BSCR) defines the bank size for bank-switching wait states. Figure 3−7
shows the BSCR and its bits are described in Table 3−4.
15
12
11
10
8
BNKCMP
R/W-1111
PS−DS
R/W-1
Reserved
R-0
7
3
2
1
0
Reserved
R-0
LEGEND: R = Read, W = Write, n = value present after reset
HBH
R/W-0
BH
EXIO
R/W-0
R/W-0
Figure 3−7. Bank-Switching Control Register (BSCR) [MMR Address 0029h]
Table 3−4. Bank-Switching Control Register (BSCR) Bit Fields
BIT
NAME
RESET
VALUE
FUNCTION
NO.
Bank compare. Determines the external memory-bank size. BNKCMP is used to mask the four MSBs of
an address. For example, if BNKCMP = 1111b, the four MSBs (bits 12−15) are compared, resulting in a
bank size of 4K words. Bank sizes of 4K words to 64K words are allowed.
15−12 BNKCMP
1111
Program read − data read access. Inserts an extra cycle between consecutive accesses of program read
and data read or data read and program read.
11
10−3
2
PS - DS
Reserved
HBH
1
0
0
PS-DS = 0
PS-DS = 1
No extra cycles are inserted by this feature.
One extra cycle is inserted between consecutive data and program reads.
These bits are reserved and are unaffected by writes.
HPI Bus holder. Controls the HPI bus holder feature. HBH is cleared to 0 at reset.
HBH = 0
HBH = 1
The bus holder is disabled.
The bus holder is enabled. When not driven, the HPI data bus (HD[7:0]) is held in the
previous logic level.
Bus holder. Controls the data bus holder feature. BH is cleared to 0 at reset.
BH = 0
BH = 1
The bus holder is disabled.
The bus holder is enabled. When not driven, the data bus (D[15:0]) is held in the
previous logic level.
1
0
BH
0
0
External bus interface off. The EXIO bit controls the external bus-off function.
EXIO = 0
EXIO = 1
The external bus interface functions as usual.
The address bus, data bus, and control signals become inactive after completing the
current bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the HM
bit of ST1 cannot be modified when the interface is disabled.
EXIO
25
October 2002 − Revised October 2004
SPRS199B
Functional Overview
3.2.2 Parallel I/O Ports
The UC5405 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the
PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The UC5405 can
interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding
circuits.
3.2.2.1 Enhanced 8-Bit Host-Port Interface (HPI8)
The UC5405 host-port interface, also referred to as the HPI8, is an enhanced version of the standard 8-bit
HPI found on earlier 54x DSPs (542, 545, 548, and 549). The HPI8 is an 8-bit parallel port for interprocessor
communication. The features of the HPI8 include:
Standard features:
•
•
•
Sequential transfers (with autoincrement) or random-access transfers
Host interrupt and 54x interrupt capability
Multiple data strobes and control pins for interface flexibility
Enhanced features of the UC5405 HPI8:
•
•
Access to entire on-chip RAM through DMA bus
Capability to continue transferring during emulation stop
Hex
0000
Reserved
001F
0020
McBSP
Registers
0023
0024
Reserved
005F
0060
Scratch-Pad
RAM
007F
0080
(16K x 16-bit)
On-Chip DARAM
3FFF
4000
Reserved
FFFF
Figure 3−8. HPI8 Memory Map
The HPI8 functions as a slave and enables the host processor to access the on-chip memory of the UC5405.
A major enhancement to the UC5405 HPI over previous versions is that it allows host access to the entire
on-chip memory range of the DSP. The host and the DSP both have access to the on-chip RAM at all times
and host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to
the same location, the host has priority, and the DSP waits for one HPI8 cycle. Note that since host accesses
are always synchronized to the UC5405 clock, an active input clock (CLKIN) is required for HPI8 accesses
during IDLE states, and host accesses are not allowed while the UC5405 reset pin is asserted.
26
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October 2002 − Revised October 2004
Functional Overview
The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers
are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with
the HPI8 through three dedicated registers — HPI address register (HPIA), HPI data register (HPID), and an
HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC
register is accessible by both the host and the UC5405.
3.2.2.2 Multichannel Buffered Serial Ports
The UC5405 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that
allow direct interface to other C54x/LC54x DSPs, codecs, and other devices in a system. The McBSPs are
based on the standard serial port interface found on other 54x devices. Like its predecessors, the McBSP
provides:
•
•
•
Full-duplex communication
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSP has the following capabilities:
•
Direct interface to:
−
−
−
−
T1/E1 framers
MVIP switching compatible and ST-BUS compliant devices
IOM-2 compliant devices
Serial peripheral interface devices
•
•
•
•
•
Multichannel transmit and receive of up to 128 channels
A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits
µ-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
The McBSPs consist of separate transmit and receive channels that operate independently. The external
interface of each McBSP consists of the following pins:
•
•
•
•
•
•
BCLKX
BDX
BFSX
BCLKR
BDR
Transmit reference clock
Transmit data
Transmit frame synchronization
Receive reference clock
Receive data
BFSR
Receive frame synchronization
The six pins listed are functionally equivalent to the previous serial port interface pins in the TMS320C5000
platform of DSPs. On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX
and BCLKX pins, respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit
register (DXR). Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This
structure allows DXR to be loaded with the next word to be sent while the transmission of the current word
is in progress.
On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins,
respectively. The CPU or DMA can read received data from the data receive register (DRR). Data received
on the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register
(RBR). If the DRR is empty, the RBR contents are copied into the DRR. If not, the RBR holds the data until
the DRR is available. This structure allows storage of the two previous words while the reception of the current
word is in progress.
The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP
interrupts, event signals, and status flags. The DMA is capable of handling data movement between the
McBSPs and memory with no intervention from the CPU.
TMS320C5000 is a trademark of Texas Instruments.
27
October 2002 − Revised October 2004
SPRS199B
Functional Overview
In addition to the standard serial port functions, the McBSP provides programmable clock and frame
synchronization generation. Among the programmable functions are:
•
•
•
•
•
•
Frame synchronization pulse width
Frame period
Frame synchronization delay
Clock reference (internal vs. external)
Clock division
Clock and frame synchronization polarity
The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law format.
When companding is used, transmit data is encoded according to specified companding law and received
data is decoded to 2s complement format.
The McBSP allows multiple channels to be independently selected for the transmitter and receiver. When
multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using
TDM data streams, the CPU may only need to process a few of them. Thus, to save memory and bus
bandwidth, multichannel selection allows independent enabling of particular channels for transmission and
reception. Up to 32 channels in a stream of up to 128 channels can be enabled.
The clock-stop mode (CLKSTP) in the McBSP provides compatibility with the serial peripheral interface (SPI)
protocol. Clock-stop mode works with only single-phase frames and one word per frame. The word sizes
supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP
is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or
as a slave.
The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum frequency is CPU
clock frequency divided by 2.
3.2.3 Hardware Timer
The UC5405 device features two 16-bit timing circuits with 4-bit prescalers. The main counter of each timer
is decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is
generated. The timers can be stopped, restarted, reset, or disabled by specific control bits.
3.2.4 Clock Generator
The clock generator provides clocks to the UC5405 device, and consists of an internal oscillator and a
phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided
by using a crystal resonator with the internal oscillator, or from an external reference clock source. The
reference clock input is then divided by two or four (DIV mode) to generate clocks for the UC5405 device, or
the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock
frequency by a scale factor. This allows the use of a clock source with a lower frequency than that of the
CPU.The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.
NOTE: If an external clock source is used, the CLKIN signal level should not exceed CV + 0.3 V.
DD
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,
other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the
UC5405 device.
28
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Functional Overview
This clock generator allows system designers to select the clock source. The sources that drive the clock
generator are:
•
•
A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins
of the UC5405 to enable the internal oscillator.
An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left
unconnected.
NOTE: If an external clock source is used, the CLKIN signal level should not exceed CV + 0.3 V.
DD
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to the PLL clocking mode of the device until lock is achieved. Devices that have
a built-in software-programmable PLL can be configured in one of two clock modes:
•
•
PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved
using the PLL circuitry.
DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can
be completely disabled to minimize power dissipation.
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Upon
reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the
CLKMD1 − CLKMD3 pins as shown in Table 3−5.
Table 3−5. Clock Mode Settings at Reset
CLKMD
RESET VALUE
CLKMD1
CLKMD2
CLKMD3
CLOCK MODE
0
0
0
0
0
1
E007h
PLL x 15
PLL x 10
9007h
0
1
1
1
1
0
1
0
1
1
0
1
0
0
0
1
1
1
4007h
1007h
F007h
0000h
F000h
—
PLL x 5
PLL x 2
PLL x 1
1/2 (PLL disabled)
1/4 (PLL disabled)
Reserved (bypass mode)
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Functional Overview
3.2.5 DMA Controller
The UC5405 direct memory access (DMA) controller transfers data between points in the memory map
without intervention by the CPU. The DMA controller allows movements of data to and from internal
program/data memory or internal peripherals (such as the McBSPs) to occur in the background of CPU
operation. The DMA has six independent programmable channels, allowing six different contexts for DMA
operation.
3.2.5.1 Features
The DMA has the following features:
•
•
•
•
•
The DMA operates independently of the CPU.
The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
The DMA has higher priority than the CPU for internal accesses.
Each channel has independently programmable priorities.
Each channel’s source and destination address registers can have configurable indexes through memory
on each read and write transfer, respectively. The address may remain constant, be postincremented,
postdecremented, or be adjusted by a programmable value.
•
•
Each read or write transfer may be initialized by selected events.
Upon completion of a half-block or an entire-block transfer, each DMA channel may send an interrupt to
the CPU.
•
The DMA can perform doubleword transfers (a 32-bit transfer of two 16-bit words).
3.2.5.2 DMA Memory Map
The DMA memory map allows DMA transfers to be unaffected by the status of the MP/MC, DROM, and OVLY
bits. The DMA memory map (see Figure 3−9) is identical to that of the HPI8 controller.
Hex
0000
Reserved
001F
0020
McBSP
Registers
0023
0024
Reserved
005F
0060
Scratch-Pad
RAM
007F
0080
(16K x 16-bit)
On-Chip DARAM
3FFF
4000
Reserved
FFFF
Figure 3−9. DMA Memory Map
3.2.5.3 DMA Priority Level
Each DMA channel can be independently assigned high priority or low priority relative to each other. Multiple
DMA channels that are assigned to the same priority level are handled in a round-robin manner.
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Functional Overview
3.2.5.4 DMA Source/Destination Address Modification
The DMA provides flexible address-indexing modes for easy implementation of data management schemes
such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and
can be postincremented, postdecremented, or postincremented with a specified index offset.
3.2.5.5 DMA in Autoinitialization Mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers
can be preloaded for the next block transfer through the DMA global reload registers (DMGSA, DMGDA, and
DMGCR). Autoinitialization allows:
•
Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the
completion of the current block transfer; but with the global reload registers, it can reinitialize these values
for the next block transfer any time after the current block transfer begins.
•
Repetitive operation: The CPU does not preload the global reload register with new values for each block
transfer but only loads them on the first block transfer.
3.2.5.6 DMA Transfer Counting
The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit fields
that represent the number of frames and the number of elements per frame to be transferred.
•
Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum
number of frames per block transfer is 128 (FRAME COUNT= 0ffh). The counter is decremented upon
the last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is
reloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count
of 0 (default value) means the block transfer contains a single frame.
•
Element count. This 16-bit value defines the number of elements per frame. This counter is decremented
after the read transfer of each element. The maximum number of elements per frame is 65536
(DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter is
reloaded with the DMA global count reload register (DMGCR).
3.2.5.7 DMA Transfers in Doubleword Mode
Doubleword mode allows the DMA to transfer 32-bit words in any index mode. In doubleword mode, two
consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated
following each transfer. In this mode, each 32-bit word is considered to be one element.
3.2.5.8 DMA Channel Index Registers
The particular DMA channel index register is selected by way of the SIND and DIND field in the DMA mode
control register (DMMCRx). Unlike basic address adjustment, in conjunction with the frame index DMFRI0 and
DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer is
the last in the current frame. The normal adjustment value (element index) is contained in the element index
registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame is determined
by the selected DMA frame index register, either DMFRI0 or DMFRI1.
The element index and the frame index affect address adjustment as follows:
•
Element index: For all except the last transfer in the frame, the element index determines the amount to
be added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as
selected by the SIND/DIND bits.
•
Frame index: If the transfer is the last in a frame, the frame index is used for address adjustment as
selected by the SIND/DIND bits. This occurs in both single-frame and multi-frame transfer.
3.2.5.9 DMA Interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA mode control register (DMMCRx). The available modes
are shown in Table 3−6.
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Functional Overview
Table 3−6. DMA Interrupts
MODE
ABU (non-decrement)
ABU (non-decrement)
Multi-Frame
DINM
INTERRUPT
1
1
1
1
0
0
0
At full buffer only
1
0
At half buffer and full buffer
At block transfer complete (DMCTRx = DMSEFCx[7:0] = 0)
At end of frame and end of block (DMCTRx = 0)
No interrupt generated
Multi-Frame
1
Either
X
X
Either
No interrupt generated
3.2.5.10 DMA Controller Synchronization Events
The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN
bit field of the DMA channel x sync select and frame count (DMSFCx) register selects the synchronization
event for a channel. The list of possible events and the DSYN values are shown in Table 3−7.
Table 3−7. DMA Synchronization Events
DSYN VALUE
0000b
DMA SYNCHRONIZATION EVENT
No synchronization used
0001b
McBSP0 receive event
McBSP0 transmit event
Reserved
0010b
0011−0100b
0101b
McBSP1 receive event
McBSP1 transmit event
Reserved
0110b
0111b−0110b
1101b
Timer0 interrupt
1110b
External interrupt 3
Timer1 interrupt
1111b
3.2.5.11 DMA Channel Interrupt Selection
The DMA controller can generate a CPU interrupt for each of the six channels. However, the interrupt sources
for channels 0,1, 2, and 3 are multiplexed with other interrupt sources. DMA channels 2 and 3 share an interrupt
line with the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 11), and DMA channel 1 shares an
interrupt line with timer 1 (IMR/IFR bit 7). The interrupt source for DMA channel 0 is shared with a reserved
interrupt source. When the UC5405 is reset, the interrupts from these four DMA channels are deselected. The
INTSEL bit field in the DMA channel priority and enable control (DMPREC) register can be used to select these
interrupts, as shown in Table 3−8.
Table 3−8. DMA Channel Interrupt Selection
INTSEL Value
00b (reset)
01b
IMR/IFR[6]
Reserved
Reserved
DMAC0
IMR/IFR[7]
TINT1
IMR/IFR[10]
BRINT1
IMR/IFR[11]
BXINT1
TINT1
DMAC2
DMAC3
10b
DMAC1
DMAC2
DMAC3
11b
Reserved
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Functional Overview
3.3 Memory-Mapped Registers
The UC5405 has a set of memory-mapped registers associated with the CPU, on-chip peripherals, the
McBSPs, and the DMA.
3.3.1 CPU Memory-Mapped Registers
The UC5405 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses
0h to 1Fh. Table 3−9 gives a list of the CPU memory-mapped registers (MMRs) available on UC5405.
Table 3−9. CPU Memory-Mapped Registers
ADDRESS
NAME
IMR
DESCRIPTION
DEC
0
HEX
0
Interrupt mask register
Interrupt flag register
Reserved for testing
Status register 0
IFR
–
1
1
2−5
6
2−5
6
ST0
ST1
AL
7
7
Status register 1
8
8
Accumulator A low word (15−0)
AH
9
9
Accumulator A high word (31−16)
Accumulator A guard bits (39−32)
Accumulator B low word (15−0)
Accumulator B high word (31−16)
Accumulator B guard bits (39−32)
Temporary register
AG
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
BL
B
BH
C
BG
D
TREG
TRN
AR0
AR1
AR2
AR3
AR4
AR5
AR6
AR7
SP
E
F
Transition register
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Auxiliary register 0
Auxiliary register 1
Auxiliary register 2
Auxiliary register 3
Auxiliary register 4
Auxiliary register 5
Auxiliary register 6
Auxiliary register 7
Stack pointer register
BK
Circular buffer size register
Block-repeat counter
BRC
RSA
REA
PMST
XPC
–
Block-repeat start address
Block-repeat end address
Processor mode status (PMST) register
Extended program page register
Reserved
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October 2002 − Revised October 2004
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Functional Overview
3.3.2 Peripheral Memory-Mapped Registers
The UC5405 has a set of memory-mapped registers associated with peripherals as shown in Table 3−10.
Table 3−10. Peripheral Memory-Mapped Registers
NAME
DRR20
ADDRESS
20h
DESCRIPTION
McBSP0 data receive register 2
TYPE
McBSP #0
McBSP #0
McBSP #0
McBSP #0
Timer0
DRR10
DXR20
DXR10
TIM
21h
McBSP0 data receive register 1
McBSP0 data transmit register 2
McBSP0 data transmit register 1
Timer0 register
22h
23h
24h
PRD
25h
Timer0 period counter
Timer0 control register
Reserved
Timer0
TCR
26h
Timer0
–
27h
SWWSR
BSCR
–
28h
Software wait-state register
Bank-switching control register
Reserved
External Bus
External Bus
29h
2Ah
SWCR
HPIC
–
2Bh
Software wait-state control register
HPI control register
External Bus
HPI
2Ch
2Dh−2Fh
30h
Reserved
TIM1
PRD1
TCR1
–
Timer1 register
Timer1
Timer1
Timer1
31h
Timer1 period counter
Timer1 control register
Reserved
32h
33h−37h
38h
†
SPSA0
SPSD0
–
McBSP0 subbank address register
McBSP #0
McBSP #0
†
39h
McBSP0 subbank data register
3Ah−3Bh
3Ch
Reserved
GPIOCR
GPIOSR
–
General-purpose I/O pins control register
General-purpose I/O pins status register
Reserved
GPIO
GPIO
3Dh
3Eh−3Fh
40h
DRR21
DRR11
DXR21
DXR11
–
McBSP1 data receive register 2
McBSP1 data receive register 1
McBSP1 data transmit register 2
McBSP1 data transmit register 1
Reserved
McBSP #1
McBSP #1
McBSP #1
McBSP #1
41h
42h
43h
44h−47h
48h
†
SPSA1
SPSD1
–
McBSP1 subbank address register
McBSP #1
McBSP #1
†
49h
McBSP1 subbank data register
4Ah−53h
54h
Reserved
DMPREC
DMSA
DMSDI
DMSDN
CLKMD
–
DMA channel priority and enable control register
DMA
DMA
DMA
DMA
PLL
‡
55h
DMA subbank address register
‡
56h
DMA subbank data register with autoincrement
‡
57h
DMA subbank data register
58h
Clock mode register
Reserved
59h−5Fh
†
‡
See Table 3−11 for a detailed description of the McBSP control registers and their subaddresses.
See Table 3−12 for a detailed description of the DMA subbank addressed registers.
34
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Functional Overview
3.3.3 McBSP Control Registers and Subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory
location. The serial port subbank address (SPSA) register is used as a pointer to select a particular register
within the subbank. The serial port subbank data (SPSD) register is used to access (read or write) the selected
register. Table 3−11 shows the McBSP control registers and their corresponding subaddresses.
Table 3−11. McBSP Control Registers and Subaddresses
McBSP0
ADDRESS
McBSP1
SUB-
ADDRESS
DESCRIPTION
NAME
SPCR10
NAME
ADDRESS
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
SPCR11
SPCR21
RCR11
49h
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
Serial port control register 1
SPCR20
RCR10
49h
Serial port control register 2
49h
Receive control register 1
RCR20
RCR21
49h
Receive control register 2
XCR10
XCR11
49h
Transmit control register 1
XCR20
XCR21
49h
Transmit control register 2
SRGR10
SRGR20
MCR10
MCR20
RCERA0
RCERB0
XCERA0
XCERB0
PCR0
SRGR11
SRGR21
MCR11
MCR21
RCERA1
RCERB1
XCERA1
XCERB1
PCR1
49h
Sample rate generator register 1
Sample rate generator register 2
Multichannel register 1
49h
49h
49h
Multichannel register 2
49h
Receive channel enable register partition A
Receive channel enable register partition B
Transmit channel enable register partition A
Transmit channel enable register partition B
Pin control register
49h
49h
49h
49h
3.3.4 DMA Subbank Addressed Registers
The direct memory access (DMA) controller has several control registers associated with it. The main control
register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using
the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single
memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular
register within the subbank, while the DMA subbank data (DMSDN) register or the DMA subbank data register
with autoincrement (DMSDI) is used to access (read or write) the selected register.
When the DMSDI register is used to access the subbank, the subbank address is automatically
postincremented so that a subsequent access affects the next register within the subbank. This autoincrement
feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature
is not required, the DMSDN register should be used to access the subbank. Table 3−12 shows the DMA
controller subbank addressed registers and their corresponding subaddresses.
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October 2002 − Revised October 2004
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Functional Overview
Table 3−12. DMA Subbank Addressed Registers
SUB-
ADDRESS
†
NAME
ADDRESS
DESCRIPTION
DMSRC0
DMDST0
DMCTR0
DMSFC0
DMMCR0
DMSRC1
DMDST1
DMCTR1
DMSFC1
DMMCR1
DMSRC2
DMDST2
DMCTR2
DMSFC2
DMMCR2
DMSRC3
DMDST3
DMCTR3
DMSFC3
DMMCR3
DMSRC4
DMDST4
DMCTR4
DMSFC4
DMMCR4
DMSRC5
DMDST5
DMCTR5
DMSFC5
DMMCR5
DMSRCP
DMDSTP
DMIDX0
DMIDX1
DMFRI0
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
00h
DMA channel 0 source address register
DMA channel 0 destination address register
DMA channel 0 element count register
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
DMA channel 0 sync select and frame count register
DMA channel 0 transfer mode control register
DMA channel 1 source address register
DMA channel 1 destination address register
DMA channel 1 element count register
DMA channel 1 sync select and frame count register
DMA channel 1 transfer mode control register
DMA channel 2 source address register
DMA channel 2 destination address register
DMA channel 2 element count register
DMA channel 2 sync select and frame count register
DMA channel 2 transfer mode control register
DMA channel 3 source address register
DMA channel 3 destination address register
DMA channel 3 element count register
DMA channel 3 sync select and frame count register
DMA channel 3 transfer mode control register
DMA channel 4 source address register
DMA channel 4 destination address register
DMA channel 4 element count register
DMA channel 4 sync select and frame count register
DMA channel 4 transfer mode control register
DMA channel 5 source address register
DMA channel 5 destination address register
DMA channel 5 element count register
DMA channel 5 sync select and frame count register
DMA channel 5 transfer mode control register
DMA source program page address (common channel)
DMA destination program page address (common channel)
DMA element index address register 0
DMA element index address register 1
DMA frame index register 0
DMFRI1
DMA frame index register 1
DMGSA
DMA global source address reload register
DMA global destination address reload register
DMA global count reload register
DMGDA
DMGCR
DMGFR
DMA global frame count reload register
†
Address 56h is used to access DMA subbank data registers with autoincrement (DMSDI) while address 57h is used to access DMA subbank
data register without autoincrement (DMSDN).
36
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Functional Overview
3.4 Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3−13.
Table 3−13. Interrupt Locations and Priorities
LOCATION
PRIORITY
NAME
FUNCTION
DECIMAL
0
HEX
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
4C
50
54
RS, SINTR
NMI, SINT16
SINT17
1
2
Reset (hardware and software reset)
Nonmaskable interrupt
Software interrupt #17
Software interrupt #18
Software interrupt #19
Software interrupt #20
Software interrupt #21
Software interrupt #22
Software interrupt #23
Software interrupt #24
Software interrupt #25
Software interrupt #26
Software interrupt #27
Software interrupt #28
Software interrupt #29
Software interrupt #30
External user interrupt #0
External user interrupt #1
External user interrupt #2
Timer0 interrupt
4
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
SINT18
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
SINT19
SINT20
SINT21
SINT22
SINT23
SINT24
SINT25
SINT26
SINT27
SINT28
SINT29
SINT30
INT0, SINT0
INT1, SINT1
INT2, SINT2
TINT0, SINT3
4
5
6
BRINT0, SINT4
BXINT0, SINT5
7
McBSP #0 receive interrupt
McBSP #0 transmit interrupt
8
Reserved (default) or DMA channel 0
interrupt. The selection is made in the
DMPREC register.
Reserved(DMAC0), SINT6
TINT1(DMAC1), SINT7
88
92
58
9
Timer1 interrupt (default) or DMA channel 1
interrupt. The selection is made in the
DMPREC register.
5C
10
INT3, SINT8
96
60
64
11
12
External user interrupt #3
HPI interrupt
HPINT, SINT9
100
McBSP #1 receive interrupt (default) or DMA
channel 2 interrupt. The selection is made in
the DMPREC register.
BRINT1(DMAC2), SINT10
BXINT1(DMAC3), SINT11
104
108
68
13
14
McBSP #1 transmit interrupt (default) or DMA
channel 3 interrupt. The selection is made in
the DMPREC register.
6C
DMAC4,SINT12
DMAC5,SINT13
Reserved
112
116
70
74
15
16
—
DMA channel 4 interrupt
DMA channel 5 interrupt
Reserved
120−127
78−7F
37
October 2002 − Revised October 2004
SPRS199B
Functional Overview
3.4.1 IFR and IMR Registers
The bits of the interrupt flag register (IFR) and interrupt mask register (IMR) are arranged as shown in
Figure 3−10.
15
14
13
12
11
10
9
8
BXINT1/
DMAC3
BRINT1/
DMAC2
Reserved
DMAC5
DMAC4
HPINT
INT3
7
6
5
4
3
2
1
0
TINT1/
DMAC1
Reserved/
DMAC0
BXINT0
BRINT0
TINT0
INT2
INT1
INT0
Figure 3−10. IFR and IMR Registers
Table 3−14. IFR and IMR Register Bit Fields
BIT
FUNCTION
NUMBER
15−14
13
NAME
−
Reserved for future expansion
DMAC5
DMAC4
DMA channel 5 interrupt flag/mask bit
DMA channel 4 interrupt flag/mask bit
12
This bit can be configured as either the McBSP1 transmit interrupt flag/mask bit, or the DMA
channel 3 interrupt flag/mask bit. The selection is made in the DMPREC register.
11
10
BXINT1/DMAC3
BRINT1/DMAC2
This bit can be configured as either the McBSP1 receive interrupt flag/mask bit, or the DMA
channel 2 interrupt flag/mask bit. The selection is made in the DMPREC register.
9
8
HPINT
INT3
Host−to-C54x interrupt flag/mask
External interrupt 3 flag/mask
This bit can be configured as either the timer1 interrupt flag/mask bit, or the DMA channel 1
interrupt flag/mask bit. The selection is made in the DMPREC register.
7
6
TINT1/DMAC1
This bit can be configured either as reserved or as the DMA channel 0 interrupt flag/mask bit. The
selection is made in the DMPREC register.
Reserved or DMAC0
5
4
3
2
1
0
BXINT0
BRINT0
TINT0
INT2
McBSP0 transmit interrupt flag/mask bit
McBSP0 receive interrupt flag/mask bit
Timer 0 interrupt flag/mask bit
External interrupt 2 flag/mask bit
External interrupt 1 flag/mask bit
External interrupt 0 flag/mask bit
INT1
INT0
38
SPRS199B
October 2002 − Revised October 2004
Device Support
4
Device Support
4.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality
and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped with against the following
disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package
type (for example, GQW or ZQW) and temperature range (for example, “Blank” is the default temperature
range). Figure 4−1 provides a legend for reading the complete device name for the TMS320UC5405 device.
For device part numbers and further ordering information for TMS320UC5405 in the GQW and ZQW package
types, see the TI website (http://www.ti.com) or contact your TI sales representative.
TMS320 is a trademark of Texas Instruments.
39
October 2002 − Revised October 2004
SPRS199B
Device and Development-Support Tool Nomenclature
5405
TMS 320 UC
GQW
(
)
(R)
PREFIX
PACKAGING
TMX= Experimental device
TMP= Prototype device
TMS= Qualified device
R = Tape and Reel
TEMPERATURE RANGE
Blank = −40°C TO 100°C (default)
DEVICE FAMILY
320 = TMS320 Family
†
PACKAGE TYPE
GQW = 143-pin plastic PBGA
ZQW = 143-pin plastic BGA with Pb-free soldered balls
TECHNOLOGY
C = CMOS
E
F
=
=
CMOS EPROM
CMOS Flash EEPROM
‡
DEVICE
LC = Low-Voltage CMOS (3.3 V)
C54x DSP:
5405
VC= Low Voltage CMOS [3 V (2.5 V Core)]
UC= Ultra-Low Voltage CMOS [1.8-V to 3.6-V I/O (1.8-v Core)]
†
BGA = Ball Grid Array
For actual part numbers (P/Ns) and ordering information, see the TI website (www.ti.com).
‡
Figure 4−1. TMS320UC5405 DSP Device Nomenclature
40
SPRS199B
October 2002 − Revised October 2004
Documentation Support
5
Documentation Support
Extensive documentation supports all TMS320 DSP family of devices from product announcement through
applications development. The following types of documentation are available to support the design and use
of the C5000 platform of DSPs:
•
•
•
•
•
TMS320C54x DSP Functional Overview (literature number SPRU307)
Device-specific data sheets
Complete user’s guides
Development support tools
Hardware and software application reports
The five-volume TMS320C54x DSP Reference Set consists of:
•
•
•
•
•
Volume 1: CPU and Peripherals (literature number SPRU131)
Volume 2: Mnemonic Instruction Set (literature number SPRU172)
Volume 3: Algebraic Instruction Set (literature number SPRU179)
Volume 4: Applications Guide (literature number SPRU173)
Volume 5: Enhanced Peripherals (literature number SPRU302)
The reference set describes in detail the TMS320C54x DSP products currently available and the hardware
and software applications, including algorithms, for fixed-point TMS320 DSP family of devices.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
TMS320 and C5000 are trademarks of Texas Instruments.
41
October 2002 − Revised October 2004
SPRS199B
Electrical Specifications
6
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320UC5405 DSP.
6.1 Absolute Maximum Ratings
The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond those
listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under Section 6.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to V . Figure 6−1 provides the test load circuit
SS
values for a 1.8-V device.
Supply voltage I/O range, DV
Supply voltage core range, CV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 2.0 V
DD
DD
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.5 V
I
Output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.5 V
O
Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 100°C
C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
stg
6.2 Recommended Operating Conditions
MIN
1.71
1.71
NOM
MAX
3.6
UNIT
V
DV
CV
Device supply voltage, I/O
Device supply voltage, core
DD
1.8
0
1.98
V
DD
V
SS
Supply voltage, GND
V
X2/CLKIN
1.35
1.35
CV + 0.3
DD
DV = 1.71 V to 1.89 V
DD
All other inputs
DV + 0.3
DD
X2/CLKIN
1.35
1.7
CV + 0.3
DD
DV = 1.90 V to 2.99 V
DD
All other inputs
X2/CLKIN
DV + 0.3
DD
1.35
CV + 0.3
DD
High-level input
voltage
V
IH
V
RS, INTn, NMI, BIO,
BCLKR0, BCLKR1, BCLKX0,
BCLKX1, HCS, HDS1,
HDS2, TDI, TMS, CLKMDn
2.2
DV + 0.3
DD
DV = 3.0 V to 3.6 V
DD
TCK, TRST
2.5
2
DV + 0.3
DD
All other inputs
DV + 0.3
DD
X2/CLKIN
−0.3
−0.3
0.6
0.6
DV = 1.71 V to 1.89 V
DD
All other inputs
X2/CLKIN
−0.3
−0.3
−0.3
0.6
0.6
0.8
Low-level input
voltage
RS, INTn, NMI, BIO,
V
IL
V
BCLKR0, BCLKR1, BCLKX0,
BCLKX1, HCS, HDS1,
HDS2, TCK, CLKMDn
DV = 1.90 V to 3.6 V
DD
All other inputs
I
High-level output current
Low-level output current
Operating case temperature
−300
1.5
µA
mA
°C
OH
I
OL
T
−40
100
C
42
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
6.3 Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted)
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
I
= MAX
DV − 0.3
V
High-level output voltage
OH
OH
DD
CLKOUT
0.4
DV = 1.71 to 1.89 V
I
I
= MAX
= MAX
DD
OL
Low-level output
voltage
All other outputs
All outputs
0.35
V
OL
DV = 1.9 to 3.6 V
0.4
DD
OL
Bus holders enabled, DV = MAX,
DD
Input current for
outputs in high
impedance
D[15:0], HD[7:0]
−175
175
V = V to DV
DD
I
SS
I
IZ
µA
All other inputs
X2/CLKIN
DV = MAX, V = V to DV
DD
−5
5
DD
O
SS
−40
40
TRST
With internal pulldown
With internal pulldown
−5
−5
300
300
HPIENA
Input current
(V = V
I SS
I
I
µA
With internal pullups,
HPIENA = 0
}
to DV
)
DD
TMS, TCK, TDI, HPI
−300
−5
5
5
All other input-only
pins
w
CV = 1.8 V, f
= 80 MHz,
DD
clock
I
I
Supply current, core CPU
35
mA
mA
DDC
T
= 25°C
C
DV = 1.71 to
1.89 V
DD
12
27
w
f
= 80 MHz,
= 25°C
clock
Supply current, pins
DDP
T
C
DV = 1.9 to
DD
3.6 V
IDLE2
PLL × 1 mode, 80 MHz input
1.6
20
mA
Supply current,
standby
I
DD
IDLE3
Divide-by-two mode, CLKIN stopped
µA
C
C
Input capacitance
Output capacitance
5
5
pF
pF
i
o
†
‡
§
All values are typical unless otherwise specified.
HPI input signals except for HPIENA.
Clock mode: PLL × 1 with external source
I
OL
50 Ω
Output
Under
Test
Tester Pin
Electronics
V
Load
C
T
I
OH
Where:
I
I
= 1.5 mA (all outputs)
= 300 µA (all outputs)
= 0.855 V
OL
OH
V
Load
C
= 40 pF typical load circuit capacitance
T
Figure 6−1. 1.8-V Test Load Circuit
43
October 2002 − Revised October 2004
SPRS199B
Electrical Specifications
6.4 Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created
in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related
terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
L
High
c
cycle time (period)
delay time
Low
d
V
Z
Valid
dis
en
f
disable time
High impedance
enable time
fall time
h
hold time
r
rise time
su
t
setup time
transition time
valid time
v
w
X
pulse duration (width)
Unknown, changing, or don’t care level
44
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
6.5 Clock Options
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four or
multiplied by one of several values to generate the internal machine cycle.
6.5.1 Internal Oscillator With External Crystal
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT
is a multiple of the oscillator frequency. The multiply ratio is determined by the bit settings in the CLKMD
register. The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series
resistance of 30 Ω and power dissipation of 1 mW. The circuit shown in Figure 6−2 represents
fundamental-mode operation.
The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in Figure 6−2.
The load capacitors, C and C , should be chosen such that the equation below is satisfied. C in the equation
1
2
L
is the load specified for the crystal.
C1C2
(C1 ) C2)
CL +
MIN
MAX
UNIT
f
Input clock frequency
10
20
MHz
clock
X1
X2/CLKIN
Crystal
C1
C2
Figure 6−2. Internal Oscillator With External Crystal
45
October 2002 − Revised October 2004
SPRS199B
Electrical Specifications
6.5.2 Divide-By-Two Clock Option (PLL disabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two to generate
the internal machine cycle. The selection of the clock mode is described in the clock generator section.
When an external clock source is used, the external frequency injected must conform to specifications listed
in Table 6−1.
NOTE: If an external clock source is used, the CLKIN signal level should not exceed CV + 0.3 V.
DD
Table 6−1 and Table 6−2 assume testing over recommended operating conditions and H = 0.5t
Figure 6−3).
(see
c(CO)
Table 6−1. Divide-By-2 and Divide-by-4 Clock Options Timing Requirements
MIN
MAX
UNIT
†
t
t
t
Cycle time, X2/CLKIN
Fall time, X2/CLKIN
Rise time, X2/CLKIN
6.25
ns
ns
ns
c(CI)
f(CI)
r(CI)
8
8
†
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz.
approaching ∞. The device is characterized at frequencies
c(CI)
Table 6−2. Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
ns
‡
†
t
Cycle time, CLKOUT
12.5
2t
c(CI)
c(CO)
t
Delay time, X2/CLKIN high to CLKOUT high/low
Fall time, CLKOUT
7
12
20
ns
d(CIH-CO)
t
4
4
ns
f(CO)
t
t
t
Rise time, CLKOUT
ns
r(CO)
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
H−2
H−2
H + 2
H + 2
ns
w(COL)
w(COH)
ns
†
‡
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz.
It is recommended that the PLL clocking option be used for maximum frequency operation.
approaching ∞. The device is characterized at frequencies
c(CI)
t
r(CI)
t
f(CI)
t
c(CI)
X2/CLKIN
CLKOUT
t
w(COH)
t
f(CO)
t
c(CO)
t
r(CO)
t
d(CIH-CO)
t
w(COL)
Figure 6−3. External Divide-by-Two Clock Timing
46
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
6.5.3 Multiply-By-N Clock Option (PLL Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to
generate the internal machine cycle. The selection of the clock mode and the value of N is described in the
clock generator section.
When an external clock source is used, the external frequency injected must conform to specifications listed
in Table 6−3.
NOTE: If an external clock source is used, the CLKIN signal level should not exceed CV + 0.3 V.
DD
Table 6−3 and Table 6−4 assume testing over recommended operating conditions and H = 0.5t
Figure 6−4).
(see
c(CO)
†
Table 6−3. Multiply-By-N Clock Option Timing Requirements
MIN
MAX
UNIT
Integer PLL multiplier N (N = 1−15)
PLL multiplier N = x.5
12.5N 400N
12.5N 200N
12.5N 100N
t
Cycle time, X2/CLKIN
ns
c(CI)
PLL multiplier N = x.25, x.75
t
t
Fall time, X2/CLKIN
Rise time, X2/CLKIN
8
8
ns
ns
f(CI)
r(CI)
†
N = Multiplication factor
Table 6−4. Multiply-By-N Clock Option Switching Characteristics
PARAMETER
MIN
12.5
7
TYP
MAX
UNIT
ns
†
t
Cycle time, CLKOUT
t
c(CI)/N
c(CO)
t
Delay time, X2/CLKIN high/low to CLKOUT high/low
Fall time, CLKOUT
10
20
ns
d(CI-CO)
t
4
4
ns
f(CO)
r(CO)
w(COL)
w(COH)
p
t
t
t
t
Rise time, CLKOUT
ns
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
Transitory phase, PLL lock up time
H−2
H−2
H + 2
H + 2
30
ns
ns
ms
†
N = Multiplication factor
t
f(CI)
t
r(CI)
t
c(CI)
X2/CLKIN
t
d(CI-CO)
t
f(CO)
t
w(COH)
t
c(CO)
t
w(COL)
t
tp
r(CO)
Unstable
CLKOUT
Figure 6−4. External Multiply-by-One Clock Timing
47
October 2002 − Revised October 2004
SPRS199B
Electrical Specifications
6.6 Memory and Parallel I/O Interface Timing
6.6.1 Memory Read
Table 6−5 and Table 6−6 assume testing over recommended operating conditions with MSTRB = 0 and
H = 0.5t
(see Figure 6−5).
c(CO)
†
Table 6−5. Memory Read Timing Requirements
MIN
MAX
2H−14
2H−14
UNIT
ns
t
t
t
t
t
t
Access time, read data access from address valid
Access time, read data access from MSTRB low
Setup time, read data before CLKOUT low
Hold time, read data after CLKOUT low
a(A)M
ns
a(MSTRBL)
su(D)R
7
0
0
0
ns
ns
h(D)R
Hold time, read data after address invalid
Hold time, read data after MSTRB high
ns
h(A-D)R
ns
h(D)MSTRBH
†
Address, PS, and DS timings are all included in timings referenced as address.
†
Table 6−6. Memory Read Switching Characteristics
PARAMETER
MIN
0
MAX
UNIT
ns
‡
t
Delay time, CLKOUT low to address valid
8
8
8
7
5
d(CLKL-A)
t
Delay time, CLKOUT low to MSTRB low
Delay time, CLKOUT low to MSTRB high
Hold time, address valid after CLKOUT low
0
ns
d(CLKL-MSL)
t
0
ns
d(CLKL-MSH)
‡
t
0
ns
h(CLKL-A)R
h(CLKH-A)R
§
t
Hold time, address valid after CLKOUT high
0
ns
†
‡
§
Address, PS, and DS timings are all included in timings referenced as address.
In the case of a memory read preceded by a memory read
In the case of a memory read preceded by a memory write
48
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
CLKOUT
t
d(CLKL-A)
t
h(CLKL-A)R
A[5:0]
t
h(A-D)R
t
su(D)R
t
a(A)M
t
h(D)R
D[15:0]
t
h(D)MSTRBH
t
d(CLKL-MSL)
t
d(CLKL-MSH)
t
a(MSTRBL)
MSTRB
R/W
PS, DS
Figure 6−5. Memory Read
49
October 2002 − Revised October 2004
SPRS199B
Electrical Specifications
6.6.2 Memory Write
Table 6−7 assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5t
(see
c(CO)
Figure 6−6).
†
Table 6−7. Memory Write Switching Characteristics
PARAMETER
MIN
MAX
UNIT
‡
t
t
Delay time, CLKOUT high to address valid
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(CLKH-A)
§
Delay time, CLKOUT low to address valid
Delay time, CLKOUT low to MSTRB low
Delay time, CLKOUT low to data valid
Delay time, CLKOUT low to MSTRB high
Delay time, CLKOUT high to R/W low
Delay time, CLKOUT high to R/W high
Delay time, R/W low to MSTRB low
0
0
8
d(CLKL-A)
t
8
d(CLKL-MSL)
t
0
17
d(CLKL-D)W
t
0
8
d(CLKL-MSH)
t
−1
−2
H − 4
0
5
5
d(CLKH-RWL)
t
d(CLKH-RWH)
t
H + 2
5
d(RWL-MSTRBL)
‡
t
Hold time, address valid after CLKOUT high
h(A)W
t
t
t
t
Hold time, write data valid after MSTRB high
Pulse duration, MSTRB low
H−3 H+14
2H−5
h(D)MSH
w(SL)MS
su(A)W
Setup time, address valid before MSTRB low
Setup time, write data valid before MSTRB high
2H−4
2H−14 2H+5
su(D)MSH
t
t
Enable time, data bus driven from R/W low
H−5
ns
ns
en(D−RWL)
Disable time, data bus high impedance from R/W high
0
dis(RWH−D)
†
‡
§
Address, PS, and DS timings are all included in timings referenced as address.
In the case of a memory write preceded by a memory write
In the case of a memory write preceded by an I/O cycle
50
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
CLKOUT
A[5:0]
t
d(CLKH-A)
t
d(CLKL-A)
t
h(A)W
t
d(CLKL-D)W
t
h(D)MSH
t
su(D)MSH
D[15:0]
MSTRB
R/W
t
d(CLKL-MSL)
t
dis(RWH-D)
t
d(CLKL-MSH)
t
su(A)W
t
t
d(CLKH-RWL)
d(CLKH-RWH)
t
t
w(SL)MS
en(D-RWL)
t
d(RWL-MSTRBL)
PS, DS
Figure 6−6. Memory Write
51
October 2002 − Revised October 2004
SPRS199B
Electrical Specifications
6.6.3 I/O Read
Table 6−8 and Table 6−9 assume testing over recommended operating conditions, IOSTRB = 0, and
H = 0.5t (see Figure 6−7).
c(CO)
Table 6−8. I/O Read Timing Requirements
MIN
MAX
3H−17
3H−17
UNIT
ns
†
t
t
t
t
t
Access time, read data access from address valid
a(A)IO
Access time, read data access from IOSTRB low
Setup time, read data before CLKOUT high
Hold time, read data after CLKOUT high
Hold time, read data after IOSTRB high
ns
a(ISTRBL)IO
su(D)IOR
9
0
0
ns
ns
h(D)IOR
ns
h(ISTRBH-D)R
†
Address and IS timings are included in timings referenced as address.
Table 6−9. I/O Read Switching Characteristics
PARAMETER
MIN
0
MAX
UNIT
ns
†
t
Delay time, CLKOUT low to address valid
8
5
5
8
d(CLKL-A)
t
Delay time, CLKOUT high to IOSTRB low
Delay time, CLKOUT high to IOSTRB high
−2
−2
0
ns
d(CLKH-ISTRBL)
t
ns
d(CLKH-ISTRBH)
†
t
Hold time, address after CLKOUT low
ns
h(A)IOR
†
Address and IS timings are included in timings referenced as address.
CLKOUT
t
t
h(A)IOR
d(CLKL-A)
A[5:0]
t
h(D)IOR
t
su(D)IOR
t
a(A)IO
D[15:0]
t
h(ISTRBH-D)R
t
a(ISTRBL)IO
t
d(CLKH-ISTRBH)
t
d(CLKH-ISTRBL)
IOSTRB
R/W
IS
Figure 6−7. Parallel I/O Port Read
52
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
6.6.4 I/O Write
Table 6−10 assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5t
(see
c(CO)
Figure 6−8).
Table 6−10. I/O Write Switching Characteristics
PARAMETER
MIN MAX
UNIT
†
t
Delay time, CLKOUT low to address valid
0
8
5
ns
ns
ns
ns
ns
ns
d(CLKL-A)
t
Delay time, CLKOUT high to IOSTRB low
Delay time, CLKOUT high to write data valid
Delay time, CLKOUT high to IOSTRB high
Delay time, CLKOUT low to R/W low
Delay time, CLKOUT low to R/W high
−2
d(CLKH-ISTRBL)
t
H−5 H+14
d(CLKH-D)IOW
t
−2
0
5
8
8
d(CLKH-ISTRBH)
t
d(CLKL-RWL)
d(CLKL-RWH)
t
t
t
t
t
0
†
Hold time, address valid after CLKOUT low
0
8
ns
ns
ns
ns
h(A)IOW
Hold time, write data after IOSTRB high
Setup time, write data before IOSTRB high
Setup time, address valid before IOSTRB low
H−3 H+11
h(D)IOW
H−11
H−2
H+1
H+2
su(D)IOSTRBH
su(A)IOSTRBL
†
†
Address and IS timings are included in timings referenced as address.
CLKOUT
t
su(A)IOSTRBL
t
h(A)IOW
t
d(CLKL-A)
A[5:0]
t
d(CLKH-D)IOW
t
h(D)IOW
D[15:0]
t
d(CLKH-ISTRBL)
t
d(CLKH-ISTRBH)
t
su(D)IOSTRBH
IOSTRB
R/W
t
t
d(CLKL-RWH)
d(CLKL-RWL)
IS
Figure 6−8. Parallel I/O Port Write
53
October 2002 − Revised October 2004
SPRS199B
Electrical Specifications
6.7 Ready Timing for Externally Generated Wait States
Table 6−11 assumes testing over recommended operating conditions and H = 0.5t
through Figure 6−12).
(see Figure 6−9
c(CO)
†
Table 6−11. Ready Timing Requirements for Externally Generated Wait States
MIN
MAX
UNIT
ns
t
t
t
t
t
t
Setup time, READY before CLKOUT low
Hold time, READY after CLKOUT low
7
su(RDY)
−2
ns
h(RDY)
‡
Valid time, READY after MSTRB low
4H−11
5H−11
ns
v(RDY)MSTRB
h(RDY)MSTRB
v(RDY)IOSTRB
h(RDY)IOSTRB
‡
Hold time, READY after MSTRB low
4H−4
5H−3
ns
‡
Valid time, READY after IOSTRB low
ns
‡
Hold time, READY after IOSTRB low
ns
†
‡
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
CLKOUT
A[5:0]
t
su(RDY)
t
h(RDY)
READY
MSTRB
t
v(RDY)MSTRB
t
h(RDY)MSTRB
Wait State
Generated
by READY
Wait States
Generated Internally
Figure 6−9. Memory Read With Externally Generated Wait States
54
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
CLKOUT
A[5:0]
D[15:0]
READY
MSTRB
t
h(RDY)
t
su(RDY)
t
v(RDY)MSTRB
t
h(RDY)MSTRB
Wait States
Generated Internally
Wait State Generated
by READY
Figure 6−10. Memory Write With Externally Generated Wait States
CLKOUT
A[5:0]
READY
IOSTRB
t
h(RDY)
t
su(RDY)
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
Wait State Generated
by READY
Wait
States
Generated
Internally
Figure 6−11. I/O Read With Externally Generated Wait States
55
October 2002 − Revised October 2004
SPRS199B
Electrical Specifications
CLKOUT
A[5:0]
D[15:0]
READY
t
h(RDY)
t
su(RDY)
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
IOSTRB
Wait State Generated
by READY
Wait States
Generated
Internally
Figure 6−12. I/O Write With Externally Generated Wait States
56
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
6.8 HOLD and HOLDA Timings
Table 6−12 and Table 6−13 assume testing over recommended operating conditions and H = 0.5t
Figure 6−13).
(see
c(CO)
Table 6−12. HOLD and HOLDA Timing Requirements
MIN
4H+7
7
MAX
UNIT
t
t
Pulse duration, HOLD low
ns
ns
w(HOLD)
Setup time, HOLD low/high before CLKOUT low
su(HOLD)
Table 6−13. HOLD and HOLDA Switching Characteristics
PARAMETER
MIN
MAX
3
UNIT
ns
t
t
t
t
t
t
Disable time, address, PS, DS, IS high impedance from CLKOUT low
Disable time, R/W high impedance from CLKOUT low
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low
Enable time, address, PS, DS, IS from CLKOUT low
Enable time, R/W enabled from CLKOUT low
dis(CLKL-A)
dis(CLKL-RW)
dis(CLKL-S)
en(CLKL-A)
en(CLKL-RW)
en(CLKL-S)
3
ns
3
ns
2H+7
2H+7
2H+7
ns
ns
Enable time, MSTRB, IOSTRB enabled from CLKOUT low
ns
0
0
8
8
ns
ns
ns
Valid time, HOLDA low after CLKOUT low
t
t
v(HOLDA)
Valid time, HOLDA high after CLKOUT low
Pulse duration, HOLDA low duration
2H
w(HOLDA)
CLKOUT
t
t
su(HOLD)
su(HOLD)
t
w(HOLD)
HOLD
t
t
v(HOLDA)
v(HOLDA)
t
w(HOLDA)
HOLDA
t
dis(CLKL-A)
t
en(CLKL-A)
A[5:0]
PS, DS, IS
D[15:0]
R/W
t
t
t
t
dis(CLKL-RW)
dis(CLKL-S)
dis(CLKL-S)
en(CLKL-RW)
t
en(CLKL-S)
MSTRB
IOSTRB
t
en(CLKL-S)
Figure 6−13. HOLD and HOLDA Timings (HM = 1)
57
October 2002 − Revised October 2004
SPRS199B
Electrical Specifications
6.9 Reset, BIO, Interrupt, and MP/MC Timings
Table 6−14 assumes testing over recommended operating conditions and H = 0.5t
Figure 6−15, and Figure 6−16).
(see Figure 6−14,
c(CO)
Table 6−14. Reset, BIO, Interrupt, and MP/MC Timing Requirements
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Hold time, RS after CLKOUT low
Hold time, BIO after CLKOUT low
Hold time, INTn, NMI, after CLKOUT low
Hold time, MP/MC after CLKOUT low
0
−2
h(RS)
h(BIO)
†
−3
h(INT)
0
h(MPMC)
w(RSL)
‡§
Pulse duration, RS low
4H+5
2H+4
4H
2H−1
4H
2H+1
4H
8
Pulse duration, BIO low, synchronous
Pulse duration, BIO low, asynchronous
w(BIO)S
w(BIO)A
w(INTH)S
w(INTH)A
w(INTL)S
w(INTL)A
w(INTL)WKP
su(RS)
Pulse duration, INTn, NMI high (synchronous)
Pulse duration, INTn, NMI high (asynchronous)
Pulse duration, INTn, NMI low (synchronous)
Pulse duration, INTn, NMI low (asynchronous)
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
¶
Setup time, RS before X2/CLKIN low
5
Setup time, BIO before CLKOUT low
7
12
12
su(BIO)
Setup time, INTn, NMI, RS before CLKOUT low
Setup time, MP/MC before CLKOUT low
8
su(INT)
10
su(MPMC)
†
‡
The external interrupts (INT0−INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is
corresponding to three CLKOUT sampling sequences.
If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure synchronization
and lock-in of the PLL.
§
¶
Note that RS may cause a change in clock frequency, therefore changing the value of H.
Divide-by-two mode
X2/CLKIN
t
su(RS)
t
w(RSL)
RS, INTn, NMI
CLKOUT
BIO
t
su(INT)
t
h(RS)
t
su(BIO)
t
h(BIO)
t
w(BIO)S
Figure 6−14. Reset and BIO Timings
58
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
CLKOUT
t
t
su(INT)
t
h(INT)
su(INT)
INTn, NMI
t
w(INTH)A
t
w(INTL)A
Figure 6−15. Interrupt Timing
CLKOUT
RS
t
h(MPMC)
t
su(MPMC)
MP/MC
Figure 6−16. MP/MC Timing
59
October 2002 − Revised October 2004
SPRS199B
Electrical Specifications
6.10 Interrupt Acknowledge (IACK) Timings
Table 6−15 assumes testing over recommended operating conditions and H = 0.5t
(see Figure 6−17).
c(CO)
Table 6−15. Interrupt Acknowledge (IACK) Switching Characteristics
PARAMETER
Delay time, CLKOUT low to IACK low
Delay time , CLKOUT low to IACK high
Delay time, address valid to IACK low
Hold time, IACK high after address invalid
MIN
0
MAX
UNIT
ns
t
9
6
2
d(CLKL-IACKL)
t
t
t
t
1
ns
d(CLKL-IACKH)
d(A)IACK
ns
−2
ns
h(A)IACK
Pulse duration, IACK low
2H−1
ns
w(IACKL)
CLKOUT
A[5:0]
t
t
d(CLKL-IACKH)
d(CLKL-IACKL)
t
h(A)IACK
t
d(A)IACK
t
w(IACKL)
IACK
MSTRB
Figure 6−17. IACK Timings
60
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
6.11 External Flag (XF) and TOUT Timings
Table 6−16 assumes testing over recommended operating conditions and H = 0.5t
Figure 6−19).
(see Figure 6−18 and
c(CO)
Table 6−16. External Flag (XF) and TOUT Switching Characteristics
PARAMETER
MIN
−1
MAX
UNIT
Delay time, CLKOUT low to XF high
8
8
t
ns
d(XF)
Delay time, CLKOUT low to XF low
−1
t
t
t
Delay time, CLKOUT low to TOUT high
Delay time, CLKOUT low to TOUT low
Pulse duration, TOUT
0
0
11
9
ns
ns
ns
d(TOUTH)
d(TOUTL)
w(TOUT)
2H−1
CLKOUT
t
d(XF)
XF
Figure 6−18. XF Timing
CLKOUT
TOUT
t
t
d(TOUTL)
d(TOUTH)
t
w(TOUT)
Figure 6−19. TOUT Timing
61
October 2002 − Revised October 2004
SPRS199B
Electrical Specifications
6.12 Multichannel Buffered Serial Port (McBSP) Timing
6.12.1 McBSP Transmit and Receive Timings
Table 6−17 and Table 6−18 assume testing over recommended operating conditions and H = 0.5t
Figure 6−20 and Figure 6−21).
(see
c(CO)
†
Table 6−17. McBSP Transmit and Receive Timing Requirements
MIN
4H
2H−1
20
0
MAX UNIT
t
t
Cycle time, BCLKR/X
BCLKR/X ext
BCLKR/X ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKR/X ext
BCLKR/X ext
ns
ns
c(BCKRX)
Pulse duration, BCLKR/X high or BCLKR/X low
w(BCKRX)
t
t
t
t
t
t
Setup time, external BFSR high before BCLKR low
Hold time, external BFSR high after BCLKR low
Setup time, BDR valid before BCLKR low
ns
ns
ns
ns
ns
ns
su(BFRH-BCKRL)
h(BCKRL-BFRH)
su(BDRV-BCKRL)
h(BCKRL-BDRV)
su(BFXH-BCKXL)
h(BCKXL-BFXH)
−3
4
17
0
0
Hold time, BDR valid after BCLKR low
8
20
0
Setup time, external BFSX high before BCLKX low
Hold time, external BFSX high after BCLKX low
−4
5
t
t
Rise time, BCLKR/X
Fall time, BCLKR/X
8
8
ns
ns
r(BCKRX)
f(BCKRX)
†
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
62
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
†
Table 6−18. McBSP Transmit and Receive Switching Characteristics
PARAMETER
MIN
MAX UNIT
t
t
Cycle time, BCLKR/X
BCLKR/X int
BCLKR/X int
4H
ns
c(BCKRX)
‡
‡
Pulse duration, BCLKR/X high
Pulse duration, BCLKR/X low
D − 3
D + 2
ns
w(BCKRXH)
‡
‡
t
BCLKR/X int
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
C − 3
C + 2
ns
ns
ns
w(BCKRXL)
−3
7
6
13
6
t
Delay time, BCLKR high to internal BFSR valid
Delay time, BCLKX high to internal BFSX valid
d(BCKRH-BFRV)
0
t
t
t
ns
ns
ns
d(BCKXH-BFXV)
dis(BCKXH-BDXHZ)
d(BCKXH-BDXV)
5
19
6
1
Disable time, BCLKX high to BDX high impedance following last data
bit of transfer
7
13
6
¶
0
§
Delay time, BCLKX high to BDX valid
Delay time, BFSX high to BDX valid
DXENA = 0
5
19
¶
BFSX int
BFSX ext
1
2
t
ns
d(BFXH-BDXV)
7
18
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
†
‡
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
T = BCLKRX period = (1 + CLKGDV) * 2H
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
The transmit delay enable (DXENA) and A-bis mode (ABIS) features of the McBSP are not implemented on the TMS320UC5405.
Minimum delay times also represent minimum output hold times.
§
¶
63
October 2002 − Revised October 2004
SPRS199B
Electrical Specifications
t
t
t
c(BCKRX)
w(BCKRXH)
w(BCKRXL)
t
r(BCKRX)
BCLKR
t
d(BCKRH−BFRV)
t
t
r(BCKRX)
d(BCKRH−BFRV)
BFSR (int)
BFSR (ext)
t
su(BFRH−BCKRL)
t
h(BCKRL−BFRH)
t
h(BCKRL−BDRV)
t
su(BDRV−BCKRL)
BDR
(RDATDLY=00b)
Bit (n−1)
(n−2)
(n−3)
(n−4)
t
su(BDRV−BCKRL)
t
h(BCKRL−BDRV)
BDR
(RDATDLY=01b)
Bit (n−1)
(n−2)
(n−3)
t
su(BDRV−BCKRL)
t
h(BCKRL−BDRV)
BDR
(RDATDLY=10b)
Bit (n−1)
(n−2)
Figure 6−20. McBSP Receive Timings
t
t
c(BCKRX)
w(BCKRXH)
t
r(BCKRX)
t
f(BCKRX)
t
w(BCKRXL)
BCLKX
BFSX (int)
BFSX (ext)
t
d(BCKXH−BFXV)
t
d(BCKXH−BFXV)
t
su(BFXH−BCKXL)
t
h(BCKXL−BFXH)
t
d(BFXH−BDXV)
t
t
d(BCKXH−BDXV)
BDX
Bit 0
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−4)
(n−3)
(n−2)
(XDATDLY=00b)
d(BCKXH−BDXV)
BDX
(XDATDLY=01b)
Bit (n−1)
(n−2)
t
t
d(BCKXH−BDXV)
dis(BCKXH−BDXHZ)
BDX
(XDATDLY=10b)
Bit 0
Bit (n−1)
Figure 6−21. McBSP Transmit Timings
64
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
6.12.2 McBSP General-Purpose I/O Timing
Table 6−19 and Table 6−20 assume testing over recommended operating conditions (see Figure 6−22).
Table 6−19. McBSP General-Purpose I/O Timing Requirements
MIN
9
MAX UNIT
†
t
t
Setup time, BGPIOx input mode before CLKOUT high
ns
ns
su(BGPIO-COH)
†
Hold time, BGPIOx input mode after CLKOUT high
0
h(COH-BGPIO)
†
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
Table 6−20. McBSP General-Purpose I/O Switching Characteristics
PARAMETER
MIN
MAX UNIT
‡
t
Delay time, CLKOUT high to BGPIOx output mode
0
5
ns
d(COH-BGPIO)
‡
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
t
t
d(COH-BGPIO)
su(BGPIO-COH)
CLKOUT
t
h(COH-BGPIO)
BGPIOx Input
†
mode
BGPIOx Output
‡
mode
†
‡
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
Figure 6−22. McBSP General-Purpose I/O Timings
65
October 2002 − Revised October 2004
SPRS199B
Electrical Specifications
6.12.3 McBSP as SPI Master or Slave Timing
Table 6−21 to Table 6−28 assume testing over recommended operating conditions and H = 0.5t
Figure 6−23, Figure 6−24, Figure 6−25, and Figure 6−26).
(see
c(CO)
†
Table 6−21. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
MASTER
SLAVE
MIN MAX
UNIT
MIN
16
4
MAX
t
t
t
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
Setup time, BFSX low before BCLKX high
− 12H
12H + 5
10
ns
ns
ns
su(BDRV-BCKXL)
h(BCKXL-BDRV)
su(BFXL-BCKXH)
c(BCKX)
t
Cycle time, BCLKX
12H
32H
ns
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
†
Table 6−22. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
‡
MASTER
SLAVE
MIN MAX
PARAMETER
UNIT
MIN
MAX
§
t
t
t
Hold time, BFSX low after BCLKX low
T − 4 T + 5
C − 6 C + 4
ns
ns
ns
h(BCKXL-BFXL)
d(BFXL-BCKXH)
d(BCKXH-BDXV)
¶
Delay time, BFSX low to BCLKX high
Delay time, BCLKX high to BDX valid
−3
7
6H + 6 10H + 20
Disable time, BDX high impedance following last data bit from
BCLKX low
t
C − 2 C + 3
ns
dis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
t
t
2H+ 8
4H −3
6H + 21
8H + 21
ns
ns
dis(BFXH-BDXHZ)
Delay time, BFSX low to BDX valid
d(BFXL-BDXV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
§
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
¶
t
c(BCKX)
MSB
LSB
t
su(BFXL-BCKXH)
BCLKX
BFSX
t
h(BCKXL-BFXL)
t
d(BFXL-BCKXH)
t
dis(BFXH-BDXHZ)
t
d(BFXL-BDXV)
t
t
d(BCKXH-BDXV)
dis(BCKXL-BDXHZ)
BDX
BDR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCKXL)
t
h(BCKXL-BDRV)
Bit 0
(n-2)
(n-3)
(n-4)
Figure 6−23. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
66
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
†
Table 6−23. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
MASTER
SLAVE
MIN MAX
UNIT
MIN
16
4
MAX
t
t
t
t
Setup time, BDR valid before BCLKX high
Hold time, BDR valid after BCLKX high
Setup time, BFSX low before BCLKX high
Cycle time, BCLKX
− 12H
12H + 5
10
ns
ns
ns
ns
su(BDRV-BCKXH)
h(BCKXH-BDRV)
su(BFXL-BCKXH)
c(BCKX)
12H
32H
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
†
Table 6−24. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
‡
MASTER
SLAVE
MIN MAX
PARAMETER
UNIT
MIN
MAX
§
t
t
t
Hold time, BFSX low after BCLKX low
C −4 C + 5
T − 6 T + 4
ns
ns
ns
h(BCKXL-BFXL)
d(BFXL-BCKXH)
d(BCKXL-BDXV)
¶
Delay time, BFSX low to BCLKX high
Delay time, BCLKX low to BDX valid
−3
7
6H + 6 10H + 20
6H +7 10H + 21
Disable time, BDX high impedance following last data bit from
BCLKX low
t
0
6
ns
ns
dis(BCKXL-BDXHZ)
t
Delay time, BFSX low to BDX valid
D − 2 D + 4
4H −3
8H + 21
d(BFXL-BDXV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
§
¶
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
t
t
c(BCKX)
MSB
su(BFXL-BCKXH)
LSB
BCLKX
t
t
d(BFXL-BCKXH)
h(BCKXL-BFXL)
BFSX
t
t
t
d(BCKXL-BDXV)
d(BFXL-BDXV)
dis(BCKXL-BDXHZ)
BDX
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCKXH)
t
h(BCKXH-BDRV)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
Figure 6−24. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
67
October 2002 − Revised October 2004
SPRS199B
Electrical Specifications
†
Table 6−25. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
MASTER
SLAVE
MIN MAX
UNIT
MIN
16
4
MAX
t
t
t
t
Setup time, BDR valid before BCLKX high
Hold time, BDR valid after BCLKX high
Setup time, BFSX low before BCLKX low
Cycle time, BCLKX
− 12H
12H + 5
10
ns
ns
ns
ns
su(BDRV-BCKXH)
h(BCKXH-BDRV)
su(BFXL-BCKXL)
c(BCKX)
12H
32H
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
†
Table 6−26. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
‡
MASTER
SLAVE
MIN MAX
PARAMETER
UNIT
MIN
MAX
§
t
t
t
Hold time, BFSX low after BCLKX high
T − 4 T + 5
D − 6 D + 4
ns
ns
ns
h(BCKXH-BFXL)
d(BFXL-BCKXL)
d(BCKXL-BDXV)
¶
Delay time, BFSX low to BCLKX low
Delay time, BCLKX low to BDX valid
− 3
7
6H + 6 10H + 20
Disable time, BDX high impedance following last data bit from
BCLKX high
t
D − 2 D + 3
ns
dis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
t
t
2H + 7
4H − 3
6H + 21
8H + 21
ns
ns
dis(BFXH-BDXHZ)
Delay time, BFSX low to BDX valid
d(BFXL-BDXV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
§
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
¶
t
t
c(BCKX)
su(BFXL-BCKXL)
LSB
MSB
BCLKX
BFSX
t
h(BCKXH-BFXL)
t
d(BFXL-BCKXL)
t
t
d(BFXL-BDXV)
dis(BFXH-BDXHZ)
t
t
t
d(BCKXL-BDXV)
dis(BCKXH-BDXHZ)
BDX
BDR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCKXH)
h(BCKXH-BDRV)
(n-2)
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 6−25. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
68
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
†
Table 6−27. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
MASTER
SLAVE
MIN MAX
UNIT
MIN
16
4
MAX
t
t
t
t
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
Setup time, BFSX low before BCLKX low
Cycle time, BCLKX
− 12H
12H + 5
10
ns
ns
ns
ns
su(BDRV-BCKXL)
h(BCKXL-BDRV)
su(BFXL-BCKXL)
c(BCKX)
12H
32H
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
†
Table 6−28. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
‡
MASTER
SLAVE
MIN MAX
PARAMETER
UNIT
MIN
MAX
§
t
t
t
Hold time, BFSX low after BCLKX high
D − 4 D + 5
T − 6 T + 4
ns
ns
ns
h(BCKXH-BFXL)
d(BFXL-BCKXL)
d(BCKXH-BDXV)
¶
Delay time, BFSX low to BCLKX low
Delay time, BCLKX high to BDX valid
− 3
7
6H + 6 10H + 20
6H +7 10H + 21
Disable time, BDX high impedance following last data bit from
BCLKX high
t
0
6
ns
ns
dis(BCKXH-BDXHZ)
t
Delay time, BFSX low to BDX valid
C − 2 C + 4
4H − 3
8H + 21
d(BFXL-BDXV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
§
¶
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
t
t
su(BFXL-BCKXL)
c(BCKX)
MSB
LSB
BCLKX
t
t
h(BCKXH-BFXL)
d(BFXL-BCKXL)
BFSX
t
t
t
t
d(BCKXH-BDXV)
dis(BCKXH-BDXHZ)
d(BFXL-BDXV)
BDX
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
su(BDRV-BCKXL)
t
h(BCKXL-BDRV)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
Figure 6−26. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
69
October 2002 − Revised October 2004
SPRS199B
Electrical Specifications
6.13 Host-Port Interface Timing (HPI8)
Table 6−29 and Table 6−30 assume testing over recommended operating conditions and H = 0.5t
(see
c(CO)
Figure 6−27 through Figure 6−30). In the following tables, DS refers to the logical OR of HCS, HDS1, and
HDS2. HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). HAD stands for HCNTL0, HCNTL1,
and HR/W. GPIO refers to the HD pins when they are configured as general-purpose input/outputs.
NOTE: During all cycles, DS should not be driven high to complete the cycle until HRDY is
high. In the case of a read cycle, HDx should also be valid before rising DS.
Table 6−29. HPI8 Mode Timing Requirements
MIN
5
MAX
UNIT
ns
t
t
Setup time, HBIL valid before DS low
Hold time, HBIL valid after DS low
su(HBV-DSL)
6
ns
h(DSL-HBV)
t
t
t
t
t
t
t
Setup time, HAS low before DS low
5
ns
ns
ns
ns
ns
ns
ns
su(HSL-DSL)
Pulse duration, DS low
20
10
12
8
w(DSL)
Pulse duration, DS high
w(DSH)
Setup time, HDx valid before DS high, HPI write
Hold time, HDx valid after DS high, HPI write
su(HDV-DSH)
h(DSH-HDV)W
su(GPIO-COH)
h(GPIO-COH)
Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
Hold time, HDx input valid after CLKOUT high, HDx configured as general-purpose input
9
−3
70
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
Table 6−30. HPI8 Mode Switching Characteristics
PARAMETER
MIN
5
MAX
UNIT
t
Enable time, HD driven from DS low
21
ns
en(DSL-HD)
Case 1a: Memory accesses when
DMAC is active in 16-bit mode and
18H + 21 − t
w(DSH)
†
t
< 18H
w(DSH)
Case 1b: Memory accesses when
DMAC is active in 16-bit mode and
21
26H + 21 − t
21
†
t
≥ 18H
w(DSH)
Case 1c: Memory access when
DMAC is active in 32-bit mode and
w(DSH)
†
t
< 26H
Delay time, DS low to HDx valid for
first byte of an HPI read
w(DSH)
t
ns
d(DSL-HDV1)
Case 1d: Memory access when
DMAC is active in 32-bit mode and
†
t
≥ 26H
w(DSH)
Case 2a: Memory accesses when
10H + 21 − t
21
w(DSH)
†
†
DMAC is inactive and t
< 10H
w(DSH)
Case 2b: Memory accesses when
DMAC is inactive and t ≥ 10H
w(DSH)
Case 3: Register accesses
21
21
9
t
t
t
t
Delay time, DS low to HDx valid for second byte of an HPI read
Hold time, HDx valid after DS high, for a HPI read
Valid time, HDx valid after HRDY high
ns
ns
ns
ns
d(DSL-HDV2)
h(DSH-HDV)R
v(HYH-HDV)
d(DSH-HYL)
5
12
21
Delay time, DS high to HRDY low (see Note 1)
Case 1a: Memory accesses when
DMAC is active in 16-bit mode
18H + 21
26H + 21
10H + 21
ns
ns
†
Case 1b: Memory accesses when
†
DMAC is active in 32-bit mode
t
Delay time, DS high to HRDY high
d(DSH-HYH)
Case 2: Memory accesses when
†
DMAC is inactive
ns
Case 3: Write accesses to HPIC
register (see Note 2)
6H + 21
19
5
ns
ns
ns
t
t
t
Delay time, HCS low/high to HRDY low/high
Delay time, CLKOUT high to HRDY high
Delay time, CLKOUT high to HINT change
d(HCS-HRDY)
)
d(COH-HYH
5
d(COH-HTX)
d(COH-GPIO)
Delay time, CLKOUT high to HDx output change. HDx is configured as a
general-purpose output.
t
9
ns
NOTES: 1. The HRDY output is always high when the HCS input is high, regardless of DS timings.
2. This timing applies to the first byte of an access, when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes
to the HPIC occur asynchronously, and do not cause HRDY to be deasserted.
DMAC stands for direct memory access (DMA) controller. The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are
affected by DMAC activity.
†
71
October 2002 − Revised October 2004
SPRS199B
Electrical Specifications
Second Byte
First Byte
Second Byte
HAS
t
su(HBV-DSL)
t
su(HSL-DSL)
†
HAD
Valid
Valid
‡
t
su(HBV-DSL)
‡
t
h(DSL-HBV)
HBIL
HCS
t
w(DSH)
t
w(DSL)
HDS
t
d(DSH-HYH)
t
d(DSH-HYL)
HRDY
t
en(DSL-HD)
t
d(DSL-HDV2)
t
d(DSL-HDV1)
t
h(DSH-HDV)R
HD READ
Valid
Valid
Valid
t
su(HDV-DSH)
t
v(HYH-HDV)
t
h(DSH-HDV)W
HD WRITE
Valid
Valid
Valid
t
d(COH-HYH)
CLKOUT
†
HAD refers to HCNTL0, HCNTL1, and HR/W.
When HAS is not used (HAS always high)
‡
Figure 6−27. Using HDS to Control Accesses (HCS Always Low)
72
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
Second Byte
First Byte
Second Byte
HCS
HDS
t
d(HCS-HRDY)
HRDY
Figure 6−28. Using HCS to Control Accesses
CLKOUT
t
d(COH-HTX)
HINT
Figure 6−29. HINT Timing
CLKOUT
t
su(GPIO-COH)
t
h(GPIO-COH)
†
GPIOx Input Mode
t
d(COH-GPIO)
†
GPIOx Output Mode
†
GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O).
†
Figure 6−30. GPIOx Timings
73
October 2002 − Revised October 2004
SPRS199B
Mechanical Data
7
Mechanical Data
Table 7−1 and Table 7−2 show the thermal resistance characteristics for the GQW (PBGA) and ZQW (PBGA)
mechanical packages.
Table 7−1. Thermal Resistance Characteristics for GQW
PARAMETER
GQW PACKAGE
UNIT
†
R
36.24
°C/W
Θ
JA
JC
R
17.93
°C/W
Θ
†
Based on a JEDEC 2s2p-style (high-k) board with 0 linear feet per minute (lfm) airflow.
Table 7−2. Thermal Resistance Characteristics for ZQW
PARAMETER
ZQW PACKAGE
UNIT
†
R
36.24
°C/W
Θ
JA
JC
R
17.93
°C/W
Θ
†
Based on a JEDEC 2s2p-style (high-k) board with 0 linear feet per minute (lfm) airflow.
The following mechanical package diagram(s) reflect the most up-to-date mechanical data released for these
designated device(s).
74
SPRS199B
October 2002 − Revised October 2004
PACKAGE OPTION ADDENDUM
www.ti.com
29-Oct-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TMS320UC5405GQW
ACTIVE
BGA MI
CROSTA
R JUNI
OR
GQW
143
250
TBD
SNPB
Level-3-220C-168HR
TMS320UC5405ZQW
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQW
143
250
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
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