TMS320VC5409PGE [TI]
FIXED-POINT DIGITAL SIGNAL PROCESSOR; 定点数字信号处理器
| 型号： | TMS320VC5409PGE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 文件： | 总89页 (文件大小：903K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320VC5409 Fixed-Point
Digital Signal Processor
Data Manual
Literature Number: SPRS082E
April 1999 − Revised February 2004
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
IMPORTANT NOTICE
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and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
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Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
Revision History
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS082D device-specific data
sheet to make it an SPRS082E revision.
Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of the
specified release date with the following changes.
PAGE(S)
ADDITIONS/CHANGES/DELETIONS
NO.
All
Several
15
Reformatted document into data manual format.
Reformatted all register bit layouts.
Added CPU Core Section 3.1.
21
Added RAM/ROM security restrictions to Section 3.2.4, On-Chip Memory Security.
Replaced “CLKOUT cycle” with “CPU clock cycle” in Section 3.3.3, Hardware Timer.
Added TRAP/INTR NUMBER (K) column to Table 3−17.
Updated HOLDA description in Table 3−19.
30
40
43
49
Added Section 4.1, Device and Development Tool Support Nomenclature.
Updated GGU mechanical.
87
3
April 1999 − Revised February 2004
SPRS082E
Revision History
4
SPRS082E
April 1999 − Revised February 2004
Contents
Contents
Section
Page
1
2
TMS320VC5409 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
12
14
2.1
2.2
2.3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GGU Package Layout and Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PGE Package Layout and Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
17
19
20
20
21
21
21
22
22
23
23
26
30
30
32
39
40
42
3.1
CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1
3.1.2
3.1.3
Software Programmable Wait−State Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable Bank-Switching Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip ROM With Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Memory Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Relocatable Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Buffered Serial Ports (McBSPs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
3.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
5
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Device and Development Tool Support Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
49
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
50
50
51
52
53
54
55
55
57
59
60
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Oscillator with External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Divide-By-Two/Divide-By-Four Clock Option (PLL Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option (PLL Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory and Parallel I/O Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.1
5.7.2
5.7.3
5.7.4
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Port Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Port Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
April 1999 − Revised February 2004
SPRS082E
Contents
Section
Page
5.8
5.9
5.10
5.11
5.12
5.13
Ready Timing for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset, BIO, Interrupt, and MP/MC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings . . . . . . . . . . . . . . . . .
External Flag (XF) and TOUT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
65
66
68
69
70
70
73
74
78
78
82
86
5.13.1
5.13.2
5.13.3
McBSP Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP as SPI Master or Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.14
5.15
Host-Port Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.14.1
5.14.2
HPI8 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI16 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
87
88
6.1
6.2
Ball Grid Array Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Profile Quad Flatpack Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
SPRS082E
April 1999 − Revised February 2004
Figures
Page
List of Figures
Figure
2−1
2−2
GGU Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PGE Package (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
14
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
3−9
TMS320VC5409 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] . . .
Software Wait-State Configuration Register (SWCR) [MMR Address 002Bh] . . . . . . . . . . . . . . . . .
Bank-Switching Control Register (BSCR) [MMR Address 0029h] . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5409 HPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Rate Generator Register 2 (SRGR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
16
17
17
20
23
24
26
29
34
41
3−10 TMS320VC5409 DMA Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 IFR and IMR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1
5−2
5−3
5−4
5−5
5−6
5−7
5−8
5−9
3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Divide-by-Two Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Multiply-by-One Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Port Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Port Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
52
53
54
56
58
59
60
61
62
63
64
65
67
67
67
68
69
69
72
72
73
5−10 Memory Write With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−11 I/O Read With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−12 I/O Write With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−13 HOLD and HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−14 Reset and BIO Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−15 Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−16 MP/MC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−17 IAQ and IACK Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−18 XF Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−19 TOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−20 McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−21 McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−22 McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
April 1999 − Revised February 2004
SPRS082E
Figures
Figure
Page
5−23 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . .
5−24 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . .
5−25 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . .
5−26 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . .
5−27 Using HDS to Control Accesses (HCS Always Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−28 Using HCS to Control Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−29 HRDY Relative to CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−30 HINT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−31 Nonmultiplexed Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−32 Nonmultiplexed Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−33 GPIOx Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
75
76
77
80
81
81
81
84
85
86
6−1
6−2
TMS320VC5416 144-Ball Plastic Ball Grid Array Package (GGU) . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320VC5416 144-Pin Low-Profile Quad Flatpack (PGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
88
8
SPRS082E
April 1999 − Revised February 2004
Tables
List of Tables
Table
Page
2−1
Pin Assignments for the GGU (144-Pin BGA Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
Software Wait-State Register (SWWSR) Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Wait-State Configuration Register (SWCR) Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank-Switching Control Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard On-Chip ROM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Holder Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Control Register (PCR) Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Rate Generator Clock Input Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Rate Generator Register 2 (SRGR2) Bit Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Control Registers and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mode Settings at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Channel Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IFR and IMR Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
17
18
19
21
25
27
29
29
30
31
36
36
37
37
39
40
41
42
3−9
3−10
3−11
3−12
3−13
3−14
3−15
3−16
3−17
3−18
3−19
5−1
5−2
5−3
5−4
5−5
5−6
5−7
5−8
Recommended Operating Conditions of Internal Oscillator With External Crystal . . . . . . . . . . . . .
Divide-By-Two/Divide-By-Four Clock Option (PLL Disabled) Timing Requirements . . . . . . . . . . . .
Divide-By-Two/Divide-By-Four Clock Option (PLL Disabled) Switching Characteristics . . . . . . . .
Multiply-By-N Clock Option (PLL Enabled) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option (PLL Enabled) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Read Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Port Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Port Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ready Timing Requirements for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . .
Ready Switching Characteristics for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset, BIO, Interrupt, and MP/MC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics . . . .
External Flag (XF) and TOUT Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Transmit and Receive Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Transmit and Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
53
53
54
54
55
55
57
59
59
60
61
61
65
65
66
68
69
70
71
73
73
5−9
5−10
5−11
5−12
5−13
5−14
5−15
5−16
5−17
5−18
5−19
5−20
5−21
5−22
9
April 1999 − Revised February 2004
SPRS082E
Tables
Table
Page
5−23
5−24
5−25
5−26
5−27
5−28
5−29
5−30
5−31
5−32
5−33
5−34
5−35
5−36
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . .
HPI8 Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI8 Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI16 Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI16 Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
74
75
75
76
76
77
77
78
79
82
83
86
86
6−1
6−2
Thermal Resistance Characteristics for 144-Ball GGU Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance Characteristics for 144-Ball PGE Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
88
10
SPRS082E
April 1999 − Revised February 2004
Features
1
TMS320VC5409 Features
D Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
D Arithmetic Instructions With Parallel Store
and Parallel Load
D Conditional Store Instructions
D Fast Return From Interrupt
D 40-Bit Arithmetic Logic Unit (ALU),
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
D On-Chip Peripherals
− Software-Programmable Wait-State
Generator and Programmable Bank
Switching
− On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
D 17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
D Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
− Three Multichannel Buffered Serial Ports
(McBSPs)
− Enhanced 8-Bit Parallel Host-Port
Interface With 16-Bit Data/Addressing
− One 16-Bit Timer
− Six-Channel Direct Memory Access
(DMA) Controller
D Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
D Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
D Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
D Data Bus With a Bus-Holder Feature
D Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program
Space
D CLKOUT Off Control to Disable CLKOUT
D On-Chip Scan-Based Emulation Logic,
†
IEEE Std 1149.1 (JTAG) Boundary Scan
D 16K x 16-Bit On-Chip ROM
Logic
D 32K x 16-Bit Dual-Access On-Chip RAM
D 12.5-ns Single-Cycle Fixed-Point
Instruction Execution Time (80 MIPS) for
3.3-V Power Supply (1.8-V Core)
D Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
D Block-Memory-Move Instructions for Better
D 10-ns Single-Cycle Fixed-Point Instruction
Execution Time (100 MIPS) for 3.3-V Power
Supply (1.8-V Core)
Program and Data Management
D Instructions With a 32-Bit Long Word
Operand
D Available in a 144-Pin Plastic Thin Quad
Flatpack (TQFP) (PGE Suffix) and a 144-Pin
Ball Grid Array (BGA) (GGU Suffix)
D Instructions With Two- or Three-Operand
Reads
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible
to damage because very small parametric changes could cause the device not to meet its published specifications.
All trademarks are the property of their respective owners.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
11
April 1999 − Revised February 2004
SPRS082E
Introduction
2
Introduction
The TMS320VC5409 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5409 unless
otherwise specified) is based on an advanced modified Harvard architecture that has one program memory
bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree
of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The
basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing
the high degree of parallelism. Two read operations and one write operation can be performed in a single cycle.
Instructions with parallel store and application-specific instructions can fully utilize this architecture. In
addition, data can be transferred between data and program spaces. Such parallelism supports a powerful
set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle.
In addition, the 5409 includes the control mechanisms to manage interrupts, repeated operations, and function
calls.
NOTE:This data manual is designed to be used in conjunction with the TMS320C54x DSP
Functional Overview (literature number SPRU307).
2.1 Pin Assignments
Figure 2−1 illustrates the ball number and location for the 144-pin GGU ball grid array. The pin assignments
in Table 2−1 lists each signal quadrant and BGA ball number for the TMS320VC5409GGU (144-pin BGA
package) which is footprint-compatible with the LC548, LC/VC549, and VC5410 devices.The DV pins in
DD
are the power supply for the I/O pins while CV is the power supply for the core CPU. V is the ground for
DD
SS
both the I/O pins and the core CPU.
Figure 2−2 illustrates the pin number, location, and signal name for the 144-pin PGE package type.
2.2 GGU Package Layout and Pin Assignments
13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
Figure 2−1. GGU Package (Bottom View)
TMS320C54x is a trademark of Texas Instruments.
12
SPRS082E
April 1999 − Revised February 2004
Introduction
Table 2−1. Pin Assignments for the GGU (144-Pin BGA Package)†
SIGNAL
QUADRANT 1
SIGNAL
QUADRANT 2
SIGNAL
QUADRANT 3
SIGNAL
QUADRANT 4
BGA BALL #
BGA BALL #
BGA BALL #
BGA BALL #
V
A1
B1
C2
C1
D4
D3
D2
D1
E4
E3
E2
E1
F4
F3
F2
F1
G2
G1
G3
G4
H1
H2
H3
H4
J1
BFSX1
BDX1
N13
M13
L12
L13
K10
K11
K12
K13
J10
J11
V
N1
N2
M3
N3
K4
A19
A20
A13
A12
B11
A11
D10
C10
B10
A10
D9
C9
B9
SS
SS
A22
BCLKR1
HCNTL0
V
DV
V
SS
SS
DD
DV
V
V
DV
DD
DD
SS
SS
A10
CLKMD1
CLKMD2
CLKMD3
HPI16
HD2
BCLKR0
BCLKR2
BFSR0
BFSR2
BDR0
D6
HD7
A11
A12
A13
A14
A15
L4
D7
D8
M4
N4
K5
D9
D10
D11
D12
HD4
D13
D14
D15
HD5
TOUT
EMU0
EMU1/OFF
TDO
HCNTL1
BDR2
L5
J12
J13
H10
H11
H12
H13
G12
G13
G11
G10
F13
F12
F11
F10
E13
E12
E11
E10
D13
D12
D11
C13
C12
C11
B13
B12
M5
N5
K6
CV
BCLKX0
BCLKX2
A9
DD
HAS
D8
C8
B8
V
V
TDI
V
L6
SS
SS
SS
TRST
HINT
CV
M6
N6
M7
N7
L7
CV
TCK
A8
DD
DD
HCS
HR/W
READY
PS
TMS
BFSX0
BFSX2
HRDY
CV
B7
DD
V
V
A7
SS
SS
CV
HDS1
C7
D7
A6
DD
HPIENA
DV
K7
V
SS
DD
DS
V
V
N8
M8
L8
HDS2
DV
SS
SS
IS
CLKOUT
HD3
X1
HD0
BDX0
BDX2
IACK
HBIL
NMI
B6
DD
R/W
A0
C6
D6
A5
MSTRB
IOSTRB
MSC
XF
K8
A1
A2
A3
HD6
A4
A5
A6
A7
A8
A9
X2/CLKIN
RS
N9
M9
L9
J2
B5
J3
D0
C5
D5
A4
HOLDA
IAQ
J4
D1
INT0
INT1
INT2
INT3
K9
K1
K2
K3
L1
D2
N10
M10
L10
N11
M11
L11
N12
M12
HOLD
BIO
D3
B4
D4
C4
A3
MP/MC
D5
CV
DD
DV
L2
A16
HD1
B3
DD
V
L3
V
V
CV
DD
C3
A2
SS
SS
SS
BDR1
M1
M2
A17
A18
BCLKX1
A21
BFSR1
V
V
B2
SS
SS
†
DV is the power supply for the I/O pins while CV is the power supply for the core CPU. V is the ground for both the I/O pins and the core
DD
DD
SS
CPU.
13
April 1999 − Revised February 2004
SPRS082E
Introduction
2.3 PGE Package Layout and Pin Assignments
V
A22
V
SS
1
108
107
106
105
104
103
102
101
100
99
A18
A17
2
SS
3
V
SS
DV
DD
4
A16
D5
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
A10
HD7
A11
A12
A13
A14
A15
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
CV
DD
97
HAS
96
V
V
SS
SS
DD
95
HD3
CLKOUT
94
CV
93
V
SS
HCS
HR/W
READY
PS
92
HPIENA
CV
91
DD
90
V
SS
89
TMS
TCK
TRST
TDI
DS
88
IS
87
R/W
86
MSTRB
IOSTRB
MSC
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
85
TDO
84
EMU1/OFF
EMU0
TOUT
HD2
HPI16
CLKMD3
CLKMD2
CLKMD1
83
82
81
80
79
78
77
76
V
DV
DD
SS
75
DV
DD
V
BDR1
BFSR1
SS
74
BDX1
BFSX1
73
NOTE: DV is the power supply for the I/O pins while CV is the power supply for the core CPU. V is the ground for both the I/O pins and
DD
DD
SS
the core CPU.
The TMS320VC5409PGE (144-pin TQFP) package is footprint-compatible with the LC548, LC/VC549, and
VC5410 devices.
Figure 2−2. PGE Package (Top View)
14
SPRS082E
April 1999 − Revised February 2004
Functional Overview
3
Functional Overview
The following functional overview is based on the block diagram in Figure 3−1.
P, C, D, E Buses and Control Signals
32K RAM
Dual Access
Program/Data
16K Program
54X cLEAD
ROM
MBus
GPIO
RHEA
Bridge
TI BUS
RHEA Bus
McBSP1
XIO
Enhanced XIO
McBSP2
McBSP3
HPI
HPI
xDMA
logic
RHEAbus
TIMER
APLL
JTAG
Clocks
Figure 3−1. TMS320VC5409 Functional Block Diagram
3.1 CPU Core
The TMS320VC5409 is based on the TMS320C54x (cLEAD v2) DSP core, and is completely code compatible
with other 54x products. The core includes the following features:
•
•
•
•
•
•
•
LEAD2 CPU
Software programmable wait-state generator with bank-switching wait-state logic
External memory interface
Program space
Data space
I/O space
Scan-based emulation logic
3.1.1 Software Programmable Wait−State Generator
The software wait-state generator of the 5409 is similar to that of the 5410 and it can extend external bus cycles
by up to fourteen machine cycles. Devices that require more than fourteen wait states can be interfaced using
the hardware READY line. When all external accesses are configured for zero wait states, the internal clocks
to the wait-state generator are automatically disabled. Disabling the wait-state generator clocks reduces the
power consumption of the 5409.
The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs
of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five
separate address ranges. This allows a different number of wait states for each of the five address ranges.
Additionally, the software wait-state multiplier (SWSM) bit of the system configuration register (SCR) defines
a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized to
provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 3−2
and described in Table 3−1.
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Functional Overview
15
14
6
12
11
3
9
8
XPA
I/O
DATA
DATA
R/W-0
R/W-111
R/W-111
7
5
2
0
DATA
R/W−111
PROGRAM
PROGRAM
R/W−111
R/W−111
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3−2. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
Table 3−1. Software Wait-State Register (SWWSR) Bit Fields
BIT
RESET
VALUE
FUNCTION
NO.
NAME
Extended program address control bit. XPA is used in conjunction with the program space fields
(bits 0 through 5) to select the address range for program space wait states.
15
XPA
0
1
I/O space. The field value (0−7) corresponds to the base number of wait states for I/O space accesses
within addresses 0000−FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for
the base number of wait states.
14−12
11−9
8−6
I/O
Upper data space. The field value (0−7) corresponds to the base number of wait states for external
data space accesses within addresses 8000−FFFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
Data
Data
1
1
Lower data space. The field value (0−7) corresponds to the base number of wait states for external
data space accesses within addresses 0000−7FFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
Upper program space. The field value (0−7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
-
-
XPA = 0: x8000 − xFFFFh
5−3
2−0
Program
Program
1
1
XPA = 1: The upper program space bit field has no effect on wait states.
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
Program space. The field value (0−7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
-
-
XPA = 0: x0000−x7FFFh
XPA = 1: 00000−FFFFFh
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
The software wait-state multiplier bit of the software wait-state configuration register is used to extend the base
number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 3−3 and described
in Table 3−2.
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Functional Overview
15
7
8
Reserved
R/W-0
1
0
Reserved
R/W-0
SWSM
R/W−0
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3−3. Software Wait-State Configuration Register (SWCR) [MMR Address 002Bh]
Table 3−2. Software Wait-State Configuration Register (SWCR) Bit Fields
PIN
RESET
VALUE
FUNCTION
These bits are reserved and are unaffected by writes.
NO.
NAME
15−1
Reserved
0
Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor
of 1 or 2.
0
SWSM
0
-
-
SWSM = 0: wait-state base values are unchanged (multiplied by 1).
SWSM = 1: wait-state base values are multiplied by 2 for a maximum of 14 wait states.
3.1.2 Programmable Bank-Switching Wait States
The programmable bank-switching logic of the 5409 is functionally equivalent to that of the 548/549 devices.
This feature automatically inserts one cycle when accesses cross memory-bank boundaries within program
or data memory space. A bank-switching wait state can also be automatically inserted when accesses cross
the data space boundary into program space.
The bank-switching control register (BSCR) defines the bank size for bank-switching wait-states. Figure 3−4
shows the BSCR and its bits are described in Table 3−3.
15
7
12
11
10
8
BNKCMP
R/W-1111
PS−DS
R/W−1
Reserved
R−0
3
2
1
0
Reserved
R−0
HBH
R/W-0
BH
EXIO
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3−4. Bank-Switching Control Register (BSCR) [MMR Address 0029h]
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Functional Overview
Table 3−3. Bank-Switching Control Register Fields
BIT
RESET
VALUE
FUNCTION
NO.
NAME
Bank compare. BNKCMP determines the external memory-bank size. BNKCMP is used to mask the four
MSBs of an address. For example, if BNKCMP = 1111b, the four MSBs (bits 12−15) are compared, resulting
in a bank size of 4K words. Bank sizes of 4K words to 64K words are allowed.
15−12 BNKCMP
1111
Program read − data read access. PS-DS inserts an extra cycle between consecutive accesses of program
read and data read or data read and program read.
11
PS-DS
1
0
PS-DS = 0
PS-DS = 1
No extra cycles are inserted by this feature.
One extra cycle is inserted between consecutive data and program reads.
10−3
Reserved
These bits are reserved and are unaffected by writes.
HPI bus holder. HBH controls the HPI bus holder feature. HBH is cleared to 0 at reset.
8-bit Mode
HBH = 0
HBH = 1
The bus holder is disabled for the HPI data bus (HD[7:0]).
The bus holders are enabled on HD[7:0]. When not driven, the HPI data bus (HD[7:0]) is held
in the previous logic level.
2
HBH
0
HPI bus holder. HBH controls the HPI bus holder feature. HBH is cleared to 0 at reset.
16-bit Mode
HBH = 0
The bus holder is disabled for the HPI address bus (HA[15:0]). The HPI GPIO pins (HD[7:0])
are held in the previous logic level.
HBH = 1
The bus holders are enabled on HA[15:0]. When not driven, the HPI address bus (A[15:0])
and HPI GPIO pins (HD[7:0]) are held in the previous logic level.
Bus holder. BH controls the data bus holder feature. BH is cleared to 0 at reset.
BH = 0
BH = 1
The bus holder is disabled.
The bus holder is enabled. When not driven, the data bus (D[15:0]) is held in the previous
logic level.
1
0
BH
0
0
External bus interface off. The EXIO bit controls the external bus-off function.
EXIO = 0
EXIO = 1
The external bus interface functions as usual.
The address bus, data bus, and control signals become inactive after completing the current
bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the HM bit of ST1
cannot be modified when the interface is disabled.
EXIO
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Functional Overview
3.1.3 CPU Memory-Mapped Registers
The 5409 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses 0h
to 1Fh.
Table 3−4. CPU Memory-Mapped Registers
ADDRESS
NAME
DESCRIPTION
DEC
0
HEX
0
IMR
IFR
–
Interrupt mask register
Interrupt flag register
Reserved for testing
Status register 0
1
1
2−5
6
2−5
6
ST0
ST1
AL
7
7
Status register 1
8
8
Accumulator A low word (15−0)
AH
9
9
Accumulator A high word (31−16)
Accumulator A guard bits (39−32)
Accumulator B low word (15−0)
Accumulator B high word (31−16)
Accumulator B guard bits (39−32)
Temporary register
AG
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
BL
B
BH
C
BG
D
TREG
TRN
AR0
AR1
AR2
AR3
AR4
AR5
AR6
AR7
SP
E
F
Transition register
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Auxiliary register 0
Auxiliary register 1
Auxiliary register 2
Auxiliary register 3
Auxiliary register 4
Auxiliary register 5
Auxiliary register 6
Auxiliary register 7
Stack pointer register
BK
Circular buffer size register
Block repeat counter
BRC
RSA
REA
PMST
XPC
–
Block repeat start address
Block repeat end address
Processor mode status (PMST) register
Extended program page register
Reserved
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3.2 Memory
The 5409 device provides both on-chip ROM and RAM memories to aid in system performance and
integration.
3.2.1 Memory Map
Page 0 Program
Page 0 Program
Data
Hex
0000
Hex
0000
Hex
0000
Memory-
Mapped
Registers
Reserved
(OVLY = 1)
External
(OVLY = 0)
Reserved
(OVLY = 1)
External
(OVLY = 0)
005F
0060
Scratch-Pad
RAM
007F
0080
007F
0080
007F
0080
On-Chip
On-Chip
†
†
On-Chip
DARAM
DARAM
†
DARAM
(OVLY = 1)
(OVLY = 1)
(32K words)
External
(OVLY = 0)
External
(OVLY = 0)
7FFF
8000
7FFF
8000
7FFF
8000
External
External
BFFF
C000
BFFF
C000
External
On-Chip ROM
(16K Words)
ROM
(DROM=1)
FEFF
FF00
or External
(DROM=0)
Reserved
FF7F
FF80
FF7F
FF80
FEFF
FF00
Reserved
(DROM=1)
or External
(DROM=0)
Interrupts
(On-Chip)
Interrupts
(External)
FFFF
FFFF
FFFF
MP/MC= 1
(Microprocessor Mode)
MP/MC= 0
(Microcomputer Mode)
†
DARAM0= 0060h − 1FFFh, DARAM1= 2000h − 3FFFh
DARAM2= 4000h − 5FFFh, DARAM3= 6000h − 7FFFh
Figure 3−5. Memory Map
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Functional Overview
3.2.2 On-Chip ROM With Bootloader
A bootloader is available in the standard 5409 on-chip ROM. This bootloader can be used to automatically
transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC
pin is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This
location contains a branch instruction to the start of the bootloader program. The standard 5409 bootloader
provides different ways to download the code to accommodate various system requirements:
•
•
•
•
•
Parallel from 8-bit or 16-bit-wide EPROM
Parallel from I/O space 8-bit or 16-bit mode
Serial boot from serial ports 8-bit or 16-bit mode
Host-port interface boot
SPI serial EEPROM 8-bit boot mode
The standard on-chip ROM layout is shown in Table 3−5.
Table 3−5. Standard On-Chip ROM Layout
†
ADDRESS RANGE
DESCRIPTION
0x0000h − 0xBFFFh External program space
0xC000h − 0xF7FFh Reserved
0xF800h − 0xFBFFh Bootloader
0xFC00h − 0xFEFFh Reserved
†
0xFF00h − 0xFF7Fh Reserved
0xFF80h − 0xFFFFh Interrupt vector table
†
In the VC5409 ROM, 128 words are reserved for factory device-testing purposes. Application
code to be implemented in on-chip ROM must reserve these 128 words at addresses
FF00h–FF7Fh in program space.
3.2.3 On-Chip RAM
The 5409 device contains 32K × 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed of
four blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and
a write in one cycle. The DARAM is located in the address range 0080h−7FFFh in data space, and can be
mapped into program/data space by setting the OVLY bit to one.
3.2.4 On-Chip Memory Security
The 5409 features a 16K-word × 16-bit on-chip maskable ROM.
Customers can arrange to have the ROM of the 5409 programmed with contents unique to any particular
application. A security option is available to protect a custom ROM. The ROM and ROM/RAM security options
are available on the 5409. These security options are described in the TMS320C54x DSP Reference Set,
Volume 1: CPU and Peripherals (literature number SPRU131). When the security options are enabled, JTAG
emulation is inhibited or nonfunctional.
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Functional Overview
3.2.5 Relocatable Interrupt Vector Table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch
instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate
interrupt service routine with minimal overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.
However, these vectors can be remapped to the beginning of any 128-word page in program space after
device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the
appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped
to the new 128-word page.
NOTE:The hardware reset (RS) vector cannot be remapped because a hardware reset loads
the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in program
space.
3.2.6 Extended Program Memory
The 5409 CPU uses a paged extended memory scheme in program space to allow access of up to 8M program
memory locations. In order to implement this scheme, the 5409 includes several features that are also present
on the 548/549 devices:
•
•
Twenty-three address lines, instead of sixteen
An extra memory-mapped register, the XPC register defines the page selection. This register is
memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.
Six extra instructions for addressing extended program space. These six instructions affect the XPC.
•
−
−
FB[D] pmad (23 bits) − Far branch
FBACC[D] Accu[22:0] − Far branch to the location specified by the value in accumulator A or
accumulator B
−
−
FCALL[D] pmad (23 bits) − Far call
FCALA[D] Accu[22:0] − Far call to the location specified by the value in accumulator A or
accumulator B
−
−
FRET[D] − Far return
FRETE[D] − Far return with interrupts enabled
•
In addition to these new instructions, two 54x instructions are extended to use 23 bits in the 5409:
−
−
READA data_memory (using 23-bit accumulator address)
WRITA data_memory (using 23-bit accumulator address)
All other instructions, software interrupts, and hardware interrupts do not modify the XPC register and access
only memory within the current page.
Program memory in the 5409 is organized into 127 pages that are each 64K in length, as shown in Figure 3−6.
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Functional Overview
00 0000
1 0000
2 0000
7F 0000
. . .
Page 0
Page 1
Lower
32K
Page 2
Lower
32K
Page 127
Lower
32K
†
64K
‡
‡
‡
External
External
External
. . .
. . .
1 7FFF
1 8000
2 7FFF
2 8000
7F 7FFF
7F 8000
Page 1
Upper
32K
Page 2
Upper
32K
Page 127
Upper
32K
External
External
External
. . .
2 FFFF
7F FFFF
0 FFFF
1 FFFF
†
‡
Refer to Figure 1. 5409 Memory Map.
The Lower 32K words of pages 1 through 126 are available only when the OVLY bit is cleared to 0. If the OVLY bit is set to 1,
the on-chip RAM is mapped to the lower 32K words of all program space pages.
Figure 3−6. Extended Program Memory
3.3 On-Chip Peripherals
The 5409 device has the following peripherals:
•
•
•
•
•
An enhanced 8-bit host-port interface (HPI8/16) with 16-bit data/addressing
Three multichannel buffered serial ports (McBSPs)
One hardware timer
A clock generator with a phase-locked loop (PLL)
A direct memory access (DMA) controller
3.3.1 Parallel I/O Ports
The 5409 CPU has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the
PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The 5409 can interface
easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.
3.3.1.1 Enhanced 8-Bit Host-Port Interface (HPI8/16)
The 5409 host-port interface, also referred to as the HPI8/16, is an enhanced version of the standard 8-bit HPI
found on earlier 54x DSPs (542, 545, 548, and 549). The HPI8/16 is an 8-bit parallel port for interprocessor
communication. The features of the HPI8/16 include:
Standard features:
•
•
•
Sequential transfers (with autoincrement) or random-access transfers
Host interrupt and 54x interrupt capability
Multiple data strobes and control pins for interface flexibility
Enhanced features of the 5409 HPI8/16:
•
•
•
Access to entire on-chip RAM through DMA bus
Capability to continue transferring during emulation stop
Capability to transfer 16-bit address and 16-bit data (non-multiplexed mode)
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Functional Overview
The HPI8/16 functions as a slave and enables the host processor to access the on-chip memory of the 5409.
A major enhancement to the 5409 HPI over previous versions is that it allows host access to the entire on-chip
memory range of the DSP. The HPI8/16 does not have access to external memory. The host and the DSP both
have access to the on-chip RAM at all times and host accesses are always synchronized to the DSP clock.
If the host and the DSP contend for access to the same location, the host has priority, and the DSP waits for
one HPI8/16 cycle. Note that since host accesses are always synchronized to the 5409 clock, an active input
clock (CLKIN) is required for HPI8/16 accesses during IDLE states, and host accesses are not allowed while
the 5409 reset pin is asserted.
0000h
Reserved
005Fh
0060h
Scratch-Pad
RAM
007Fh
0080h
On-Chip RAM
(32K x 16 Bits)
7FFFh
8000h
Reserved
FFFFh
Figure 3−7. 5409 HPI Memory Map
3.3.1.2 Standard 8-Bit Mode
The HPI8/16 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit
transfers are accomplished in two parts with the HBIL input designating high or low byte. The host
communicates with the HPI8 through three dedicated registers — HPI address register (HPIA), HPI data
register (HPID), and an HPI control register (HPIC). The HPIA and HPID registers are only accessible by the
host, and the HPIC register is accessible by both the host and the 5409. If the HPI is disabled (HPIENA = 0)
or in HPI16 mode (HPI16 = 1), the 8-bit bidirectional data pins HD0−HD7 can be used as general-purpose
input/output (GPIO).
3.3.1.3 16-Bit Nonmultiplexed Mode
In nonmultiplexed mode, a host with separate address/data buses can access the HPI16 data register (HPID)
via the HD 16-bit bidirectional data bus, and the address register (HPIA) via the 16-bit HA address bus,
external address and data pins, A0–A15 and D0–D15, respectively. The host initiates an access with the
strobe signals (HDS1, HDS2, HCS) and controls the direction of the access with the HR/W signal. The HPI16
can stall host accesses via the HRDY signal. Note that the HPIC register is not available in nonmultiplexed
mode since there are no HCNTL signals available. All host accesses initiate a DMA read or write access. The
HPI16 nonmultiplexed mode does not support host-to-DSP and DSP-to-host interrupts. When the HPI is
disabled or in HPI16 mode, HD0–HD7 can be configured as general-purpose input/output (GPIO). The HPI16
pin is sampled at RESET. The HPI16 pin should never be changed while the device RESET is HIGH.
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Functional Overview
3.3.1.3.1 Host Bus Holder Configuration
The 5409 has two bus holder control bits, BH (BSCR[1]) and HBH (BSCR[2]), to control the bus keepers of
the address bus (A[15−0]), data bus (D[15−0]) and the HPI data bus (HD[7−0]). The bus keeper
enabling/disabling is described in Table 5.
Table 3−6. Bus Holder Control Bits
HPI16 pin
BH
HBH
D[15−0]
A[15−0]
HD[7−0]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
ON
OFF
ON
OFF
ON
ON
ON
ON
ON
ON
OFF
OFF
ON
OFF
ON
ON
The HPI bus holders are activated via the HBH bit in the Bank Switch Control Register (BSCR). The HBH bit
can control bus holder behavior for both the 8-bit and 16-bit modes. In the 8-bit mode, the HBH bit controls
the bus holders on the host data pins HD7−HD0. When HBH = 1, the host data bus holders are active. When
HBH = 0 the host data bus holders are inactive. In the 16-bit nonmultiplexed mode, the bus holders for pins
HD7−HD0 are always active; however, the HBH bit controls the host address pins A15−A0. When HBH = 1,
the host address bus holders are active. When HBH = 0, the host address bus holders are inactive.
3.3.1.4 Operation During IDLE2
The HPI can continue to operate during IDLE1 or IDLE2 by using special clock management logic that turns
on relevant clocks to perform a synchronous memory access, and then turns the clocks back off to save power.
The DSP CPU does not wake up from the IDLE mode during this process.
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Functional Overview
3.3.2 Multichannel Buffered Serial Ports (McBSPs)
The 5409 device has three high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow
direct interface to other C54x/LC54x devices, codecs, and other devices in a system. The McBSPs are based
on the standard serial port interface found on other 54x devices. Like its predecessors, the McBSP provides:
•
•
•
Full-duplex communication
Double-buffer data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSP has the following capabilities:
•
Direct interface to:
−
−
−
−
−
T1/E1 framers
MVIP switching-compatible and ST-BUS compliant devices
IOM-2 compliant devices
AC97-compliant devices
Serial peripheral interface (SPI) devices
•
•
•
•
•
Multichannel transmit and receive of up to 32 channels in a 128 channel stream.
A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits
µ-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
For detailed information on the standard features of the McBSP, refer to the TMS320C54x DSP Reference
Set, Volume 5: Enhanced Peripherals, (literature number SPRU302).
Although the BCLKS pin is not available on the 5409 PGE and GGU packages, the 5409 is capable of
synchronization to external clock sources. BCLKX or BCLKR can be used by the sample rate generator for
external synchronization. The sample rate clock mode extended (SCLKME) bit field is located in the PCR to
accommodate this option.
15
14
13
XIOEN
RW
12
RIOEN
RW
11
10
FSRM
RW
9
8
Reserved
RW
FSXM
RW
CLKXM
RW
CLKRM
RW
7
6
5
4
3
2
1
0
SCLKME
RW
CLKS STAT
RW
DX STAT
RW
DR STAT
RW
FSXP
RW
FSRP
RW
CLKXP
RW
CLKRP
RW
LEGEND: R = Read, W = Write
Figure 3−8. Pin Control Register (PCR)
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Functional Overview
Table 3−7. Pin Control Register (PCR) Bit Field Description
BIT
NAME
FUNCTION
15 – 14
Reserved
Reserved. Pins are not used.
Transmit/Receive general-purpose I/O mode ONLY when XRST=0 in the SPCR(1/2)
XIOEN = 0
XIOEN = 1
DX pin is not a general-purpose output. FSX and CLKX are not general-purpose I/Os.
DX pin is a general-purpose output. FSX and CLKX are general-purpose I/Os. These serial port
pins do not perform serial port operations.
13
12
XIOEN
RIOEN
Transmit/Receive general-purpose I/O mode ONLY when RRST=0 in the SPCR(1/2)
RIOEN = 0
RIOEN = 1
DR and CLKS pins are not general-purpose inputs. FSR and CLKR are not general-purpose
I/Os.
DR and CLKS pins are general-purpose inputs. FSR and CLKR are general-purpose I/Os.
These serial port pins do not perform serial port operations. The CLKS pin is affected by a
combination of RRST and RIOEN signals of the receiver.
Transmit frame synchronization mode
FSRM = 0
FSRM = 1
Frame synchronization signal derived from an external source.
Frame synchronization is determined by the sample rate generator frame synchronization mode
bit (FSGM) in the SRGR2.
11
10
FSXM
FSRM
Receive frame synchronization mode
FSRM = 0
FSRM = 1
Frame synchronization pulses generated by an external device. FSR is an input pin.
Frame synchronization generated internally by the sample rate generator. FSR is an output pin
except when GSYNC=1 in the SRGR.
Transmitter clock mode
CLKXM = 0
CLKXM= 1
Receiver/transmitter clock is driven by an external clock with CLK(R/X) as an input pin
CLK(R/X) is an output pin and is driven by the internal sample rate generator
9
CLKXM
During SPI mode (CLKSTP is a non-zero value):
CLKXM = 0
CLKXM= 1
McBSP is a slave and clock (CLKX) is driven by the SPI master in the system. CLKR is
internally driven by CLKX.
McBSP is a master and generates the clock (CLKX) to drive its receive clock (CLKR) and the
shift clock of the SPI-compliant slaves in the system.
Receiver clock mode
Case 1: Digital loop-back mode is not set (DLB=0) in SPCR1.
CLKRM = 0
CLKRM= 1
Receive clock (CLKR) is an input pin driven by an external clock.
CLKR is an output pin and is driven by the internal sample rate generator
8
CLKRM
Case 2: Digital loop-back mode set (DLB=1) in SPCR1
CLKRM = 0
CLKRM= 1
Receive clock (Not the CLKR pin) is driven by transmit clock (CLKX), which is based on CLKXM
bit in the PCR. CLKR pin is in high-impedance mode.
CLKR is an output pin and is driven by the transmit clock. The transmit clock is derived based
on the CLKXM bit in the PCR.
Sample rate clock mode extended
7
6
SCLKME
SCLKME = 0
SCLKME = 1
External clock via CLKS or CPU clock is used as a reference by the sample rate generator.
External clock via CLKR or CLKX clock is used as a reference by the sample rate generator.
CLKS STAT CLKS pin status. CLKS STAT reflects value on CLKS pin when selected as a general-purpose input.
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Functional Overview
Table 3−7. Pin Control Register (PCR) Bit Field Description (Continued)
BIT
5
NAME
FUNCTION
DX STAT
DR STAT
DX pin status. DX STAT reflects value on DX pin when it is selected as a general-purpose output.
DR pin status. DR STAT reflects value on DR pin when it is selected as a general-purpose input.
Receive/Transmit frame synchronization polarity.
4
3
2
FSXP
FSRP
FS(R/X)P = 0 Frame synchronization pulse FS(R/X) is active high
FS(R/X)P = 1 Frame synchronization pulse FS(R/X) is active low
Transmit clock polarity
1
0
CLKXP
CLKRP
CLKXP = 0
CLKXP = 1
Transmit data sampled on rising edge of CLKR
Transmit data sampled on falling edge of CLKR
Receive clock polarity
CLKRP = 0
CLKRP = 1
Receive data sampled on falling edge of CLKR
Receive data sampled on rising edge of CLKR
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Functional Overview
3.3.2.1 Sample Rate Generator
The 5409 sample rate generator has four clock input options that are only available when both the PCR and
SRGR2 are used. Table 3−8 shows the sample rate generator clock input options.
Table 3−8. Sample Rate Generator Clock Input Options
SCLKME
(PCR.7)
CLKSM
MODE
(SRGR2.13)
CLKS pin
CPU
0
0
1
1
0
1
0
1
CLKR pin
CLKX pin
15
14
13
12
11
8
GSYNC
R/W-0
CLKSP
R/W
CLKSM
R/W
FSGM
R/W
FPER
R/W
7
0
FPER
R/W
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3−9. Sample Rate Generator Register 2 (SRGR2)
Table 3−9. Sample Rate Generator Register 2 (SRGR2) Bit Field Descriptions
BIT
NAME
FUNCTION
Sample rate generator clock synchronization. Only used when the external clock (CLKS) drives the sample rate
generator clock (CLKSM=0)
GSYNC = 0
GSYNC = 1
The sample rate generator clock (CLKG) is free-running.
15
GSYNC
CLKSP
The sample rate generator clock (CLKG) is running. But CLKG is resynchronized and frame sync
signal (FSG) is generated only after detecting the receive frame synchronization signal (FSR). Also,
frame period (FPER) is a don’t care because the period is dictated by the external frame sync pulse.
CLKS polarity clock edge select. Only used when the external clock (CLKS) drives the sample rate generator clock
(CLKSM=0).
14
13
CLKSP = 0
CLKSP = 1
Rising edge of CLKS generates CLKG and FSG.
Falling edge of CLKS generates CLKG and FSG.
McBSP sample rate generator clock mode
SCLKME = 0
(in PCR)
CLKSM = 0
CLKSM = 1
Sample rate generator clock derived from the CLKS pin
Sample rate generator clock derived from CPU clock
CLKSM
SCLKME = 1
(in PCR)
CLKSM = 0
CLKSM = 1
Sample rate generator clock derived from CLKR pin
Sample rate generator clock derived from CLKX pin
Sample rate generator transmit frame synchronization mode. Used when FSXM=1 in the PCR.
12
FSGM
FPER
FSGM = 0
FSGN = 1
Transmit frame sync signal (FSX) due to DXR(1/2) copy
Transmit frame sync signal driven by the sample rate generator frame sync signal (FSG)
12
Frame period. This determines when the next frame sycn signal should become active. Range: up to 2
1 to 4096 CLKG periods.
;
11 − 0
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Functional Overview
3.3.2.2 McBSP Control Registers and Subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory
location. The serial port subbank address (SPSA) register is used as a pointer to select a particular register
within the subbank. The serial port subbank data (SPSD) register is used to access (read or write) the selected
register. Table 3−10 shows the McBSP control registers and their corresponding subaddresses.
Table 3−10. McBSP Control Registers and Subaddresses
McBSP0
McBSP1
McBSP2
SUB
ADDRESS
DESCRIPTION
NAME
ADDRESS
39h
NAME
ADDRESS
49h
NAME
ADDRESS
35h
SPCR10
SPCR20
RCR10
RCR20
XCR10
SPCR11
SPCR21
RCR11
SPCR12
SPCR22
RCR12
RCR22
XCR12
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
Serial port control register 1
Serial port control register 2
Receive control register 1
Receive control register 2
Transmit control register 1
Transmit control register 2
Sample rate generator register 1
Sample rate generator register 2
Multichannel register 1
39h
49h
35h
39h
49h
35h
39h
RCR21
XCR11
49h
35h
39h
49h
35h
XCR20
39h
XCR21
SRGR11
SRGR21
MCR11
MCR21
49h
XCR22
35h
SRGR10
SRGR20
MCR10
MCR20
39h
49h
SRGR12
SRGR22
MCR12
MCR22
35h
39h
49h
35h
39h
49h
35h
39h
49h
35h
Multichannel register 2
Receive channel enable register
partition A
RCERA0
RCERB0
XCERA0
39h
39h
39h
RCERA1
RCERB1
XCERA1
49h
49h
49h
RCERA2
RCERB2
XCERA2
35h
35h
35h
0Ah
0Bh
0Ch
Receive channel enable register
partition B
Transmit channel enable register
partition A
Transmit channel enable register
partition B
XCERB0
PCR0
39h
39h
XCERB1
PCR1
49h
49h
XCERB2
PCR2
35h
35h
0Dh
0Eh
Pin control register
3.3.3 Hardware Timer
The 5409 device features one 16-bit timing circuit with a 4-bit prescaler. The main counter of each timer is
decremented by one every CPU clock cycle. Each time the counter decrements to 0, a timer interrupt is
generated. The timer can be stopped, restarted, reset, or disabled by specific control bits.
3.3.4 Clock Generator
The clock generator provides clocks to the 5409 device, and consists of an internal oscillator and a
phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided
by using a crystal resonator with the internal oscillator, or from an external clock source. The reference clock
input is then divided by two (DIV mode) to generate clocks for the 5409 device, or the PLL circuit can be used
(PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor,
allowing use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive circuit that,
once synchronized, locks onto and tracks an input clock signal.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,
other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the 5409
device.
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Functional Overview
This clock generator allows system designers to select the clock source. The sources that drive the clock
generator are:
•
•
A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins
of the 5409 to enable the internal oscillator.
An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left
unconnected.
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a
built-in software-programmable PLL can be configured in one of two clock modes:
•
•
PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved
using the PLL circuitry.
DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can
be completely disabled in order to minimize power dissipation.
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Upon
reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the
CLKMD1 − CLKMD3 pins as shown in Table 3−11.
Table 3−11. Clock Mode Settings at Reset
CLKMD
RESET VALUE
CLKMD1
CLKMD2
CLKMD3
CLOCK MODE
0
0
0
0
0
1
E007h
PLL x 15
PLL x 10
9007h
0
1
1
1
1
0
1
0
1
1
0
1
0
0
0
1
1
1
4007h
1007h
F007h
0000h
F000h
—
PLL x 5
PLL x 2
PLL x 1
1/2 (PLL disabled)
1/4 (PLL disabled)
Reserved
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Functional Overview
3.3.5 DMA Controller
The 5409 direct memory access (DMA) controller transfers data between points in the memory map without
intervention by the CPU. The DMA controller allows movements of data to and from internal program/data
memory, internal peripherals (such as the McBSPs), and external program/data memory to occur in the
background of CPU operation. The DMA has six independent programmable channels allowing six different
contexts for DMA operation.
The DMA has the following features:
•
•
•
•
•
•
The DMA has external memory access.
The DMA operates independently of the CPU.
The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
The DMA has higher priority than the CPU for internal accesses.
Each channel has independently programmable priorities.
Each channel’s source and destination address registers can have configurable indexes through memory
on each read and write transfer, respectively. The address may remain constant, be post-incremented,
post-decremented, or be adjusted by a programmable value.
•
•
•
Each internal read or write transfer may be initialized by selected sync events.
Each DMA channel is capable of sending interrupts to the CPU.
The DMA can perform double-word transfers (a 32-bit transfer of two 16-bit words). (Internally only)
3.3.5.1 DMA External Access
The 5409 DMA supports external accesses to extended program, extended data, and extended I/O memory.
These overlay pages are only visible to the DMA controller. A maximum of two DMA channels can be used
for external memory accesses. The DMA external accesses require 9 cycle minimums for external writes and
13 cycle minimums for external reads.
The control of the bus is arbitrated between the CPU and the DMA. While the DMA or CPU is in control of the
external bus the other will be held−off via wait states until the current transfer is complete. The DMA takes
precedence over XIO requests. The HOLD/HOLDA feature of the 5409 affects external CPU transfers as well
as external DMA transfers. When an external processor asserts the HOLD pin to gain control of the memory
interface, the HOLDA signal is not asserted until all pending DMA transfers are complete. To prevent the DMA
from blocking out the CPU or HOLD/HOLDA feature from accessing the external bus, uninterrupted burst
transfers are not supported by the DMA. Subsequently, CPU and DMA arbitration testing is performed for
each external bus cycle, regardless of the bus activity.
•
•
•
•
•
•
Only two channels are available for external accesses. (One for external reads/one for external writes.)
Single-word (16-bit) transfers are supported for external accesses.
The DMA does not support transfers from peripherals to external memory.
The DMA does not support transfers from external memory to the peripherals.
The DMA does not support external to external transfers.
The DMA does not support synchronized external transfers.
The HM bit in the ST1 register indicates whether the processor continues internal execution when
acknowledging an active HOLD signal.
•
HM = 0, the processor continues execution from internal program memory but places its external interface
in the high impedance state.
•
HM = 1, the processor halts internal execution.
To ensure that proper arbitration occurs, the HM bit should be set to 0 in the memory-mapped ST1 register.
If the HM is set to 1 the processor will halt during DMA external transfers.
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Functional Overview
3.3.5.2 DMA External Transfer
Unlike the 5410, the 5409 DMA mode control register (DMMCRx) has two additional bits; DLAXS
(DMMCRn[5]) and SLAXS (DMMCRn[11]). These new bits specify the on/off-chip memory for the source and
destination of the program/data/IO spaces.
•
•
When DLAXS is set to 0 (default), the DMA does not perform an external access for the destination. When
DLAXS is set to 1, the DMA performs an external access to the destination location.
When SLAXS is set to 0 (default), the DMA does not perform an external access for the source. When
DLAXS is set to 1, the DMA performs an external access from the source location.
Two new registers are added to the 5409 DMA to support DMA accesses to/from DMA extended data memory,
page 1 to page 127.
•
•
The DMA extended source data page register (XSRCDP[6:0]) is located at subbank address 028h.
The DMA extended destination data page register (XDSTDP[6:0]) is located at subbank address 029h.
3.3.5.3 DMA Memory Map
The DMA memory map, as shown in Figure 3−10, allows DMA transfers to be unaffected by the status of the
MP/MC, DROM, and OVLY bits.
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Functional Overview
Data
Program
Data
I/O
Program
Program
Hex
010000
Hex
xx0000
Hex
xx0000
Hex
0000
Hex
0000
Hex
0000
Reserved
DRR20
DRR10
DXR20
DXR10
001F
0020
0021
0022
0023
0024
Reserved
007F
0080
Reserved
002F
0030
0031
0032
DRR22
DRR12
DXR22
DXR12
0033
0034
DARAM
Internal
32K
External
Reserved
0035
0036
0037
0038
RCERA2
XCERA2
Reserved
0039
003A
003B
003C
RCERA0
XCERA0
External
External
External
Reserved
DRR21
DRR11
DXR21
DXR11
7FFF
8000
017FFF
018000
003F
0040
0041
0042
0043
0044
On-Chip
ROM
Reserved
0049
004A
RCERA1
XCERA1
004B
004C
External
BFFF
C000
Reserved
005F
0060
Scratch-
Pad RAM
007F
0080
DARAM
External
7FFF
8000
xxFFFF
FFFF
FFFF
01FFFF
xxFFFF
FFFF
Page 0, 1, ... 127
Page 0
Page 1, 2, ... 127
Page 5, 6, ...
Page n
NOTE: n = 1, 2, 3, or 4
Figure 3−10. TMS320VC5409 DMA Memory Map
3.3.5.4 DMA Priority Level
Each DMA channel can be independently assigned high priority or low priority relative to each other. Multiple
DMA channels that are assigned to the same priority level are handled in a round-robin manner.
3.3.5.5 DMA Source/Destination Address Modification
The DMA provides flexible address-indexing modes for easy implementation of data management schemes
such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and
can be post-incremented, post-decremented, or post-incremented with a specified index offset.
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Functional Overview
3.3.5.6 DMA in Autoinitialization Mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers
can be preloaded for the next block transfer through the DMA global reload registers (DMGSA, DMGDA, and
DMGCR). Autoinitialization allows:
•
Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the
completion of the current block transfer; but with the global reload registers, it can reinitialize these values
for the next block transfer any time after the current block transfer begins.
•
Repetitive operation: The CPU does not preload the global reload register with new values for each block
transfer but only loads them on the first block transfer.
3.3.5.7 DMA Transfer Counting
The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit fields
that represent the number of frames and the number of elements per frame to be transferred.
•
Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum
number of frames per block transfer is 128 (FRAME COUNT= 0ffh). The counter is decremented upon
the last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is
reloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count
of 0 (default value) means the block transfer contains a single frame.
•
Element count. This 16-bit value defines the number of elements per frame. This counter is decremented
after the read transfer of each element. The maximum number of elements per frame is 65536
(DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter is
reloaded with the DMA global count reload register (DMGCR).
3.3.5.8 DMA Transfers in Double-word Mode (Internal Only)
Double-word mode allows the DMA to transfer 32-bit words in any index mode. In double-word mode, two
consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated
following each transfer. In this mode, each 32-bit word is considered to be one element.
3.3.5.9 DMA Channel Index Registers
The particular DMA channel index register is selected by way of the SIND and DIND field in the DMA mode
control register (DMMCRx). Unlike basic address adjustment, in conjunction with the frame index DMFRI0 and
DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer is
the last in the current frame. The normal adjustment value (element index) is contained in the element index
registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame is determined
by the selected DMA frame index register (either DMFRI0 or DMFRI1).
The element index and the frame index affect address adjustment as follows:
•
•
Element index: For all except the last transfer in the frame, the element index determines the amount to
be added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as
selected by the SIND/DIND bits.
Frame index: If the transfer is the last in a frame, the frame index is used for address adjustment as
selected by the SIND/DIND bits. This occurs in both single-frame and multi-frame transfer.
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April 1999 − Revised February 2004
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Functional Overview
3.3.5.10 DMA Interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA channel mode control register (DMMCRn). The available
modes are shown in Table 3−12.
Table 3−12. DMA Interrupts
MODE
ABU (non-decrement)
ABU (non-decrement)
Multi-Frame
DINM
IMOD
INTERRUPT
1
1
1
1
0
0
0
1
0
1
X
X
At full buffer only
At half buffer and full buffer
At block-transfer complete (DMCTRn = DMSEFCn[7:0] = 0)
At end of frame and end of block (DMCTRn = 0)
No interrupt generated
Multi-Frame
Either
Either
No interrupt generated
3.3.5.10.1 DMA Controller Synchronization Events
The internal transfers associated with each DMA channel can be synchronized to one of several events. The
DSYN bit field of the DMSEFCn register selects the synchronization event for a channel. The list of possible
events and the DSYN values are shown in Table 3−13.
Table 3−13. DMA Synchronization Events
DSYN VALUE
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
DMA SYNCHRONIZATION EVENT
No synchronization used
McBSP0 receive event
McBSP0 transmit event
McBSP2 receive event
McBSP2 transmit event
McBSP1 receive event
McBSP1 transmit event
Reserved
1000b
1001b
1010b
1011b
1100b
1101b
1110b
Reserved
Reserved
Reserved
Reserved
Reserved
Timer interrupt event
External interrupt 3
Reserved
1111b
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Functional Overview
3.3.5.10.2 DMA Channel Interrupt Selection
The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on the
number of internal CPU interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt sources.
DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the McBSP. When
the 5409 is reset, the interrupts from these three DMA channels are deselected. The INTSEL bit field in the
DMPREC register can be used to select these interrupts, as shown in Table 3−14.
Table 3−14. DMA Channel Interrupt Selection
INTSEL Value
00b (reset)
01b
IMR/IFR[6]
BRINT2
BRINT2
DMAC0
IMR/IFR[7]
BXINT2
IMR/IFR[10]
BRINT1
IMR/IFR[11]
BXINT1
BXINT2
DMAC2
DMAC3
10b
DMAC1
DMAC2
DMAC3
11b
Reserved
3.3.5.11 DMA Subbank Addressed Registers
The direct memory access (DMA) controller has several control registers associated with it. The main control
register (DMPREC) is a standard memory mapped register. However, the other registers are accessed using
the subbank addressing scheme. This allows a set, or subbank of registers to be accessed through a single
memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular
register within the subbank, while the DMA subbank data (DMSDN) register or the DMA subbank data register
with autoincrement (DMSDI) is used to access (read or write) the selected register.
When the DMSDI register is used to access the subbank, the subbank address is automatically
postincremented so that a subsequent access affects the next register within the subbank. This autoincrement
feature is intended for efficient, successive accesses to several control registers. If the auto-increment feature
is not required, the DMSDN register should be used to access the subbank. Table 3−15 shows the DMA
controller subbank addressed registers and their corresponding subaddresses.
Table 3−15. DMA Subbank Addressed Registers
DMA
SUB
ADDRESS
DESCRIPTION
DMA channel 0 source address register
NAME
DMSRC0
DMDST0
DMCTR0
DMSFC0
DMMCR0
DMSRC1
DMDST1
DMCTR1
DMSFC1
DMMCR1
DMSRC2
DMDST2
DMCTR2
DMSFC2
DMMCR2
DMSRC3
DMDST3
DMCTR3
DMSFC3
ADDRESS
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
DMA channel 0 destination address register
DMA channel 0 element count register
DMA channel 0 sync select and frame count register
DMA channel 0 transfer mode control register
DMA channel 1 source address register
DMA channel 1 destination address register
DMA channel 1 element count register
DMA channel 1 sync select and frame count register
DMA channel 1 transfer mode control register
DMA channel 2 source address register
DMA channel 2 destination address register
DMA channel 2 element count register
DMA channel 2 sync select and frame count register
DMA channel 2 transfer mode control register
DMA channel 3 source address register
DMA channel 3 destination address register
DMA channel 3 element count register
DMA channel 3 sync select and frame count register
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April 1999 − Revised February 2004
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Functional Overview
Table 3−15. DMA Subbank Addressed Registers (Continued)
DMA
SUB
DESCRIPTION
ADDRESS
NAME
DMMCR3
DMSRC4
DMDST4
DMCTR4
DMSFC4
DMMCR4
DMSRC5
DMDST5
DMCTR5
DMSFC5
DMMCR5
DMSRCP
DMDSTP
DMIDX0
DMIDX1
DMFRI0
DMFRI1
DMGSA
ADDRESS
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
DMA channel 3 transfer mode control register
DMA channel 4 source address register
DMA channel 4 destination address register
DMA channel 4 element count register
DMA channel 4 sync select and frame count register
DMA channel 4 transfer mode control register
DMA channel 5 source address register
DMA channel 5 destination address register
DMA channel 5 element count register
DMA channel 5 sync select and frame count register
DMA channel 5 transfer mode control register
DMA source program page address (common channel)
DMA destination program page address (common channel)
DMA element index address register 0
DMA element index address register 1
DMA frame index register 0
DMA frame index register 1
DMA global source address reload register
DMA global destination address reload register
DMA global count reload register
DMGDA
DMGCR
DMGFR
DMA global frame count reload register
DMA global extended source register
XSRCDP
XDSTDP
DMA global extended destination register
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Functional Overview
3.3.6 Peripheral Memory-Mapped Registers
The device provides a set of memory-mapped registers associated with peripherals. Table 3−4 gives a list of
CPU memory-mapped registers (MMRs) available on 5409. Table 3−16 shows additional peripheral MMRs
associated with the 5409.
Table 3−16. Peripheral Memory-Mapped Registers
NAME
ADDRESS
20h
DESCRIPTION
TYPE
McBSP #0
McBSP #0
McBSP #0
McBSP #0
Timer
DRR20
DRR10
DXR20
DXR10
TIM
Data receive register 2
Data receive register 1
Data transmit register 2
Data transmit register 1
Timer register
21h
22h
23h
24h
PRD
25h
Timer period counter
Timer control register
Reserved
Timer
TCR
26h
Timer
–
27h
SWWSR
BSCR
–
28h
Software wait-state register
Bank-switching control register
Reserved
External Bus
External Bus
29h
2Ah
SWCR
HPIC
2Bh
Software wait-state control register
HPI control register
External Bus
HPI
2Ch
–
2Dh−2Fh
30h
Reserved
DRR22
DRR12
DXR22
DXR12
SPSA2
SPSD2
–
Data receive register 2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
31h
Data receive register 1
32h
Data transmit register 2
Data transmit register 2
McBSP2 subbank address register
McBSP2 subbank data register
Reserved
33h
34h
35h
36−37h
38h
SPSA0
SPCD0
–
McBSP0 subbank address register
McBSP0 subbank data register
Reserved
McBSP #0
McBSP #0
39h
3Ah−3Bh
3C
GPIOCR
GPIOSR
–
General-purpose I/O pins control register
General-purpose I/O pins status register
Reserved
GPIO
GPIO
3D
3E−3F
40h
DRR21
DRR11
DXR21
DXR11
–
Data receive register 1
McBSP #1
McBSP #1
McBSP #1
McBSP #1
41h
Data receive register 2
42h
Data transmit register 1
Data transmit register 2
Reserved
43h
44h−47h
48h
SPSA1
SPCD1
–
McBSP1 subbank address register
McBSP1 subbank data register
Reserved
McBSP #1
McBSP #1
49h
4Ah−53h
54h
DMPREC
DMSA
DMSDI
DMSDN
CLKMD
–
DMA channel priority and enable control register
DMA subbank address register
DMA subbank data register with autoincrement
DMA subbank data registrer
Clock mode register
DMA
DMA
DMA
DMA
PLL
55h
56h
57h
58h
59h−5Fh
Reserved
39
April 1999 − Revised February 2004
SPRS082E
Functional Overview
3.4 Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3−17.
Table 3−17. Interrupt Locations and Priorities
TRAP/INTR
NUMBER (K)
LOCATION
DECIMAL
NAME
PRIORITY
FUNCTION
HEX
00
RS, SINTR
0
1
0
4
1
2
Reset (hardware and software reset)
Nonmaskable interrupt
NMI, SINT16
SINT17
04
08
2
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
Software interrupt #17
SINT18
3
12
0C
10
Software interrupt #18
SINT19
4
16
Software interrupt #19
SINT20
5
20
14
Software interrupt #20
SINT21
6
24
18
Software interrupt #21
SINT22
7
28
1C
20
Software interrupt #22
SINT23
8
32
Software interrupt #23
SINT24
9
36
24
Software interrupt #24
SINT25
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30−31
40
28
Software interrupt #25
SINT26
44
2C
30
Software interrupt #26
SINT27
48
Software interrupt #27
SINT28
52
34
Software interrupt #28
SINT29
56
38
Software interrupt #29
SINT30
60
3C
40
Software interrupt #30
INT0, SINT0
INT1, SINT1
INT2, SINT2
TINT, SINT3
BRINT0, SINT4
BXINT0, SINT5
BRINT2, SINT7, DMAC0
BXINT2, SINT6, DMAC1
INT3, SINT8
HINT, SINT9
BRINT1, SINT10, DMAC2
BXINT1, SINT11, DMAC3
DMAC4,SINT12
DMAC5,SINT13
Reserved
64
External user interrupt #0
External user interrupt #1
External user interrupt #2
Timer interrupt
68
44
4
72
48
5
76
4C
50
6
80
7
McBSP #0 receive interrupt (default)
McBSP #0 transmit interrupt (default)
McBSP #2 receive interrupt (default)
McBSP #2 transmit interrupt (default)
External user interrupt #3
HPI interrupt
84
54
8
88
58
9
92
5C
60
10
11
12
13
14
15
16
—
96
100
104
108
112
116
120−127
64
68
McBSP #1 receive interrupt (default)
McBSP #1 transmit interrupt (default)
DMA channel 4 interrupt (default)
DMA channel 5 interrupt (default)
Reserved
6C
70
74
78−7F
40
SPRS082E
April 1999 − Revised February 2004
Functional Overview
The bits of the interrupt flag register (IFR) and interrupt mask register (IMR) are arranged as shown in
Figure 3−11. The function of each bit is described in Table 3−18.
15
14
13
12
11
10
9
8
BXINT1/
DMAC3
BRINT1/
DMAC2
Reserved
DMAC5
DMAC4
HINT
INT3
7
6
5
4
3
2
1
0
BXINT2/
DMAC1
BRINT2/
DMAC0
BXINT0
BRINT0
TINT
INT2
INT1
INT0
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3−11. IFR and IMR Registers
Table 3−18. IFR and IMR Register Bit Fields
BIT
FUNCTION
NUMBER
NAME
−
15−14
Reserved for future expansion
13
12
11
10
9
DMAC5
DMAC4
DMA channel 5 interrupt flag/mask bit
DMA channel 4 interrupt flag/mask bit
McBSP1 transmit interrupt flag/mask bit
McBSP1 receive interrupt flag/mask bit
Host to 54x interrupt flag/mask
BXINT1/DMAC3
BRINT1/DMAC2
HINT
8
INT3
External interrupt 3 flag/mask
7
BXINT2/DMAC1
BRINT2/DMAC0
BXINT0
McBSP2 transmit interrupt flag/mask bit
McBSP2 receive interrupt flag/mask bit
McBSP0 transmit interrupt flag/mask bit
McBSP0 receive interrupt flag/mask bit
Timer interrupt flag/mask bit
6
5
4
BRINT0
3
TINT
2
INT2
External interrupt 2 flag/mask bit
External interrupt 1 flag/mask bit
External interrupt 0 flag/mask bit
1
INT1
0
INT0
41
April 1999 − Revised February 2004
SPRS082E
Functional Overview
3.5 Terminal Functions
The 5409 signal descriptions table lists each pin name, function, and operating mode(s) for the 5409 device.
Some of the 5409 pins can be configured for one of two functions; a primary function and a secondary function.
The names of these pins in secondary mode are shaded in grey in the following table.
Table 3−19. Terminal Functions
INTERNAL
PIN STATE
TERMINAL
NAME
†
I/O
DESCRIPTION
DATA SIGNALS
A22 (MSB)
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
O/Z
Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The
lower sixteen address pins (A15 to A0) are multiplexed to address all external memory (program,
data) or I/O while the upper seven address pins (A22 to A16) are only used to address external
program space. These pins are placed in the high-impedance state when the hold mode is enabled,
or when OFF is low.
Bus holders
available
(A15−A0)
A8
A7
A6
A5
A4
A3
A2
A1
A0
(LSB)
D15 (MSB)
D14
D13
D12
D11
D10
D9
I/O/Z
Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D15 to D0) are multiplexed
to transfer data between the core CPU and external data/program memory or I/O devices. The data
bus is placed in the high-impedance state when not outputting or when RS or HOLD is asserted.
The data bus also goes into the high-impedance state when OFF is low.
D8
D7
D6
D5
D4
D3
Bus holders
available
The data bus has bus holders to reduce the static power dissipation caused by floating, unused
pins. These bus holders also eliminate the need for external bias resistors on unused pins. When
the data bus is not being driven by the 5409, the bus holders keep the pins at the previous logic level.
The data bus holders on the 5409 are disabled at reset and can be enabled/disabled via the BH bit
of the bank-switching control register (BSCR).
D2
D1
D0
(LSB)
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter
IACK
is fetching the interrupt vector location designated by A15−A0. IACK also goes into the
O/Z
high-impedance state when OFF is low.
INT0
INT1
INT2
INT3
†
Schmitt
trigger
External user interrupts. INT0−INT3 are prioritized and are maskable by the interrupt mask register
and the interrupt mode bit. INT0 −INT3 can be polled and reset by way of the interrupt flag register.
I
I = Input, O = Output, Z = High-impedance, S = Supply
42
SPRS082E
April 1999 − Revised February 2004
Functional Overview
Table 3−19. Terminal Functions (Continued)
INTERNAL
PIN STATE
TERMINAL
NAME
†
I/O
DESCRIPTION
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED)
Schmitt
trigger
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or
the IMR. When NMI is activated, the processor traps to the appropriate vector location.
NMI
I
I
Reset. RS causes the DSP to terminate execution and causes a reinitialization of the CPU and
peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program
memory. RS affects various registers and status bits.
Schmitt
trigger
RS
Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is
selected, and the internal program ROM is mapped into the upper program memory space. If the
pin is driven high during reset, microprocessor mode is selected, and the on-chip ROM is removed
from program space. MP/MC is only sampled at reset, and the MP/MC bit of the PMST register can
override the mode that is selected at reset.
MP/MC
I
MULTIPROCESSING SIGNALS
Branch control. A branch can be conditionally executed when BIO is active. If low, the processor
executes the conditional instruction. For the XC instruction, the BIO condition is sampled during the
decode phase of the pipeline; all other instructions sample BIO during the read phase of the
pipeline.
Schmitt
trigger
BIO
XF
I
External flag output (latched software-programmable signal). XF is set high by the SSBX XF
instruction, set low by the RSBX XF instruction or by loading ST1. XF is used for signaling other
processors in multiprocessor configurations or used as a general-purpose output pin. XF goes into
the high-impedance state when OFF is low, and is set high at reset.
O/Z
MEMORY CONTROL SIGNALS
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for
accessing a particular external memory space. Active period corresponds to valid address
information. DS, PS, and IS are placed into the high-impedance state in the hold mode; the signals
also go into the high-impedance state when OFF is low.
DS
PS
IS
O/Z
O/Z
I
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus
access to data or program memory. MSTRB is placed in the high-impedance state in the hold mode;
it also goes into the high-impedance state when OFF is low.
MSTRB
READY
Data ready. READY indicates that an external device is prepared for a bus transaction to be
completed. If the device is not ready (READY is low), the processor waits one cycle and checks
READY again. Note that the processor performs ready detection if at least two software wait states
are programmed. The READY signal is not sampled until the completion of the software wait states.
Read/write signal. R/W indicates transfer direction during communication to an external device.
R/W is normally in the read mode (high), unless it is asserted low when the DSP performs a write
operation. R/W is placed in the high-impedance state in hold mode; it also goes into the
high-impedance state when OFF is low.
R/W
O/Z
I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus
access to an I/O device. IOSTRB is placed in the high-impedance state in the hold mode; it also
goes into the high-impedance state when OFF is low.
IOSTRB
HOLD
O/Z
I
Hold. HOLD is asserted to request control of the address, data, and control lines. When
acknowledged by the C54x, these lines go into the high-impedance state.
Hold acknowledge. HOLDA indicates that the 5409 is in a hold state and that the address, data, and
control lines are in the high-impedance state, allowing the external memory interface to be
accessed by other devices. HOLDA also goes into the high-impedance state when OFF is low. This
pin is driven high during reset.
HOLDA
MSC
O/Z
Microstate complete. MSC indicates completion of all software wait states. When two or more
software wait states are enabled, the MSC pin goes low during the last of these wait states. If
connected to the READY input, MSC forces one external wait state after the last internal wait state
is completed. MSC also goes into the high-impedance state when OFF is low.
O/Z
O/Z
Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on
the address bus. IAQ goes into the high-impedance state when OFF is low.
IAQ
†
I = Input, O = Output, Z = High-impedance, S = Supply
43
April 1999 − Revised February 2004
SPRS082E
Functional Overview
Table 3−19. Terminal Functions (Continued)
INTERNAL
PIN STATE
TERMINAL
NAME
†
I/O
DESCRIPTION
OSCILLATOR/TIMER SIGNALS
Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal
machine cycle is bounded by rising edges of this signal. CLKOUT also goes into the
high-impedance state when OFF is low.
CLKOUT
O/Z
I
Clock mode select signals. These inputs select the mode that the clock generator is initialized to
after reset. The logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the
clock mode register is initialized to the selected mode. After reset, the clock mode can be changed
through software, but the clock mode select signals have no effect until the device is reset again.
CLKMD1
CLKMD2
CLKMD3
Schmitt
trigger
Schmitt
trigger
Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock
input.
X2/CLKIN
X1
I
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should
be left unconnected. X1 does not go into the high-impedance state when OFF is low.
O
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is
one CLKOUT cycle wide. TOUT also goes into the high-impedance state when OFF is low.
TOUT
O/Z
MULTICHANNEL BUFFERED SERIAL PORT SIGNALS
Receive clocks. BCLKR serves as the serial shift clock for the buffered serial-port receiver. Input
from an external clock source for clocking data into the McBSP. When not being used as a clock,
these pins can be used as general-purpose I/O by setting RIOEN = 1.
BCLKR0
BCLKR1
BCLKR2
Schmitt
trigger
I/O/Z
BCLKR can be configured as an output by the way of the CLKRM bit in the PCR register.
BDR0
BDR1
BDR2
Buffered serial data receive (input) pin. When not being used as data-receive pins, these pins can
be used as general-purpose I/O by setting RIOEN = 1.
I
BFSR0
BFSR1
BFSR2
Frame synchronization pin for buffered serial-port input data. The BFSR pulse initiates the
receive-data process over the BDR pin.When not being used as data-receive synchronization pins,
these pins can be used as general-purpose I/O by setting RIOEN = 1.
I/O/Z
Transmit clocks. Clock signal used to clock data from the transmit register. This pin can also be
configured as an input by setting the CLKXM = 0 in the PCR register. When not being used as a
clock, these pins can be used as general-purpose I/O by setting XIOEN = 1.
BCLKX0
BCLKX1
BCLKX2
Schmitt
trigger
I/O/Z
O/Z
These pins are placed into the high-impedance state when OFF is low.
Buffered serial-port transmit (output) pin. When not being used as data-transmit pins, these pins
can be used as general-purpose I/O by setting XIOEN = 1.
BDX0
BDX1
BDX2
These pins are placed into the high-impedance state when OFF is low.
Buffered serial-port frame synchronization pin for transmitting data. The BFSX pulse initiates the
transmit-data process over BDX pin. If RS is asserted when BFSX is configured as output, then
BFSX is turned into input mode by the reset operation. When not being used as data-transmit
synchronization pins, these pins can be used as general-purpose I/O by setting XIOEN = 1.
BFSX0
BFSX1
BFSX2
I/O/Z
These pins are placed into the high-impedance state when OFF is low.
†
I = Input, O = Output, Z = High-impedance, S = Supply
44
SPRS082E
April 1999 − Revised February 2004
Functional Overview
Table 3−19. Terminal Functions (Continued)
INTERNAL
PIN STATE
TERMINAL
NAME
†
I/O
DESCRIPTION
HOST-PORT INTERFACE SIGNALS
PRIMARY
SECONDARY
These pins can be used to address internal memory via the HPI
when the HPI16 pin is high. The sixteen address pins, A15 to A0,
are multiplexed to transfer address between the core CPU and
external data/program memory, I/O devices, or HPI in 16-bit mode.
Bus holders
available
The address bus includes bus holders to reduce the static power
dissipation caused by floating, unused pins. The bus holders also
eliminate the need for external bias resistors on unused pins. When
the address bus is not being driven by the 5409, the bus holders
keep the pins at the logic level that was most recently driven. The
address bus holders of the 5409 are disabled at reset, and can be
enabled/disabled via the HBH bit of the BSCR.
HA15 − HA0
I/O/Z
A15 − A0
O/Z
These pins can be used to read/write internal memory via the HPI
when the HPI16 pin is high. The sixteen data pins, D15 to D0, are
multiplexed to transfer data between the core CPU and external
data/program memory, I/O devices, or HPI in 16-bit mode. The data
bus is placed in the high-impedance state when not outputting or
when RS or HOLD is asserted. The data bus also goes into the
high-impedance state when OFF is low.
Bus holders
available
HD15 − HD0
I/O/Z
D15 − D0
O/Z
The data bus includes bus holders to reduce the static power
dissipation caused by floating, unused pins. The bus holders also
eliminate the need for external bias resistors on unused pins. When
the data bus is not being driven by the 5409, the bus holders keep
the pins at the logic level that was most recently driven. The data
bus holders of the 5409 are disabled at reset, and can be
enabled/disabled via the BH bit of the BSCR.
Parallel bidirectional data bus. When the HPI is disabled or when the HPI16 pin is high, these pins
can also be used as general-purpose I/O pins. HD7–HD0 are placed in the high-impedance state
when not outputting data or when OFF is low.
Bus holders
available
HD7 – HD0
I/O/Z
The HPI data bus includes bus holders to reduce the static power dissipation caused by floating,
unused pins. When the HPI data bus is not being driven by the 5409, the bus holders keep the pins
at the logic level that was most recently driven. The HPI data bus holders are disabled at reset. In
8-bit mode the bus holders can be enabled/disabled via the HBH bit of the BSCR. In 16-bit mode
the bus holders are always active on the HD7–HD0 pins.
HCNTL0
HCNTL1
Pullup
resistor
Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control
inputs have internal pullup resistors that are only enabled when HPIENA = 0.
I
I
Pullup
resistor
Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal
pullup resistor that is only enabled when HPIENA = 0.
HBIL
HCS
Schmitt
trigger/pullup
resistor
Chip select. HCS is the select input for the HPI and must be driven low during accesses. The
chip-select input has an internal pullup resistor that is only enabled when HPIENA = 0.
I
I
I
Schmitt
trigger/pullup
resistor
HDS1
HDS2
Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers. The
strobe inputs have internal pullup resistors that are only enabled when HPIENA = 0.
Schmitt
trigger/pullup
resistor
Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in
the HPIA register. HAS has an internal pullup resistor that is only enabled when HPIENA = 0.
HAS
†
I = Input, O = Output, Z = High-impedance, S = Supply
45
April 1999 − Revised February 2004
SPRS082E
Functional Overview
Table 3−19. Terminal Functions (Continued)
INTERNAL
PIN STATE
TERMINAL
NAME
†
I/O
DESCRIPTION
HOST-PORT INTERFACE SIGNALS (CONTINUED)
Pullup
resistor
Read/write. HR/W controls the direction of an HPI transfer. R/W has an internal pullup resistor that
is only enabled when HPIENA = 0.
HR/W
HRDY
HINT
I
Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes
into the high-impedance state when OFF is low.
O/Z
O/Z
Interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high.
The signal goes into the high-impedance state when OFF is low.
HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal
pulldown resistor is always active and the HPIENA pin is sampled on the rising edge of RS. If
HPIENA is left open or is driven low during reset, the HPI module is disabled. Once the HPI is
disabled, the HPIENA pin has no effect until the 5409 is reset.
Pulldown
resistor
HPIENA
I
HPI 16-bit select pin (internal pulldown, default HPI8). HPI16 = 1 selects the non-multiplexed mode.
The non-multiplexed mode allows hosts with separate address/data buses to access the HPI
address range via the 16 address pins (A15–A0). 16-bit data is also accessible through pins D0
through D15. Host-to-DSP and DSP-to-Host interrupts are not supported. There are no HPIC and
HPIA register accesses in the non-multiplexed mode.
Pulldown
resistor
HPI16
I
The HPI16 pin is sampled at RESET. The user should never change the value of the HPI16 pin while
the RESET signal is HIGH.
SUPPLY PINS
CV
DV
S
S
S
+V . Dedicated 1.8-V power supply for the core CPU
DD
DD
DD
+V . Dedicated 3.3-V power supply for the I/O pins
DD
V
Ground
SS
TEST PINS
IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle.
The changes on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP
controller, instruction register, or selected test data register on the rising edge of TCK. Changes at
the TAP output signal (TDO) occur on the falling edge of TCK.
Schmitt
trigger/pullup
resistor
TCK
I
Pullup
resistor
IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected
register (instruction or data) on a rising edge of TCK.
TDI
I
O/Z
I
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data)
are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when
the scanning of data is in progress. TDO also goes into the high-impedance state when OFF is low.
TDO
TMS
Pullup
resistor
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is
clocked into the TAP controller on the rising edge of TCK.
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system
control of the operations of the device. If TRST is not connected or is driven low, the device operates
in its functional mode, and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown
device.
Pulldown
resistor
TRST
I
†
I = Input, O = Output, Z = High-impedance, S = Supply
46
SPRS082E
April 1999 − Revised February 2004
Functional Overview
Table 3−19. Terminal Functions (Continued)
INTERNAL
PIN STATE
TERMINAL
NAME
†
I/O
DESCRIPTION
Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition.
When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is
defined as input/output by way of the IEEE standard 1149.1 scan system.
EMU0
I/O/Z
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt
to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1
scan system. When TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal,
when active low, puts all output drivers into the high-impedance state. Note that OFF is used
exclusively for testing and emulation purposes (not for multiprocessing applications). Therefore, for
the OFF feature, the following apply:
EMU1/OFF
I/O/Z
TRST = low
EMU0 = high
EMU1/OFF = low
†
I = Input, O = Output, Z = High-impedance, S = Supply
47
April 1999 − Revised February 2004
SPRS082E
Documentation Support
4
Documentation Support
Extensive documentation supports all TMS320t DSP family of devices from product announcement through
applications development. The following types of documentation are available to support the design and use
of the C5000 family of DSPs:
•
•
•
•
•
TMS320C54xt DSP Functional Overview (literature number SPRU307)
Device-specific data sheets (such as this document)
Complete User Guides
Development-support tools
Hardware and software application reports
The five-volume TMS320C54x DSP Reference Set (literature number SPRU210) consists of:
•
•
•
•
•
Volume 1: CPU and Peripherals (literature number SPRU131)
Volume 2: Mnemonic Instruction Set (literature number SPRU172)
Volume 3: Algebraic Instruction Set (literature number SPRU179)
Volume 4: Applications Guide (literature number SPRU173)
Volume 5: Enhanced Peripherals (literature number SPRU302)
The reference set describes in detail the TMS320C54x products currently available, and the hardware and
software applications, including algorithms, for fixed-point TMS320 devices.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 newsletter, Details on Signal Processing, is published
quarterly and distributed to update TMS320 customers on product information.
Information regarding TIt DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
TMS320, TMS320C5000, and TI are trademarks of Texas Instruments.
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4.1 Device and Development Tool Support Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical
specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
TMS Fully-qualified production device
Support tool development evolutionary flow:
TMDX Development support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development support product
TMX and TMP devices and TMDX development−support tools are shipped with appropriate disclaimers
describing their limitations and intended uses. Experimental devices (TMX) may not be representative of a
final product and Texas Instruments reserves the right to change or discontinue these products without notice.
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because
their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
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5
Electrical Specifications
5.1 Absolute Maximum Ratings
†
Supply voltage I/O range, DV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.0 V
DD
Supply voltage core range, CV † . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 2.4 V
DD
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.5 V
I
Output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.5 V
O
Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 100°C
C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
stg
NOTE: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
†
All voltage values are with respect to V
.
SS
5.2 Recommended Operating Conditions
MIN NOM
MAX
3.6
UNIT
V
‡
DV
CV
Device supply voltage, I/O
Device supply voltage, core
3
3.3
1.8
DD
DD
‡
1.71
1.98
V
V
V
Supply voltage, GND
0
V
SS
RS, INTn, NMI, BIO, BCLKR0, BCLKR1,
BCLKR2, BCLKX0, BCLKX1, BCLKX2, HAS,
2.2
DV + 0.3
DD
HCS, HDS1, HDS2, TCK, CLKMDn, DV
=
DD
3.3"0.3 V
High-level input voltage, I/O
V
IH
TRST
2.5
1.4
2.0
DV + 0.3
DD
X2/CLKIN
All other inputs
CV + 0.3
DD
DV + 0.3
DD
RS, INTn, NMI, X2/CLKIN, BIO, BCLKR0,
BCLKR1, BCLKR2, BCLKX0, BCLKX1,
BCLKX2, HAS, HCS, HDS1, HDS2, TCK,
−0.3
−0.3
0.6
0.8
V
Low-level input voltage
V
IL
CLKMDn, DV = 3.3"0.3 V
DD
All other inputs
I
I
High-level output current
Low-level output current
Operating case temperature
−300
1.5
µA
mA
°C
OH
OL
T
−40
100
C
‡
Texas Instrument DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be
designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage.
Excessive exposure to these conditions can adversely affect the long-term reliability of the devices. System-level concerns such as bus
contention may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as or prior
to the I/O buffers, and then powered down after the I/O buffers.
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5.3 Electrical Characteristics
†
PARAMETER
TEST CONDITIONS
MIN
2.4
TYP
MAX
UNIT
V
V
I
I
= MAX
= MAX
V
High-level output voltage
Low-level output voltage
OH
OL
OH
OL
0.4
V
Bus holders enabled, DV = MAX,
DD
Input current for
outputs in high
impedance
D[15:0], HD[7:0], A[15:0]
−200
200
V = V to DV
I
SS
DD
I
µA
IZ
All other inputs
X2/CLKIN
DV = MAX, V = V to DV
−5
5
DD
O
SS
DD
−40
40
TRST
With internal pulldown
With internal pulldown
−5
−5
200
200
Input current
HPIENA, HPI16
(V = V
I SS
I
µA
I
to DV
)
DD
With internal pullups,
HPIENA = 0
}
TMS, TCK, TDI, HPI
−200
−5
5
5
All other input-only pins
w
¶
#
I
I
Supply current, core CPU
CV = 1.8 V, f
= 100 MHz, T = 25°C
37
mA
DDC
DDP
DD
clock
C
w
Supply current, pins
DV = 3.3 V, f
= 100 MHz, T = 25°C
45
2
mA
mA
DD
clock
C
IDLE2
IDLE3
PLL × 2 mode, 50 MHz input
Supply current,
standby
I
DD
Divide-by-two mode, CLKIN stopped
20
µA
C
C
Input capacitance
Output capacitance
5
5
pF
pF
i
o
†
‡
§
¶
All values are typical unless otherwise specified.
HPI input signals except for HPIENA.
Clock mode: PLL × 1 with external source
This value represents the current consumption of the CPU, on-chip memory, and on-chip peripherals. Conditions include: program execution from
on-chip RAM, with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being executed.
This value was obtained using the following conditions: external memory writes at a rate of 20 million writes per second, CLKOFF=0, full-duplex
operation of all three McBSPs at a rate of 10 million bits per second each, and 15-pF loads on all outputs. For more details on how this calculation
is performed, refer to the Calculation of TMS320LC54x Power Dissipation Application Report (literature number SPRA164).
#
The following load circuit in Figure 5−1 was used on all outputs pins and I/O pins in input mode. All timing
measurements in this data sheet were measured from the 5409 connection to the following load circuit.
I
OL
50 Ω
Output
Under
Test
Tester Pin
Electronics
V
Load
C
T
I
OH
Where:
I
I
= 1.5 mA (all outputs)
= 300 µA (all outputs)
= 1.5 V
OL
OH
V
Load
C
T
= 40-pF typical load circuit capacitance
Figure 5−1. 3.3-V Test Load Circuit
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5.4 Internal Oscillator with External Crystal
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT
is a multiple of the oscillator frequency. The multiply ratio is determined by the bit settings in the CLKMD
register. The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series
resistance of 30 Ω and power dissipation of 1 mW.
The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in Figure 5−2.
The load capacitors, C and C , should be chosen such that the equation below is satisfied. C in the equation
1
2
L
is the load specified for the crystal.
C1C2
(C1 ) C2)
CL +
Table 5−1. Recommended Operating Conditions of Internal Oscillator With External Crystal
MIN
MAX
UNIT
f
Input clock frequency
10
20
MHz
clock
X1
X2/CLKIN
Crystal
C1
C2
Figure 5−2. Internal Oscillator With External Crystal
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5.5 Divide-By-Two/Divide-By-Four Clock Option (PLL Disabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four
to generate the internal machine cycle. The selection of the clock mode is described in the clock generator
section.
When an external clock source is used, the frequency injected must conform to specifications listed in the
timing requirements table. Table 5−2 and Table 5−3 assumes testing over recommended operating conditions
and H = 0.5t
(see Figure 5−3).
c(CO)
Table 5−2. Divide-By-Two/Divide-By-Four Clock Option (PLL Disabled) Timing Requirements
MIN
MAX
UNIT
ns
†
t
t
t
Cycle time, X2/CLKIN
Fall time, X2/CLKIN
Rise time, X2/CLKIN
20
c(CI)
f(CI)
r(CI)
8
8
ns
ns
tw(CIL) Pulse duration, X2/CLKIN low
tw(CIH) Pulse duration, X2/CLKIN high
5
5
ns
ns
†
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz.
approaching ∞. The device is characterized at frequencies
c(CI)
Table 5−3. Divide-By-Two/Divide-By-Four Clock Option (PLL Disabled) Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
ns
†
t
t
t
t
t
t
Cycle time, CLKOUT
40 2t
c(CO)
c(CI)
Delay time, X2/CLKIN high to CLKOUT high/low
Fall time, CLKOUT
4
10
17
ns
d(CIH-CO)
f(CO)
2
2
ns
Rise time, CLKOUT
ns
r(CO)
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
H−2
H−2
H−1
H−1
H
H
ns
w(COL)
w(COH)
ns
†
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz.
approaching ∞. The device is characterized at frequencies
c(CI)
t
t
r(CI)
w(CIH)
t
t
f(CI)
w(CIL)
t
c(CI)
X2/CLKIN
CLKOUT
t
w(COH)
t
f(CO)
t
c(CO)
t
r(CO)
t
d(CIH-CO)
t
w(COL)
Figure 5−3. External Divide-by-Two Clock Timing
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5.6 Multiply-By-N Clock Option (PLL Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to
generate the internal machine cycle. The selection of the clock mode and the value of N is described in the
clock generator section.
When an external clock source is used, the external frequency injected must conform to specifications listed
in the timing requirements table. Table 5−4 and Table 5−5 assumes testing over recommended operating
conditions and H = 0.5t
(see Figure 5−4).
c(CO)
Table 5−4. Multiply-By-N Clock Option (PLL Enabled) Timing Requirements
MIN
MAX
200
100
50
UNIT
‡
Integer PLL multiplier N (N = 1−15)
PLL multiplier N = x.5
20
20
20
‡
‡
t
Cycle time, X2/CLKIN
ns
c(CI)
PLL multiplier N = x.25, x.75
t
t
Fall time, X2/CLKIN
Rise time, X2/CLKIN
8
8
ns
ns
ns
ns
f(CI)
r(CI)
tw(CIL) Pulse duration, X2/CLKIN low
tw(CIH) Pulse duration, X2/CLKIN high
N = Multiplication factor
5
5
†
‡
The multiplication factor and minimum X2/CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within the specified
range (tc(CO))
Table 5−5. Multiply-By-N Clock Option (PLL Enabled) Switching Characteristics
−80
−100
PARAMETER
Cycle time, CLKOUT
UNIT
MIN
12.5
4
TYP
MAX
MIN
10
4
TYP
MAX
†
†
t
t
/N
10
2
t
/N
10
2
ns
ns
ns
ns
ns
ns
ms
c(CO)
c(CI)
c(CI)
t
Delay time, X2/CLKIN high/low to CLKOUT high/low
Fall time, CLKOUT
17
17
d(CI-CO)
t
f(CO)
r(CO)
w(COL)
w(COH)
p
t
t
t
t
Rise time, CLKOUT
2
2
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
Transitory phase, PLL lock up time
H−3
H−3
H−1
H−1
H
H
H−2
H−2
H−1
H−1
H
H
30
30
†
N = Multiplication factor
t
t
f(CI)
w(CIH)
t
t
r(CI)
w(CIL)
t
c(CI)
X2/CLKIN
t
d(CI-CO)
t
f(CO)
t
w(COH)
t
c(CO)
t
w(COL)
t
tp
r(CO)
Unstable
CLKOUT
Figure 5−4. External Multiply-by-One Clock Timing
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5.7 Memory and Parallel I/O Interface Timing
5.7.1 Memory Read
External memory reads can be performed in consecutive or nonconsecutive mode under control of the
CONSEC bit in the BSCR. Table 5−6 and Table 5−7 assume testing over recommended operating conditions
with MSTRB = 0 and H = 0.5t
(see Figure 5−5).
c(CO)
Table 5−6. Memory Read Timing Requirements
MIN
MAX
UNIT
ns
¶
t
t
t
t
t
Access time, read data access from address valid
2H−10
a(A)M
¶
Access time, read data access from MSTRB low
Setup time, read data before CLKOUT low
Hold time, read data after CLKOUT low
Hold time, read data after address invalid
Hold time, read data after MSTRB high
2H−10
ns
a(MSTRBL)
su(D)R
8
0
0
1
ns
ns
h(D)R
ns
h(A-D)R
t
ns
h(D)MSTRBH
†
‡
Address, PS, and DS timings are all included in timings referenced as address.
This access timing reflects a zero wait-state timing.
Table 5−7. Memory Read Switching Characteristics
PARAMETER
MIN
MAX
UNIT
ns
§
t
t
Delay time, CLKOUT low to address valid
0
0
0
0
0
0
3
3
3
3
3
3
d(CLKL-A)
d(CLKH-A)
¶
Delay time, CLKOUT high (transition) to address valid
Delay time, CLKOUT low to MSTRB low
ns
t
ns
d(CLKL-MSL)
t
Delay time, CLKOUT low to MSTRB high
ns
d(CLKL-MSH)
§
t
Hold time, address valid after CLKOUT low
ns
h(CLKL-A)R
h(CLKH-A)R
¶
t
Hold time, address valid after CLKOUT high
ns
†
§
¶
Address, PS, and DS timings are all included in timings referenced as address.
In the case of a memory read preceded by a memory read
In the case of a memory read preceded by a memory write
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CLKOUT
t
d(CLKL-A)
t
h(CLKL-A)R
A[22:0]
D[15:0]
t
h(A-D)R
t
su(D)R
t
a(A)M
t
h(D)R
t
h(D)MSTRBH
t
d(CLKL-MSL)
t
d(CLKL-MSH)
t
a(MSTRBL)
MSTRB
R/W
PS, DS
NOTE A: A[22:16] apply to DMA accesses to extended I/O, DATA, PROGRAM memory. The CPU has access to only extended
PROGRAM memory.
Figure 5−5. Memory Read
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5.7.2 Memory Write
Table 5−8 assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5t
(see
c(CO)
Figure 5−6).
†
Table 5−8. Memory Write Switching Characteristics
PARAMETER
MIN
MAX
UNIT
‡
t
t
Delay time, CLKOUT high to address valid
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(CLKH-A)
d(CLKL-A)
§
Delay time, CLKOUT low to address valid
Delay time, CLKOUT low to MSTRB low
Delay time, CLKOUT low to data valid
Delay time, CLKOUT low to MSTRB high
Delay time, CLKOUT high to R/W low
Delay time, CLKOUT high to R/W high
Delay time, R/W low to MSTRB low
0
3
t
0
3
d(CLKL-MSL)
t
0
8
d(CLKL-D)W
t
0
3
d(CLKL-MSH)
t
0
0
4
4
d(CLKH-RWL)
t
d(CLKH-RWH)
t
H − 2
0
H + 1
3
d(RWL-MSTRBL)
‡
t
Hold time, address valid after CLKOUT high
h(A)W
§
t
t
t
t
Hold time, write data valid after MSTRB high
Pulse duration, MSTRB low
H−3
2H−2
2H−2
H+6
ns
ns
ns
ns
h(D)MSH
w(SL)MS
su(A)W
Setup time, address valid before MSTRB low
Setup time, write data valid before MSTRB high
§
2H−6 2H+6
H−5
su(D)MSH
t
t
Enable time, data bus driven after R/W low
ns
ns
en(D−RWL)
dis(RWH−D)
Disable time, R/W high to data bus high impedance
0
†
‡
§
Address, PS, and DS timings are all included in timings referenced as address.
In the case of a memory write preceded by a memory write
In the case of a memory write preceded by an I/O cycle
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CLKOUT
t
d(CLKH-A)
t
d(CLKL-A)
t
h(A)W
A[22:0]
D[15:0]
MSTRB
R/W
t
d(CLKL-D)W
t
h(D)MSH
t
su(D)MSH
t
d(CLKL-MSL)
t
dis(RWH-D)
t
d(CLKL-MSH)
t
su(A)W
t
t
d(CLKH-RWL)
d(CLKH-RWH)
t
t
w(SL)MS
en(D-RWL)
t
d(RWL-MSTRBL)
PS, DS
NOTE A: A[22:16] apply to DMA accesses to extended I/O, DATA, PROGRAM memory. The CPU has access to only extended
PROGRAM memory.
Figure 5−6. Memory Write
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5.7.3 Parallel I/O Port Read
Table 5−9 and Table 5−10 assume testing over recommended operating conditions, IOSTRB = 0, and
H = 0.5t (see Figure 5−7).
c(CO)
†
Table 5−9. Parallel I/O Read Port Timing Requirements
MIN
MAX
3H−9
2H−8
UNIT
ns
‡
t
t
t
t
t
Access time, read data access from address valid
a(A)IO
‡
Access time, read data access from IOSTRB low
Setup time, read data before CLKOUT high
Hold time, read data after CLKOUT high
Hold time, read data after IOSTRB high
ns
a(ISTRBL)IO
su(D)IOR
8
0
0
ns
ns
h(D)IOR
ns
h(ISTRBH-D)R
†
‡
Address and IS timings are included in timings referenced as address.
This access timing reflects a zero wait-state timing.
†
Table 5−10. Parallel I/O Port Read Switching Characteristics
PARAMETER
Delay time, CLKOUT low to address valid
Delay time, CLKOUT high to IOSTRB low
Delay time, CLKOUT high to IOSTRB high
Hold time, address after CLKOUT low
MIN
MAX
UNIT
ns
t
0
0
0
0
3
3
3
3
d(CLKL-A)
t
ns
d(CLKH-ISTRBL)
t
ns
d(CLKH-ISTRBH)
t
ns
h(A)IOR
†
Address and IS timings are included in timings referenced as address.
CLKOUT
t
t
h(A)IOR
d(CLKL-A)
A[22:0]
t
h(D)IOR
t
su(D)IOR
t
a(A)IO
D[15:0]
t
h(ISTRBH-D)R
d(CLKH-ISTRBH)
t
a(ISTRBL)IO
t
t
d(CLKH-ISTRBL)
IOSTRB
R/W
IS
NOTE A: A[22:16] apply to DMA accesses to extended I/O, DATA, PROGRAM memory. The CPU has access to only extended
PROGRAM memory.
Figure 5−7. Parallel I/O Port Read
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5.7.4 Parallel I/O Port Write
Table 5−11 assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5t
Figure 5−8).
(see
c(CO)
†
Table 5−11. Parallel I/O Port Write Switching Characteristics
PARAMETER
Delay time, CLKOUT low to address valid
Delay time, CLKOUT high to IOSTRB low
Delay time, CLKOUT high to write data valid
Delay time, CLKOUT high to IOSTRB high
Delay time, CLKOUT low to R/W low
MIN MAX
UNIT
t
0
0
3
3
ns
ns
ns
ns
ns
ns
d(CLKL-A)
t
d(CLKH-ISTRBL)
t
H−5
0
H+8
3
d(CLKH-D)IOW
t
d(CLKH-ISTRBH)
t
0
3
d(CLKL-RWL)
d(CLKL-RWH)
t
t
t
t
t
Delay time, CLKOUT low to R/W high
0
3
Hold time, address valid after CLKOUT low
Hold time, write data after IOSTRB high
Setup time, write data before IOSTRB high
Setup time, address valid before IOSTRB low
0
H−3
H−7
H−2
3
H+7
H+1
H+2
ns
ns
ns
ns
h(A)IOW
h(D)IOW
su(D)IOSTRBH
su(A)IOSTRBL
†
Address and IS timings are included in timings referenced as address.
CLKOUT
t
su(A)IOSTRBL
t
h(A)IOW
t
d(CLKL-A)
A[22:0]
t
d(CLKH-D)IOW
t
h(D)IOW
D[15:0]
t
d(CLKH-ISTRBL)
t
d(CLKH-ISTRBH)
t
su(D)IOSTRBH
IOSTRB
R/W
t
t
d(CLKL-RWH)
d(CLKL-RWL)
IS
NOTE A: A[22:16] apply to DMA accesses to extended I/O, DATA, PROGRAM memory. The CPU has access to only extended
PROGRAM memory.
Figure 5−8. Parallel I/O Port Write
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5.8 Ready Timing for Externally Generated Wait States
Table 5−12 and Table 5−13 assume testing over recommended operating conditions and H = 0.5t
Figure 5−9, Figure 5−10, Figure 5−11, and Figure 5−12).
(see
c(CO)
†
Table 5−12. Ready Timing Requirements for Externally Generated Wait States
MIN
7
MAX
UNIT
t
t
t
t
t
t
Setup time, READY before CLKOUT low
Hold time, READY after CLKOUT low
ns
ns
ns
ns
ns
ns
su(RDY)
0
h(RDY)
‡
Valid time, READY after MSTRB low
4H−9
5H−9
v(RDY)MSTRB
h(RDY)MSTRB
v(RDY)IOSTRB
h(RDY)IOSTRB
‡
Hold time, READY after MSTRB low
4H
5H
‡
Valid time, READY after IOSTRB low
‡
Hold time, READY after IOSTRB low
†
‡
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using
READY, at least two software wait states must be programmed.
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
†
Table 5−13. Ready Switching Characteristics for Externally Generated Wait States
PARAMETER
Delay time, CLKOUT low to MSC low
Delay time, CLKOUT low to MSC high
MIN
MAX
UNIT
ns
t
0
3
d(MSCL)
t
0
3
ns
d(MSCH)
†
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
CLKOUT
A[22:0]
t
su(RDY)
t
h(RDY)
READY
MSTRB
MSC
t
v(RDY)MSTRB
t
h(RDY)MSTRB
t
v(MSCH)
t
v(MSCL)
Wait State
Generated
by READY
Wait States
Generated Internally
NOTE A: A[22:16] apply to DMA accesses to extended I/O, DATA, PROGRAM memory. The CPU has access to only extended
PROGRAM memory.
Figure 5−9. Memory Read With Externally Generated Wait States
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CLKOUT
A[22:0]
D[15:0]
READY
MSTRB
MSC
t
h(RDY)
t
su(RDY)
t
v(RDY)MSTRB
t
h(RDY)MSTRB
t
v(MSCH)
t
v(MSCL)
Wait States
Generated Internally
Wait State Generated
by READY
NOTE A: A[22:16] apply to DMA accesses to extended I/O, DATA, PROGRAM memory. The CPU has access to only extended
PROGRAM memory.
Figure 5−10. Memory Write With Externally Generated Wait States
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CLKOUT
A[22:0]
READY
IOSTRB
MSC
t
h(RDY)
t
su(RDY)
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
t
v(MSCH)
t
v(MSCL)
Wait State Generated
by READY
Wait
States
Generated
Internally
NOTE A: A[22:16] apply to DMA accesses to extended I/O, DATA, PROGRAM memory. The CPU has access to only extended
PROGRAM memory.
Figure 5−11. I/O Read With Externally Generated Wait States
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CLKOUT
A[22:0]
D[15:0]
READY
t
h(RDY)
t
su(RDY)
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
IOSTRB
MSC
t
v(MSCH)
t
v(MSCL)
Wait State Generated
by READY
Wait States
Generated
Internally
NOTE A: A[22:16] apply to DMA accesses to extended I/O, DATA, PROGRAM memory. The CPU has access to only extended
PROGRAM memory.
Figure 5−12. I/O Write With Externally Generated Wait States
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5.9 HOLD and HOLDA Timings
Table 5−14 and Table 5−15 assume testing over recommended operating conditions and H = 0.5t
Figure 5−13).
(see
c(CO)
Table 5−14. HOLD and HOLDA Timing Requirements
MIN
4H+8
8
MAX
UNIT
t
t
Pulse duration, HOLD low
ns
ns
w(HOLD)
su(HOLD)
Setup time, HOLD low/high before CLKOUT low
Table 5−15. HOLD and HOLDA Switching Characteristics
PARAMETER
MIN
MAX
5
UNIT
ns
t
t
t
t
t
t
Disable time, address, PS, DS, IS high impedance from CLKOUT low
Disable time, R/W high impedance from CLKOUT low
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low
Enable time, address, PS, DS, IS from CLKOUT low
Enable time, R/W enabled from CLKOUT low
dis(CLKL-A)
dis(CLKL-RW)
dis(CLKL-S)
en(CLKL-A)
en(CLKL-RW)
en(CLKL-S)
5
ns
5
ns
2H+5
2H+5
2H+5
ns
ns
Enable time, MSTRB, IOSTRB enabled from CLKOUT low
1
0
ns
4
4
ns
ns
ns
Valid time, HOLDA low after CLKOUT low
t
t
v(HOLDA)
w(HOLDA)
0
Valid time, HOLDA high after CLKOUT low
Pulse duration, HOLDA low duration
2H−1
CLKOUT
t
su(HOLD)
t
su(HOLD)
t
w(HOLD)
HOLD
t
t
v(HOLDA)
v(HOLDA)
t
w(HOLDA)
HOLDA
t
dis(CLKL-A)
t
en(CLKL-A)
A[22:0]
PS, DS, IS
D[15:0]
R/W
t
t
dis(CLKL-RW)
en(CLKL-RW)
t
en(CLKL-S)
t
t
dis(CLKL-S)
MSTRB
IOSTRB
t
dis(CLKL-S)
en(CLKL-S)
NOTE A: A[22:16] apply to DMA accesses to extended I/O, DATA, PROGRAM memory. The CPU has access to only extended
PROGRAM memory.
Figure 5−13. HOLD and HOLDA Timings
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5.10 Reset, BIO, Interrupt, and MP/MC Timings
Table 5−16 assumes testing over recommended operating conditions and H = 0.5t
Figure 5−15, and Figure 5−16).
(see Figure 5−14,
c(CO)
Table 5−16. Reset, BIO, Interrupt, and MP/MC Timing Requirements
MIN
0
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Hold time, RS after CLKOUT low
Hold time, BIO after CLKOUT low
h(RS)
0
h(BIO)
†
Hold time, INTn, NMI, after CLKOUT low
0
h(INT)
Hold time, MP/MC after CLKOUT low
0
h(MPMC)
w(RSL)
‡§
Pulse duration, RS low
4H+4
2H+1
4H
2H+1
4H
2H+1
4H
8
Pulse duration, BIO low, synchronous
w(BIO)S
w(BIO)A
w(INTH)S
w(INTH)A
w(INTL)S
w(INTL)A
w(INTL)WKP
su(RS)
Pulse duration, BIO low, asynchronous
Pulse duration, INTn, NMI high (synchronous)
Pulse duration, INTn, NMI high (asynchronous)
Pulse duration, INTn, NMI low (synchronous)
Pulse duration, INTn, NMI low (asynchronous)
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
¶
Setup time, RS before X2/CLKIN low
6
Setup time, BIO before CLKOUT low
7
10
10
su(BIO)
Setup time, INTn, NMI, RS before CLKOUT low
Setup time, MP/MC before CLKOUT low
8
su(INT)
8
su(MPMC)
†
‡
The external interrupts (INT0−INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is
corresponding to three CLKOUT sampling sequences.
If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure synchronization
and lock-in of the PLL.
§
¶
Note that RS may cause a change in clock frequency, therefore changing the value of H.
Divide-by-two mode
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X2/CLKIN
RS, INTn, NMI
CLKOUT
t
su(RS)
t
w(RSL)
t
su(INT)
t
h(RS)
t
su(BIO)
t
h(BIO)
BIO
t
w(BIO)S
Figure 5−14. Reset and BIO Timings
CLKOUT
t
t
su(INT)
t
su(INT)
h(INT)
INTn, NMI
t
w(INTH)A
t
w(INTL)A
Figure 5−15. Interrupt Timing
CLKOUT
RS
t
h(MPMC)
t
su(MPMC)
MP/MC
Figure 5−16. MP/MC Timing
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5.11 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
Table 5−17 assumes testing over recommended operating conditions and H = 0.5t
(see Figure 5−17).
c(CO)
Table 5−17. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics
PARAMETER
Delay time, CLKOUT low to IAQ low
MIN
0
MAX
UNIT
ns
t
3
3
1
3
3
1
d(CLKL-IAQL)
t
t
Delay time, CLKOUT low to IAQ high
Delay time, address valid to IAQ low
Delay time, CLKOUT low to IACK low
Delay time , CLKOUT low to IACK high
Delay time, address valid to IACK low
Hold time, IAQ high after address invalid
Hold time, IACK high after address invalid
Pulse duration, IAQ low
0
ns
d(CLKL-IAQH)
d(A)IAQ
ns
t
0
0
ns
d(CLKL-IACKL)
t
ns
d(CLKL-IACKH)
d(A)IACK
h(A)IAQ
t
t
t
t
t
ns
− 2
− 2
ns
ns
h(A)IACK
w(IAQL)
2H−2
2H−2
ns
Pulse duration, IACK low
ns
w(IACKL)
CLKOUT
A[22:0]
t
t
t
d(CLKL-IAQH)
d(CLKL-IAQL)
t
h(A)IAQ
t
d(A)IAQ
t
w(IAQL)
IAQ
t
d(CLKL-IACKH)
d(CLKL-IACKL)
t
h(A)IACK
t
d(A)IACK
t
w(IACKL)
IACK
MSTRB
NOTE A: A[22:16] apply to DMA accesses to extended I/O, DATA, PROGRAM memory. The CPU has access to only extended
PROGRAM memory.
Figure 5−17. IAQ and IACK Timings
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5.12 External Flag (XF) and TOUT Timings
Table 5−18 assumes testing over recommended operating conditions and H = 0.5t
Figure 5−19).
(see Figure 5−18 and
c(CO)
Table 5−18. External Flag (XF) and TOUT Switching Characteristics
PARAMETER
MIN
0
MAX
UNIT
Delay time, CLKOUT low to XF high
2
2
t
ns
d(XF)
Delay time, CLKOUT low to XF low
0
t
t
t
Delay time, CLKOUT low to TOUT high
Delay time, CLKOUT low to TOUT low
Pulse duration, TOUT
0
0
4
4
ns
ns
ns
d(TOUTH)
d(TOUTL)
w(TOUT)
2H
CLKOUT
t
d(XF)
XF
Figure 5−18. XF Timing
CLKOUT
TOUT
t
t
d(TOUTL)
d(TOUTH)
t
w(TOUT)
Figure 5−19. TOUT Timing
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5.13 Multichannel Buffered Serial Port (McBSP) Timing
5.13.1 McBSP Transmit and Receive Timings
Table 5−19 and Table 5−20 assume testing over recommended operating conditions and H = 0.5t
Figure 5−20 and Figure 5−21).
(see
c(CO)
†
Table 5−19. McBSP Transmit and Receive Timing Requirements
MIN
MAX
UNIT
t
t
Cycle time, BCLKR/X
BCLKR/X ext
BCLKR/X ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKR/X ext
BCLKR/X ext
4H
ns
ns
c(BCKRX)
w(BCKRX)
Pulse duration, BCLKR/X or BCLKR/X high
2H−1
0
4
0
4
0
4
7
2
7
2
7
2
t
t
t
t
t
t
Hold time, external BFSR high after BCLKR low
Hold time, BDR valid after BCLKR low
ns
ns
ns
ns
ns
ns
h(BCKRL-BFRH)
h(BCKRL-BDRV)
h(BCKXL-BFXH)
su(BFRH-BCKRL)
su(BDRV-BCKRL)
su(BFXH-BCKXL)
Hold time, external BFSX high after BCLKX low
Setup time, external BFSR high before BCLKR low
Setup time, BDR valid before BCLKR low
Setup time, external BFSX high before BCLKX low
t
t
Rise time, BCKR/X
Fall time, BCKR/X
8
8
ns
ns
r(BCKRX)
f(BCKRX)
†
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
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†
Table 5−20. McBSP Transmit and Receive Switching Characteristics
PARAMETER
MIN
MAX
UNIT
ns
t
t
t
t
Cycle time, BCLKR/X
BCLKR/X int
BCLKR/X int
BCLKR/X int
BCLKR int
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
4H
c(BCKRX)
‡
‡
Pulse duration, BCLKR/X high
D−3
D+1
ns
w(BCKRXH)
w(BCKRXL)
d(BCKRH-BFRV)
‡
‡
Pulse duration, BCLKR/X low
C−3
C+1
ns
Delay time, BCLKR high to internal BFSR valid
−2
0
2
6
ns
t
t
Delay time, BCLKX high to internal BFSX valid
ns
ns
d(BCKXH-BFXV)
4
12
7
−4
3
Disable time, BCLKX high to BDX high impedance following last data bit
dis(BCKXH-BDXHZ)
9
0
7
Delay time, BCLKX high to BDX valid. This applies to all bits except the first
bit transmitted.
4
12
§¶
t
ns
d(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid.
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BFSX int
7
DXENA = 0
DXENA = 0
DXENA = 0
DXENA = 0
Only applies to first bit transmitted when in Data Delay 1
or 2 (XDATDLY=01b or 10b) modes
12
§¶
Enable time, BCLKX high to BDX driven.
−4
t
t
t
ns
ns
ns
Only applies to first bit transmitted when in Data Delay 1
or 2 (XDATDLY=01b or 10b) modes
e(BCKXH-BDX)
d(BFXH-BDXV)
e(BFXH-BDX)
2
§¶
Delay time, BFSX high to BDX valid.
2
Only applies to first bit transmitted when in Data Delay 0
(XDATDLY=00b) mode.
BFSX ext
BFSX int
12
§¶
Enable time, BFSX high to BDX driven.
−1
Only applies to first bit transmitted when in Data Delay 0
(XDATDLY=00b) mode
BFSX ext
2
†
‡
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
T=BCLKRX period = (1 + CLKGDV) * 2H
C=BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D=BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
See the TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302) for a description of the DX enable
(DXENA) and data delay features of the McBSP.
§
¶
The transmit delay enable (DXENA) and A-bis mode (ABIS) features of the McBSP are not implemented on the TMS320VC5409.
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t
t
t
c(BCKRX)
w(BCKRXH)
w(BCKRXL)
t
r(BCKRX)
BCLKR
t
d(BCKRH−BFRV)
t
t
r(BCKRX)
d(BCKRH−BFRV)
BFSR (int)
t
su(BFRH−BCKRL)
t
h(BCKRL−BFRH)
BFSR (ext)
t
h(BCKRL−BDRV)
t
su(BDRV−BCKRL)
BDR
Bit (n−1)
(n−2)
(n−3)
(n−4)
(n−3)
(RDATDLY=00b)
t
su(BDRV−BCKRL)
t
h(BCKRL−BDRV)
BDR
(RDATDLY=01b)
Bit (n−1)
(n−2)
t
su(BDRV−BCKRL)
t
h(BCKRL−BDRV)
BDR
(RDATDLY=10b)
Bit (n−1)
(n−2)
Figure 5−20. McBSP Receive Timings
t
t
c(BCKRX)
w(BCKRXH)
t
r(BCKRX)
t
f(BCKRX)
t
w(BCKRXL)
BCLKX
t
d(BCKXH−BFXV)
t
d(BCKXH−BFXV)
BFSX (int)
BFSX (ext)
t
su(BFXH−BCKXL)
t
h(BCKXL−BFXH)
t
d(BDFXH−BDXV)
t
t
t
d(BCKXH−BDXV)
e(BDFXH−BDX)
BDX
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−4)
(n−3)
(n−2)
(XDATDLY=00b)
d(BCKXH−BDXV)
t
e(BCKXH−BDX)
BDX
Bit (n−1)
(n−2)
Bit 0
(XDATDLY=01b)
t
t
d(BCKXH−BDXV)
dis(BCKXH−BDXHZ)
t
e(BCKXH−BDX)
BDX
Bit 0
Bit (n−1)
(XDATDLY=10b)
Figure 5−21. McBSP Transmit Timings
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5.13.2 McBSP General-Purpose I/O Timing
Table 5−21 and Table 5−22 assume testing over recommended operating conditions (see Figure 5−22).
Table 5−21. McBSP General-Purpose I/O Timing Requirements
MIN
9
MAX
UNIT
ns
†
t
t
Setup time, BGPIOx input mode before CLKOUT high
su(BGPIO-COH)
h(COH-BGPIO)
†
Hold time, BGPIOx input mode after CLKOUT high
0
ns
†
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
Table 5−22. McBSP General-Purpose I/O Switching Characteristics
PARAMETER
MIN
MAX
UNIT
‡
t
Delay time, CLKOUT high to BGPIOx output mode
−10
10
ns
d(COH-BGPIO)
‡
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
t
t
su(BGPIO-COH)
d(COH-BGPIO)
CLKOUT
t
h(COH-BGPIO)
BGPIOx Input
†
Mode
BGPIOx Output
‡
Mode
†
‡
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
Figure 5−22. McBSP General-Purpose I/O Timings
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5.13.3 McBSP as SPI Master or Slave Timing
Table 5−23 to Table 5−30 assume testing over recommended operating conditions and H = 0.5t
Figure 5−23, Figure 5−24, Figure 5−25, and Figure 5−26).
(see
c(CO)
†
Table 5−23. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
MASTER
SLAVE
UNIT
MIN
10
0
MAX
MIN MAX
t
t
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
− 12H
ns
ns
su(BDRV-BCKXL)
h(BCKXL-BDRV)
5 + 12H
10
t
t
Setup time, BFSX low before BCLKX high
Cycle time, BCLKX
ns
ns
su(BFXL-BCKXH)
c(BCKX)
12H
32H
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
†
Table 5−24. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
‡
MASTER
SLAVE
PARAMETER
UNIT
MIN
MAX
MIN MAX
§
t
t
t
Hold time, BFSX low after BCLKX low
T − 4 T + 4
C − 5 C + 3
ns
ns
ns
h(BCKXL-BFXL)
d(BFXL-BCKXH)
d(BCKXH-BDXV)
¶
Delay time, BFSX low to BCLKX high
Delay time, BCLKX high to BDX valid
− 3
7
6H + 5 10H + 14
Disable time, BDX high impedance following last data bit from
BCLKX low
t
C − 2 C + 3
ns
dis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
t
t
2H+ 3
6H + 17
8H + 17
ns
ns
dis(BFXH-BDXHZ)
d(BFXL-BDXV)
Delay time, BFSX low to BDX valid
4H + 2
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
§
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
¶
t
c(BCKX)
MSB
LSB
t
su(BFXL-BCKXH)
BCLKX
BFSX
t
h(BCKXL-BFXL)
t
d(BFXL-BCKXH)
t
dis(BFXH-BDXHZ)
t
d(BFXL-BDXV)
t
t
d(BCKXH-BDXV)
dis(BCKXL-BDXHZ)
BDX
BDR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCLXL)
t
h(BCKXL-BDRV)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 5−23. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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Documentation Support
†
Table 5−25. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
MASTER
SLAVE
UNIT
MIN
10
0
MAX
MIN MAX
t
t
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX high
− 12H
ns
ns
su(BDRV-BCKXL)
h(BCKXH-BDRV)
5 + 12H
10
t
t
Setup time, BFSX low before BCLKX high
Cycle time, BCLKX
ns
ns
su(BFXL-BCKXH)
c(BCKX)
32H
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
†
Table 5−26. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
‡
MASTER
SLAVE
PARAMETER
UNIT
MIN
MAX
MIN MAX
§
t
t
t
Hold time, BFSX low after BCLKX low
C − 4 C + 4
T − 5 T + 3
ns
ns
ns
h(BCKXL-BFXL)
d(BFXL-BCKXH)
d(BCKXL-BDXV)
¶
Delay time, BFSX low to BCLKX high
Delay time, BCLKX low to BDX valid
− 3
7
6H + 5 10H + 14
6H + 3 10H + 17
Disable time, BDX high impedance following last data bit from
BCLKX low
t
− 2
4
ns
ns
dis(BCKXL-BDXHZ)
t
Delay time, BFSX low to BDX valid
D − 1 D + 4 4H − 2
8H + 17
d(BFXL-BDXV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
§
¶
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
t
t
c(BCKX)
MSB
su(BFXL-BCKXH)
LSB
BCLKX
t
t
d(BFXL-BCKXH)
h(BCKXL-BFXL)
BFSX
t
t
t
d(BCKXL-BDXV)
d(BFXL-BDXV)
dis(BCKXL-BDXHZ)
BDX
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCKXH)
t
h(BCKXH-BDRV)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
Figure 5−24. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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Documentation Support
†
Table 5−27. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
MASTER
SLAVE
UNIT
MIN
10
0
MAX
MIN MAX
t
t
Setup time, BDR valid before BCLKX high
Hold time, BDR valid after BCLKX high
− 12H
ns
ns
su(BDRV-BCKXH)
h(BCKXH-BDRV)
5 + 12H
10
t
t
Setup time, BFSX low before BCLKX low
Cycle time, BCLKX
ns
ns
su(BFXL-BCKXL)
c(BCKX)
32H
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
†
Table 5−28. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
‡
MASTER
SLAVE
PARAMETER
UNIT
MIN
MAX
MIN MAX
§
t
t
t
Hold time, BFSX low after BCLKX high
T − 4 T + 4
D − 5 D + 3
ns
ns
ns
h(BCKXH-BFXL)
d(BFXL-BCKXL)
d(BCKXL-BDXV)
¶
Delay time, BFSX low to BCLKX low
Delay time, BCLKX low to BDX valid
− 3
7
6H + 5 10H + 14
Disable time, BDX high impedance following last data bit from
BCLKX high
t
D − 2 D + 3
ns
dis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
t
t
2H + 3
6H + 17
8H + 17
ns
ns
dis(BFXH-BDXHZ)
d(BFXL-BDXV)
Delay time, BFSX low to BDX valid
4H − 2
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
§
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
¶
t
t
c(BCKX)
su(BFXL-BCKXL)
LSB
MSB
BCLKX
BFSX
t
h(BCKXH-BFXL)
t
d(BFXL-BCKXL)
t
t
d(BFXL-BDXV)
dis(BFXH-BDXHZ)
t
t
t
d(BCKXL-BDXV)
dis(BCKXH-BDXHZ)
BDX
BDR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCKXH)
h(BCKXH-BDRV)
(n-2)
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 5−25. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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†
Table 5−29. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
MASTER
SLAVE
UNIT
MIN
10
0
MAX
MIN MAX
t
t
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
− 12H
ns
ns
su(BDRV-BCKXL)
h(BCKXL-BDRV)
5 + 12H
10
t
t
Setup time, BFSX low before BCLKX low
Cycle time, BCLKX
ns
ns
su(BFXL-BCKXL)
c(BCKX)
32H
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
†
Table 5−30. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
‡
MASTER
SLAVE
PARAMETER
UNIT
MIN
MAX
MIN MAX
§
t
t
t
Hold time, BFSX low after BCLKX high
D − 4 D + 4
T − 5 T + 3
ns
ns
ns
h(BCKXH-BFXL)
d(BFXL-BCKXL)
d(BCKXH-BDXV)
¶
Delay time, BFSX low to BCLKX low
Delay time, BCLKX high to BDX valid
− 3
7
6H + 5 10H + 14
6H + 3 10H + 17
Disable time, BDX high impedance following last data bit from
BCLKX high
t
− 2
4
ns
ns
dis(BCKXH-BDXHZ)
t
Delay time, BFSX low to BDX valid
C − 1 C + 4 4H − 2
8H + 17
d(BFXL-BDXV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
§
¶
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
t
t
su(BFXL-BCKXL)
c(BCKX)
MSB
LSB
BCLKX
t
t
h(BCKXH-BFXL)
d(BFXL-BCKXL)
BFSX
t
t
t
dis(BCKXH-BDXHZ)
d(BCKXH-BDXV)
(n-2)
d(BFXL-BDXV)
BDX
Bit 0
Bit(n-1)
Bit(n-1)
(n-3)
(n-4)
t
su(BDRV-BCKXL)
t
h(BCKXL-BDRV)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
Figure 5−26. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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Documentation Support
5.14 Host-Port Interface Timing
5.14.1 HPI8 Mode
Table 5−31 and Table 5−32 assume testing over recommended operating conditions and H = 0.5t
(see
c(CO)
Figure 5−27 through Figure 5−30). In the following tables, DS refers to the logical OR of HCS, HDS1, and
HDS2. HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). HAD stands for HCNTL0, HCNTL1,
and HR/W.
†‡§
Table 5−31. HPI8 Mode Timing Requirements
MIN
5
MAX
UNIT
ns
t
t
t
t
t
t
t
Setup time, HBIL valid before DS low
Hold time, HBIL valid after DS low
Setup time, HAS low before DS low
Pulse duration, DS low
su(HBV-DSL)
h(DSL-HBV)
5
ns
5
ns
su(HSL-DSL)
w(DSL)
20
10
5
ns
Pulse duration, DS high
ns
w(DSH)
Setup time, HDx valid before DS high, HPI write
Hold time, HDx valid after DS high, HPI write
ns
su(HDV-DSH)
5
ns
h(DSH-HDV)W
†
‡
§
DS refers to the logical OR of HCS, HDS1, and HDS2.
HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).
GPIO refers to the HD pins when they are configured as general-purpose input/outputs.
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†‡§¶
Table 5−32. HPI8 Mode Switching Characteristics
PARAMETER
MIN
2
MAX
UNIT
t
Enable time, HD driven from DS low
19
ns
en(DSL-HD)
Case 1a: Memory accesses when
DMAC is active in 16-bit mode and
18H+19 – t
19
w(DSH)
t
< 18H
w(DSH)
Case 1b: Memory accesses when
DMAC is active in 16-bit mode and
t
≥ 18H
w(DSH)
Case 1c: Memory access when
DMAC is active in 32-bit mode and
26H+19 – t
19
w(DSH)
t
< 26H
Delay time, DS low to HDx valid for
first byte of an HPI read
w(DSH)
t
ns
d(DSL-HDV1)
Case 1d: Memory access when
DMAC is active in 32-bit mode and
t
≥ 26H
w(DSH)
Case 2a: Memory accesses when
DMAC is inactive and t < 10H
10H+19 – t
19
w(DSH)
w(DSH)
Case 2b: Memory accesses when
DMAC is inactive and t ≥ 10H
w(DSH)
Case 3: Register accesses
19
19
5
t
t
t
t
Delay time, DS low to HDx valid for second byte of an HPI read
Hold time, HDx valid after DS high, for a HPI read
Valid time, HDx valid after HRDY high
ns
ns
d(DSL-HDV2)
h(DSH-HDV)R
v(HYH-HDV)
d(DSH-HYL)
3
5
Delay time, DS high to HRDY low (see Note 1)
10
ns
ns
Case 1a: Memory accesses when
DMAC is active in 16-bit mode
18H+10
26H+10
10H+10
6H+10
Case 1b: Memory accesses when
DMAC is active in 32-bit mode
ns
ns
t
Delay time, DS high to HRDY high
d(DSH-HYH)
Case 2: Memory accesses when
DMAC is inactive
Case 3: Write accesses to HPIC
register (see Note 2)
15
2
ns
ns
ns
t
t
t
Delay time, HCS low/high to HRDY low/high
Delay time, CLKOUT high to HRDY high
Delay time, CLKOUT high to HINT change
d(HCS-HRDY)
)
d(COH-HYH
5
d(COH-HTX)
NOTES: 1. The HRDY output is always high when the HCS input is high, regardless of DS timings.
2. This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur
asynchronously, and do not cause HRDY to be deasserted.
DS refers to the logical OR of HCS, HDS1, and HDS2.
HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).
DMAC stands for direct memory access (DMA) controller. The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are
affected by DMAC activity.
†
‡
§
¶
GPIO refers to the HD pins when they are configured as general-purpose input/outputs.
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Second Byte
First Byte
Second Byte
HAS
t
su(HBV-DSL)
t
su(HSL-DSL)
t
h(DSL-HBV)
†
Valid
Valid
HAD
‡
t
su(HBV-DSL)
‡
t
h(DSL-HBV)
HBIL
HCS
t
w(DSH)
t
w(DSL)
HDS
t
d(DSH-HYH)
t
d(DSH-HYL)
HRDY
t
en(DSL-HD)
t
d(DSL-HDV2)
t
d(DSL-HDV1)
t
h(DSH-HDV)R
HD READ
HD WRITE
Valid
Valid
Valid
t
su(HDV-DSH)
t
v(HYH-HDV)
t
h(DSH-HDV)W
Valid
Valid
Valid
t
d(COH-HYH)
CLKOUT
†
HAD refers to HCNTL0, HCNTL1, and HR/W.
When HAS is not used (HAS always high)
‡
Figure 5−27. Using HDS to Control Accesses (HCS Always Low)
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Second Byte
First Byte
Second Byte
HCS
HDS
t
d(HCS-HRDY)
HRDY
Figure 5−28. Using HCS to Control Accesses
HRDY
t
d(COH−HYH)
CLKOUT
Figure 5−29. HRDY Relative to CLKOUT
CLKOUT
t
d(COH-HTX)
HINT
Figure 5−30. HINT Timing
81
April 1999 − Revised February 2004
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Documentation Support
5.14.2 HPI16 Mode
Table 5−33 and Table 5−34 assume testing over recommended operating conditions and H = 0.5t
(see
c(CO)
Figure 5−31 through Figure 5−32). In the following tables, DS refers to the logical OR of HCS, HDS1, and
HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). These timings are shown
assuming that HDS is the signal controlling the transfer. See the TMS320C54x DSP Reference Set, Volume
5: Enhanced Peripherals (literature number SPRU302) for additional information.
Table 5−33. HPI16 Mode Timing Requirements
MIN
5
MAX
UNIT
ns
†‡
†
t
t
Setup time, HAD valid before DS falling edge
su(HBV-DSL)
h(DSL-HBV)
†‡
Hold time, HAD valid after DS falling edge
5
ns
t
t
t
t
t
t
Setup time, HAD valid before DS falling edge
−4H+3
ns
ns
ns
ns
ns
ns
su(HAV-DSL)
h(DSH-HAV)
su(HDV-DSH)
h(DSH-HDV)W
w(DSL)
†
Hold time, address valid after DS rising edge
1
3
Setup time, Dx valid before DS high (HPI write)
Hold time, Dx valid after DS high (HPI write)
2
‡
Pulse duration, DS low
20
10
‡
Pulse duration, DS high
w(DSH)
Cycle time, DS rising edge to next DS rising
edge
Nonmultiplexed mode (no increment)
with no DMA activity.
12H
20H
ns
ns
‡
t
c(DSH-DSH)
Nonmultiplexed mode (no increment)
with 16-bit DMA activity.
(Minimum timings represent WRITEs while
maximum timings represent READs)
†
‡
DS refers to the logical OR of HCS and HDS1 and HDS2.
Dx refers to any of the HPI data bus pins (D0, D1, D2, etc.).
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†‡§¶
Table 5−34. HPI16 Mode Switching Characteristics
PARAMETER
MIN
MAX
UNIT
t
Enable time, Dx driven from DS low
6
19
ns
en(DSL-HD)
Case 1a: Memory accesses when
DMAC is active in 16-bit mode and
18H+19 – t
19
w(DSH)
t
< 18H
w(DSH)
Case 1b: Memory accesses when
DMAC is active in 16-bit mode and
t
≥ 18H
Delay time, DS low to Dx valid for an
HPI read
w(DSH)
t
t
ns
d(DSL-HDV1)
Case 2a: Memory accesses when
DMAC is inactive and t < 10H
10H+19 – t
19
w(DSH)
w(DSH)
Case 2b: Memory accesses when
DMAC is inactive and t ≥ 10H
w(DSH)
Case 3: Register accesses
19
8
Hold time, Dx valid after DS rising edge, read
Valid time, Dx valid before HRDY rising edge
Delay time, DS or HCS high to HRDY low
1
0
ns
ns
ns
h(DSH-HDV)R
6
tv
(HYH-HDV)
t
t
10
d(DSH-HYL)
Case 1: Memory access when DMAC
is active in 16-bit mode
18H+10
10H+10
Delay time, DS high to HRDY high
(writes and autoincrement reads)
ns
d(DSH-HYH)
Case 2: Memory access when DMAC
is inactive
t
t
Delay time, HDS or HCS low/high to HRDY low/high
Delay time, CLKOUT high to HRDY high
10
2
ns
ns
d(DSL-HYL)
d(COH−HYH)
NOTE: The HRDY output is always high when the HCS input is high, regardless of DS timings.
†
DS refers to the logical OR of HCS, HDS1, or HDS2.
Dx refers to any of the DPI data bus pins (D0, D1, D2, etc.).
DMAC stands for direct memory access (DMA) controller. The HPI16 shares the internal DMA bus with the DMAC, thus HPI16 access times are
affected by DMAC activity.
GPIO refers to the HD pins when they are configured as general-purpose input/outputs.
‡
§
¶
83
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HCS
t
c(DSH−DSH)
t
w(DSH)
HDS
t
w(DSL)
t
su(HBV−DSL)
t
h(DSL−HBV)
HR/W
t
t
h(DSH−HAV)
t
su(HAV−DSL)
HA[15:0]
(A[15:0])
Valid Address
Valid Address
t
d(DSL−HDV1)
h(DSH−HDV)R
t
en(DSL−HD)
D[15:0]
HRDY
Data Valid
Data Valid
t
v(HYH−HDV)
t
d(DSL−HYH)
Figure 5−31. Nonmultiplexed Read Timings
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HCS
HDS
t
w(DSH)
t
t
c(DSH−DSH)
t
t
su(HBV−DSL)
w(DSL)
h(DSL−HBV)
HR/W
t
su(HAV−DSH)
t
h(DSH−HAV)
HA[15:0]
A[15:0]
Valid Address
Data Valid
Valid Address
t
su(HDV−DSH)
t
h(DSH−HDV)W
D[15:0]
HRDY
Data Valid
t
d(DSH−HYH)
t
d(DSL−HYL)
Figure 5−32. Nonmultiplexed Write Timings
85
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Documentation Support
5.15 GPIO Timing Requirements
Table 5−35 to Table 5−36 assume testing over recommended operating conditions (see Figure 5−33).
Table 5−35. GPIO Timing Requirements
MIN
MAX
UNIT
Setup time, GPIOx input valid before CLKOUT high, GPIOx configured as
general-purpose input.
t
t
7
ns
su(GPIO-COH)
h(GPIO-COH)
Hold time, GPIOx input valid after CLKOUT high, GPIOx configured as general-purpose
input.
0
ns
Table 5−36. GPIO Switching Characteristics
PARAMETER
MIN
MAX
UNIT
Delay time, CLKOUT high to GPIOx output change. GPIOx configured as
general-purpose output.
t
0
6
ns
d(COH-GPIO)
CLKOUT
t
su(GPIO-COH)
t
h(GPIO-COH)
†
†
GPIOx Input Mode
t
d(COH-GPIO)
GPIOx Output Mode
†
GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O).
†
Figure 5−33. GPIOx Timings
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Mechanical Data
6
Mechanical Data
6.1
Ball Grid Array Mechanical Data
GGU (S−PBGA−N144)
PLASTIC BALL GRID ARRAY
12,10
11,90
SQ
9,60 TYP
0,80
N
M
L
K
J
H
G
F
E
D
C
B
A
A1 Corner
1
2
3
4
5
6 7 8 9 10 11 12 13
Bottom View
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,45
0,08
0,45
0,35
4073221-2/C 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice
C. MicroStar BGAt configuration
Figure 6−1. TMS320VC5416 144-Ball Plastic Ball Grid Array Package (GGU)
Table 6−1. Thermal Resistance Characteristics for 144-Ball GGU Package
PARAMETER
°C/W
R
Θ
56
JA
R
Θ
5
JC
MicroStar BGA is a trademark of Texas Instruments.
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Mechanical Data
6.2
Low-Profile Quad Flatpack Mechanical Data
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
M
0,08
0,50
0,13 NOM
144
37
1
36
Gage Plane
17,50 TYP
20,20
SQ
19,80
0,25
0,05 MIN
22,20
SQ
0°−ꢀ7°
21,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Figure 6−2. TMS320VC5416 144-Pin Low-Profile Quad Flatpack (PGE)
Table 6−2. Thermal Resistance Characteristics for 144-Ball PGE Package
PARAMETER
°C/W
R
Θ
38
JA
R
Θ
5
JC
88
SPRS082E
April 1999 − Revised February 2004
PACKAGE OPTION ADDENDUM
www.ti.com
29-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TMS320VC5409GGU-80
TMS320VC5409GGU100
TMS320VC5409PGE-80
ACTIVE
ACTIVE
ACTIVE
BGA
GGU
144
144
144
160
160
TBD
TBD
SNPB
SNPB
Level-3-220C-168HR
Level-3-220C-168HR
BGA
GGU
LQFP
PGE
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TMS320VC5409PGE100
TMS320VC5409ZGU-80
TMS320VC5409ZGU100
ACTIVE
ACTIVE
ACTIVE
LQFP
BGA
BGA
PGE
ZGU
ZGU
144
144
144
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
160 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168HR
160 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
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