TMS370C736A_技术文档

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

FZ AND FN PACKAGES

(TOP VIEW)

CMOS/EEPROM/EPROM Technologies on

a Single Device

– Mask-ROM Devices for High-Volume

Production

– One-Time-Programmable (OTP) EPROM

Devices for Low-Volume Production

– Reprogrammable-EPROM Devices for

Prototyping Purposes

Internal System Memory Configurations

– On-Chip Program Memory Versions

– ROM: 16K Bytes

6

5

4

3

2

1 44 43 42 41 40

39

AN3

AN4

A5

7

A4

8

38

37

36

35

34

33

32

31

AN5

A3

9

AN6

A2

10

11

12

13

14

15

16

17

AN7

A1

– EPROM: 16K Bytes

D6/CP6

D7/CP5

D4/CP4

D5/CP1

OP1/CP3

OP2/CP2

A0

– Data EEPROM: 256 Bytes

– Static RAM: 256 Bytes Usable as

Registers

– Standby RAM With Separate Power

Supply Pin: 256 Bytes

MC

RESET

SPICLK

30 SPISOMI

29 SPISIMO

18 19 20 21 22 23 24 25 26 27 28

Flexible Operating Features

– Low-Power Modes: STANDBY and HALT

– Commercial, Industrial, and Automotive

Temperature Ranges

– Clock Options

– Divide-by-1 (2 MHz–5 MHz SYSCLK)

Phase-Locked Loop (PLL)

– Divide-by-4 (0.5 MHz–5 MHz SYSCLK)

Serial Peripheral Interface (SPI)

– Variable-Length High-Speed Shift

Register

– Supply Voltage (V ) 5 V ±10%

CC

– Synchronous Master/Slave Operation

Programmable Acquisition and Control

Timer (PACT) Module

– Input Capture on up to Six Pins, Four of

Which Can Have a Programmable

Prescaler

– One Input Capture Pin Can Drive an 8-Bit

Event Counter

– Up to Eight Timer-Driven Outputs

– Interaction Between Event Counter and

Timer Activity

– 18 Independent Interrupt Vectors

– Watchdog With Selectable Time-Out

Period

– Asynchronous Mini Serial

Communication Interface (Mini SCI)

Flexible Interrupt Handling

– Two Software-Programmable Interrupt

Levels

Eight Channel 8-Bit Analog-to-Digital

Converter 1 (ADC1)

TMS370 Series Compatibility

– Register-to-Register Architecture

– 256 General-Purpose Registers

– 14 Powerful Addressing Modes

– Instructions Upwardly Compatible With

All TMS370 Devices

CMOS/TTL Compatible I/O Pins/Packages

– All Peripheral Function Pins Software

Configurable for Digital I/O

– 16 Bidirectional Pins, Nine Input Pins

– 44-Pin Plastic and Ceramic Leaded Chip

Carrier (LCC) Packages

Workstation/PC-Based Development

System

– C Compiler and C Source Debugger

– Real-Time In-Circuit Emulation

– Multi-Window User Interface

– Microcontroller Programmer

– Global- and Individual-Interrupt Masking

– Programmable Rising- or Falling-Edge

Detect

– Individual-Interrupt Vectors

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

Pin Descriptions

44 PINS

†

DESCRIPTION

I/O

NAME

NO.

A0

A1

A2

A3

A4

A5

A6

A7

34

35

36

37

38

39

40

41

I / O

Port A is a general-purpose bidirectional I/O port.

D3

27

14

15

12

13

Port D is a general-purpose bidirectional port. Also configurable as SYSCLK (see Note 1)

PACT input capture 4 (see Note 2)

PACT input capture 1 (see Note 2)

PACT input capture 6 (see Note 2)

PACT input capture 5 (see Note 2)

D4/CP4

D5/CP1

D6/CP6

D7/CP5

I / O

AN0/E0

AN1/E1

AN2/E2

AN3/E3

AN4/E4

AN5/E5

AN6/E6

AN7/E7

4

5

6

7

8

9

10

11

ADC1 analog input pins (AN0–AN7)/port E digital input pins (E0–E7)

Port E can be programmed individually as a general-purpose digital input pin if it is not used as ADC1 analog

input or positive reference input.

I

INT1

28

External interrupt (non-maskable or maskable)/general-purpose input pin

OP1/CP3

OP2/CP2

OP3

OP4

OP5

OP6

OP7

OP8

16

17

21

22

23

24

25

26

PACT PWM output 1/input capture 3 (see Note 3)

PACT output pin 2/input capture 2 (see Note 3)

PACT PWM output 3

PACT PWM output 4

PACT PWM output 5

PACT PWM output 6

PACT PWM output 7

PACT PWM output 8

O

SCIRXD

SCITXD

19

20

I

O

PACT mini SCI data receive input pin

PACT mini SCI data transmit output pin

SPISOMI

SPISIMO

SPICLK

30

29

31

SPI slave output pin, master input pin/general-purpose bidirectional pin

SPI slave input pin, master output pin/general-purpose bidirectional pin

SPI bidirectional serial clock pin/general-purpose bidirectional pin

I / O

System reset bidirectional pin; as input pin, RESET initializes the microcontroller; as open-drain output,

RESET indicates that an internal failure was detected by watchdog or oscillator fault circuit.

RESET

MC

32

33

I / O

I

Mode control input pin; enables EEPROM write protection override (WPO) mode, also EPROM V

PP

XTAL2/CLKIN

XTAL1

43

44

I

O

Internal oscillator crystal input/External clock source input

Internal oscillator output for crystal

V

1

18

2

3

42

Positive supply voltage for digital logic and digital I/O pins

Ground reference for digital logic and digital I/O pins

ADC1 positive supply voltage and optional positive reference input

ADC1 ground supply and low reference input pin

CC1

SS1

CC3

SS3

Positive supply voltage pin for standby RAM

CCSTBY

†

I = input, O = output

NOTES: 1. D3 can be configured as SYSCLK by appropriately programming the DPORT1 and DPORT2 registers.

2. These digital I/O buffers are connected internally to some of the PACT module’s input capture pins. This allows the microcontroller

to read the level on the input capture pin, or if the port D pin is configured as an output, to generate a capture. Be careful to leave

the port D pin configured as an input if the corresponding input capture pin is being driven by external circuitry.

3. CP2 and CP3 are connected internally to OP2 and OP1. CP2 and CP3 can be used only to capture OP2 and OP1, respectively and

not as external capture inputs.

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

functional block diagram

E0-E7

or

AN0-AN7

XTAL2/

CLKIN

INT1

XTAL1

MC

RESET

Clock Options:

Divide-By-4 or

Divide-By-1 (PLL)

V

CC3

System

Control

A-to-D

Converter 1

Interrupts

SS3

Serial

Peripheral

Interface

SPISOMI

SPISIMO

SPICLK

RAM

Register File

256 Bytes

Standby RAM

256 Bytes

CPU

V

CCSTBY

CP1

Program Memory

ROM: 16K Bytes

EPROM: 16K Bytes

.

Data EEPROM

256 Bytes

CP6

OP1

PACT

.

OP8

128 BYTES

Dual Port

RAM

SCITXD

SCIRXD

Mini SCI

Watchdog

V

CC1

Port A

8

Port D

5

V

SS1

description

The TMS370C036, TMS370C736, and SE370C736 devices are members of the TMS370 family of single-chip

8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx36 refers to these devices. The TMS370

family provides cost-effective real-time system control through advanced peripheral-function modules and

various on-chip memory configurations.

The TMS370Cx36 family of devices uses high-performance silicon-gate CMOS EPROM and EEPROM

technologies. Low operating power, wide operating temperature range, and noise immunity of CMOS

technology coupled with the high performance and extensive on-chip peripheral functions make the

TMS370Cx36 devices attractive for system designs for automotive electronics, industrial motors, computer

peripheral controls, telecommunications, and consumer applications.

All TMS370Cx36 devices contain the following on-chip peripheral modules:

Programmable acquisition and control timer (PACT)

–

Asynchronous mini SCI

PACT watchdog timer

Serial peripheral interface (SPI)

Eight channel, 8-bit analog-to-digital converter 1 (ADC1)

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

description (continued)

Table 1 provides a memory configuration overview of the TMS370Cx36 devices.

Table 1. Memory Configurations

PROGRAM MEMORY

(BYTES)

DATA MEMORY

(BYTES)

DEVICE

44 PIN PACKAGES

ROM

EPROM

RAM

EEPROM

TMS370C036A

TMS370C736A

16K

—

512

256

FN – PLCC

FZ – CLCC

—

16K

256

†

SE370C736A

256

†

System evaluators and development are for use only in prototype environment, and their reliability has not been characterized.

The suffix letter A appended to the device names in Table 1 indicates the configuration of the devices. ROM

or EPROM devices have different configurations as indicated in Table 2. ROM devices with the suffix letter A

are configured through a programmable contact during manufacture.

Table 2. Suffix Letter Configuration

‡

DEVICE

CLOCK

LOW-POWER MODE

Enabled

EPROM A

ROM A

Divide-by-4 (Standard oscillator)

Divide-by-4 or Divide-by-1 (PLL)

Enabled or disabled

‡

Refer to the “device numbering conventions” section for device nomenclature and to the “device part numbers” section for ordering.

The 16K bytes of mask-programmable ROM in the associated TMS370Cx36 devices are replaced in the

TMS370C736 with 16K bytes of EPROM. All other available memory and on-chip peripherals are identical. The

OTP (TMS370C736) and reprogrammable (SE370C736) devices are available.

The TMS370C736 OTP device is available in a plastic package. This microcontroller is effective to use for

immediate production updates for other members of the TMS370Cx36 family or for low-volume production runs

when the mask charge or cycle time for the low-cost mask ROM devices is not practical.

The SE370C736 has a windowed ceramic package to allow reprogramming of the program EPROM memory

during the development/prototyping phase of design. The SE370C736 device allows quick updates to

breadboards and prototype systems while iterating initial designs.

The TMS370Cx36 family provides two low-power modes (STANDBY and HALT) for applications where

low-power consumption is critical. Both modes stop all CPU activity (that is, no instructions are executed). In

the STANDBY mode, the internal oscillator, the PACT counter, and PACT’s first command/definition entry

remain active. This allows the PACT module to bring the device out of STANDBY mode. In the HALT mode, all

device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both

low-power modes.

The TMS370Cx36 features advanced register-to-register architecture that allows direct arithmetic and logical

operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to

the contents of register 47 and store the result in register 47). The TMS370Cx36 family is fully

instruction-set-compatible, providing easy transition between members of the family.

The TMS370Cx36 has a PACT module that acts as a timer coprocessor by gathering timing information on input

signals and controlling output signals with little or no intervention by the CPU. The coprocessor nature of this

module allows for levels of flexibility and power not found in traditional microcontroller timers.

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

description (continued)

TheTMS370Cx36familyprovidesthesystemdesignerwithaneconomical, efficientsolutiontoreal-timecontrol

applications. The PACT compact development tool (CDT ) meets the challenge of efficiently developing the

software and hardware required to design the TMS370Cx36 into an ever-increasing number of complex

applications. The application source code can be written in assembly and C language, and the output code can

be generated by the linker. Precise real-time in-circuit emulation and extensive symbolic debug and analysis

tools ensure efficient software and hardware implementation as well as a reduced time-to-market cycle.

The TMS370Cx36 family together with the TMS370 PACT CDT370, BP programmer, software tools,

SE370C736reprogrammable devices, comprehensive product documentation, and customer support provides

a complete solution to the needs of the system designer.

central processing unit (CPU)

TheCPUontheTMS370Cx36deviceisthehigh-performance8-bitTMS370CPUmodule. The’x36implements

an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The

complete ’x36 instruction map is shown in Table 16.

The ’370Cx36 CPU architecture provides the following components:

CPU registers:

A stack pointer (SP) that points to the last entry in the memory stack

A status register (ST) that monitors the operation of the instructions and contains the global interrupt-enable

bits

A program counter (PC) that points to the memory location of the next instruction to be executed

A memory map that includes:

256-byte general-purpose RAM that can be used for data memory storage, program instructions, general

purpose register, or the stack

256-byte general-purpose standby RAM, which is powered through a separate V

pin to protect the

CCSTBY

memory against power failures on the main V

pins

CC1

128-byte dual-port RAM that contains the capture registers, the circular buffer, and a command/definition

area

A peripheral file that provides access to all internal peripheral modules, system-wide control functions, and

EEPROM/EPROM programming control

256-byte EEPROM module, that provides in-circuit programmability and data retention in power-off

conditions

16K-byte ROM or 16K-byte EPROM

CDT is a trademark of Texas Instruments Incorporated.

5

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

central processing unit (CPU) (continued)

Figure 1 Illustrates the CPU registers and memory blocks.

Program Counter

15

0

Legend:

Stack Pointer (SP)

7

0

C=Carry

N=Negative

Status Register (ST)

Z=Zero

C

7

N

6

Z

5

V

4

IE2 IE1

V=Overflow

IE2=Level 2 interrupts Enable

IE1=Level 1 interrupts Enable

3

2

1

0

RAM (Includes up to 256-Byte Registers File)

0000h

R0(A)

R1(B)

256-Byte RAM

00FFh

0100h

†

Reserved

0001h

0002h

0003h

017Fh

0180h

01FFh

0200h

02FFh

0300h

0FFFh

1000h

10BFh

10C0h

128-Byte PACT Dual-Port RAM

256-Byte Standby RAM

R2

R3

†

Reserved

Peripheral File

†

Reserved

1EFFh

1F00h

R127

R255

256-Byte Data EEPROM

007Fh

1FFFh

2000h

†

Reserved

3FFFh

4000h

16K-Byte ROM/EPROM

7F9Bh

7F9Ch

Interrupts and Reset Vectors;

Trap Vectors

7FFFh

8000h

00FFh

†

Reserved

FFFFh

†

Reserved means the address space is reserved for future expansion.

Figure 1. Programmer’s Model

stack pointer (SP)

The SP is an 8-bit CPU register. Stack operates as a last-in, first-out, read/write memory. Typically, the stack

is used to store the return address on subroutine calls as well as the ST contents during interrupt sequences.

The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed

onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the

on-chip RAM.

status register (ST)

The ST monitors the operation of the instructions and contains the global interrupt-enable bits. The ST includes

four status bits (condition flags) and two interrupt-enable bits.

The four status bits indicate the outcome of the previous instruction; conditional instructions (for example,

the conditional-jump instructions) use the status bits to determine program flow.

The two interrupt-enable bits control the two interrupt levels.

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TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

central processing unit (CPU) (continued)

The ST, status-bit notation, and status-bit definitions are shown in Table 3.

Table 3. Status Registers

7

C

6

N

5

Z

4

V

3

2

1

0

IE2

IE1

Reserved

RW-0

R = read, W = write, 0 = value after reset

program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists

of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These

registers contain the most significant byte (MSbyte) and least significant byte (LSbyte) of a 16-bit address.

During reset, the contents of the reset vector (7FFEh, 7FFFh) are loaded into the PC. The PCH (MSbyte of the

PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is loaded with the

contents of memory location 7FFFh. Figure 2 shows this operation using an example value of 4000h as the

contents of the reset vector.

Program Counter (PC)

Memory

PCH

40

PCL

00

0000h

40

00

7FFEh

7FFFh

Figure 2. Program Counter After Reset

memory map

The TMS370Cx36 architecture is based on the Von Neuman architecture, where the program memory and data

memory share a common address space. All peripheral input/output is memory mapped in this same common

address space. As shown in Figure 3, the TMS370Cx36 provides memory-mapped RAM, ROM, EPROM, data

EEPROM, I/O pins, peripheral functions, and system-interrupt vectors.

The peripheral file contains all I/O port control, peripheral status and control, EEPROM, EPROM, and

system-wide control functions. The peripheral file is located between 1000h to 107Fh and is divided logically

into eight peripheral file frames of 16 bytes each. The eight PF frames consist of five control frames and three

reserved frames.Each on-chip peripheral is assigned to a separate frame through which peripheral control and

data information are passed.

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TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

central processing unit (CPU) (continued)

Peripheral File Control Registers

†

Reserved

1000h–100Fh

1010h–101Fh

1020h–102Fh

1030h–103Fh

0000h

System Control

256-Byte RAM

Digital Port Control

00FFh

0100h

017Fh

0180h

†

Reserved

SPI Peripheral Control

PACT Peripheral Control

1040h–104Fh

1050h–105Fh

1060h–106Fh

1070h–107Fh

128-Byte PACT Dual-Port RAM

256-Byte PACT Standby RAM

01FFh

0200h

†

Reserved

02FFh

0300h

†

Reserved

ADC1 Peripheral Control

0FFFh

1000h

Vectors

Peripheral File

10BFh

10C0h

PACT Interrupt 1-18

Trap 15–0

7F9Ch–7FBFh

7FC0h–7FDFh

7FE0h–7FEBh

7FECh–7FEDh

7FEEh–7FF5h

7FF6h–7FF7h

†

Reserved

1EFFh

†

Reserved

1F00h

1FFFh

2000h

256-Byte Data EEPROM

ADC1

†

Reserved

†

Reserved

3FFFh

4000h

7F9Bh

7F9Ch

16K-Byte ROM/EPROM

Serial Peripheral Interface

†

Reserved

Interrupts and Reset Vectors;

Trap and PACT Vectors

7FF8h–7FFBh

7FFFh

8000h

Interrupt 1

Reset

7FFCh–7FFDh

7FFEh–7FFFh

†

Reserved

FFFFh

†

Reserved means that the address space is reserved for future expansion.

Figure 3. TMS370Cx36 Memory Map

RAM/register file (RF)

Locations within the RAM address space can serve as the RF, general-purpose read/write memory, program

memory, or the stack instructions. The TMS370Cx36 devices contain 256 bytes of internal RAM,

memory-mapped beginning at location 0000h (R0) and continuing through location 00FFh (R255) which is

shown in Figure 1.

The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly

use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the

stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.

dual-port RAM

The upper 128 bytes of the register files can be used by the PACT module to contain commands and definitions

as well as timer values. Any RAM not used by PACT can be used as an additional CPU register or as

general-purpose memory.

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TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

standby RAM module

The 256 byte standby RAM is general-purpose and powered through a separate V

pin. The data stored

CCSTBY

in this memory is protected against power failures on the main V

pins.

CC1

The standby RAM data is saved if the power failure on the main V

pins is detected externally and an external

CC1

reset is generated when V

falls below 4.3 V (see Figure 4). The external reset must remain low during the

CC1

entire power failures. The falling edge of the reset signal is internally detected to set the standby RAM in

low-power HALT mode. After the next power up, the RESET pin must be pulled high to get out of the HALT mode

of the standby RAM. In halt mode, the standby RAM consumes only leakage current.

4.3 Volt

V

CC1

RESET

Standby RAM Locked in Halt Mode

Figure 4. Standby RAM Locked in Halt Mode

peripheral file (PF)

The TMS370Cx36 control registers contain all the registers necessary to operate the system and peripheral

modules on the device. The instruction set includes some instructions that access the PF directly. These

instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal

designator or P for a decimal designator. For example, the system-control register 0 (SCCR0) is located at

address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 4

lists the TMS370Cx36 PF address map.

Table 4. TMS370Cx36 Peripheral File Address Map

PERIPHERAL FILE

ADDRESS RANGE

DESCRIPTION

DESIGNATOR

P000–P00F

P010–P01F

P020–P02F

P030–P03F

P040–P04F

P050–P06F

P070–P07F

P080–P0FF

1000h–100Fh

1010h–101Fh

1020h–102Fh

1030h–103Fh

1040h–104Fh

1050h–106Fh

1070h–107Fh

1080h–10FFh

Reserved

System and EPROM/EEPROM control registers

Digital I/O port control registers

SPI registers

PACT registers

Reserved

Analog-to-digital converter 1 registers

Reserved

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TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

data EEPROM

The TMS370Cx36 devices, containing 256 bytes of data EEPROM, have a memory mapped beginning at

location 1F00h and continuing through location 1FFFh. Writing to the data EEPROM module is controlled by

the data EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm

examples are available in the TMS370 Family User’s Guide (literature number SPNU127) or the

TMS370FamilyDataManual(literaturenumberSPNS014B). ThedataEEPROMfeaturesincludethefollowing:

Programming:

–

Bit-, byte-, and block-write/erase modes.

Internal charge pump circuitry. No external EEPROM programming voltage supply is needed.

Control register: Data EEPROM programming is controlled by the DEECTL located in the PF frame

beginning at location P01A. See Table 5.

–

In-circuit programming capability. There is no need to remove the device to program.

Write protection. Writes to the data EEPROM are disabled during the following conditions.

–

Reset. All programming of the data EEPROM module is halted.

Write protection active. There is one write-protect bit per 32-byte EEPROM block.

Low-power mode operation

Write protection can be overridden by applying 12 V to MC.

Table 5. Data EEPROM and PROGRAM EPROM Control Registers Memory Map

ADDRESS

P01A

SYMBOL

DEECTL

—

NAME

Data EEPROM Control Register

Reserved

P01B

P01C

EPCTLL

Program EPROM Control Register – Low Array

†

program EPROM

The TMS370C736 device contains 16K bytes of EPROM mapped, beginning at location 4000h and continuing

through location 7FFFh as shown in Figure 3. Reading the program EPROM modules is identical to reading

other internal memory. During programming, the EPROM is controlled by the EPROM control register

(EPCTLL). The program EPROM module features include:

Programming

–

In-circuit programming capability if V is applied to MC

PP

Control register: EPROM programming is controlled by the EPROM control register (EPCTLL) located

in the peripheral file (PF) frame at location P01C as shown in Table 5.

Write protection: Writes to the program EPROM are disabled under the following conditions:

–

Reset: All programming to the EPROM module is halted

Low-power modes

13 V not applied to MC

†

Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments (TI ), and addresses 7FECh through 7FFFh are reserved

for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and

7FDFh.

TI is a trademark of Texas Instruments Incorporated.

10

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TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

†

program ROM

The program ROM consists of 16K bytes of mask programmable read-only memory. The program ROM is used

for permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device

fabrication. Refer to Figure 3 for ROM memory map.

system reset

The system-reset operation ensures an orderly start-up sequence for the TMS370Cx36 CPU-based device.

There are up to three different actions that can cause a system reset to the device. Two of these actions are

generated internally, while one (RESET pin) is controlled externally. These actions are as follows:

PACT watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD

key register, or if the re-initialization does not occur before the watchdog timer timeout . See the TMS370

User’s Guide (literature number SPNU127) for more information.

Oscillator reset. Reset occurs when the oscillator operates outside of the recommended operating range.

See the TMS370 User’s Guide (literature number SPNU127) for more information.

External RESET pin. A low level signal can trigger an external reset. To ensure a reset, the external signal

should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 User’s Guide (literature number SPNU127) for more information.

Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK

cycles. This allows the ’x36 device to reset external system components. Additionally, if a cold start (V

is off

CC

for several hundred milliseconds) condition or oscillator failure occurs or the RESET pin is held low, then the

reset logic holds the device in a reset state for as long as these actions are active.

After a reset, the program can check the oscillator-fault flag (OSC FLT FLAG, SCCR0.4) and the cold-start flag

(COLD START, SCCR0.7) to determine the source of the reset. A reset does not clear these flags.Table 6 lists

the reset sources. If none of the sources indicated in Table 6 caused the reset, then the RESET pin was pulled

low by the external hardware or the PACT module’s watchdog.

Table 6. Reset Sources

REGISTER

SCCR0

ADDRESS

1010h

PF

BIT NO.

CONTROL BIT

COLD START

OSC FLT FLAG

SOURCE OF RESET

Cold (power-up)

Oscillator out of range

P010

7

4

1010h

Once a reset is activated, the following sequence of events occurs:

1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state).

2. Registers A and B are initialized to 00h (no other RAM is changed).

3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.

4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.

5. Program execution begins with an opcode fetch from the address pointed to the PC.

The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode

fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control

register bits are initialized to their reset state.

†

Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments, and addresses 7FECh through 7FFFh are reserved for

interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and

7FDFh.

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interrupts

The TMS370 family software-programmable interrupt structure permits flexible on-chip and external interrupt

configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure

incorporates two priority levels as shown in Figure 5. Interrupt level 1 has a higher priority than interrupt

level 2. The two priority levels can be masked independently by the global interrupt mask bits (IE1 and IE2) of

the ST.

PACT

GROUP 3

Cmd/Def Entry 7

GROUP 2

GROUP 1

Default Timer

Overflow

CP1 Edge

CP2 Edge

CP3 Edge

CP4 Edge

CP5 Edge

CP6 Edge

Circular Buffer

Cmd/Def Entry 6

Cmd/Def Entry 5

Cmd/Def Entry 4

Cmd/Def Entry 3

Cmd/Def Entry 2

Cmd/Def Entry 1

Cmd/Def Entry 0

SCI TXINT

SCI RXINT

PACT 3 PRI

PACT 2 PRI

PACT 1 PRI

AD INT

ADC1

SPI INT

EXT INT1

CPU

INT1

SPI

NMI

Priority

Logic

INT1 PRI

STATUS REG

AD PRI

SPI PRI

IE1

IE2

Level 1 INT

Level 2 INT

Enable

Figure 5. Interrupt Control

Each system interrupt is configured independently to either the high- or low-priority chain by the application

program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of

the system interrupt. However, since each system interrupt is selectively configured on either the high- or

low-priority-interrupt chain, the application program can elevate any system interrupt to the highest priority.

Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority

12

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interrupts (continued)

chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending

interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and

priority conditions.

The TMS370Cx36 has 21 hardware system interrupts (plus RESET) as shown in Table 7. Each system interrupt

has a dedicated vector located in program memory through which control is passed to the interrupt service

routines. A system interrupt may have multiple interrupt sources. All of the interrupt sources are individually

maskable by local interrupt enable control bits in the associated peripheral file. Each interrupt source FLAG bit

is individually readable for software polling or for determining which interrupt source generated the associated

system interrupt.

Twenty of the system interrupts are generated by on-chip peripheral functions, and one external interrupt is

supported. Software configuration of the external interrupts is performed through the INT1 control register in

peripheral file frame 1. Each external interrupt is individually software configurable for input polarity (rising or

falling edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable

or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked by the individual-

or global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and, therefore, should

be configured during the initialization sequence following reset. To maximize pin flexibility, external interrupt

INT1 can be software configured as a general-purpose input pin if the interrupt function is not required.

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interrupts (continued)

Table 7. Hardware System Interrupts

PRIORITY

IN

GROUP

INTERRUPT

SOURCE

INTERRUPT

FLAG

SYSTEM

INTERRUPT

VECTOR

ADDRESS

MODULE

PRIORITY

OSC FLT FLG

†

External RESET

Watchdog Overflow

Oscillator Fault

COLD START

(No Flag)

OSC FLT FLAG

†

RESET

7FFEh, 7FFFh

1

‡

INT1

SPI

External Interrupt 1

INT1 FLAG

INT1

7FFCh, 7FFDh

7FF6h, 7FF7h

2

3

SPI RX/TX Complete

SPI INT FLAG

SPIINT

Buffer Half/Full

Interrupt Flag

PACT Circular Buffer

BUFINT

7FB0h, 7FB1h

1

PACT CP6 Event

PACT CP5 Event

PACT CP4 Event

PACT CP3 Event

PACT CP2 Event

PACT CP1 Event

CP6 INT FLAG

CP5 INT FLAG

CP4 INT FLAG

CP3 INT FLAG

CP2 INT FLAG

CP1 INT FLAG

CP6INT

CP5INT

CP4INT

CP3INT

CP2INT

CP1INT

7FB2h, 7FB3h

7FB4h, 7FB5h

7FB6h, 7FB7h

7FB8h, 7FB9h

7FBAh, 7FBBh

7FBCh, 7FBDh

2

3

4

5

6

7

PACT (Group 1)

4

5

Default Timer

Overflow

DEFTIM OVRFL INT

FLAG

POVRL

INT

7FBEh, 7FBFh

8

PACT SCI Rx Int

PACT RX RDY

PRXINT

PTXINT

CDINT 0

CDINT 1

CDINT 2

CDINT 3

CDINT 4

CDINT 5

CDINT 6

CDINT 7

ADINT

7F9Eh, 7F9Fh

7F9Ch, 7F9Dh

7FA0h, 7FA1h

7FA2h, 7FA3h

7FA4h, 7FA5h

7FA6h, 7FA7h

7FA8h, 7FA9h

7FAAh, 7FABh

7FACh, 7FADh

7FAEh, 7FAFh

7FECh, 7FEDh

1

2

1

2

3

4

5

6

7

8

PACT (Group 2)

PACT SCI Tx Int

PACT TX RDY

PACT Cmd/Def Entry 0

PACT Cmd/Def Entry 1

PACT Cmd/Def Entry 2

PACT Cmd/Def Entry 3

PACT Cmd/Def Entry 4

PACT Cmd/Def Entry 5

PACT Cmd/Def Entry 6

PACT Cmd/Def Entry 7

ADC1 Conversion Complete

CMD/DEF INT 0 FLAG

CMD/DEF INT 1 FLAG

CMD/DEF INT 2 FLAG

CMD/DEF INT 3 FLAG

CMD/DEF INT 4 FLAG

CMD/DEF INT 5 FLAG

CMD/DEF INT 6 FLAG

CMD/DEF INT 7 FLAG

AD INT FLAG

PACT (Group 3)

6

7

ADC1

†

‡

Relative priority within an interrupt level

Release microcontroller from STANDBY and HALT low-power modes

privileged operation and EEPROM write protection override

The TMS370Cx36 family is designed with significant flexibility to enable the designer to software-configure the

system and peripherals to meet the requirements of a variety of applications. The nonprivileged mode of

operation ensures the integrity of the system configuration, once it is defined for an application. Following a

hardware reset, the TMS370Cx36 operates in the privileged mode, where all peripheral file registers have

unrestricted read/write access, and the application program configures the system during the initialization

sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is

set to 1 to enter the nonprivileged mode, disabling write operations to specific configuration-control bits within

the PF. Table 8 lists the control bits shown in the table which are write-protected during the nonprivileged mode

and must be configured by software prior to exiting the privileged mode.

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privileged operation and EEPROM write protection override (continued)

Table 8. Privilege Bits

†

REGISTER

CONTROL BIT

PF AUTO WAIT

NAME

LOCATION

P010.5

P010.6

SCCRO

OSC POWER

P011.2

P011.4

MEMORY DISABLE

AUTOWAIT DISABLE

SCCR1

SCCR2

P012.0

P012.1

P012.3

P012.4

P012.6

P012.7

PRIVILEGE DISABLE

INT1 NMI

CPU STEST

BUS STEST

PWRDWN/IDLE

HALT/STANDBY

P03F.5

P03F.6

P03F.7

SPI ESPEN

SPI PRIORITY

SPI STEST

SPIPRI

P040.0

P040.1

P040.2

P040.3

P040.4

PACT PRESCALE SELECT 0

PACT PRESCALE SELECT 1

PACT PRESCALE SELECT 2

PACT PRESCALE SELECT 3

FAST MODE SELECT

PACTSCR

P04F.0

P04F.1

P04F.2

P04F.3

P04F.4

P04F.5

P04F.7

PACT WD PRESCALE SELECT 0

PACT WD PRESCALE SELECT 1

PACT MODE SELECT

PACT GROUP 3 PRIORITY

PACT GROUP 2 PRIORITY

PACT GROUP 1 PRIORITY

PACT STEST

PACTPRI

ADPRI

P07F.5

P07F.6

P07F.7

AD ESPEN

AD PRIORITY

AD STEST

†

The privilege bits are shown in a bold typeface and shaded areas in the

system configuration registers section of Table 10.

low-power and IDLE modes

The TMS370Cx36 devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For

mask-ROM devices, low-power modes can be disabled permanently through a programmable contact when

the mask is manufactured.

The STANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping

the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes

is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The

HALT/STANDBY bit in SCCR2 controls the low-power mode selection.

In the STANDBY mode (HALT/STANDBY = 0), all CPU activity and most peripheral module activity is stopped;

however, the oscillator, internal clocks, the PACT counter, and the first PACT command entry remain active in

all modules. System processing is suspended until a qualified interrupt (hardware RESET or external interrupt

on INT1) is detected.

In the HALT mode (HALT/STANDBY = 1), the TMS370Cx36 is placed in its lowest power consumption mode.

The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is

suspended until a qualified interrupt (hardware RESET or external interrupt on the INT1) is detected. The

power-down mode-selection bits are summarized in Table 9.

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low-power and IDLE modes (continued)

Table 9. Low-Power/Idle Control Bits

POWER-DOWN CONTROL BITS

MODE SELECTED

PWRDWN/IDLE

(SCCR2.6)

HALT/STANDBY

(SCCR2.7)

1

0

1

STANDBY

HALT

1

0

†

X

IDLE

†

X = Don’t care

When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the

SCCR2.6-7 bits is ignored. In addition, if an IDLE instruction is executed when low-power modes are disabled

through a programmable contact, the device always enters the IDLE mode.

To provide a method for always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically

as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This

means that the NMI is generated always, regardless of the interrupt enable flags.

The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file),

CPU registers (SP, PC, and ST), I/O pin direction and output data, and status registers of all on-chip peripheral

functions. Since all CPU instruction processing is stopped during the STANDBY and HALT modes, the clocking

of the WD timer is inhibited.

clock modules

The ’x36 family provides two clock options that are referred to as divide-by-1 (phase-locked loop) and

divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the

manufacturing process of a TMS370 microcontroller. The ’x36 masked-ROM devices offer both options to meet

system engineering requirements. Only one of the two clock options is allowed on each ROM device. The ’736A

EPROM has only the divide-by-4.

The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with

no added cost.

The divide-by-1 provides a one-to-one match of the external resonator frequency (CLKIN) to the internal system

clock (SYSCLK) frequency, whereas the divide-by-4 produces a SYSCLK which is one-fourth the frequency of

the external resonator. Inside of the divide-by-1 module, the frequency of the external resonator is multiplied

by four, and the clock module then divides the resulting signal by four to provide the four-phased internal system

clock signals. The resulting SYSCLK is equal to the resonator frequency. These are formulated as follows:

external resonator frequency

4

CLKIN

4

Divide-by-4 option : SYSCLK

Divide-by-1 option : SYSCLK

external resonator frequency

4

CLKIN

The main advantage of choosing a divide-by-1 oscillator is the reduced EMI. The harmonics of low-speed

resonators extend through fewer of the emissions spectrum than the harmonics of faster resonators. The

divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a steeper

decay of emissions produced by the oscillator.

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system configuration registers

Table 10 contains system-configuration and control functions and registers for controlling EEPROM

programming. The privileged bits are shown in a bold typeface and shaded areas.

Table 10. Peripheral File Frame 1: System-Configuration Registers

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

COLD

START

OSC

POWER

PF AUTO

WAIT

OSC FLT

FLAG

MC PIN

WPO

MC PIN

DATA

µP/µC

MODE

P010

—

SCCR0

AUTO

WAIT

DISABLE

MEMORY

DISABLE

P011

—

SCCR1

SCCR2

HALT/

STANDBY

PWRDWN/

IDLE

BUS

STEST

CPU

STEST

INT1

NMI

PRIVILEGE

DISABLE

P012

—

P013

to

Reserved

P016

INT1

FLAG

INT1

PIN DATA

INT1

POLARITY

INT1

PRIORITY

INT1

ENABLE

P017

—

INT1

P018

P019

P01A

P01B

P01C

Reserved

BUSY

—

AP

—

W1W0

W0

EXE

DEECTL

EPCTLL

Reserved

VPPS

P01D

P01E

P01F

Reserved

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digital port control registers

Peripheral file frame 2 contains the digital I/O pin configuration and control registers. Table 11showsthespecific

addresses, registers, and control bits within this peripheral file frame. Table 12 shows the port configuration

register setup.

Table 11. Peripheral File Frame 2: Digital Port-Control Registers

PF

P020

P021

P022

P023

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

Reserved

BIT 2

BIT 1

BIT 0

APORT1

APORT2

ADATA

ADIR

Port A Control Register 2 (must be 0)

Port A Data

Port A Direction

P024

to

Reserved

P02B

P02C

P02D

P02E

P02F

Port D Control Register 1 (must be 0)

—

DPORT1

DPORT2

DDATA

DDIR

†

Port D Control Register 2 (must be 0)

Port D Data

Port D Direction

†

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

Table 12. Port Configuration Register Setup

abcd

00q1

abcd

00y0

PORT

A

D

0 – 7

3 – 7

Data out q

Data In y

a = Port x Control Register 1

b = Port x Control Register 2

c = Data

d = Direction

serial peripheral interface

The SPI is a high-speed synchronous serial I/O port that allows a serial bit stream of programmed length (one

to eight bits) to be shifted into and out of the device at a programmable bit transfer rate. The SPI normally is

used for communications between the microcontroller and external peripherals or another microcontroller.

Typical applications include external I/O or peripheral expansion by way of devices such as shift registers,

display drivers, and A/D converters. Multi-device communications are supported by the master/slave operation

of the SPI. The SPI module features include the following:

Three external pins

–

SPISOMI: SPI slave output/master input pin or general-purpose bidirectional I/O pin

SPISIMO: SPI slave input/master output pin or general-purpose bidirectional I/O pin

SPICLK: SPI serial clock pin or general-purpose bidirectional I/O pin

Two operational modes: Master and slave

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serial peripheral interface (continued)

Baud rate: Eight different programmable rates

–

Maximum baud rate in master mode: 2.5M bps at 5-MHz SYSCLK

SYSCLK

2

SPI BAUD RATE

2^b

where b=bit rate in SPICCR.5-3 (range 0–7)

–

Maximum baud rate in slave mode: 625K bps at 5-MHz SYSCLK

for maximum slave SPI BAUD RATE < SYSCLK/8

Data word format: one to eight data bits

Simultaneous receiver and transmitter operations (transmit function can be disabled in software)

Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.

Seven SPI module control registers located in control register frame beginning at address P030h

The SPI module-control registers are listed in Table 13.

Table 13. SPI Module-Control Register Memory Map

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

SPI SW

RESET

CLOCK

POLARITY

SPI BIT

RATE2

SPI BIT

RATE1

SPI BIT

RATE0

SPI

CHAR2

SPI

CHAR1

SPI

CHAR0

P030

SPICCR

RECEIVER

OVERRUN

SPI INT

FLAG

MASTER/

SLAVE

SPI INT

ENA

P031

—

TALK

SPICTL

P032

to

Reserved

P036

P037

P038

P039

RCVD7

SDAT7

RCVD6

SDAT6

RCVD5

SDAT5

RCVD4

SDAT4

RCVD3

RCVD2

SDAT2

RCVD1

SDAT1

RCVD0

SDAT0

SPIBUF

SPIDAT

RESERVED

SDAT3

P03A

to

Reserved

P03C

SPICLK

DATA IN

SPICLK

DATA OUT

SPICLK

FUNCTION

SPICLK

DATA DIR

P03D

P03E

P03F

—

SPIPC1

SPIPC2

SPIPRI

SPISIMO

DATA IN

SPISIMO

DATA OUT

SPISIMO

FUNCTION

SPISIMO

DATA DIR

SPISOMI

DATA IN

SPISOMI

DATA OUT

SPISOMI

FUNCTION

SPISOMI

DATA DIR

SPI

STEST

SPI

PRIORITY

SPI

ESPEN

—

19

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serial peripheral interface (continued)

The SPI block diagram is illustrated in Figure 6.

RECEIVER

SPIBUF.7-0

OVER RUN

SPIBUF Buffer

SPICTL.7

Register

SPIPRI.6

8

0

1

Level 1 INT

Level 2 INT

SPICTL.0

SPI INT FLAG

SPICTL.6

SPIINT ENA

SPIPC2.7-4

SPIDAT

Data Register

SPISIMO

SPICTL.1

TALK

SPIDAT.7-0

SPIPC2.3-0

SPISOMI

State Control

SPICCR.2-0

†

MASTER/SLAVE

SPI CHAR

SPICTL.2

2

1

0

SPIPC1.3-0

SPICLK

System

Clock

SPICCR.6

CLOCK POLARITY

SPICCR.5-3

5

4

3

SPI BIT RATE

The block diagram is shown in slave mode.

†

Figure 6. SPI Block Diagram

programmable acquisition and control timer (PACT) module

Traditionally, timers in microcontrollers provide limited capture and compare functions consuming significant

CPU processing power and leading to inaccurate timings due to interrupt latencies. The programmable

acquisition and control timer (PACT) acts as a coprocessor combining configurable capture and compare

features, within a flexible dual-port RAM, able to run real-time tasks with little or no CPU intervention. The PACT

structure allows concatenation of tasks, thus enabling the CPU to perform data manipulation while the PACT

module both captures and outputs real-time-related information. Since all the PACT control information is held

within the dual-port Ram, the CPU can access these parameters quickly.

To use the PACT, the user must set up three distinct areas of memory. The first is the dual-port RAM, which

contains the capture area, the commands, and the timer definitions. The second is the peripheral frame. The

third is an area near the end of the program memory which holds the interrupt vectors of PACT.

20

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programmable acquisition and control timer (PACT) module (continued)

The PACT module features include the following:

Input-capture functions on up to six input pins (CP1 to CP6), depending on the mode selected:

–

Mode A: CP1–2 are dedicated capture, CP3–6 are circular buffer capture, and CP6 is also an event pin.

Mode B: CP1–4 are dedicated capture, CP5–6 are circular buffer capture, and CP6 is also an event pin.

Multiple timer-driven outputs on eight pins (OP1 to OP8)

–

Standard compare command: set or clear an output pin whenever the timer/counter is equal to a certain

value

–

Virtual timers: enable variations of the PWM’s period and provides periodic interrupts to the processor.

Double event-compare command: comparisons of the 8-bit event counter with two event-compare

values and the actions that can be performed are based on each value:

–

Event-compare 1 matching the event counter: sets or resets the selected output pin (OP1–OP8),

generates interrupt, and generates a 32-bit capture into the circular buffer.

–

Event-compare 2 matching the event counter: sets or resets the selected output pin (OP1–OP8),

generates interrupt, generates a 32-bit capture into the circular buffer, and resets the 20-bit default

timer.

–

Offset timer definition-time from last event:

–

Generates an interrupt when the maximum event count is reached

Stores the 16-bit virtual timer in the circular buffer on each event

Stores the 20-bit default timer and 8-bit event counter in the circular buffer when the maximum

event count is reached

–

Resets the 20-bit hardware default timer when the maximum event count is reached.

–

Conditional-compare command has a timer-compare value and an event-compare value.

–

Generates an interrupt when the event-compare value equals the event counter and the

timer-compare value equals the last defined timer

–

Sets or clears one of the seven output pins (OP1–OP7) when the event compare value equals the

event counter and the timer-compare value equals the last defined timer

Baud rate timer definition: runs the mini-serial communications port built into the PACT module.

Configurable timer overflow rates

One 8-bit event counter driven by CP6

Up to 20-bit timer capability

Interaction between event counter and timer activity

Register-based organization allowing direct access to timer parameters by the CPU

18 independent interrupt vectors with two priority levels

Integrated, configurable watchdog with selectable time-out period

21

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programmable acquisition and control timer (PACT) module (continued)

Mini-serial communications interface works as a simplified full duplex universal asychronous

receiver/transmitter (UART) with independent setup of baud rate for receive and transmit lines.

–

Asynchronous communications mode

Asynchronous Baud

1

–2

(Max Virtual Timer Value) (4) (PACT Resolution)

where PACT Resolution = SYSCLK × Prescale Value

PACT block diagram

The PACT module block diagram is illustrated in Figure 7.

PACT PRESCALED CLOCK

20-Bit Timer/Counter

Prescale

8-Bit Event Counter

Watchdog Timer

CP1

CP2

Dedicated Capture Register 1

Dedicated Capture Register 2

Dedicated Capture Register 3

Dedicated Capture Register 4

Reset

CP3

CP4

CP5

CP6

3-Bit Prescaler

MODE

Circular Buffer

(32–Bit Captures)

OPT1

OPT2

OPT3

OPT4

OPT5

OPT6

OPT7

OPT8

Outputs

EVENT ONLY

Command/Definition Area

Command Analyzer

and

Output Controller

Int Level 1

Int Level 2

SCITXD

Mini SCI

SCIRXD

Figure 7. PACT Block diagram

22

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

PACT control registers

The PACT module is controlled and accessed through registers in peripheral frame 4. These registers are listed

in Table 14. The bits in shaded boxes are privileged mode bits; that is, they can be written to only in theprivileged

mode.

Table 14. PACT Control Registers

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

PACT

BIT 1

PACT

BIT 0

PACT

REG

DEFTIM

OVRFL

INT ENA

DEFTIM

OVRFL

INT FLAG

FAST

MODE

SELECT

PACT

PRESCALE

SELECT3

CMD/DEF

AREA ENA

P040

PRESCALE PRESCALE

SELECT2

PRESCALE PACTSCR

SELECT0

SELECT1

CMD/DEF

AREA

INT ENA

CMD/DEF

AREA

CMD/DEF

AREA

CMD/DEF

AREA

CMD/DEF

AREA

P041

P042

P043

—

CDSTART

CDEND

START BIT 5 START BIT 4 START BIT 3 START BIT 2

CMD/DEF

AREA

END BIT 6

CMD/DEF

AREA

END BIT 5

CMD/DEF

AREA

END BIT 4

CMD/DEF

AREA

END BIT 3

CMD/DEF

AREA END

BIT 2

—

1

—

BUFFER

POINTER

BIT 5

BUFFER

POINTER

BIT 4

BUFFER

POINTER

BIT 3

BUFFER

POINTER

BIT 2

BUFFER

POINTER

BIT 1

1

BUFPTR

P044

P045

Reserved

PACT

RXRDY

PACT

TXRDY

PACT

PARITY

PACT SCI

RX INT ENA TX INT ENA

PACT SCI

SW RESET

PACT FE

—

SCICTLP

RXBUFP

TXBUFP

PSTATE

PACT

RXDT7

PACT

RXDT6

PACT

RXDT5

PACT

RXDT2

PACT

RXDT1

PACT

RXDT0

P046

P047

P048

P049

RXDT4

RXDT3

PACT

TXDT7

PACT

TXDT6

PACT

TXDT5

PACT

TXDT2

PACT

TXDT1

PACT

TXDT0

TXDT4

TXDT3

PACT OP8

STATE

PACT OP7

STATE

PACT OP6

STATE

PACT OP5

STATE

PACT OP4

STATE

PACT OP3

STATE

PACT OP2

STATE

PACT OP1

STATE

CMD/DEF

INT 7 FLAG INT 6 FLAG

CMD/DEF

INT 5 FLAG

CMD/DEF

INT 2 FLAG

CMD/DEF

INT 1 FLAG

CMD/DEF

INT 0 FLAG

CDFLAGS

INT 4 FLAG

INT 3 FLAG

CP2 CAPT

RISING

EDGE

CP2 CAPT

FALLING

EDGE

CP1 CAPT

RISING

EDGE

CP1 CAPT

FALLING

EDGE

CP2 INT

ENA

CP2 INT

FLAG

CP1 INT

ENA

CP1 INT

FLAG

P04A

P04B

P04C

CPCTL1

CPCTL2

CPCTL3

CP4 CAPT

RISING

EDGE

CP4 CAPT

FALLING

EDGE

CP3 CAPT

RISING

EDGE

CP3 CAPT

FALLING

EDGE

CP4 INT

ENA

CP4 INT

FLAG

CP3 INT

ENA

CP3 INT

FLAG

CP6 CAPT

RISING

EDGE

CP6 CAPT

FALLING

EDGE

CP5 CAPT

RISING

EDGE

CP5 CAPT

FALLING

EDGE

CP6 INT

ENA

CP6 INT

FLAG

CP5 INT

ENA

CP5 INT

FLAG

INPUT

CAPT

PRESCALE

SELECT 3

INPUT

CAPT

PRESCALE

SELECT 2

INPUT

CAPT

PRESCALE

SELECT 1

BUFFER

P04D HALF/FULL

INT ENA

BUFFER

HALF/FULL

INT FLAG

EVENT

COUNTER

SW RESET

CP6 EVENT

ONLY

OP/ SET/CLR

SELECT

CPPRE

WDRST

P04E

WATCHDOG REST KEY

PACT

GROUP 1

PRIORITY

PACT

GROUP 2

PRIORITY

PACT

GROUP 3

PRIORITY

PACT

MODE

SELECT

PACT WD

PRESCALE

SELECT 1

PACT WD

PRESCALE PACTPRI

SELECT 0

PACT

P04F

PACT

SUSPEND

STEST

23

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

analog-to-digital converter 1 module

The analog-to-digital converter 1 (ADC1) module is an 8-bit, successive approximation converter with internal

sample-and-hold circuitry. The module has four multiplexed analog input channels that allow the processor to

convert the voltage levels from up to eight different sources. The ADC1 module features include the following:

Minimum conversion time: 32.8 µs at 5-MHz SYSCLK

Ten external pins:

–

Eight analog-input channels (AN0–AN7), any of which can be software-configured as digital inputs

(E0–E7) when not needed as analog channels

–

AN1–AN7 also can be configured as positive-input voltage reference.

V

: ADC1 module high-voltage reference input

CC3

: ADC1 module low-voltage reference input

SS3

The ADDATA register, which contains the digital result of the last ADC1 conversion.

ADC1 operations can be accomplished through either interrupt-driven or polled algorithms.

Six ADC1 module control registers located in the control-register frame beginning at address 1070h

The ADC1 module control registers are listed in Table 15.

Table 15. ADC1 Module Control Register Memory Map

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

CONVERT

START

SAMPLE

START

REF VOLT

SELECT2

REF VOLT

SELECT1

REF VOLT

SELECT0

AD INPUT

SELECT2

AD INPUT

SELECT1

AD INPUT

SELECT0

P070

ADCTL

AD INT

FLAG

AD INT

ENA

P071

P072

—

AD READY

ADSTAT

ADDATA

A/D Conversion Data Register

RESERVED

P073

to

P07C

P07D

P07E

Port E Data Input Register

Port E Input Enable Register

ADIN

ADENA

AD

PRIORITY

P07F AD STEST

AD ESPEN

—

ADPRI

24

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

analog-to-digital converter 1 module (continued)

The ADC1 module block diagram is illustrated in Figure 8.

Port E Input

Port E Data

ENA 0

AN 0

ADENA.0

SAMPLE

START

CONVERT

START

ADIN.0

2

1

0

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

ADCTL.2–0

ADCTL.6

ADCTL.7

Port E Input

ENA 1

Port E Data

AN 1

AD INPUT SELECT

ADENA.1

ADIN.1

Port E Input

ENA 2

Port E Data

AN 2

ADENA.2

ADIN.2

Port E Input

ENA 3

Port E Data

AN 3

ADENA.3

ADIN.3

ADDATA.7–0

A/D

Port E Input

ENA 4

Port E Data

AN 4

A-to-D

Conversion

Data Register

ADENA.4

ADIN.4

Port E Input

ENA 5

AD READY

ADSTAT.2

Port E Data

AN 5

ADENA.5

ADIN.5

AD PRIORITY

0

Level 1 INT

ADPRI.6

Port E Input

ENA 6

Port E Data

AN 6

1

Level 2 INT

ADENA.6

ADIN.6

5

4

3

ADCTL.5–3

Port E Input

ENA 7

AD INT FLAG

ADSTAT.1

Port E Data

AN 7

REF VOLTS SELECT

ADENA.7

ADIN.7

ADSTAT.0

AD INT ENA

V

CC3

V

SS3

Figure 8. ADC1 Block Diagram

25

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

instruction set overview

Table 16 provides an opcode to instruction cross reference of all 73 instructions and 274 opcodes of the

‘370Cx36 instruction set. The numbers at the top of this table represent the most significant nibble (MSN) of

the opcode while the numbers at the left side of the table represent the least significant nibble (LSN). The

instruction of these two opcode nibbles contains the mnemonic, operands, and byte/cycle particular to that

opcode.

For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes

in eight SYSCLK cycles.

26

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

development system support

The TMS370 family development support tools include an assembler, a C-compiler, a linker, CDT and an

EEPROM/UVEPROM programmer.

Assembler/linker (Part No. TMDS3740850–02 for PC)

–

Includes extensive macro capability

Provides high-speed operation

Includes format conversion utilities for popular formats

ANSI C Compiler (Part No. TMDS3740855–02 for PC, Part No. TMDS3740555–09 for HP700 , Sun-3

or Sun-4 )

–

Generate assembly code for the TMS370 that can be inspected easily

Improves code execution speed and reduces code size with optional optimizer pass

Enables direct reference the TMS370’s port registers by using a naming convention

Provides flexibility in specifying the storage for data objects

Interfaces C functions and assembly functions easily

Includes assembler and linker

CDT370 (Compact Development Tool) PACT real-time in-circuit emulation

–

Base (Part Number EDSCDT37P – for PC, requires cable)

Cable for 44-pin PLCC (Part No. EDSTRG44PLCC36)

–

EEPROM and EPROM programming support

Allows inspection and modification of memory locations

Includes compatibility to upload/download program and data memory

Execute programs and software routines

Includes 1024-sample trace buffer

Includes single-step executable instructions

Uses software breakpoints to halt program execution at selected address

Microcontroller programmer

–

Base (Part No. TMDS3760500A – for PC, requires programmer head)

Single unit head for 44-pin PLCC (Part No. TMDS3780512A)

PC-based, window/function-key-orienteduserinterfaceforeaseofuseandrapidlearningenvironment

–

HP700 is a trademark of Hewlett Packard, Incorporated.

Sun-3 and Sun-4 are trademarks of Sun Microsystems, Incorporated.

29

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

device numbering conventions

Figure 9 illustrates the numbering and symbol nomenclature for the TMS370Cx36 family.

TMS 370 C 7 36

A FN T

Prefix: TMS = Standard prefix for fully qualified devices

SE = System evaluator (window EPROM) that is used for

prototyping purpose.

Family: 370 = TMS370 8-Bit Microcontroller Family

Technology:

C = CMOS

Program Memory Types:

0 = Mask ROM

7 = EPROM

Device Type:

36 = x36 device containing the following modules:

– Analog-to-Digital Converter 1

– Serial Peripheral Interface

– Programmable Acquisition and

Control Timer (PACT)

Memory Size:

6 = 16K bytes

Temperature Ranges:

A = –40°C to 85°C

L =

0°C to 70°C

T = –40°C to 105°C

Packages:

FN = Plastic Leaded Chip Carrier

FZ = Ceramic Leaded Chip Carrier

ROM and EPROM Option:

A = For ROM device, the watchdog timer can be configured

as one of the three different mask options:

– A standard watchdog or

– A hard watchdog or

– A simple watchdog

The clock can be either:

– Divide-by-4 clock or

– Divide-by-1 (PLL) clock

The low-power modes can be either:

– Enabled or

– Disabled

A = For EPROM device, a standard watchdog, a divide-by-

4 clock, and low-power modes are enabled

Figure 9. TMS370Cx36 Family Nomenclature

30

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

device part numbers

Table 17 provides a listing of all the ’x36 devices available. The device part number nomenclature is designed

to assist ordering. Upon ordering, the customer must specify not only the device part number, but also the clock

and watchdog timer options desired. Each device can have only one of the three possible watchdog timer

options and one of the two clock options. The options to be specified pertain solely to orders involving ROM

devices.

Table 17. Device Part Numbers

DEVICE PART NUMBERS

FOR 44 PINS (LCC)

TMS370C036AFNA

TMS370C036AFNL

TMS370C036AFNT

TMS370C736AFNT

†

SE370C736AFZT

†

System evaluators are for use in prototype environment, and their

reliability has not been characterized.

31

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

new code release form

Figure 10 shows a sample of the new code release form.

NEW CODE RELEASE FORM

TEXAS INSTRUMENTS

DATE:

TMS370 MICROCONTROLLER PRODUCTS

To release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information:

1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media)

2. An attached specification if not using TI standard specification as incorporated in TI’s applicable device data book.

Company Name:

Street Address:

City:

Contact Mr./Ms.:

Phone: (

)

Ext.:

State

Zip

Customer Purchase Order Number:

Customer Print Number *Yes:

No:

*If Yes: Customermust provide ”print” to TI w/NCRF for approvalbefore ROM

code processing starts.

#

Customer Part Number:

Customer Application:

(Std. spec to be followed)

TMS370 Device:

TI Customer ROM Number:

(provided by Texas Instruments)

CONTACT OPTIONS FOR THE ’A’ VERSION TMS370 MICROCONTROLLERS

OSCILLATOR FREQUENCY

Low Power Modes

[] Enabled

[] Disabled

Watchdog counter

[] Standard

[] Hard Enabled

[] Simple Counter

Clock Type

[] Standard (/4)

[] PLL (/1)

MIN

TYP

MAX

[] External Drive (CLKIN)

[] Crystal

[] Ceramic Resonator

NOTE:

Non ’A’ version ROM devices of the TMS370 microcontrollers will have the

“Low-powermodesEnabled”, “Divide-by-4”Clock, and“Standard”Watchdog

options. See the TMS370 Family User’s Guide (literature number SPNU127)

or the TMS370 Family Data Manual (literature number SPNS014B).

[] Supply Voltage MIN:

(std range: 4.5V to 5.5V)

MAX:

TEMPERATURE RANGE

PACKAGE TYPE

[] ’L’:

[] ’A’:

[] ’T’:

0° to 70°C (standard)

–40° to 85°C

–40° to 105°C

[] ’N’ 28-pin PDIP

[] “FN” 28-pin PLCC

[] “N” 40-pin PDIP

[] “FN” 44-pin PLCC

[] “FN” 68-pin PLCC

[] “NM” 64-pin PSDIP

[] “NJ” 40-pin PSDIP (formerly known as N2)

SYMBOLIZATION

BUS EXPANSION

[] TI standard symbolization

[] YES

[] NO

[] TI standard w/customer part number

[] Customer symbolization

(per attached spec, subject to approval)

NON-STANDARD SPECIFICATIONS:

ALL NON-STANDARDS SPECIFICATIONS MUST BE APPROVED BY THE TI ENGINEERING STAFF: If the customer requires expedited production material

(i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the

satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard

TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a ’P’ in the symbolization preceding the

TI part number.

RELEASE AUTHORIZATION:

This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must

be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification

code is approved by the customer.

1. Customer:

Date:

2. TI: Field Sales:

Marketing:

Prod. Eng.:

Proto. Release:

Figure 10. Sample New Code Release Form

32

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

Table 18. Peripheral File Frame Compilation

Table 18 is a collection of all the peripheral file frames used in the ’Cx36 (provided for a quick reference).

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

System Configuration Registers

COLD

START

OSC

POWER

PF AUTO

WAIT

OSC FLT

FLAG

MC PIN

WPO

MC PIN

DATA

µP/µC

MODE

P010

P011

P012

—

SCCR0

SCCR1

SCCR2

AUTO

WAIT

DISABLE

MEMORY

DISABLE

—

HALT/

STANDBY

PWRDWN/

IDLE

BUS

STEST

CPU

STEST

INT1

NMI

PRIVILEGE

DISABLE

—

P013

to

Reserved

P016

INT1

FLAG

INT1

PIN DATA

INT1

POLARITY

INT1

PRIORITY

INT1

ENABLE

P017

—

INT1

P018

P019

P01A

P01B

P01C

Reserved

BUSY

—

AP

—

W1W0

W0

EXE

DEECTL

EPCTLL

Reserved

VPPS

P01D

P01E

P01F

Digital Port Control Registers

P020

P021

P022

P023

Reserved

APORT1

APORT2

ADATA

ADIR

Port A Control Register 2 (must be 0)

Port A Data

Port A Direction

P024

to

Reserved

P02B

P02C

P02D

P02E

P02F

Port D Control Register 1 (must be 0)

—

DPORT1

DPORT2

DDATA

DDIR

†

Port D Control Register 2 (must be 0)

Port D Data

Port D Direction

SPI Module Control Register Memory Map

SPI SW

RESET

CLOCK

POLARITY

SPI BIT

RATE2

SPI BIT

RATE1

SPI BIT

RATE0

SPI

CHAR2

SPI

CHAR1

SPI

CHAR0

P030

P031

SPICCR

SPICTL

RECEIVER

OVERRUN

SPI INT

FLAG

MASTER/

SLAVE

SPI INT

ENA

—

TALK

P032

to

Reserved

P036

P037

P038

P039

RCVD7

SDAT7

RCVD6

SDAT6

RCVD5

SDAT5

RCVD4

SDAT4

RCVD3

Reserved

SDAT3

RCVD2

SDAT2

RCVD1

SDAT1

RCVD0

SDAT0

SPIBUF

SPIDAT

†

To configure D3 as SYSCLK, set port D register 2 = 08h.

33

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

Table 18. Peripheral File Frame Compilation (Continued)

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

SPI Module Control Register Memory Map (Continued)

P03A

to

Reserved

P03C

SPICLK

DATA IN

SPICLK

DATA OUT

SPICLK

FUNCTION

SPICLK

DATA DIR

P03D

P03E

P03F

—

SPIPC1

SPIPC2

SPIPRI

SPISIMO

DATA IN

SPISIMO

DATA OUT

SPISIMO

FUNCTION

SPISIMO

DATA DIR

SPISOMI

DATA IN

SPISOMI

DATA OUT

SPISOMI

FUNCTION

SPISOMI

DATA DIR

SPI

STEST

SPI

PRIORITY

SPI

ESPEN

—

PACT Module Register Memory Map

DEFTIM

OVRFL

INT ENA

DEFTIM

OVRFL

INT FLAG

FAST

MODE

SELECT

PACT

PRESCALE

SELECT0

CMD/DEF

AREA ENA

P040

P041

PRESCALE PRESCALE PRESCALE

SELECT3

PACTSCR

CDSTART

SELECT2

SELECT1

CMD/DEF

AREA

START

BIT 5

CMD/DEF

AREA

START

BIT 4

CMD/DEF

AREA

START

BIT 3

CMD/DEF

AREA

START

BIT 2

CMD/DEF

AREA

INT ENA

—

CMD/DEF

AREA

END BIT 6

CMD/DEF

AREA

END BIT 5

CMD/DEF

AREA

END BIT 4

CMD/DEF

AREA

END BIT 3

CMD/DEF

AREA END

BIT 2

P042

P043

—

1

—

CDEND

BUFFER

POINTER

BIT 5

BUFFER

POINTER

BIT 4

BUFFER

POINTER

BIT 3

BUFFER

POINTER

BIT 2

BUFFER

POINTER

BIT 1

1

BUFPTR

P044

P045

Reserved

PACT SCI

PACT

RXRDY

PACT

TXRDY

PACT

PARITY

PACT SCI

PACT SCI SW

RESET

PACT FE

—

SCICTLP

RX INT ENA TX INT ENA

PACT

RXDT7

PACT

RXDT6

PACT

RXDT5

PACT

RXDT4

PACT

RXDT3

PACT

RXDT2

PACT

RXDT1

P046

P047

P048

P049

PACT RXDT0 RXBUFP

PACT TXDT0 TXBUFP

PACT

TXDT7

PACT

TXDT6

PACT

TXDT5

PACT

TXDT4

PACT

TXDT3

PACT

TXDT2

PACT

TXDT1

PACT OP8

STATE

PACT OP7

STATE

PACT OP6

STATE

PACT OP5

STATE

PACT OP4

STATE

PACT OP3

STATE

PACT OP2

STATE

PACT OP1

PSTATE

STATE

CMD/DEF

INT 7 FLAG

CMD/DEF

INT 6 FLAG

CMD/DEF

INT 5 FLAG

CMD/DEF

INT 4 FLAG

CMD/DEF

INT 3 FLAG

CMD/DEF

INT 2 FLAG

CMD/DEF

INT 1 FLAG

CMD/DEF

CDFLAGS

INT 0 FLAG

CP2 CAPT

RISING

EDGE

CP2 CAPT

FALLING

EDGE

CP1 CAPT

RISING

EDGE

CP1 CAPT

FALLING

EDGE

CP2 INT

ENA

CP2 INT

FLAG

CP1 INT

ENA

CP1 INT

FLAG

P04A

P04B

P04C

CPCTL1

CPCTL2

CPCTL3

CP4 CAPT

RISING

EDGE

CP4 CAPT

FALLING

EDGE

CP3 CAPT

RISING

EDGE

CP3 CAPT

FALLING

EDGE

CP4 INT

ENA

CP4 INT

FLAG

CP3 INT

ENA

CP3 INT

FLAG

CP6 CAPT

RISING

EDGE

CP6 CAPT

FALLING

EDGE

CP5 CAPT

RISING

EDGE

CP5 CAPT

FALLING

EDGE

CP6 INT

ENA

CP6 INT

FLAG

CP5 INT

ENA

CP5 INT

FLAG

INPUT

CAPT

PRESCALE

SELECT 3

INPUT

CAPT

PRESCALE

SELECT 2

INPUT

CAPT

PRESCALE

SELECT 1

BUFFER

P04D HALF/FULL

INT ENA

BUFFER

HALF/FULL

INT FLAG

EVENT

COUNTER

SW RESET

CP6 EVENT

ONLY

OP/ SET/CLR

SELECT

CPPRE

34

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

Table 18. Peripheral File Frame Compilation (Continued)

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

PACT Module Register Memory Map (Continued)

P04E

P04F

WATCHDOG RESET KEY

WDRST

PACT

GROUP 1

PRIORITY

PACT

MODE

SELECT

PACT WD

PRESCALE

SELECT 1

PACT WD

PRESCALE

SELECT 0

PACT

STEST

PACT

SUSPEND

GROUP 2

PRIORITY

GROUP 3

PRIORITY

PACTPRI

ADC1 Module Control Register Memory Map

CONVERT

START

SAMPLE

START

REF VOLT

SELECT2

REF VOLT

SELECT1

REF VOLT

SELECT0

AD INPUT

SELECT2

AD INPUT

SELECT1

AD INPUT

SELECT0

P070

ADCTL

AD INT

FLAG

P071

P072

—

AD READY

AD INT ENA

ADSTAT

ADDATA

ADC1 Conversion Data Register

RESERVED

P073

to

P07C

P07D

P07E

Port E Data Input Register

Port E Input Enable Register

ADIN

ADENA

AD

PRIORITY

P07F AD STEST

AD ESPEN

—

ADPRI

35

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range,V

(see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 7 V

CC1

Input voltage range, All pins except MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to7 V

MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 14 V

Input clamp current, I (V < 0 or V > V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

IK

I

CC)

Output clamp current, I

OK

O

CC

Continuous output current per buffer, I (V = 0 to V ) (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA

O

CC)

Maximum I

current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 mA

CC

Maximum I current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 170 mA

SS

Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W

Operating free-air temperature, T : L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A

A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 105°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 4. Unless otherwise noted, all voltage values are with respect to V

.

SS1

5. Electrical characteristics are specified with all output buffers loaded with specified I current. Exceeding the specified I current in

O

any buffer can affect the levels on other buffers.

recommended operating conditions

MIN

4.5

3

NOM

MAX

UNIT

V

Supply voltage (see Note 4)

5

5.5

0.3

0.8

0.3

V

CC1

RAM data-retention supply voltage (see Note 6)

Standby RAM supply voltage

V

4.5

3

5

V

CCSTBY

Standby RAM data retention supply voltage (see Note 6)

Analog supply voltage (see Note 4)

Analog supply ground

V

4.5

– 0.3

5

0

V

CC3

SS3

All pins except MC

Low-level input voltage

V

SS1

V

IL

MC, normal operation

V

SS1

All pins except MC, XTAL2/CLKIN, and

RESET

2

V

CC1

V

IH

High-level input voltage

V

XTAL2/CLKIN

0.8 V

0.7 V

V

CC1

RESET

CC1

13

EEPROM write protect override (WPO)

11.7

12

V

MC

MC (mode control) voltage

EPROM programming voltage (V

Microcomputer

L version

)

13

13.2

13.5

0.3

70

V

PP

V

SS1

0

T

A

Operating free-air temperature

A version

– 40

85

°C

T version

105

NOTES: 4. Unless otherwise noted, all voltage values are with respect to V

.

SS1

6. RESET must be externally activated when V

CC1

or SYSCLK is not within the recommended operating range.

36

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

Low-level output voltage

All outputs

I

= 1.4 mA

0.4

V

OL

All outputs

except PACT

outputs

= –50 µA

0.9 V

OH

CC1

V

OH

High-level output voltage

V

PACT outputs

All outputs

I

= –50 µA

0.7 V

OH

= –2 mA

2.4

OH

0 V ≤ V ≤ 0.3 V

10

50

µA

mA

µA

mA

I

0.3 V < V < V

– 0.3 V

I

CC1

MC

I

Input current

V

–0.3 < V < V

+0.3 V

CC1

10

CC1

I

+0.3 V < V < 13 V

650

± 10

CC1

I

I/O pins

0 V <V < V

I

CC1

= 0.4 V

I

Low-level output current

High-level output current

All outputs

V

OL

V

OH

V

OH

1.4

– 50

– 2

OL

= 0.9 V

= 2.4 V

CC1

All outputs

OH

Supply current (operating mode)

OSC POWER bit = 0

See Notes 7 and 8

SYSCLK = 5 MHz

36

7

45

12

mA

µA

Supply current (STANDBY mode)

OSC POWER bit = 0

See Notes 7 and 8

SYSCLK = 5 MHz

I

CC1

See Notes 7 and 8

XTAL2/CLKIN < 0.2 V

Supply current (HALT mode)

5

30

Standby RAM supply current (operating mode OSC SYSCLK = 5 MHz

POWER bit = 0) = 4.5 V

1

1.5

mA

CCSTBY

V

CCSTBY

NOTES: 7. Single chip mode, ports configured as inputs or outputs with no load. All inputs ≤ 0.2 V or ≥ V

– 0.2V.

CC1

8. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current

can be higher with a crystal oscillator. At 5-MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance

in pF).

37

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

XTAL2/CLKIN

XTAL1

XTAL2/CLKIN

XTAL1

C3

(see Note A)

C1

(see Note A)

C2

Crystal/Ceramic

Resonator

(see Note B)

External

Clock Signal

(see Note A)

NOTES: A. The values of C1 and C2 are typically 15 pF and C3 value is typically 50 pF. See the manufacturer’s recommendations for ceramic

resonators.

B. The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period.

Figure 11. Recommended Crystal/Clock Connections

Load Voltage

1.2 kΩ

V

O

20 pF

Case 1: V = V

= 2.4 V; Load Voltage = 0 V

= 0.4 V; Load Voltage = 2.1 V

O

OH

OL

Case 2: V = V

O

NOTE A: All measurements are made with the pin loading as shown unless otherwise noted. All measurements are made with XTAL2/CLKIN

driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated.

Figure 12. Typical Output Load Circuit (See Note A)

V

CC

V

CC

Pin Data

300 Ω

30 Ω

6 kΩ

Output

Enable

I/O

INT1

20 Ω

GND

Figure 13. Typical Buffer Circuitry

38

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

PARAMETER MEASUREMENT INFORMATION

timing parameter symbology

Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten the

symbols, some of the pin names and other related terminology have been abbreviated as follows:

AR

B

CI

M

S

Array

Byte

XTAL2/CLKIN

Master mode

Slave mode

SC

SYSCLK

SPISIMO

SPISOMI

SPICLK

SIMO

SOMI

SPC

Lowercase subscripts and their meanings are:

c

d

f

cycle time (period)

delay time

fall time

su

v

w

setup time

valid time

pulse duration (width)

r

rise time

The following additional letters are used with these meanings:

H

L

V

High

Low

Valid

All timings are measured between high and low measurement points as indicated in Figure 14 and Figure 15.

0.8 V

V (High)

2 V (High)

CC

0.8 V (Low)

Figure 14. XTAL2/CLKIN Measurement Points

Figure 15. General Measurement Points

39

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

external clocking requirements for clock divided by 4 (see Note 9 and Figure 16)

NO.

1

PARAMETER

Pulse duration, XTAL2/CLKIN (see Note 10)

Rise time, XTAL2/CLKIN

MIN

MAX

UNIT

ns

t

20

w(Cl)

2

30

100

20

5

ns

r(Cl)

3

Fall time, XTAL2/CLKIN

ns

f(CI)

4

Delay time, XTAL2/CLKIN rise to SYSCLK fall

Crystal operating frequency

ns

d(CIH-SCL)

CLKIN

2

MHz

†

SYSCLK

Internal system clock operating frequency

0.5

†

SYSCLK = CLKIN/4

NOTES: 9. For V and V , refer to recommended operating conditions.

IL IH

10. This pulse may be either a high pulse, as illustrated below, which extends from the earliest valid high to the final valid high in an

XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

1

XTAL2/CLKIN

2

3

4

SYSCLK

Figure 16. External Clock Timing for Divide-by-4

external clocking requirements for clock divided by 1 (PLL) (see Note 9 and Figure 17)

NO.

1

PARAMETER

Pulse duration, XTAL2/CLKIN (see Note 10)

Rise time, XTAL2/CLKIN

MIN

MAX

UNIT

ns

t

20

w(Cl)

2

30

100

5

ns

r(Cl)

3

Fall time, XTAL2/CLKIN

ns

f(CI)

4

Delay time, XTAL2/CLKIN rise to SYSCLK rise

Crystal operating frequency

ns

d(CIH-SCH)

CLKIN

2

MHz

‡

SYSCLK

Internal system clock operating frequency

5

‡

SYSCLK = CLKIN/1

NOTES: 9. For V and V , refer to recommended operating conditions.

IL IH

10. This pulse can be either a high pulse, as illustrated below, which extends from the earliest valid high to the final valid high in an

XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

1

XTAL2/CLKIN

4

2

3

SYSCLK

Figure 17. External Clock Timing for Divide-by-1

40

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

switching characteristics and timing requirements (see Note 11 and Figure 18)

NO.

PARAMETER

MIN

200

MAX

2000

500

UNIT

Divide by 4

Divide by 1

5

t

c

Cycle time, SYSCLK (system clock)

ns

6

7

t

Pulse duration, SYSCLK low

Pulse duration, SYSCLK high

0.5 t –20

0.5 t

c

ns

w(SCL)

c

0.5 t

0.5 t + 20

c

w(SCH)

c

NOTE 11: t = system clock cycle time = 1/SYSCLK

c

5

7

6

SYSCLK

Figure 18. SYSCLK Timing

general purpose output signal switching time requirements (see Figure 19)

MIN

TYP

30

MAX

UNIT

t

Rise time

Fall time

ns

r

30

f

t

r

t

f

Figure 19. Signal Switching Timing

recommended EEPROM timing requirements for programming

MIN

MAX

UNIT

ms

t

Pulse duration, programming signal to ensure valid data is stored (byte mode)

Pulse duration, programming signal to ensure valid data is stored (array mode)

10

20

w(PGM)B

ms

w(PGM)AR

recommended EPROM operating conditions for programming

MIN

TYP

5.5

MAX

6

UNIT

V

Supply voltage

4.75

13

CC

Supply voltage at MC pin

13.2

30

13.5

50

5

V

PP

I

Supply current at MC pin during programming (V

= 13 V)

mA

PP

Divide by 4

Divide by 1

0.5

2

SYSCLK

System clock

MHz

5

recommended EPROM timing requirements for programming

MIN

TYP

MAX

UNIT

t

Pulse duration, programming signal (see Note 12)

0.40

0.50

3

ms

w(EPGM)

NOTE 12: Programming pulse is active when both EXE (EPCTL.0) and V

(EPCTL.6) are set.

PPS

41

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

SPI master mode external timing characteristics and requirements (see Note 11 and Figure 20)

NO.

38

39

40

41

42

43

MIN

2t

MAX

256t

UNIT

ns

t

Cycle time, SPICLK

c(SPC)M

c

Pulse duration, SPICLK low

t

– 45

– 55

0.5t

+45

ns

w(SPCL)M

c

c(SPC)

Pulse duration, SPICLK high

t

ns

w(SPCH)M

c(SPC)

50

Delay time, SPISIMO valid after SPICLK low (polarity = 1)

Valid time, SPISIMO data valid after SPICLK high (polarity =1)

Setup time, SPISOMI to SPICLK high (polarity = 1)

– 65

ns

d(SPCL-SIMOV)M

v(SPCH-SIMO)M

su(SOMI-SPCH)M

t

– 50

ns

w(SPCH)

0.25 t + 150

c

ns

Valid time, SPISOMI data valid after SPICLK high

(polarity = 1)

44

t

0

ns

v(SPCH-SOMI)M

NOTE 11: t = system clock cycle time = 1/SYSCLK

c

38

40

39

SPICLK

41

42

Data Valid

SPISIMO

43

44

Data Valid

SPISOMI

†

The diagram is for polarity = 1. SPICLK is inverted when polarity = 0.

†

Figure 20. SPI Master External Timing

42

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

SPI slave mode external timing characteristics and requirements (see Note 11 and Figure 21)

NO.

45

46

47

48

49

50

51

MIN

8t

MAX

UNIT

ns

t

Cycle time, SPICLK

c(SPC)S

c

Pulse duration, SPICLK low

4t – 45 0.5t

c

+45

ns

w(SPCL)S

c(SPC)S

Pulse duration, SPICLK high

4t – 45 0.5t

c

ns

w(SPCH)S

c(SPC)S

+ 130

Delay time, SPISOMI valid after SPICLK low (polarity = 1)

Valid time, SPISOMI data valid after SPICLK high (polarity =1)

Setup time, SPISIMO to SPICLK high (polarity = 1)

Valid time, SPISIMO data after SPICLK high (polarity = 1)

3.25t

ns

d(SPCL-SOMIV)S

v(SPCH-SOMI)S

su(SIMO-SPCH)S

v(SPCH-SIMO)S

c

t

ns

w(SPCH)S

0

ns

3t + 100

C

ns

NOTE 11: t = system clock cycle time = 1/SYSCLK

c

45

47

46

SPICLK

48

49

Data Valid

SPISIMO

50

51

Data Valid

SPISOMI

†

The diagram is for polarity = 1. SPICLK is inverted when polarity = 0.

†

Figure 21. SPI Slave External Timing

43

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

ADC1 converter

The ADC1 converter has a separate power bus for its analog circuitry. These pins are referred to as V

and

CC3

V

. The purpose is to enhance ADC1 performance by preventing digital switching noise of the logic circuitry

SS3

that can be present on V

given with respect to V

and V

from coupling into the ADC1 analog stage. All ADC1 specifications are

SS1

CC1

unless otherwise noted.

SS3

Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-bits (256 values)

Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Yes

Output conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00h to FFh (00 for V ≤ V

Conversion time (excluding sample time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 t

≤; FF for V ≤ V

)

I

SS3

I

ref

c

recommended operating conditions

MIN

NOM

MAX

UNIT

4.5

5

5.5

V

Analog supply voltage

Analog ground

V

CC3

V

–0.3

CC1

V

+0.3

CC1

V

–0.3

SS1

V

+0.3

SS1

V

SS3

†

V

ref

Non-V

CC3

reference

2.5

V

+ 0.1

CC3

Analog input for conversion

V

ref

SS3

†

V

ref

must be stable, within ± 1/2 LSB of the required resolution, during the entire conversion time.

operating characteristics over recommended ranges operating conditions

PARAMETER

MIN

MAX

±1.5

±0.9

2

UNIT

LSB

mA

µA

‡

Absolute accuracy

V

= 5.5 V

V

= 5.1 V

CC3

ref

‡§

Differential/integral linearity error

V

ref

CC3

Converting

I

Analog supply current

CC3

Nonconverting

5

I

Input current, AN0–AN7

Input charge current

0 V ≤ V ≤ 5.5 V

2

µA

I

1

mA

kΩ

ref

SYSCLK ≤ 3 MHz

24

10

Z

Source impedance of V

ref

3 MHz < SYSCLK ≤ 5 MHz

kΩ

‡

§

Absolute resolution = 20 mV. At V = 5 V, this is one LSB. As V decreases, LSB size decreases; therefore, the absolute accuracy and

differential/integral linearity errors in terms of LSBs increase.

Excluding quantization error of 1/2 LSB

ref

44

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

ADC1 converter (continued)

The ADC1 module allows complete freedom in design of the sources for the analog inputs. The period of the

sample time is user-defined so that the high-impedance can be accommodated without penalty to the

low-impedance sources. The sample period begins when the SAMPLE START bit of the ADC1 control register

(ADCTL.6) is set to 1. The end of the signal sample period occurs when the conversion bit (CONVERT START,

ADCTL.7) is set to 1. After a hold time, the converter will reset the SAMPLE START and CONVERT START bits,

signaling that a conversion has started and that the analog signal can be removed.

analog timing requirements (see Figure 22)

MIN

MAX

UNIT

ns

t

Setup time, analog to sample command

0

su(S)

h(AN)

w(S)

Hold time, analog input from start of conversion

Pulse duration, sample time per kilo-Ω of source impedance

18t

ns

c

†

1

µs/kΩ

†

The value given is valid for a signal with a source impedance > 1 kΩ. If the source impedance is < 1 kΩ, use a minimum sampling time of 1µs.

Analog Stable

Analog In

t

su(S)

Sample Start

Convert Start

t

h(AN)

t

w(S)

Figure 22. Analog Timing

Table 19 is designed to aid the user in referencing a device part number to a mechanical drawing. The table

shows a cross-reference of the device part number to the TMS370 generic package name and the associated

mechanical drawing by drawing number and name.

Table 19. TMS370Cx36 Family Package Type and Mechanical Cross-Reference

PKG TYPE

(mil pin spacing)

PKG TYPE NO. AND

MECHANICAL NAME

TMS370 GENERIC NAME

DEVICE PART NUMBERS

TMS370C036AFNA

TMS370C036AFNL

TMS370C036AFNT

TMS370C736AFNT

FN – 44 pin

(50-mil pin spacing)

PLASTIC LEADED CHIP CARRIER

(PLCC)

FN(S-PQCC-J**) PLASTIC J-LEADED

CHIP CARRIER

FZ – 44 pin

(50-mil pin spacing)

CERAMIC LEADED CHIP CARRIER

(CLCC)

FZ(S-CQCC-J**) J-LEADED CERAMIC

CHIP CARRIER

†

SE370C736AFZT

45

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

MECHANICAL DATA

FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

0.180 (4,57) MAX

0.120 (3,05)

D

0.090 (2,29)

D1

0.020 (0,51) MIN

3

1

19

0.032 (0,81)

0.026 (0,66)

4

18

D2/E2

E

E1

8

14

0.021 (0,53)

0.013 (0,33)

0.050 (1,27)

9

13

0.007 (0,18)

M

0.008 (0,20) NOM

D/E

D1/E1

D2/E2

NO. OF

PINS

**

MIN

0.385 (9,78)

MAX

MIN

MAX

MIN

MAX

0.395 (10,03)

0.350 (8,89)

0.356 (9,04)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

20

28

44

52

68

84

0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)

0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)

0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)

0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

46

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

J-LEADED CERAMIC CHIP CARRIER

Seating Plane

MECHANICAL DATA

FZ (S-CQCC-J**)

28 LEAD SHOWN

0.040 (1,02)

45°

0.180 (4,57)

0.155 (3,94)

0.140 (3,55)

A

B

1

0.120 (3,05)

26

4

25

5

0.050 (1,27)

C

(at Seating

Plane)

A

B

0.032 (0,81)

0.026 (0,66)

0.020 (0,51)

0.014 (0,36)

19

11

18

12

0.025 (0,64) R TYP

0.040 (1,02) MIN

0.120 (3,05)

0.090 (2,29)

A

B

C

JEDEC

NO. OF

PINS**

OUTLINE

MIN

MAX

MIN

MAX

MIN

MAX

0.485

0.495

0.430

0.455

0.410

0.430

MO-087AA

MO-087AB

MO-087AC

MO-087AD

28

44

52

68

(12,32)

(12,57)

(10,92)

(11,56)

(10,41)

(10,92)

0.685

0.695

0.630

0.655

0.610

0.630

(17,40)

(17,65)

(16,00)

(16,64)

(15,49)

(16,00)

0.785

0.795

0.730

0.765

0.680

0.740

(19,94)

(20,19)

(18,54)

(19,43)

(17,28)

(18,79)

0.985

0.995

0.930

0.955

0.910

0.930

(25,02)

(25,27)

(23,62)

(24,26)

(23,11)

(23,62)

4040219/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

47

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型号：	TMS370C736A
厂家：	TEXAS INSTRUMENTS
描述：	8-BIT MICROCONTROLLER 8位微控制器微控制器
文件：	总48页 (文件大小：711K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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