TMS470R1B1M_12_技术文档

TMS470R1B1M

16/32-Bit RISC Flash Microcontroller

www.ti.com

SPNS109A–SEPTEMBER 2005–REVISED AUGUST 2006

FEATURES

•

Twelve Communication Interfaces:

– Two Serial Peripheral Interfaces (SPIs)

– 255 Programmable Baud Rates

•

High-Performance Static CMOS Technology

•

TMS470R1x 16/32-Bit RISC Core

(ARM7TDMI™)

– Three Serial Communication Interfaces

(SCIs)

• 2²⁴Selectable Baud Rates

– 60-MHz System Clock (Pipeline Mode)

– Independent 16/32-Bit Instruction Set

– Open Architecture With Third-Party Support

– Built-In Debug Module

• Asynchronous/Isosynchronous Modes

– Two High-End CAN Controllers (HECC)

• 32-Mailbox Capacity

•

Integrated Memory

– 1M-Byte Program Flash

• Fully Compliant With CAN Protocol,

Version 2.0B

• Two Banks With 16 Contiguous Sectors

– 64K-Byte Static RAM (SRAM)

– Memory Security Module (MSM)

– JTAG Security Module

– Five Inter-Integrated Circuit (I2C) Modules

• Multi-Master and Slave Interfaces

• Up to 400 Kbps (Fast Mode)

• 7- and 10-Bit Address Capability

High-End Timer Lite (HET)

•

Operating Features

•

– Low-Power Modes: STANDBY and HALT

– Industrial Temperature Range

470+ System Module

– 12 Programmable I/O Channels:

• 12 High-Resolution Pins

– High-Resolution Share Feature (XOR)

– High-End Timer RAM

– 32-Bit Address Space Decoding

– Bus Supervision for Memory/Peripherals

– Digital Watchdog (DWD) Timer

– Analog Watchdog (AWD) Timer

– Enhanced Real-Time Interrupt (RTI)

– Interrupt Expansion Module (IEM)

– System Integrity and Failure Detection

– ICE Breaker

• 64-Instruction Capacity

•

External Clock Prescale (ECP) Module

– Programmable Low-Frequency External

Clock (CLK)

12-Channel, 10-Bit Multi-Buffered ADC

(MibADC)

– 64-Word FIFO Buffer

•

Direct Memory Access (DMA) Controller

– 32 Control Packets and 16 Channels

– Single- or Continuous-Conversion Modes

– 1.55 µs Minimum Sample and Conversion

Time

Zero-Pin Phase-Locked Loop (ZPLL)-Based

Clock Module With Prescaler

– Calibration Mode and Self-Test Features

Flexible Interrupt Handling

– Multiply-by-4 or -8 Internal ZPLL Option

– ZPLL Bypass Mode

•

Expansion Bus Module (EBM)

– Supports 8- and 16-Bit Expansion Bus

Memory Interface Mappings

– 42 I/O Expansion Bus Pins

•

46 Dedicated General-Purpose I/O (GIO) Pins

and 47 Additional Peripheral I/Os

•

Sixteen External Interrupts

On-Chip Scan-Base Emulation Logic, IEEE

Standard 1149.1⁽¹⁾(JTAG) Test-Access Port

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TMS470R1B1M

16/32-Bit RISC Flash Microcontroller

www.ti.com

SPNS109A–SEPTEMBER 2005–REVISED AUGUST 2006

•

144-Pin Plastic Low-Profile Quad Flatpack

(PGE Suffix)

(1)

The test-access port is compatible with the IEEE Standard

1149.1-1990, IEEE Standard Test-Access Port and Boundary

Scan Architecture specification. Boundary scan is not

supported on this device.

TMS470R1B1M 144-Pin PGE Package Without Expansion Bus (Top View)

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

AD

109

HET[1]

HET[2]

GIOE[6]

REFHI

AD

REFLO

110

111

112

V

CCAD

V

SSAD

CCIO

ADIN[4] 113

ADIN[3] 114

ADIN[2] 115

ADIN[1] 116

ADIN[0] 117

PORRST 118

SSIO

GIOE[5]

HET[3]

HET[4]

GIOE[4]

HET[5]

SPI2SCS

GIOE[3]

SPI2ENA

SPI2SIMO

GIOE[2]

SPI2SOMI

SPI2CLK

CAN2HTX

CAN2HRX

GIOC[4]

GIOC[3]

119

120

RST 121

V

SS

122

123

V

CC

TEST 124

GIOH[5]

GIOC[2]

GIOA[4]/INT[4]

GIOC[1]

125

126

127

128

129

130

131

V

CC

V

SS

CC

SS

SCI2CLK

SCI2RX

SCI2TX

SCI1CLK

GIOE[1]

SCI1RX

SCI1TX

GIOE[0]

GIOB[0]

GIOD[0]

I2C4SDA

I2C4SCL

GIOD[1]

I2C5SDA

I2C5SCL

V

CCP

FLTP2 132

GIOA[3]/INT[3]

GIOA[2]/INT[2]

GIOC[0]

133

134

135

GIOA[1]/INT[1]/ECLK 136

V

137

138

139

140

141

142

143

CCIO

SSIO

GIOH[0]

GIOG[7]

GIOA[0]/INT[0]

GIOG[6]

GIOG[5]

TRST 144

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TMS470R1B1M

16/32-Bit RISC Flash Microcontroller

www.ti.com

SPNS109A–SEPTEMBER 2005–REVISED AUGUST 2006

TMS470R1B1M 144-Pin PGE Package With Expansion Bus (Top View)

AD

109

110

111

112

72 HET[1]

71 HET[2]

70 EBDATA[6]

REFHI

AD

REFLO

V

CCAD

69

68

V

SSAD

CCIO

ADIN[4] 113

ADIN[3] 114

ADIN[2] 115

ADIN[1] 116

ADIN[0] 117

PORRST 118

EBCS[6] 119

EBCS[5] 120

RST 121

SSIO

67 EBDATA[5]

66 HET[3]

65 HET[4]

64 EBDATA[4]

63 HET[5]

62 SPI2SCS

61 EBDATA[3]

60 SPI2ENA

59 SPI2SIMO

58 EBDATA[2]

57 SPI2SOMI

56 SPI2CLK

55 CAN2HTX

54 CAN2HRX

V

SS

122

123

V

CC

TEST 124

EBHOLD 125

EBWR[1] 126

GIOA[4]/INT[4]

127

EBWR[0] 128

53

52

V

CC

V

129

130

131

SS

CC

SS

51 SCI2CLK

50 SCI2RX

V

CCP

FLTP2 132

49 SCI2TX

GIOA[3]/INT[3]

GIOA[2]/INT[2]

133

134

48 SCI1CLK

47 EBDATA[1]

EBOE 135

GIOA[1]/INT[1]/ECLK 136

46 SCI1RX

45 SCI1TX

V

137

138

44 EBDATA[0]

43 EBDMAREQ[0]

42 EBADDR[0]

41 EBADDR[23]/EBADDR[15]

40 EBADDR[24]/EBADDR[16]

39 EBADDR[1]

38 EBADDR[26]/EBADDR[18]

37 EBADDR[25]/EBADDR[17]

CCIO

SSIO

EBADDR[22]/EBADDR[14] 139

EBADDR[21]/EBADDR[13] 140

GIOA[0]/INT[0]

141

EBADDR[20]/EBADDR[12] 142

EBADDR[19]/EBADDR[11] 143

TRST 144

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TMS470R1B1M

16/32-Bit RISC Flash Microcontroller

www.ti.com

SPNS109A–SEPTEMBER 2005–REVISED AUGUST 2006

DESCRIPTION

The TMS470R1B1M⁽¹⁾devices are members of the Texas Instruments TMS470R1x family of general-purpose

16/32-bit reduced instruction set computer (RISC) microcontrollers. The B1M microcontroller offers high

performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a

high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views

memory as a linear collection of bytes numbered upwards from zero. The TMS470R1B1M utilizes the big-endian

format where the most significant byte of a word is stored at the lowest numbered byte and the least significant

byte at the highest numbered byte.

High-end embedded control applications demand more performance from their controllers while maintaining low

costs. The B1M RISC core architecture offers solutions to these performance and cost demands while

maintaining low power consumption.

The B1M devices contain the following:

•

ARM7TDMI 16/32-Bit RISC CPU

TMS470R1x system module (SYS) with 470+ enhancements

1M-byte flash

64K-byte SRAM

Zero-pin phase-locked loop (ZPLL) clock module

Digital watchdog (DWD) timer

Analog watchdog (AWD) timer

Enhanced real-time interrupt ( RTI) module

Interrupt expansion module (IEM)

Memory security module (MSM)

JTAG security module

Two serial peripheral interface (SPI) modules

Three serial communications interface (SCI) modules

Two high-end CAN controllers (HECC)

Five inter-integrated circuit (I2C) modules

10-bit multi-buffered analog-to-digital converter (MibADC), with 12 input channels

High-end timer lite (HET) controlling 12 I/Os

External clock prescale (ECP)

Expansion bus module (EBM)

Up to 93 I/O pins

The functions performed by the 470+ system module (SYS) include:

•

Address decoding

Memory protection

Memory and peripherals bus supervision

Reset and abort exception management

Prioritization for all internal interrupt sources

Device clock control

Parallel signature analysis (PSA)

The enhanced real-time interrupt (RTI) module on the B1M has the option to be driven by the oscillator clock.

The digital watchdog (DWD) is a 25-bit resettable decrementing counter that provides a system reset when the

watchdog counter expires. This data sheet includes device-specific information such as memory and peripheral

select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the

SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189).

The B1M memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,

half-word, and word modes.

(1) Throughout the remainder of this document, the TMS470R1B1M will be referred to as either the full device name or as B1M.

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TMS470R1B1M

16/32-Bit RISC Flash Microcontroller

www.ti.com

SPNS109A–SEPTEMBER 2005–REVISED AUGUST 2006

The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented

with a 32-bit-wide data bus interface. The flash operates with a system clock frequency of up to 24 MHz or 30

MHz, depending on the input voltage. When in pipeline mode, the flash operates with a system clock frequency

of up to 48 MHz or 60 MHz, depending on the input voltage. For more detailed information on the flash, see the

F05 Flash section of this data sheet.

The memory security module (MSM) and the JTAG security module prevent unauthorized access and visibility to

on-chip memory, thereby preventing reverse engineering or manipulation of proprietary code.

The B1M device has twelve communication interfaces: two SPIs, three SCIs, two HECCs, and five I2Cs. The

SPI provides a convenient method of serial interaction for high-speed communications between similar

shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous

communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The

HECC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control

with robust communication rates of up to 1 megabit per second (Mbps). These CAN peripherals are ideal for

applications operating in noisy and harsh environments (e.g., industrial fields) that require reliable serial

communication or multiplexed wiring. The I2C module is a multi-master communication module providing an

interface between the B1M microcontroller and an I2C-compatible device via the I2C serial bus. The I2C

supports both 100 Kbps and 400 Kbps speeds. For more detailed functional information on the SPI, SCI, and

CAN peripherals, see the specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197).

For more detailed functional information on the I2C, see the TMS470R1x Inter-Integrated Circuit (I2C) Reference

Guide (literature number SPNU223).

The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.

The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an

attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited

for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses.

The HET used in this device is the high-end timer lite. It has fewer I/Os than the usual 32 in a standard HET. For

more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide

(literature number SPNU199).

The B1M HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution

channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more

detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference

Guide (literature number SPNU199).

The B1M device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be

converted individually or can be grouped by software for sequential conversion sequences. There are three

separate groupings, two of which can be triggered by an external event. Each sequence can be converted once

when triggered or configured for continuous conversion mode. For more detailed functional information on the

MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature

number SPNU206).

The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a

clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the ZPLL is to multiply the

external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system

(SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock

(RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other B1M device modules. For more

detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock

Module Reference Guide (literature number SPNU212).

NOTE:

ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the

continuous system clock from an external resonator/crystal reference.

The expansion bus module (EBM) is a standalone module that supports the multiplexing of the GIO functions

and the expansion bus interface. For more information on the EBM, see the TMS470R1x Expansion Bus Module

(EBM) Reference Guide (literature number SPNU222).

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TMS470R1B1M

16/32-Bit RISC Flash Microcontroller

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SPNS109A–SEPTEMBER 2005–REVISED AUGUST 2006

The B1M device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous

external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the

peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the

TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).

Device Characteristics

Table 1 identifies all the characteristics of the B1M device except the SYSTEM and CPU, which are generic.

Table 1. Device Characteristics

DEVICE DESCRIPTION

CHARACTERISTICS

COMMENTS

TMS470R1B1M

MEMORY

For the number of memory selects on this device, see Table 3, TMS470R1B1M Memory Selection Assignment.

Pipeline/Non-Pipeline

Flash is pipeline-capable.

1M-Byte flash

64K-Byte SRAM

The B1M RAM is implemented in one 64K array selected by two

memory-select signals (see Table 3, TMS470R1B1M Memory

Selection Assignment ).

INTERNAL MEMORY

Memory Security Module (MSM)

JTAG Security Module

PERIPHERALS

For the device-specific interrupt priority configurations, see Table 6, Interrupt Priority. And for the 1K peripheral address ranges and their

peripheral selects, see Table 4, B1M Peripherals, System Module, and Flash Base Addresses.

CLOCK

ZPLL

Zero-pin PLL has no external loop filter pins.

Expansion Bus

Expansion bus module with 42 pins. Supports 8- and 16-bit

memories. See Table 7 for details.

EBM

GENERAL-PURPOSE I/Os

Port A has 8 external pins; Port B has only 1 external pin; Port C

has 5 external pins; Port D has 6 external pins; Ports E, F, and G

each have 8 external pins; and Port H has 2 external pins.

46 I/O

ECP

YES

3 (3-pin)

2 HECC

2 (5-pin)

5

SCI

CAN (HECC and/or SCC)

SPI (5-pin, 4-pin or 3-pin)

I2C

Two high-end CAN controllers

The high-resolution (HR) SHARE feature allows even-numbered HR

pins to share the next higher odd-numbered HR pin structures. This

HR sharing is independent of whether or not the odd pin is available

externally. If an odd pin is available externally and shared, then the

odd pin can only be used as a general-purpose I/O. For more

information on HR SHARE, see the TMS470R1x High-End Timer

(HET) Reference Guide (literature number SPNU199).

HET with XOR Share

12 I/O

HET RAM

MibADC

64-Instruction Capacity

10-bit, 12-channel

64-word FIFO

Both the logic and registers for a full 16-channel MibADC are

present.

CORE VOLTAGE

I/O VOLTAGE

PINS

1.8 V

3.3 V

144

PACKAGES

PGE

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16/32-Bit RISC Flash Microcontroller

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SPNS109A–SEPTEMBER 2005–REVISED AUGUST 2006

Functional Block Diagram

External

Pins

External

Pins

OSCIN

FLASH

(1M Byte)

2 Banks

Memory

Security

Module

(MSM)

V

CCP

RAM

(64K Bytes)

ZPLL

OSCOUT

PLLDIS

FLTP2

16 Sectors

ADIN[11:0]

ADEVT

CPU Address Data Bus

MibADC

64−Word

FIFO

AD

REFHI

REFLO

TRST

TCK

V

CCAD

SSAD

TMS470R1x CPU

ICE Breaker

TDI

TDO

HET

64 Words

HET[0:8;18,20,22]

TMS

TMS2

RST

CAN1HTX

CAN1HRX

HECC1

HECC2

TMS470R1x System Module

with Enhanced RTI Module

AWD

(A)

TEST

PORRST

CLKOUT

CAN2HTX

CAN2SRX

DMA Controller

16 Channels

Interrupt Expansion

Module (IEM)

SCI1CLK

SCI1TX

SCI1RX

SCI1

SCI2

SCC

I2C4

I2C5

Digital

Analog

I2C4SDA

I2C4SCL

SCI2CLK

SCI2TX

SCI2RX

Watchdog

(DWD)

Watchdog

(AWD)

I2C5SDA

I2C5SCL

I2C3SDA

I2C3SCL

I2C3

I2C2

I2C1

I2C2SDA

I2C2SCL

SCI3

SPI2

SPI1

ECP

GIO/EBM

I2C1SDA

I2C1SCL

A. The enhanced RTI module is the system module with two extra bits to disable the ZPLL while in STANDBY mode.

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16/32-Bit RISC Flash Microcontroller

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SPNS109A–SEPTEMBER 2005–REVISED AUGUST 2006

Table 2. Terminal Functions

TERMINAL

NAME

INTERNAL

PULLUP/

CURRENT

OUTPUT

TYPE⁽¹⁾⁽²⁾

DESCRIPTION

PULLDOWN⁽³⁾

NO.

HIGH-END TIMER (HET)

HET[0]

HET[1]

HET[2]

HET[3]

HET[4]

HET[5]

HET[6]

HET[7]

HET[8]

HET[18]

HET[20]

HET[22]

73

72

71

66

65

63

9

Timer input capture or output compare. The

HET[8:0,18,20,22] applicable pins can be programmed

as general-purpose input/output (GIO) pins. All are

high-resolution pins.

The high-resolution (HR) SHARE feature allows even

HR pins to share the next higher odd HR pin

structures. This HR sharing is independent of whether

or not the odd pin is available externally. If an odd pin

is available externally and shared, then the odd pin

can only be used as a general-purpose I/O. For more

information on HR SHARE, see the TMS470R1x

High-End Timer (HET) Reference Guide (literature

number SPNU199).

3.3 V

2 mA -z

IPD (20 µA)

11

12

15

18

19

HIGH-END CAN CONTROLLER (HECC)

CAN1HRX

CAN1HTX

CAN2HRX

CAN2HTX

83

84

54

55

5-V tolerant

3.3 V

4 mA

2 mA -z

4 mA

HECC1 receive pin or GIO pin

IPU (20 µA)

HECC1 transmit pin or GIO pin

HECC2 receive pin or GIO pin

HECC2 transmit pin or GIO pin

5-V tolerant

3.3 V

2 mA -z

STANDARD CAN CONTROLLER (SCC)

SCC receive pin. The CANSRX signal is only

connected to the pad and not to a package pin. For

reduced power consumption in low power mode,

CANSRX should be driven output LOW.

CANSRX

CANSTX

-

5-V tolerant

3.3 V

4 mA

SCC transmit pin. The CANSTX signal is only

connected to the pad and not to a package pin. For

reduced power consumption in low power mode,

CANSTX should be driven output LOW.

2 mA -z

IPU (20 µA)

GENERAL-PURPOSE I/O (GIO)

GIOA[0]/INT[0]

141

136

134

133

127

98

GIOA[1]/INT[1]/ECLK

GIOA[2]/INT[2]

General-purpose input/output pins. GIOA[7:0]/INT[7:0]

are interrupt-capable pins.

GIOA[3]/INT[3]

5-V tolerant

4 mA

GIOA[1]/INT[1]/ECLK pin is multiplexed with the

external clock-out function of the external clock

prescale (ECP) module.

GIOA[4]/INT[4]

GIOA[5]/INT[5]

GIOA[6]/INT[6]

78

GIOA[7]/INT[7]

79

GIOB[0]/EBDMAREQ0

GIOC[0]/EBOE

43

135

128

126

120

119

GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:], GIOF[7:0],

GIOG[7:0], and GIOH[5,0] are multiplexed with the

expansion bus module.

GIOC[1]/EBWR[0]

GIOC[2]/EBWR[1]

GIOC[3]/EBCS[5]

GIOC[4]/EBCS[6]

3.3 V

2 mA -z

IPD (20 µA)

See Table 7.

(1) PWR = power, GND = ground, REF = reference voltage, NC = no connect

(2) All I/O pins, except RST , are configured as inputs while PORRST is low and immediately after PORRST goes high.

(3) IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST

state.)

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SPNS109A–SEPTEMBER 2005–REVISED AUGUST 2006

Table 2. Terminal Functions (continued)

TERMINAL

INTERNAL

PULLUP/

CURRENT

OUTPUT

TYPE⁽¹⁾⁽²⁾

DESCRIPTION

PULLDOWN⁽³⁾

NAME

NO.

GIOD[0]/EBADDR[0]

GIOD[1]/EBADDR[1]

GIOD[2]/EBADDR[2]

GIOD[3]/EBADDR[3]

GIOD[4]/EBADDR[4]

GIOD[5]/EBADDR[5]

GIOE[0]/EBDATA[0]

GIOE[1]/EBDATA[1]

GIOE[2]/EBDATA[2]

GIOE[3]/EBDATA[3]

GIOE[4]/EBDATA[4]

GIOE[5]/EBDATA[5]

GIOE[6]/EBDATA[6]

GIOE[7]/EBDATA[7]

42

39

35

30

27

23

44

47

58

61

64

67

70

77

GIOF[0]/INT[8]/

EBADDR[6]/EBDATA[8]

80

82

89

90

93

96

99

100

20

10

8

GIOF[1]/INT[9]/

EBADDR[7]/EBDATA[9]

GIOF[2]/INT[10]/

EBADDR[8]/EBDATA[10]

GIOF[3]/INT[11]/

EBADDR[9]/EBDATA[11]

GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:], GIOF[7:0],

GIOG[7:0], and GIOH[5,0] are multiplexed with the

expansion bus module.

GIOF[4]/INT[12]/

EBADDR[10]/EBDATA[12]

3.3 V

2 mA -z

IPD (20 µA)

GIOF[7:0]/INT[15:8] are interrupt-capable pins.

See Table 7.

GIOF[5]/INT[13]/

EBADDR[11]/EBDATA[13]

GIOF[6]/INT[14]/

EBADDR[12]/EBDATA[14]

GIOF[7]/INT[15]/

EBADDR[13]/EBDATA[15]

GIOG[0]/EBADDR[14]/

EBADDR[6]

GIOG[1]/EBADDR[15]/

EBADDR[7]

GIOG[2]/EBADDR[16]/

EBADDR[8]

GIOG[3]/EBADDR[17]/

EBADDR[9]

6

GIOG[4]/EBADDR[18]/

EBADDR[10]

3

GIOG[5]/EBADDR[19]/

EBADDR[11]

143

142

140

GIOG[6]/EBADDR[20]/EB

ADDR[12]

GIOG[7]/EBADDR[21]/

EBADDR[13]

GIOH[0]/EBADDR[22]/

EBADDR[14]

139

125

GIOH[5]/EBHOLD

9

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Table 2. Terminal Functions (continued)

TERMINAL

NAME

INTERNAL

PULLUP/

CURRENT

OUTPUT

TYPE⁽¹⁾⁽²⁾

DESCRIPTION

PULLDOWN⁽³⁾

NO.

MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)

MibADC event input. Can be programmed as a GIO

pin.

ADEVT

101

2 mA -z

IPD (20 µA)

ADIN[0]

ADIN[1]

ADIN[2]

ADIN[3]

ADIN[4]

ADIN[5]

ADIN[6]

ADIN[7]

ADIN[8]

ADIN[9]

ADIN[10]

ADIN[11]

AD_REFHI

AD_REFLO

V_CCAD

117

116

115

114

113

108

107

106

105

104

103

102

109

110

3.3 V

MibADC analog input pins

3.3 VREF

GND REF

MibADC module high-voltage reference input

MibADC module low-voltage reference input

MibADC analog supply voltage

111 3.3-V PWR

V_SSAD

112

GND

MibADC analog ground reference

SERIAL PERIPHERAL INTERFACE 1 (SPI1)

SPI1 clock. SPI1CLK can be programmed as a GIO

SPI1CLK

SPI1ENA

SPI1SCS

4

2

1

pin.

SPI1 chip enable. Can be programmed as a GIO pin.

SPI1 slave chip select. Can be programmed as a GIO

pin.

5-V tolerant

4 mA

SPI1 data stream. Slave in/master out. Can be

programmed as a GIO pin.

SPI1SIMO

SPI1SOMI

5

7

SPI1 data stream. Slave out/master in. Can be

programmed as a GIO pin.

SERIAL PERIPHERAL INTERFACE 2 (SPI2)

SPI2 clock. Can be programmed as a GIO pin.

SPI2CLK

SPI2ENA

56

60

SPI2 chip enable. Can be programmed as a GIO pin.

SPI2 slave chip select. Can be programmed as a GIO

pin.

SPI2SCS

SPI2SIMO

SPI2SOMI

62

59

57

5-V tolerant

4 mA

SPI2 data stream. Slave in/master out. Can be

programmed as a GIO pin.

SPI2 data stream. Slave out/master in. Can be

programmed as a GIO pin.

INTER-INTEGRATED CIRCUIT 1 (I2C1)

I2C1 serial data pin or GIO pin

I2C1 serial clock pin or GIO pin

INTER-INTEGRATED CIRCUIT 2 (I2C2)

I2C2 serial data pin or GIO pin

I2C2 serial clock pin or GIO pin

I2C1SDA

I2C1SCL

87

88

5-V tolerant

4 mA

I2C2SDA

I2C2SCL

94

95

4 mA

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Table 2. Terminal Functions (continued)

TERMINAL

NAME

INTERNAL

PULLUP/

CURRENT

OUTPUT

TYPE⁽¹⁾⁽²⁾

DESCRIPTION

PULLDOWN⁽³⁾

NO.

INTER-INTEGRATED CIRCUIT 3 (I2C3)

I2C3 serial data pin or GIO pin

I2C3 serial clock pin or GIO pin

INTER-INTEGRATED CIRCUIT 4 (I2C4)

I2C4 serial data pin or GIO pin

I2C4 serial clock pin or GIO pin

INTER-INTEGRATED CIRCUIT 5 (I2C5)

I2C5 serial data pin or GIO pin

I2C5 serial clock pin or GIO pin

ZERO-PIN PHASE-LOCKED LOOP (ZPLL)

I2C3SDA

I2C3SCL

29

28

5-V tolerant

4 mA

I2C4SDA

I2C4SCL

41

40

4 mA

I2C5SDA

I2C5SCL

38

37

5-V tolerant

1.8 V

4 mA

OSCIN

33

32

Crystal connection pin or external clock input

External crystal connection pin

OSCOUT

2 mA

Enable/disable the ZPLL. The ZPLL can be bypassed

and the oscillator becomes the system clock. If not in

bypass mode, TI recommends that this pin be

connected to ground or pulled down to ground by an

external resistor.

PLLDIS

97

3.3 V

IPD (20 µA)

SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)

SCI1 clock. SCI1CLK can be programmed as a GIO

pin.

SCI1CLK

SCI1RX

SCI1TX

48

46

45

3.3 V

5-V tolerant

3.3 V

2 mA -z

4 mA

IPD (20 µA)

SCI1 data receive. SCI1RX can be programmed as a

GIO pin.

SCI1 data transmit. SCI1TX can be programmed as a

GIO pin.

2 mA -z

IPU (20 µA)

SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)

SCI2 clock. SCI2CLK can be programmed as a GIO

pin.

SCI2CLK

SCI2RX

SCI2TX

51

50

49

3.3 V

5-V tolerant

3.3 V

2 mA -z

4 mA

IPD (20 µA)

SCI2 data receive. SCI2RX can be programmed as a

GIO pin.

SCI2 data transmit. SCI2TX can be programmed as a

GIO pin.

2 mA -z

IPU (20 µA)

SERIAL COMMUNICATIONS INTERFACE 3 (SCI3)

SCI3 clock. SCI3CLK can be programmed as a GIO

pin.

SCI3CLK

SCI3RX

SCI3TX

24

22

21

3.3 V

5-V tolerant

3.3 V

2 mA -z

4 mA

IPD (20 µA)

SCI3 data receive. SCI3RX can be programmed as a

GIO pin.

SCI3 data transmit. SCI3TX can be programmed as a

GIO pin.

2 mA -z

IPU (20 µA)

SYSTEM MODULE (SYS)

Bidirectional pin. CLKOUT can be programmed as a

GIO pin or the output of SYSCLK, ICLK, or MCLK.

CLKOUT

PORRST

81

3.3 V

8 mA

Input master chip power-up reset. External V_CC

monitor circuitry must assert a power-on reset.

118

IPD (20 µA)

IPU (20 µA)

Bidirectional reset. The internal circuitry can assert a

reset, and an external system reset can assert a

device reset.

On this pin, the output buffer is implemented as an

open drain (drives low only).

RST

121

3.3 V

4 mA

To ensure an external reset is not arbitrarily generated,

TI recommends that an external pullup resistor be

connected to this pin.

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Table 2. Terminal Functions (continued)

TERMINAL

NAME

INTERNAL

PULLUP/

CURRENT

OUTPUT

TYPE⁽¹⁾⁽²⁾

DESCRIPTION

PULLDOWN⁽³⁾

NO.

WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)

Analog watchdog reset. The AWD pin provides a

system reset if the WD KEY is not written in time by

the system, providing an external RC network circuit is

connected. If the user is not using AWD, TI

recommends that this pin be connected to ground or

pulled down to ground by an external resistor.

AWD

36

3.3 V

8 mA

For more details on the external RC network circuit,

see the TMS470R1x System Module Reference Guide

(literature number SPNU189).

TEST/DEBUG (T/D)

TCK

TDI

76

74

IPD (20 µA)

Test clock. TCK controls the test hardware (JTAG).

Test data in. TDI inputs serial data to the test

instruction register, test data register, and

programmable test address (JTAG).

3.3 V

8 mA

IPU (20 µA)

IPD (20 µA)

Test data out. TDO outputs serial data from the test

instruction register, test data register, identification

register, and programmable test address (JTAG).

TDO

75

Test enable. Reserved for internal use only. TI

recommends that this pin be connected to ground or

pulled down to ground by an external resistor.

TEST

TMS

124

17

IPD (20 µA)

IPU (20 µA)

Serial input for controlling the state of the CPU test

access port (TAP) controller (JTAG).

8 mA

Serial input for controlling the second TAP. TI

recommends that this pin be connected to V_CCIOor

pulled up to V_CCIOby an external resistor.

3.3 V

TMS2

16

Test hardware reset to TAP1 and TAP2. IEEE

Standard 1149-1 (JTAG) Boundary-Scan Logic. TI

recommends that this pin be pulled down to ground by

an external resistor.

TRST

144

132

IPD (20 µA)

FLASH

Flash test pad 2. For proper operation, this pin must

not be connected [no connect (NC)].

FLTP2

V_CCP

NC

131 3.3-V PWR

Flash external pump voltage (3.3 V)

SUPPLY VOLTAGE CORE (1.8 V)

13

31

53

V_CC

1.8-V PWR

92

Core logic supply voltage

123

130

SUPPLY VOLTAGE DIGITAL I/O (3.3 V)

25

69

V_CCIO

3.3-V PWR

86

Digital I/O supply voltage

137

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Table 2. Terminal Functions (continued)

TERMINAL

NAME

INTERNAL

PULLUP/

CURRENT

OUTPUT

TYPE⁽¹⁾⁽²⁾

DESCRIPTION

PULLDOWN⁽³⁾

NO.

SUPPLY GROUND CORE

14

34

52

V_SS

GND

Core supply ground reference

91

122

129

SUPPLY GROUND DIGITAL I/O

26

68

V_SSIO

GND

Digital I/O supply ground reference

85

138

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B1M Device-Specific Information

Memory

Figure 1 shows the memory map of the B1M device.

Memory (4G Bytes)

0xFFFF_FFFF

SYSTEM with PSA, CIM, RTI,

DEC, DMA, MMC, DWD

System Module Control

Registers

0xFFFF_FD00

0xFFFF_FC00

0xFFFF_F700

0xFFF8_0000

IEM

MSM

Reserved

(512K Bytes)

0xFFF8_0000

0xFFF7_FFFF

Peripheral Control Registers

(512K Bytes)

0xFFF0_0000

Reserved

HET

Reserved

SPI1

SCI3

SCI2

0xFFF7_FC00

0xFFEF_FFFF

Reserved

0xFFE8_C000

0xFFF7_F800

0xFFF7_F600

0xFFF7_F500

0xFFF7_F400

0xFFE8_BFFF

Flash Control Registers

0xFFE8_8000

0xFFE8_7FFF

0xFFE8_4021

Reserved

SCI1

Reserved

MibADC

ECP

0xFFE8_4020

MPU Control Registers

0xFFE8_4000

0xFFF7_F000

0xFFF7_EF00

Reserved

EBM

Reserved (1 MByte)

0xFFE0_0000

0xFFF7_ED00

0xFFF7_EC00

GIO

Reserved

HECC2

Reserved

HECC1

Reserved

HECC2 RAM

Reserved

HECC1 RAM

Reserved

SCC

0xFFF7_EA00

0xFFF7_E800

0xFFF7_E600

0xFFF7_E400

0xFFF7_E000

0x7FFF_FFFF

Reserved

SCC RAM

I2C4

RAM

0xFFF7_DC00

0xFFF7_DB00

0xFFF7_DA00

0xFFF7_D900

0xFFF7_D800

0xFFF7_D500

0xFFF7_D400

0xFFF0_0000

(64K Bytes)

Program

and

Data Area

I2C3

I2C2

I2C1

FLASH

(1M Bytes)

2 Banks

I2C5

SPI2

Reserved

16 sectors

HET RAM

(1K Bytes)

0x0000_0023

0x0000_0020

0x0000_001C

0x0000_0018

0x0000_0014

0x0000_0010

0x0000_000C

0x0000_0008

0x0000_0004

0x0000_0000

Reserved

FIQ

IRQ

Reserved

0x0000_0024

0x0000_0023

Data Abort

Prefetch Abort

Software Interrupt

Undefined Instruction

Reset

Exception, Interrupt, and

Reset Vectors

0x0000_0000

A. Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.

B. The CPU registers are not part of the memory map.

Figure 1. TMS470R1B1M Memory Map

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memory selects

Memory selects allow the user to address memory arrays (i.e., flash, RAM, and HET RAM) at user-defined

addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx

and MFBALRx) that, together, define the array's starting (base) address, block size, and protection.

The base address of each memory select is configurable to any memory address boundary that is a multiple of

the decoded block size. For more information on how to control and configure these memory select registers,

see the bus structure and memory sections of the TMS470R1x System Module Reference Guide (literature

number SPNU189).

For the memory selection assignments and the memory selected, see Table 3.

Table 3. TMS470R1B1M Memory Selection Assignment

MEMORY

SELECTED

(ALL INTERNAL)

MEMORY

SELECT

MEMORY

SIZE⁽¹⁾

MEMORY BASE ADDRESS

REGISTER

STATIC MEM

CTL REGISTER

MPU

MSM

0 (fine)

1 (fine)

2 (fine)

3 (fine)

4 (fine)

FLASH/ROM

RAM

NO

YES

NO

MFBAHR0 and MFBALR0

MFBAHR1 and MFBALR1

MFBAHR2 and MFBALR2

MFBAHR3 and MFBALR3

MFBAHR4 and MFBALR4

1 M

YES

NO

64 K⁽²⁾

1 K

RAM

HET RAM

SMCR1

SMCR5

128 MB (x8)

512 K (x16)

5 (coarse)

6 (coarse)

CS[5]/GIOC[3]

CS[6]/GIOC[4]

NO

MCBAHR2 and MCBALR2

MCBAHR3 and MCBALR3

128 MB (x8)

512 K (x16)

SMCR6

(1) x8 refers to size of memory in 8-bits; x16 refers to size of memory in 16-bits.

(2) The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block

size in the memory-base address register.

JTAG security module

The B1M device includes a JTAG security module to provide maximum security to the memory contents. The

visible unlock code can be in the OTP sector or in the first bank of the user-programmable memory. For the

B1M, the visible unlock code is in the OTP sector at address 0x0000_01F8.

memory security module

The B1M device also includes a memory security module (MSM) to provide additional security and flexibility to

the memory contents' protection. The password for unlocking the MSM is located in the four words just before

the flash protection keys.

RAM

The B1M device contains 64K-bytes of internal static RAM configurable by the SYS module to be addressed

within the range of 0x0000_0000 to 0xFFE0_0000. This B1M RAM is implemented in one 64K-byte array

selected by two memory-select signals. This B1M configuration imposes an additional constraint on the memory

map for RAM; the starting addresses for both RAM memory selects cannot be offset from each other by the

multiples of the size of the physical RAM (i.e., 64K bytes for the B1M device). The B1M RAM is addressed

through memory selects 2 and 3.

The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user

finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an

operating system while allowing access to the current task. For more detailed information on the MPU portion of

the SYS module and memory protection, see the memory section of the TMS470R1x System Module Reference

Guide (literature number SPNU189).

F05 Flash

The F05 flash memory is a nonvolatile electrically erasable and programmable memory implemented with a

32-bit-wide data bus interface. The F05 flash has an external state machine for programming and erase

functions. See the Flash read and Flash program and erase sections.

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flash protection keys

The B1M device provides flash protection keys. These four 32-bit protection keys prevent

program/erase/compaction operations from occurring until after the four protection keys have been matched by

the CPU loading the correct user keys into the FMPKEY control register. The protection keys on the B1M are

located in the last 4 words of the first 64K sector.

flash read

The B1M flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000 to

0xFFE0_0000. The flash is addressed through memory selects 0 and 1.

NOTE:

The flash external pump voltage (V_CCP) is required for all operations (program, erase,

and read).

flash pipeline mode

When in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz (versus a system

clock frequency of 30 MHz in normal mode). Flash in pipeline mode is capable of accessing 64-bit words and

provides two 32-bit pipelined words to the CPU. Also, in pipeline mode the flash can be read with no wait states

when memory addresses are contiguous (after the initial 1- or 2-wait-state reads).

NOTE:

After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a 0).

In other words, the B1M device powers up and comes out of reset in non-pipeline

mode. Furthermore, setting the flash configuration mode bit (GBLCTRL.4) will

override pipeline mode.

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flash program and erase

The B1M device flash contains two 512K-byte memory arrays (or banks), for a total of 1M-byte of flash, and

consists of sixteen sectors. These sixteen sectors are sized as follows:

SECTOR

NO.

MEMORY ARRAYS

(OR BANKS)

SEGMENT

LOW ADDRESS

HIGH ADDRESS

OTP

2K Bytes

64K Bytes

0x0000_0000

0x0001_0000

0x0002_0000

0x0003_0000

0x0004_0000

0x0005_0000

0x0006_0000

0x0007_0000

0x0000_007FF

0x0000_FFFF

0x0001_FFFF

0x0002_FFFF

0x0003_FFFF

0x0004_FFFF

0x0005_FFFF

0x0006_FFFF

0x0007_FFFF

0

1

2

3

4

5

6

7

BANK0

(512K Bytes)

0

1

2

3

4

5

6

7

64K Bytes

0x0008_0000

0x0009_0000

0x000A_0000

0x000B_0000

0x000C_0000

0x000D_0000

0x000E_0000

0x000F_0000

0x0008_FFFF

0x0009_FFFF

0x000A_FFFF

0x000B_FFFF

0x000C_FFFF

0x000D_FFFF

0x000E_FFFF

0x000F_FFFF

BANK1

(512K Bytes)

The minimum size for an erase operation is one sector. The maximum size for a program operation is one 16-bit

word.

NOTE:

The flash external pump voltage (V_CCP) is required for all operations (program, erase,

and read).

Execution can occur from one bank while programming/erasing any or all sectors of another bank. However,

execution cannot occur from any sector within a bank that is being programmed or erased.

NOTE:

When the OTP sector is enabled, the rest of flash memory is disabled. The OTP

memory can only be read or programmed from code executed out of RAM.

HET RAM

The B1M device contains HET RAM. The HET RAM has a 64-instruction capability. The HET RAM is

configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET

RAM is addressed through memory select 4.

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peripheral selects and base addresses

The B1M device uses 10 of the 16 peripheral selects to decode the base addresses of the peripherals. These

peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used by the

SYS module.

Control registers for the peripherals, SYS module, and flash begin at the base addresses shown in Table 4.

Table 4. B1M Peripherals, System Module, and Flash Base Addresses

ADDRESS RANGE

CONNECTING MODULE

PERIPHERAL SELECTS

BASE ADDRESS

0 x FFFF_FFCC

0 x FFFF_FF70

0xFFFF_FF60

0 x FFFF_FF40

0 x FFFF_FF20

0 x FFFF_FF00

0 x FFFF_FE80

0 x FFFF_FE00

0xFFFF_FD80

0 x FFFF_FD00

0 x FFFF_FC00

0 x FFFF_Fb00

0 x FFFF_Fa00

0 x FFFF_F800

0xFFFF_F700

0xFFF8_0000

0 x FFF7_FD00

0xFFF7_FC00

0xFFF7_F900

0xFFF7_F800

0xFFF7_F700

0xFFF7_F600

0XFFF7_F500

0xFFF7_F400

0xFFF7_F100

0xFFF7_F000

0xFFF7_EF00

0xFFF7_EE00

0xFFF7_ED00

0xFFF7_EC00

0xFFF7_EB00

0xFFF7_EA00

0xFFF7_E900

0xFFF7_E800

0xFFF7_E700

0xFFF7_E600

0xFFF7_E500

0xFFF7_E400

0xFFF7_E100

0xFFF7_E000

ENDING ADDRESS

0 x FFFF_FFFF

0 x FFFF_FFCB

0 x FFFF_FF6F

0 x FFFF_FF5F

0 x FFFF_FF3F

0 x FFFF_FF1F

0 x FFFF_FEFF

0 x FFFF_FE7F

0xFFFF_FDFF

0 x FFFF_FD7F

0 x FFFF_FCFF

0 x FFFF_FBFF

0 x FFFF_FAFF

0 x FFFF_F9FF

0xFFFF_F7FF

0xFFFF_F6FF

0xFFF7_FFFF

0xFFF7_FCFF

0xFFF7_FBFF

0xFFF7_F8FF

0xFFF7_F7FF

0xFFF7_F6FF

0XFFF7_F5FF

0xFFF7_F4FF

0xFFF7_F3FF

0xFFF7_F0FF

0xFFF7_EFFF

0xFFF7_EEFF

0xFFF7_EDFF

0xFFF7_ECFF

0xFFF7_EBFF

0xFFF7_EAFF

0xFFF7_E9FF

0xFFF7_E8FF

0xFFF7_E7FF

0xFFF7_E6FF

0xFFF7_E5FF

0xFFF7_E4FF

0xFFF7_E3FF

0xFFF7_E0FF

SYSTEM

RESERVED

DWD

N/A

PSA

CIM

RTI

DMA

DEC

RESERVED

MMC

IEM

RESERVED

DMA CMD BUFFER

MSM

RESERVED

HET

PS[0]

PS[1]

RESERVED

SPI1

RESERVED

SCI3

PS[2]

PS[3]

PS[4]

SCI2

SCI1

RESERVED

MibADC

ECP

RESERVED

EBM

GIO

HECC2

HECC1

PS[5]

HECC2 RAM

HECC1 RAM

PS[6]

PS[7]

RESERVED

SCC

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Table 4. B1M Peripherals, System Module, and Flash Base Addresses (continued)

ADDRESS RANGE

BASE ADDRESS

CONNECTING MODULE

PERIPHERAL SELECTS

ENDING ADDRESS

0xFFF7_DFFF

0xFFF7_DCFF

0xFFF7_DBFF

0xFFF7_DAFF

0xFFF7_D9FF

0xFFF7_D8FF

0xFFF7_D7FF

0xFFF7_D5FF

0xFFF7_D4FF

0xFFF7_D3FF

0xFFF7_CBFF

0xFFF7_C7FF

0xFFF7_BFFF

0xFFE8_BFFF

0xFFF8_7FFF

0xFFE8_4023

0xFFF8_3FFF

RESERVED

0xFFF7_DD00

0xFFF7_DC00

0xFFF7_DB00

0xFFF7_DA00

0xFFF7_D900

0xFFF7_D800

0xFFF7_D600

0xFFF7_D500

0xFFF7_D400

0xFFF7_CC00

0xFFF7_C800

0xFFF7_C000

0xFFF0_0000

0xFFE8_8000

0xFFF8_4024

0xFFE8_4000

0xFFF8_0000

PS[8]

SCC RAM

I2C4

I2C3

I2C2

PS[9]

I2C1

RESERVED

I2C5

PS[10]

SPI2

RESERVED

FLASH CONTROL REGISTERS

RESERVED

MPU CONTROL REGISTERS

RESERVED

PS[11] – PS[12]

PS[13]

PS[14] – PS[15]

N/A

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direct-memory access (DMA)

The direct-memory access (DMA) controller transfers data to and from any specified location in the B1M

memory map (except for restricted memory locations like the system control registers area). The DMA manages

up to 16 channels, and supports data transfer for both on-chip and off-chip memories and peripherals. The DMA

controller is connected to both the CPU and peripheral buses, enabling these data transfers to occur in parallel

with CPU activity and thus maximizing overall system performance.

Although the DMA controller has two possible configurations, for the B1M device, the DMA controller

configuration is 32 control packets and 16 channels.

For the B1M DMA request hardwired configuration, see Table 5.

Table 5. DMA Request Lines Connections⁽¹⁾

MODULES

EBM

DMA REQUEST INTERRUPT SOURCES

DMA CHANNEL

DMAREQ[0]

DMAREQ[1]

DMAREQ[2]

DMAREQ[3]

DMAREQ[4]

DMAREQ[5]

DMAREQ[6]

DMAREQ[7]

DMAREQ[8]

DMAREQ[9]

DMAREQ[10]

DMAREQ[11]

DMAREQ[12]

DMAREQ[13]

DMAREQ[14]

DMAREQ[15]

Expansion Bus DMA request

EBDMAREQ[0]

SPI1/I2C4

MibADC/I2C1

MibADC/SCI1/I2C5

I2C1

SPI1 end-receive/I2C4 read

SPI1 end-transmit/I2C4 write

ADC EV/I2C1 read

SPI1DMA0/I2C4DMA0

SPI1DMA1/I2C4DMA1

MibADCDMA0/I2C1DMA0

MibADCDMA1/SCI1DMA0/I2C5DMA0

MibADCDMA2/SCI1DMA1/I2C5DMA1

I2C1DMA1

ADC G1/SCI1 end-receive/I2C5 read

ADC G2/SCI1 end-transmit/I2C5 write

I2C1 write

SCI3/SPI2

I2C2

SCI3 end-receive/SPI2 end-receive

SCI3 end-transmit/SPI2 end-transmit

I2C2 read end-receive

SCI3DMA0/SPI2DMA0

SCI3DMA01SPI2DMA1

I2C2DMA0

I2C2

I2C2 write end-transmit

I2C3 read

I2C2DMA1

I2C3

I2C3DMA0

I2C3

I2C3 write

I2C3DMA1

Reserved

SCI2

SCI2 end-receive

SCI2 end-transmit

SCI2DMA0

SCI2DMA1

SCI2

(1) For DMA channels with more than one assigned request source, only one of the sources listed can be the DMA request generator in a

given application. The device has software control to ensure that there are no conflicts between requesting modules.

Each channel has two control packets attached to it, allowing the DMA to continuously load RAM and generate

periodic interrupts so that the data can be read by the CPU. The control packets allow for the interrupt enable,

and the channels determine the priority level of the interrupt.

DMA transfers occur in one of two modes:

•

Non-request mode (used when transferring from memory to memory)

Request mode (used when transferring from memory to peripheral)

For more detailed functional information on the DMA controller, see the TMS470R1x Direct Memory Access

(DMA) Controller Reference Guide (literature number SPNU194).

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interrupt priority (IEM to CIM)

Interrupt requests originating from the B1M peripheral modules (i.e., SPI1 or SPI2; SCI1 or SCI2; RTI; etc.) are

assigned to channels within the 48-channel interrupt expansion module (IEM) where, via programmable register

mapping, these channels are then mapped to the 32-channel central interrupt manager (CIM) portion of the SYS

module.

Programming multiple interrupt sources in the IEM to the same CIM channel effectively shares the CIM channel

between sources.

The CIM request channels are maskable so that individual channels can be selectively disabled. All interrupt

requests can be programmed in the CIM to be of either type:

•

Fast interrupt request (FIQ)

Normal interrupt request (IRQ)

The CIM prioritizes interrupts. The precedences of request channels decrease with ascending channel order in

the CIM (0 [highest] and 31 [lowest] priority). For IEM-to-CIM default mapping, channel priorities, and their

associated modules, see Table 6.

Table 6. Interrupt Priority (IEM and CIM)

DEFAULT CIM INTERRUPT

MODULES

INTERRUPT SOURCES

IEM CHANNEL

LEVEL/CHANNEL

SPI1

RTI

SPI1 end-transfer/overrun

0

COMP2 interrupt

COMP1 interrupt

TAP interrupt

1

RTI

2

RTI

3

SPI2

SPI2 end-transfer/overrun

GIO interrupt A

4

GIO

5

Reserved

HET

6

HET interrupt 1

7

I2C1

I2C1 interrupt

8

SCI1/SCI2

SCI1

SCI1 or SCI2 error interrupt

SCI1 receive interrupt

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Reserved

I2C2

I2C2 interrupt

HECC1

SCC

HECC1 interrupt A

SCC interrupt A

Reserved

MibADC

SCI2

MibADC end event conversion

SCI2 receive interrupt

DMA interrupt 0

DMA

I2C3

I2C3 interrupt

SCI1

SCI1 transmit interrupt

SW interrupt (SSI)

System

Reserved

HET

HET interrupt 2

HECC1

SCC

HECC1 interrupt B

SCC interrupt B

SCI2

SCI2 transmit interrupt

MibADC end Group 1 conversion

DMA Interrupt 1

MibADC

DMA

GIO

GIO interrupt B

MibADC

SCI3

MibADC end Group 2 conversion

SCI3 error interrupt

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Table 6. Interrupt Priority (IEM and CIM) (continued)

DEFAULT CIM INTERRUPT

LEVEL/CHANNEL

MODULES

INTERRUPT SOURCES

IEM CHANNEL

Reserved

HECC2

SCI3

31

32–37

38

HECC2 interrupt A

HECC2 interrupt B

SCI3 receive interrupt

SCI3 transmit interrupt

I2C4 interrupt

39

40

SCI3

41

I2C4

42

I2C5

I2C5 interrupt

43

Reserved

44–47

For more detailed functional information on the IEM, see the TMS470R1x Interrupt Expansion Module (IEM)

Reference Guide (literature number SPNU211). For more detailed functional information on the CIM, see the

TMS470R1x System Module Reference Guide (literature number SPNU189).

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expansion bus module (EBM)

The expansion bus module (EBM) is a standalone module used to bond out both general-purpose input/output

pins and expansion bus interface pins. This module supports the multiplexing of the GIO and the expansion bus

interface functions. The module also supports 8- and 16- bit expansion bus memory interface mappings as well

as mapping of the following expansion bus signals:

•

27-bit address bus (EBADDR[26:0] for x8, 19-bit address bus (EBADDR[18:0] for x16

8- or 16-bit data bus (EBDATA[7:0] or EBDATA[15:0])

2 write strobes (EBWR[1:0])

2 memory chip selects (EBCS[6:5])

1 output enable (EBOE)

1 external hold signal for interfacing to slow memories (EBHOLD)

1 DMA request line (EBDMAREQ[0])

Table 7 shows the multiplexing of I/O signals with the expansion bus interface signals. The mapping of these

pins varies depending on the memory mode.

Table 7. Expansion Bus Mux Mapping⁽¹⁾

EXPANSION BUS MODULE PINS

GIO

x8⁽²⁾

x16⁽²⁾

GIOB[0]

GIOC[0]

EBDMAREQ[0]

EBOE

EBDMAREQ[0]

EBOE

GIOC[2:1]

GIOC[4:3]

GIOD[5:0]

GIOE[7:0]

GIOF[7:0]

GIOG[7:0]

GIOH[5]

EBWR[1:0]

EBCS[6:5]

EBADDR[5:0]

EBDATA[7:0]

EBADDR[13:6]

EBADDR[21:14]

EBHOLD

EBADDR[5:0]

EBDATA[7:0]

EBDATA[15:8]

EBADDR[13:6]

EBHOLD

I2C5SDA

I2C5SCL

I2C4SCL

I2C4SDA

GIOH[0]

EBADDR[26]

EBADDR[25]

EBADDR[24]

EBADDR[23]

EBADDR[22]

EBADDR[18]

EBADDR[17]

EBADDR[16]

EBADDR[15]

EBADDR[14]

(1) For more detailed information, see theTMS470R1x Expansion Bus Module (EBM) Reference Guide (literature number SPNU222) and

the TMS470R1x General Purpose Input/Output Reference Guide (literature number SPNU192).

(2) X8 refers to size of memory in 8-bits; X16 refers to size of memory in 16-bits.

Table 8 lists the names of the expansion bus interface signals and their functions.

Table 8. Expansion Bus Pins

EBDMAREQ

EBOE

DESCRIPTION

Expansion bus DMA request

Expansion bus pin enable

EBWR

Expansion bus write strobe EBWR[1] controls EBDATA[15:8] and EBWR[0]

controls EBDATA[7:0]

EBCS

Expansion bus chip select

Expansion bus address pins

Expansion bus data pins

EBADDR

EBDATA

EBHOLD

Expansion bus hold: An external device may assert this signal to add wait

states to an expansion bus transaction.

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MibADC

The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a

10-bit digital value.

The B1M MibADC module can function in two modes: compatibility mode, where its programmer's model is

compatible with the TMS470R1x ADC module and its digital results are stored in digital result registers; or in

buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion

group [event, group1 (G1), and group2 (G2)]. In buffered mode, the MibADC buffers can be serviced by

interrupts or by the DMA.

MibADC event trigger enhancements

The MibADC includes two major enhancements over the event-triggering capability of the TMS470R1x ADC.

•

Both group 1 and the event group can be configured for event-triggered operation, providing up to two

event-triggered groups.

•

The trigger source and polarity can be selected individually for both group1 and the event group from the

options identified in Table 9.

Table 9. MibADC Event Hookup Configuration

SOURCE SELECT BITS FOR G1 OR EVENT

EVENT #

SIGNAL PIN NAME

(G1SRC[1:0] OR EVSRC[1:0])

EVENT1

EVENT2

EVENT3

EVENT4

00

01

10

11

ADEVT

HET18

Reserved

For group1, these event-triggered selections are configured via the group 1 source select bits (G1SRC[1:0]) in

the AD event source register (ADEVTSRC[5:4]). For the event group, these event-triggered selections are

configured via the event group source select bits (EVSRC[1:0]) in the AD event source register

(ADEVTSRC[1:0]).

For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital

Converter (MibADC) Reference Guide (literature number SPNU206).

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JTAG Interface

There are two main test access ports (TAPs) on the device:

•

TMS470R1x CPU TAP

Device TAP for factory test

Some of the JTAG pins are shared among these two TAPs. The hookup is illustrated in Figure 2.

TMS470R1x CPU

TCK

TRST

TMS

TDI

TCK

TRST

TMS

TDI

TDO

Factory Test

TCK

TRST

TMS

TDI

TMS2

TDO

Figure 2. JTAG Interface

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documentation support

Extensive documentation supports all of the TMS470 microcontroller family generation of devices. The types of

documentation available include data sheets with design specifications; complete user's guides for all devices

and development support tools; and hardware and software applications. Useful reference documentation

includes:

•

Bulletin

– TMS470 Microcontroller Family Product Bulletin (literature number SPNB086)

User's Guides

•

– TMS470R1x System Module Reference Guide (literature number SPNU189)

– TMS470R1x General Purpose Input/Output (GIO) Reference Guide (literature number SPNU192)

– TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194)

– TMS470R1x Serial Peripheral Interface (SPI) Reference Guide (literature number SPNU195)

– TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196)

– TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197)

– TMS470R1x High End Timer (HET) Reference Guide (literature number SPNU199)

– TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202)

– TMS470R1x MultiBuffered Analog to Digital (MibADC) Reference Guide (literature number SPNU206)

– TMS470R1x Zero Pin Phase Locked Loop (ZPLL) Clock Module Reference Guide (literature number

SPNU212)

– TMS470R1x Digital Watchdog Timer Reference Guide (literature number SPNU244)

– TMS470R1x Interrupt Expansion Module (IEM) Reference Guide (literature number SPNU211)

– TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (literature number SPNU214)

– TMS470R1x Class II Serial Interface A (C2SIa) Reference Guide (literature number SPNU218)

– TMS470R1x Expansion Bus Module (EBM) Reference Guide (literature number SPNU222)

– TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (literature number SPNU223)

– TMS470R1x JTAG Security Module (JSM) Reference Guide (literature number SPNU245)

– TMS470R1x Memory Security Module (MSM) Reference Guide (literature number SPNU246)

– TMS470 Peripherals Overview Reference Guide (literature number SPNU248)

Errata Sheet

•

– TMS470R1B1M TMS470 Microcontrollers Silicon Errata (literature number SPNZ139)

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Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP

devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS

(e.g., TMS470R1B1M). Texas Instruments recommends two of three possible prefix designators for its support

tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering

prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX

TMP

TMS

Experimental device that is not necessarily representative of the final device's electrical

specifications

Final silicon die that conforms to the device's electrical specifications but has not completed quality

and reliability verification

Fully qualified production device

Support tool development evolutionary flow:

TMDX

Development-support product that has not yet completed Texas Instruments internal qualification

testing.

TMDS

Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability

of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

Figure 3 illustrates the numbering and symbol nomenclature for the TMS470R1x family.

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TMS 470 R1

B

1M

PGE

A

OPTIONS

PREFIX

TMS = Fully Qualified Device

FAMILY

TEMPERATURE RANGE

A = −40°C − 85 °C

470 = TMS470 RISC − Embedded

Microcontroller Family

PACKAGE TYPE

PGE = 144-pin Low-Profile Quad Flatpack (LQFP)

ARCHITECTURE

R1 = ARM7TDM1 CPU

REVISION CHANGE

Blank = Original

DEVICE TYPE B

With 1024K−Bytes Flash Memory:

60−MHZ Frequency

FLASH MEMORY

1.8-V Core, 3.3-V I/O

Flash Program Memory

1M = 1024K−Bytes Flash Memory

ZPLL Clock

64K−Byte Static RAM

1K−Byte HET RAM (64 Instructions)

AWD

DWD

RTI

10−Bit, 12−Input MibADC

Two SPI Modules

Three SCI Modules

Two High−End CAN HECC

HET, 16 Channels

ECP

IEM

DMA

Five I2C Modules

EMB

MSM

Figure 3. TMS470R1x Family Nomenclature

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device identification code register

The device identification code register identifies the silicon version, the technology family (TF), a ROM or flash

device, and an assigned device-specific part number (see Table 10). The B1M device identification code register

value is 0xnA5F.

Figure 4. TMS470 Device ID Bit Allocation Register [offset = 0xFFFF_FFF0h]

31

15

16

0

Reserved

12

11

10

9

3

2

1

VERSION

R-K

TF

R/F

R-K

PART NUMBER

R-K

1

R-K

R-1

LEGEND:

For bits 3-15: R = Read only, -K = Value constant after RESET.

For bits 0-2: R = Read only, -1 = Value after RESET.

Table 10. TMS470 Device ID Bit Allocation Register Field Descriptions

Bit

Field

Value Description

31-16 Reserved

15-12 VERSION

Reads are undefined and writes have no effect.

Silicon version (revision) bits

These bits identify the silicon version of the device.

11

TF

Technology family bit

This bit distinguishes the technology family core power supply:

0

1

3.3 V for F10/C10 devices

1.8 V for F05/C05 devices

10

R/F

ROM/flash bit

This bit distinguishes between ROM and flash devices:

0

1

Flash device

ROM device

9-3

2-0

PART NUMBER

1

Device-specific part number bits

These bits identify the assigned device-specific part number. The assigned device-specific part

number for the B1M device is 1001011.

Mandatory High

Bits 2, 1, and 0 are tied high by default.

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DEVICE ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS

Absolute Maximum Ratings

over operating free-air temperature range, A version (unless otherwise noted)⁽¹⁾

(2)

Supply voltage range:

Input voltage range:

V_CC

–0.3 V to 2.5 V

–0.3 V to 4.1 V

– 0.3 V to 6.0 V

–0.3 V to 4.1 V

V_CCIO, V_CCAD, V_CCP(flash pump)⁽²⁾

All 5 V tolerant input pins

All other input pins

Input clamp current:

I_IK(V_I< 0 or V_I> V_CCIO)

All pins except ADIN[0:11], PORRST, TRST , TEST,

and TCK

±20 mA

I_IK(V_I< 0 or V_I> V_CCAD

)

ADIN[0:11]

±10 mA

Operating free-air temperature

range, T_A:

A version

–40°C to 85°C

Operating junction temperature range, T_J:

Storage temperature range, T_stg

–40°C to 150°C

:

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to their associated grounds.

Device Recommended Operating Conditions⁽¹⁾

MIN

1.71

NOM

MAX

2.05

UNIT

SYSCLK = 48 MHz

(pipeline mode enabled)

V_CC

Digital logic supply voltage (Core)

V

SYSCLK = 60 MHz

(pipeline mode enabled)

1.81

2.05

V_CCIO

V_CCAD

V_CCP

V_SS

Digital logic supply voltage (I/O)

ADC supply voltage

3

3.6

V

Flash pump supply voltage

Digital logic supply ground

ADC supply ground⁽¹⁾

0

V_SSAD

T_A

–0.1

–40

0.1

Operating free-air temperature

Operating junction temperature

A version

85 ° C

T_J

150 ° C

(1) All voltages are with respect to V_SS, except V_CCAD, which is with respect to V_SSAD

.

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ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range⁽¹⁾

PARAMETER

V_hysInput hysteresis

TEST CONDITIONS

MIN

TYP⁽²⁾

MAX

UNIT

0.15

V

Low-level input

voltage

V_IL

V_IH

All inputs⁽³⁾

–0 .3

2

0.8

V_CCIO+ 0. 3

1.8

V

High-level input

voltage

All inputs

Input threshold

voltage

AWD only⁽⁴⁾

1.35

I_OL= I_OLMAX

I_OL= 50 µA

0.2 V_CCIO

0.2

V_OLLow-level output voltage⁽⁵⁾

V_OHHigh-level output voltage⁽⁵⁾

V

I_OH= I_OHMIN

I_OH= 50 µA

0.8 V_CCIO

V

V_CCIO– 0.2

V_I< V_SSIO– 0. 3 or V_I> V_CCIO

0. 3

+

I_IC

Input clamp current (I/O pins)⁽⁶⁾

I_ILPulldown

–2

2

mA

V_I= V_SS

–1

5

1

40

–5

1

I_IHPulldown

I_ILPullup

V_I= V_CCIO

V_I= V_SS

Input current

(3.3 V input pins)

–40

–1

1

µA

I_IHPullup

V_I= V_CCIO

No pullup or pulldown

V_I= V_SS

I_I

All other pins

1

V_I= V_CCIO

V_I= 5 V

5

Input current (5 V tolerant input pins)

µA

5

25

50

V_I= 5.5 V

25

CLKOUT, AWD, TDI,

TDO, TMS, TMS2

8

Low-level output

current

RST

4

2

4

I_OL

V_OL= V_OLMAX

mA

All other 3.3 V I/O⁽⁷⁾

5 V tolerant

CLKOUT, TDI, TDO,

TMS, TMS2

–8

High-level output

current

RST

–4

–2

–4

I_OH

V_OH= V_OHMIN

mA

All other 3.3 V I/O⁽⁷⁾

5 V tolerant

SYSCLK = 48 MHz,

ICLK = 24 MHz, V_CC= 2.05 V

110

125

mA

V_CCDigital supply current (operating mode)

SYSCLK = 60 MHz,

ICLK = 30 MHz, V_CC= 2.05 V

I_CC

V_CCDigital supply current (standby mode)⁽⁸⁾⁽⁹⁾OSCIN = 5 MHz, V_CC= 2.05 V

V_CCDigital supply current (halt mode)⁽⁸⁾⁽⁹⁾

All frequencies, V_CC= 2.05 V

1.30

700

mA

µA

(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.

(2) The typical values indicated in this table are the expected values during operation under normal operating conditions: nominal V_CC

,

V_CCIO, or V_CCAD, room temperature.

(3) This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST Timings section.

(4) These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide

(literature number SPNU189).

(5) V_OLand V_OHare linear with respect to the amount of load current (I_OL/I_OH) applied.

(6) Parameter does not apply to input-only or output-only pins.

(7) Some of the 2 mA buffers on this device are zero-dominant buffers, as indicated by a -z in the Output Current column of the Terminal

Functions table. If two of these buffers are shorted together and one is outputting a low level and the other is outputting a high level, the

resulting value will always be low.

(8) For flash banks/pumps in sleep mode.

(9) For reduced power consumption in low power mode, CANSRX and CANSTX should be driven output LOW.

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ELECTRICAL CHARACTERISTICS (continued)

over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

MIN

TYP⁽²⁾

MAX

UNIT

V_CCIODigital supply current (operating mode)

I_CCIOV_CCIODigital supply current (standby mode)⁽⁹⁾

V_CCIODigital supply current (halt mode)⁽⁹⁾

V_CCADsupply current (operating mode)

I_CCADV_CCADsupply current (standby mode)

V_CCADsupply current (halt mode)

No DC load, V_CCIO= 3.6 V⁽¹⁰⁾

All frequencies, V_CCAD= 3.6 V

15

10

15

10

mA

µA

µ A

mA

µA

SYSCLK = 48 MHz, V_CCP= 3.6 V

read operation

45

mA

SYSCLK = 60 MHz, V_CCP= 3.6 V

read operation

55

70

10

mA

µA

I_CCPV_CCPpump supply current

V_CCP= 3.6 V program and erase

V_CCP= 3.6 V standby mode

operation⁽⁸⁾

V_CCP= 3.6 V halt mode

operation⁽⁸⁾

10

µA

C_I

Input capacitance

Output capacitance

2

3

pF

C_O

(10) I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ V_CCIO– 0.2 V.

Parameter Measurement Information

I_OL

Tester Pin

Electronics

Output

Ω

50

V_LOAD

Under

Test

C_L

I_OH

(A)

Where:

I

= I MAX for the respective pin

OL

= I MIN for the respective pin

OH

OL

(A)

OH

V

C

= 1.5 V

LOAD

(B)

= 150-pF typical load-circuit capacitance

L

A. For these values, see the "Electrical Characteristics over Recommended Operating Free-Air Temperature Range"

table.

B. All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted.

Figure 5. Test Load Circuit

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Timing Parameter Symbology

Timing parameter symbols have been created in accordance with JEDEC Standard 100. To shorten the

symbols, some of the pin names and other related terminology have been abbreviated as follows:

CM

CO

ER

ICLK

M

Compaction, CMPCT

CLKOUT

RD

Read

RST

RX

Reset, RST

SCInRX

Erase

Interface clock

Master mode

S

Slave mode

SCInCLK

SPInSIMO

SPInSOMI

SPInCLK

System clock

SCInTX

SCC

SIMO

SOMI

SPC

SYS

TX

OSC, OSCI OSCIN

OSCO

P

OSCOUT

Program, PROG

R

Ready

R0

R1

Read margin 0, RDMRGN0

Read margin 1, RDMRGN1

Lowercase subscripts and their meanings are:

a

c

d

f

access time

cycle time (period)

delay time

r

rise time

su

t

setup time

transition time

valid time

fall time

v

h

hold time

w

pulse duration (width)

The following additional letters are used with these meanings:

H

L

High

Low

X

Z

Unknown, changing, or don't care level

High impedance

V

Valid

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External Reference Resonator/Crystal Oscillator Clock Option

The oscillator is enabled by connecting the appropriate fundamental 4–10 MHz resonator/crystal and load

capacitors across the external OSCIN and OSCOUT pins as shown in Figure 6a. The oscillator is a single-stage

inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement

and HALT mode. TI strongly encourages each customer to submit samples of the device to the

resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will

best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over

temperature/voltage extremes.

An external oscillator source can be used by connecting a 1.8-V clock signal to the OSCIN pin and leaving the

OSCOUT pin unconnected (open) as shown in Figure 6b.

OSCIN

OSCOUT

OSCIN

OSCOUT

External

Clock Signal

(toggling 0-1.8 V)

(A)

C1

C2

Crystal

(a)

(b)

A. The values of C1 and C2 should be provided by the resonator/crystal vendor.

Figure 6. Crystal/Clock Connection

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ZPLL AND CLOCK SPECIFICATIONS

Timing Requirements for ZPLL Circuits Enabled or Disabled

MIN

4

TYP

MAX UNIT

f_(OSC)

Input clock frequency

10 MHz

ns

t_c(OSC)

Cycle time, OSCIN

100

15

t_w(OSCIL)

t_w(OSCIH)

f_(OSCRST)

Pulse duration, OSCIN low

Pulse duration, OSCIN high

OSC FAIL frequency⁽¹⁾

ns

15

ns

53

kHz

(1) Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1)

bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide

(literature number SPNU189).

Switching Characteristics over Recommended Operating Conditions for Clocks^(1)(2)(3)

PARAMETER

TEST CONDITIONS⁽⁴⁾

Pipeline mode enabled

Pipeline mode disabled

MIN

MAX UNIT

60⁽⁶⁾MHz

24 MHz

30 MHz

24 MHz

30 MHz

24 MHz

ns

f_(SYS)

System clock frequency⁽⁵⁾

f_(CONFIG)

f_(ICLK)

System clock frequency - flash config mode

Interface clock frequency

Pipeline mode enabled

Pipeline mode disabled

Pipeline mode enabled

Pipeline mode disabled

Pipeline mode enabled

Pipeline mode disabled

f_(ECLK)

External clock output frequency for ECP module

16.7

41.6

33.3

41.6

33.3

41.6

t_c(SYS)

Cycle time, system clock

ns

t_c(CONFIG)

t_c(ICLK)

Cycle time, system clock - flash config mode

Cycle time, interface clock

ns

Pipeline mode enabled

Pipeline mode disabled

Pipeline mode enabled

Pipeline mode disabled

ns

t_c(ECLK)

Cycle time, ECP module external clock output

ns

(1) f_(SYS)= M × f_(OSC)/R, where M = {8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the

CLKDIVPRE [2:0] bits in the global control register (GLBCTRL[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the

GLBCTRL register (GLBCTRL.3).

f_(SYS)= f_(OSC)/R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.

f_(ICLK)= f_(SYS)/X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1]

bits in the SYS module.

(2) f_(ECLK)= f_(ICLK)/N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.

(3) Only ZPLL mode is available. FM mode must not be turned on.

(4) Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).

(5) Flash Vread must be set to 5 V to achieve maximum system clock frequency.

(6) Operating V_CCrange for this system clock frequency is 1.81 to 2.05 V.

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Switching Characteristics over Recommended Operating Conditions for External Clocks^(1)(2)(3)

(see Figure 7 and Figure 8)

PARAMETER

TEST CONDITIONS

SYSCLK or MCLK⁽⁴⁾

MIN

MAX

UNIT

0.5t_c(SYS)– t_f

t_w(COL)

t_w(COH)

t_w(EOL)

t_w(EOH)

Pulse duration, CLKOUT low

ICLK: X is even or 1⁽⁵⁾

ICLK: X is odd and not 1⁽⁵⁾

SYSCLK or MCLK⁽⁴⁾

0.5t_c(ICLK)– t_f

ns

0.5t_c(ICLK)+ 0.5t_c(SYS)– t_f

0.5t_c(SYS)– t_r

Pulse duration, CLKOUT high

Pulse duration, ECLK low

Pulse duration, ECLK high

ICLK: X is even or 1⁽⁵⁾

0.5t_c(ICLK)– t_r

ns

ICLK: X is odd and not 1⁽⁵⁾

N is even and X is even or odd

N is odd and X is even

0.5t_c(ICLK)– 0.5t_c(SYS)– t_r

0.5t_c(ECLK)– t_f

N is odd and X is odd and not 1

N is even and X is even or odd

N is odd and X is even

0.5t_c(ECLK)+ 0.5t_c(SYS)– t_f

0.5t_c(ECLK)– t_r

N is odd and X is odd and not 1

0.5t_c(ECLK)– 0.5t_c(SYS)– t_r

(1) X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1] bits in the SYS module.

(2) N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.

(3) CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.

(4) Clock source bits are selected as either SYSCLK (CLKCNTL[6:5] = 11 binary) or MCLK (CLKCNTL[6:5] = 10 binary).

(5) Clock source bits are selected as ICLK (CLKCNTL[6:5] = 01 binary).

t

w(COH)

CLKOUT

t

w(COL)

Figure 7. CLKOUT Timing Diagram

t

w(EOH)

ECLK

t

w(EOL)

Figure 8. ECLK Timing Diagram

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RST AND PORRST TIMINGS

Timing Requirements for PORRST

(see Figure 9)

MIN

MAX UNIT

V_CCPORL

V_CClow supply level when PORRST must be active during power up

0.6

V

V_CChigh supply level when PORRST must remain active during power up and become

active during power down

V_CCPORH

V_CCIOPORL

V_CCIOPORH

1.5

V_CCIOlow supply level when PORRST must be active during power up

1.1

V_CCIOhigh supply level when PORRST must remain active during power up and become

active during power down

2.75

V_IL

Low-level input voltage after V_CCIO> V_CCIOPORH

0.2 V_CCIO

0.5

V

V_IL(PORRST)

t_su(PORRST)r

t_su(VCCIO)r

t_h(PORRST)r

t_su(PORRST)f

t_h(PORRST)rio

t_h(PORRST)d

Low-level input voltage of PORRST before V_CCIO> V_CCIOPORL

Setup time, PORRST active before V_CCIO> V_CCIOPORLduring power up

Setup time, V_CCIO>V_CCIOPORLbefore V_CC> V_CCPORL

Hold time, PORRST active after V_CC> V_CCPORH

V

0

1

8

1

0

ms

µs

ms

ns

Setup time, PORRST active before V_CC≤ V_CCPORHduring power down

Hold time, PORRST active after V_CC> V_CCIOPORH

Hold time, PORRST active after V_CC< V_CCPORL

t_{su(PORRST)fio}Setup time, PORRST active before V_CC≤ V_CCIOPORHduring power down

t_su(VCCIO)f

Setup time, V_CC< V_CCPORLbefore V_CCIO< V_CCIOPORL

V_CCP/V_CCIO

V_CCIOPORH

V_CCIO

t

h(PORRST)rio

t

su(VCCIO)f

V_CC

V_CCPORH

t

su(PORRST)f

t

h(PORRST)r

t

su(PORRST)fio

t

V_CCIOPORL

su(PORRST)f

V_CCPORL

t

h(PORRST)r

V_CC

t

su(VCCIO)r

V /V

CCP CCIO

t

h(PORRST)d

t

su(PORRST)r

V_IL(PORRST)

V_IL

V_IL(PORRST)

PORRST

NOTE: V_CCIO> 1.1 V before V_CC> 0.6 V

Figure 9. PORRST Timing Diagram

Switching Characteristics over Recommended Operating Conditions for RST⁽¹⁾

PARAMETER

MIN

MAX UNIT

Valid time, RST active after PORRST inactive

Valid time, RST active (all others)

4112t_c(OSC)

8t_c(SYS)

t_v(RST)

t_fsu

ns

Flash start up time, from RST inactive to fetch of first instruction from flash (flash pump

stabilization time)

836t_c(OSC)

ns

(1) Specified values do NOT include rise/fall times. For rise and fall timings, see the "switching characteristics for output timings versus load

capacitance" table.

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JTAG SCAN INTERFACE TIMING (JTAG CLOCK SPECIFICATION 10-MHz AND 50-pF LOAD ON

TDO OUTPUT)

MIN

50

MAX UNIT

t_c(JTAG)

Cycle time, JTAG low and high period

Setup time, TDI, TMS before TCK rise (TCKr)

Hold time, TDI, TMS after TCKr

ns

t_{su(TDI/TMS - TCKr)}

t_{h(TCKr -TDI/TMS)}

t_{h(TCKf -TDO)}

t_{d(TCKf -TDO)}

15

ns

Hold time, TDO after TCKf

10

ns

Delay time, TDO valid after TCK fall (TCKf)

45 ns

T CK

t

c(J TAG )

t

c(J TAG )

T M S

T DI

t

su(TDI /TMS Ć TCKr)

t

h(TCKr Ć TDI /TMS)

T DO

t

h(TCKf Ć TDO )

t

d(TCKf Ć TDO )

Figure 10. JTAG Scan Timings

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OUTPUT TIMINGS

Switching Characteristics for Output Timings versus Load Capacitance ©_L)

(see Figure 11)

PARAMETER

C_L= 15 pF

C_L= 50 pF

MIN

0.5

1.5

3.0

4.5

0.5

1.5

3.0

4.5

2.5

5

MAX UNIT

2.5

5.0

ns

t_r

t_f

t_r

Rise time, AWD, CLKOUT, TDI, TDO, TMS, TMS2

Fall time, AWD, CLKOUT, TDI, TDO, TMS, TMS2

Rise time, RST

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 400 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 400 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

9.0

12.5

2.5

5.0

ns

9.0

12.5

8

14

ns

23

9

13

3

32

10

12

3.5

7

t_r

Rise time, 4mA, 5 V tolerant pins

21

28

40

8

ns

9

18

2

2.5

8

9

t_f

Fall time, 4mA, 5 V tolerant pins

Rise time, all other output pins

25

35

45

10

25

45

65

10

25

45

65

11

20

2.5

6.0

12

18

3

t_r

ns

8.5

16

23

t_f

Fall time, all other output pins

t_r

t_f

V_CC

80%

Output

20%

0

Figure 11. CMOS-Level Outputs

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INPUT TIMINGS

Timing Requirements for Input Timings⁽¹⁾

(see Figure 12)

MIN

MAX UNIT

t_pw

Input minimum pulse width

t_c(ICLK)+ 10

ns

(1) t_c(ICLK)= interface clock cycle time = 1/f_(ICLK)

t_pw

V_CC

Input

80%

20%

0

Figure 12. CMOS-Level Inputs

FLASH TIMINGS

Timing Requirements for Program Flash⁽¹⁾

MIN

TYP

16

MAX UNIT

t_prog(16-bit)

t_prog(Total)

t_{erase(sector)}

t_wec

Half word (16-bit) programming time

1M-byte programming time⁽²⁾

4

200

32

µs

s

8

Sector erase time

1.7

s

Write/erase cycles at T_A= –40°C to 85°C

Flash pump settling time from RST to SLEEP

Initial flash pump settling time from SLEEP to STANDBY

50000

cycles

ns

t_fp(RST)

167t_c(SYS)

84t_c(SYS)

t_fp(SLEEP)

ns

t_fp(STANDBY)Initial flash pump settling time from STANDBY to ACTIVE

ns

(1) For more detailed information on the flash core sectors, see the flash program and erase section of this data sheet.

(2) The 1M-byte programming time includes overhead of state machine.

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SPIn MASTER MODE TIMING PARAMETERS

SPIn Master Mode External Timing Parameters

(CLOCK PHASE = 0, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input)^(1)(2)(3)(see Figure 13)

NO.

MIN

MAX

256t_c(ICLK)

0.5t_c(SPC)M+ 5

10

UNIT

1

t_c(SPC)M

Cycle time, SPInCLK⁽⁴⁾

100

t_w(SPCH)M

t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPInCLK high (clock polarity = 0)

Pulse duration, SPInCLK low (clock polarity = 1)

Pulse duration, SPInCLK low (clock polarity = 0)

Pulse duration, SPInCLK high (clock polarity = 1)

0.5t_c(SPC)M– t_r

0.5t_c(SPC)M– t_f

0.5t_c(SPC)M– t_r

2⁽⁵⁾

3⁽⁵⁾

4⁽⁵⁾

5⁽⁵⁾

6⁽⁵⁾

7⁽⁵⁾

t_{d(SPCH-SIMO)M}Delay time, SPInCLK high to SPInSIMO valid (clock polarity = 0)

t_{d(SPCL-SIMO)M}

t_{v(SPCL-SIMO)M}

t_{v(SPCH-SIMO)M}

Delay time, SPInCLK low to SPInSIMO valid (clock polarity = 1)

Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0)

Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1)

10

ns

t_c(SPC)M– 5 – t_f

t_c(SPC)M– 5 – t_r

t_{su(SOMI-SPCL)M}Setup time, SPInSOMI before SPInCLK low (clock polarity = 0)

t_{su(SOMI-SPCH)M}Setup time, SPInSOMI before SPInCLK high (clock polarity = 1)

6

4

t_{v(SPCL-SOMI)M}

t_{v(SPCH-SOMI)M}

Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 0)

Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 1)

(1) The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.

(2) t_c(ICLK)= interface clock cycle time = 1/f_(ICLK)

(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.

(4) When the SPI is in master mode, the following must be true:

For PS values from 1 to 255: t _c(SPC)M≥ (PS +1)t_c(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.

For PS values of 0: t_c(SPC)M= 2t _c(ICLK)≥ 100 ns.

(5) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

1

SPInCLK

(clock polarity = 0)

2

3

SPInCLK

(clock polarity = 1)

4

5

SPInSIMO

Master Out Data Is Valid

6

7

Master In Data

Must Be Valid

SPInSOMI

Figure 13. SPIn Master Mode External Timing (CLOCK PHASE = 0)

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SPIn Master Mode External Timing Parameters

(CLOCK PHASE = 1, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input)^(1)(2)(3)(see Figure 14)

NO.

MIN

MAX

UNIT

1

t_c(SPC)M

Cycle time, SPInCLK⁽⁴⁾

100

256t_c(ICLK)

t_w(SPCH)M

t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPInCLK high (clock polarity = 0)

Pulse duration, SPInCLK low (clock polarity = 1)

Pulse duration, SPInCLK low (clock polarity = 0)

Pulse duration, SPInCLK high (clock polarity = 1)

0.5t_c(SPC)M– t_r

0.5t_c(SPC)M– t_f

0.5t_c(SPC)M– t_r

0.5t_c(SPC)M+ 5

2⁽⁵⁾

3⁽⁵⁾

Valid time, SPInCLK high after SPInSIMO data valid

(clock polarity = 0)

t_{v(SIMO-SPCH)M}

t_{v(SIMO-SPCL)M}

t_{v(SPCH-SIMO)M}

t_{v(SPCL-SIMO)M}

t_{su(SOMI-SPCH)M}

t_{su(SOMI-SPCL)M}

t_{v(SPCH-SOMI)M}

t_{v(SPCL-SOMI)M}

0.5t_c(SPC)M– 10

4⁽⁵⁾

5⁽⁵⁾

6⁽⁵⁾

7⁽⁵⁾

Valid time, SPInCLK low after SPInSIMO data valid

(clock polarity = 1)

0.5t_c(SPC)M– 10

Valid time, SPInSIMO data valid after SPInCLK high

(clock polarity = 0)

0.5t_c(SPC)M– 5 – t_r

ns

Valid time, SPInSIMO data valid after SPInCLK low

(clock polarity = 1)

0.5t_c(SPC)M– 5 – t_f

Setup time, SPInSOMI before SPInCLK high

(clock polarity = 0)

6

4

Setup time, SPInSOMI before SPInCLK low

(clock polarity = 1)

Valid time, SPInSOMI data valid after SPInCLK high

(clock polarity = 0)

Valid time, SPInSOMI data valid after SPInCLK low

(clock polarity = 1)

(1) The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.

(2) t_c(ICLK)= interface clock cycle time = 1/f_(ICLK)

(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.

(4) When the SPI is in master mode, the following must be true:

For PS values from 1 to 255: t _c(SPC)M≥ (PS +1)t_c(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.

For PS values of 0: t_c(SPC)M= 2t _c(ICLK)≥ 100 ns.

(5) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

1

SPInCLK

(clock polarity = 0)

2

3

SPInCLK

(clock polarity = 1)

4

5

SPInSIMO

Master Out Data Is Valid

6

Data Valid

7

Master In Data

Must Be Valid

SPInSOMI

Figure 14. SPIn Master Mode External Timing (CLOCK PHASE = 1)

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SPIn SLAVE MODE TIMING PARAMETERS

SPIn Slave Mode External Timing Parameters

(CLOCK PHASE = 0, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output)^(1)(2)(3)(4)(see Figure 15)

NO.

MIN

MAX

UNI

T

1

t_c(SPC)S

Cycle time, SPInCLK⁽⁵⁾

100

256t_c(ICLK)

t_w(SPCH)S

t_w(SPCL)S

t_w(SPCH)S

Pulse duration, SPInCLK high (clock polarity = 0)

Pulse duration, SPInCLK low (clock polarity = 1)

Pulse duration, SPInCLK low (clock polarity = 0)

Pulse duration, SPInCLK high (clock polarity = 1)

0.5t_c(SPC)S– 0.25t_c(ICLK)0.5t_c(SPC)S+ 0.25t_c(ICLK)

2⁽⁶⁾

3⁽⁶⁾

Delay time, SPInCLK high to SPInSOMI valid

(clock polarity = 0)

t_{d(SPCH-SOMI)S}

t_{d(SPCL-SOMI)S}

t_{v(SPCH-SOMI)S}

t_{v(SPCL-SOMI)S}

t_{su(SIMO-SPCL)S}

t_{su(SIMO-SPCH)S}

t_{v(SPCL-SIMO)S}

t_{v(SPCH-SIMO)S}

6 + t_r

4⁽⁶⁾

Delay time, SPInCLK low to SPInSOMI valid

(clock polarity = 1)

6 + t_f

Valid time, SPInSOMI data valid after SPInCLK high

(clock polarity = 0)

t_c(SPC)S– 6 – t_r

ns

5⁽⁶⁾

6⁽⁶⁾

7⁽⁶⁾

Valid time, SPInSOMI data valid after SPInCLK low

(clock polarity = 1)

t_c(SPC)S– 6 – t_f

Setup time, SPInSIMO before SPInCLK low

(clock polarity = 0)

6

Setup time, SPInSIMO before SPInCLK high

(clock polarity = 1)

Valid time, SPInSIMO data valid after SPInCLK low

(clock polarity = 0)

Valid time, SPInSIMO data valid after SPInCLK high

(clock polarity = 1)

(1) The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.

(2) If the SPI is in slave mode, the following must be true: t_c(SPC)S≥ (PS + 1) t_c(ICLK), where PS = prescale value set in SPInCTL1[12:5].

(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.

(4) t_c(ICLK)= interface clock cycle time = 1/f_(ICLK)

(5) When the SPIn is in slave mode, the following must be true:

For PS values from 1 to 255: t _c(SPC)S≥ (PS +1)t_c(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.

For PS values of 0: t_c(SPC)S= 2t _c(ICLK)≥ 100 ns.

(6) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

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1

SPInCLK

(clock polarity = 0)

2

3

SPInCLK

(clock polarity = 1)

4

5

SPISOMI Data Is Valid

SPInSOMI

6

7

SPISIMO Data

Must Be Valid

SPInSIMO

Figure 15. SPIn Slave Mode External Timing (CLOCK PHASE = 0)

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SPIn Slave Mode External Timing Parameters

(CLOCK PHASE = 1, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output)^(1)(2)(3)(4)(see Figure 16)

NO.

MIN

MAX

UNI

T

1

t_c(SPC)S

Cycle time, SPInCLK⁽⁵⁾

100

256t_c(ICLK)

t_w(SPCH)S

t_w(SPCL)S

t_w(SPCH)S

Pulse duration, SPInCLK high (clock polarity = 0)

Pulse duration, SPInCLK low (clock polarity = 1)

Pulse duration, SPInCLK low (clock polarity = 0)

Pulse duration, SPInCLK high (clock polarity = 1)

0.5t_c(SPC)S– 0.25t_c(ICLK)0.5t_c(SPC)S+ 0.25t_c(ICLK)

2⁽⁶⁾

3⁽⁶⁾

Valid time, SPInCLK high after SPInSOMI data valid

(clock polarity = 0)

t_{v(SOMI-SPCH)S}

t_{v(SOMI-SPCL)S}

t_{v(SPCH-SOMI)S}

t_{v(SPCL-SOMI)S}

0.5t_c(SPC)S– 6 – t_r

4⁽⁶⁾

Valid time, SPInCLK low after SPInSOMI data valid

(clock polarity = 1)

0.5t_c(SPC)S– 6 – t_f

Valid time, SPInSOMI data valid after SPInCLK high

(clock polarity = 0)

0.5t_c(SPC)S– 6 – t_r

ns

5⁽⁶⁾

6⁽⁶⁾

7⁽⁶⁾

Valid time, SPInSOMI data valid after SPInCLK low

(clock polarity = 1)

0.5t_c(SPC)S– 6 – t_f

Setup time, SPInSIMO before SPInCLK high

(clock polarity = 0)

t_{su(SIMO-SPCH)}

S

6

Setup time, SPInSIMO before SPInCLK low

(clock polarity = 1)

t_{su(SIMO-SPCL)}

t_{v(SPCH-SIMO)S}

t_{v(SPCL-SIMO)S}

S

Valid time, SPInSIMO data valid after SPInCLK high

(clock polarity = 0)

Valid time, SPInSIMO data valid after SPInCLK low

(clock polarity = 1)

(1) The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.

(2) If the SPI is in slave mode, the following must be true: t_c(SPC)≥ (PS + 1) t_c(ICLK), where PS = prescale value set in SPInCTL1[12:5].

(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.

(4) t_c(ICLK)= interface clock cycle time = 1/f_(ICLK)

(5) When the SPIn is in slave mode, the following must be true:

For PS values from 1 to 255: t _c(SPC)S≥ (PS +1)t_c(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.

For PS values of 0: t_c(SPC)S= 2t _c(ICLK)≥ 100 ns.

(6) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

1

SPInCLK

(clock polarity = 0)

2

3

SPInCLK

(clock polarity = 1)

4

5

SPInSOMI

SPISOMI Data Is Valid

6

Data Valid

7

SPISIMO Data Must

Be Valid

SPInSIMO

Figure 16. SPIn Slave Mode External Timing (CLOCK PHASE = 1)

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SCIn ISOSYNCHRONOUS MODE TIMINGS - INTERNAL CLOCK

Timing Requirements for Internal Clock SCIn Isosynchronous Mode^(1)(2)(3)

(see Figure 17)

(BAUD + 1)

IS EVEN OR BAUD = 0

IS ODD AND BAUD ≠ 0

UNIT

MIN

MAX

MIN

MAX

Cycle time,

SCInCLK

t_c(SCC)

2t_c(ICLK)

2²⁴t_c(ICLK)

3t_c(ICLK)

(2²⁴– 1) t_c(ICLK)

ns

Pulse duration,

SCInCLK low

t_w(SCCL)

t_w(SCCH)

0.5t_c(SCC)– t_f

0.5t_c(SCC)– t_r

0.5t_c(SCC)+ 5

0.5t_c(SCC)+ 0.5t_c(ICLK)– t_f

0.5t_c(SCC)– 0.5t_c(ICLK)– t_r

0.5t_c(SCC)+ 0.5t_c(ICLK)

0.5t_c(SCC)– 0.5t_c(ICLK)

Pulse duration,

SCInCLK high

Delay time,

t_d(SCCH-TXV)

SCInCLK high to

SCInTX valid

10

ns

Valid time,

SCInTX data

after SCInCLK

low

t_v(TX)

t_c(SCC)– 10

t_c(ICLK)+ t_f+ 20

–t_c(ICLK)+ t_f+ 20

t_c(SCC)– 10

t_c(ICLK)+ t_f+ 20

–t_c(ICLK)+ t_f+ 20

Setup time,

SCInRX before

SCInCLK low

t_su(RX-SCCL)

Valid time,

SCInRX data

after SCInCLK

low

t_v(SCCL-RX)

(1) BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.

(2) t_c(ICLK)= interface clock cycle time = 1/f_(ICLK)

(3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

t

c(SCC)

t

w(SCCH)

t

w(SCCL)

SCICLK

SCITX

SCIRX

t

v(TX)

t

d(SCCHĆTXV)

Data Valid

t

su(RXĆSCCL)

t

v(SCCLĆRX)

Data Valid

A. Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the

asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the

SCICLK falling edge.

Figure 17. SCIn Isosynchronous Mode Timing Diagram for Internal Clock

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SCIn ISOSYNCHRONOUS MODE TIMINGS - EXTERNAL CLOCK

Timing Requirements for External Clock SCIn Isosynchronous Mode⁽¹⁾⁽²⁾

(see Figure 18)

MIN

MAX

UNIT

ns

t_c(SCC)

Cycle time, SCInCLK⁽³⁾

8t_c(ICLK)

t_w(SCCH)

t_w(SCCL)

t_d(SCCH-TXV)

t_v(TX)

t_su(RX-SCCL)

t_v(SCCL-RX)

Pulse duration, SCInCLK high

0.5t_c(SCC)– 0.25t_c(ICLK)

0.5t_c(SCC)+ 0.25t_c(ICLK)

2t_c(ICLK)+ 12 + t _r

ns

Pulse duration, SCInCLK low

ns

Delay time, SCInCLK high to SCInTX valid

Valid time, SCInTX data after SCInCLK low

Setup time, SCInRX before SCInCLK low

Valid time, SCInRX data after SCInCLK low

ns

2t_c(SCC)– 10

0

ns

2t_c(ICLK)+ 10

ns

(1) t_c(ICLK)= interface clock cycle time = 1/f_(ICLK)

(2) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

(3) When driving an external SCInCLK, the following must be true: t_c(SCC)≥ 8t_c(ICLK)

.

t

c(SCC)

t

w(SCCH)

t

w(SCCL)

SCICLK

SCITX

SCIRX

t

v(TX)

t

d(SCCHĆTXV)

Data Valid

t

su(RXĆSCCL)

t

v(SCCLĆRX)

Data Valid

A. Data transmission / reception characteristics for isosynchronous mode with external clocking are similar to the

asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the

SCICLK falling edge.

Figure 18. SCIn Isosynchronous Mode Timing Diagram for External Clock

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I2C TIMING

Table 11 assumes testing over recommended operating conditions.

I2C Signals (SDA and SCL) Switching Characteristics⁽¹⁾

STANDARD MODE

FAST MODE

PARAMETER

UNIT

MIN

75

MAX

MIN

75

MAX

t_c(I2CCLK)

t_c(SCL)

Cycle time, I2C module clock

Cycle time, SCL

150

ns

µs

10

2.5

Setup time, SCL high before SDA low (for a repeated START

condition)

t_{su(SCLH-SDAL)}

t_h(SCLL-SDAL)

4.7

4

0.6

µs

Hold time, SCL low after SDA low (for a repeated START

condition)

t_w(SCLL)

t_w(SCLH)

t_su(SDA-SCLH)

t_h(SDA-SCLL)

t_w(SDAH)

t_r(SCL)

Pulse duration, SCL low

4.7

4

1.3

0.6

µs

ns

µs

ns

µs

ns

pF

Pulse duration, SCL high

Setup time, SDA valid before SCL high

250

0

100

Hold time, SDA valid after SCL low

For I2C bus devices

3.45⁽²⁾

0

0.9

Pulse duration, SDA high between STOP and START conditions

4.7

1.3

(3)

Rise time, SCL

Rise time, SDA

Fall time, SCL

Fall time, SDA

1000

300

20+0.1C_b

0.6

300

t_r(SDA)

t_f(SCL)

t_f(SDA)

300

t_{su(SCLH-SDAH)}Setup time, SCL high before SDA high (for STOP condition)

4.0

t_w(SP)

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

0

50

(3)

C_b

400

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down.

(2) The maximum t_h(SDA-SCLL)for I2C bus devices needs to be met only if the device does not stretch the low period (t_w(SCLL)) of the SCL

signal.

(3) C _b= The total capacitance of one bus line in pF. If mixed with HS=mode devices, faster fall-times are allowed.

SDA

t

w(SDAH)

w(SP)

t

su(SDA−SCLH)

r(SCL)

t

su(SCLH−SDAH)

t

w(SCLL)

t

w(SCLH)

SCL

t

f(SCL)

t

)

c(SCL

t

)

h(SCLL−SDAL

t

h(SDA−SCLL)

t

su(SCLH−SDAL)

t

h(SCLL−SDAL)

Stop

Start

Repeated

Stop

A. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHminof the SCL

signal) to bridge the undefined region of the falling edge of SCL.

B. The maximum t_h(SDA-SCLL)needs only be met if the device does not stretch the LOW period (t_w(SCLL)) of the SCL

signal.

C. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement t_su(SDA-SCLH)≥ 250

ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL

signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA

line t_rmax + t_su(SDA-SCLH)

.

D. C_b= total capacitance of one bus line in pF. If mixed with HS=mode devices, faster fall-times are allowed.

Figure 19. I2C Timings

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STANDARD CAN CONTROLLER (SCC) MODE TIMINGS

Dynamic Characteristics for the CANSTX and CANSRX Pins

PARAMETER

t_d(CANSTX) Delay time, transmit shift register to CANSTX pin⁽¹⁾

t_d(CANSRX) Delay time, CANSRX pin to receive shift register

MIN

MAX UNIT

15

5

ns

(1) These values do not include the rise/fall times of the output buffer.

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EXPANSION BUS MODULE TIMING

Expansion Bus Timing Parameters

–40°C ≤ T_J≤ 150°C, 3.0 V ≤ V _CC≤ 3.6 V (see Figure 20 and Figure 21)

MIN

MAX UNIT

t_c(CO)

Cycle time, CLKOUT

20.8

ns

t_d(COH-EBADV)

t_{h(COH-EBADIV)}

t_d(COH-EBOE)

Delay time, CLKOUT high to EBADDR valid

Hold time, EBADDR invalid after CLKOUT high

Delay time, CLKOUT high to EBOE fall

21.4

12.4

11.4

11.3

11.6

ns

t_h(COH-EBOEH)

t_d(COL-EBWR)

t_h(COL-EBWRH)

t_{su(EBRDATV-COH)}

t_{h(COH-EBRDATIV)}

t_{d(COL-EBWDATV)}

t_{h(COL-EBWDATIV)}

Hold time, EBOE rise after CLKOUT high

Delay time, CLKOUT low to write strobe (EBWR) low

Hold time, EBWR high after CLKOUT low

Setup time, EBDATA valid before CLKOUT high (READ)⁽¹⁾

Hold time, EBDATA invalid after CLKOUT high (READ)

Delay time, CLKOUT low to EBDATA valid (WRITE)⁽²⁾

Hold time, EBDATA invalid after CLKOUT low (WRITE)

SECONDARY TIMES

15.2

(–14.7)

16.1

14.7

t_d(COH-EBCS0)

Delay, CLKOUT high to EBCS0 fall

13.6

13.2

ns

t_{h(COH-EBCS0H)}

t_{su(COH-EBHOLDL)}

t_{su(COH-EBHOLDH)}

Hold, EBCS0 rise after CLKOUT high

Setup time, EBHOLD low to CLKOUT high⁽¹⁾

Setup time, EBHOLD high to CLKOUT high⁽¹⁾

10.9

10.5

(1) Setup time is the minimum time under worst case conditions. Data with less setup time will not work.

(2) Valid after CLKOUT goes low for write cycles.

t

c(CO)

CLKOUT

t

h(COH-EBADIV)

t

d(COH-EBADV)

Valid

EBADDR

EBDATA

t

h(COH-EBRDATIV)

t

su(EBRDATV-COH)

Valid

t

h(COH-EBOEH)

t

d(COH-EBOE)

EBOE

t

d(COH-EBCS0)

h(COH-EBCS0H)

EBCS0

t

su(COH-EBHOLDH)

1 Hold State

t

su(COH-EBHOLDL)

EBHOLD

Figure 20. Expansion Memory Signal Timing - Reads

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t

c(CO)

CLKOUT

t

h(COH-EBADIV)

t

d(COH-EBADV)

Valid

EBADDR

EBDATA

t

h(COL-EBWDATIV)

t

d(COL-EBWDATV)

Valid

t

h(COL-EBWRH)

t

d(COL-EBWR)

EBWR

t

d(COH-EBCS0)

t

d(COH-EBCS0)

EBCS0

t

su(COH-EBHOLDH)

t

su(COH-EBHOLDL)

EBHOLD

1 Hold State

Figure 21. Expansion Memory Signal Timing - Writes

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HIGH-END TIMER (HET) TIMINGS

Minimum PWM Output Pulse Width:

This is equal to one high resolution clock period (HRP). The HRP is defined by the 6-bit high resolution prescale

factor (hr), which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes.

Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK

For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33ns

Minimum Input Pulses that Can Be Captured:

The input pulse width must be greater or equal to the low resolution clock period (LRP), i.e., the HET loop (the

HET program must fit within the LRP). The LRP is defined by the 3-bit loop-resolution prescale factor (lr), which

is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32.

Therefore, the minimum input pulse width = LRP(min) = hr(min) * lr(min)/SYSCLK = 1 * 1/SYSCLK

For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 * 1/30 = 33.33 ns

NOTE:

Once the input pulse width is greater than LRP, the resolution of the measurement is

still HRP. (That is, the captured value gives the number of HRP clocks inside the

pulse.)

Abbreviations:

hr = HET high resolution divide rate = 1, 2, 3,...63, 64

lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32

High resolution clock period = HRP = hr/SYSCLK

Loop resolution clock period = LRP = hr*lr/SYSCLK

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MULTI-BUFFERED A-TO-D CONVERTER (MibADC)

The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances

the A-to-D performance by preventing digital switching noise on the logic circuitry, which could be present on V

SS and V CC , from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to AD

REFLO unless otherwise noted.

Resolution

10 bits (1024 values)

Assured

Monotonic

Output conversion code

00h to 3FFh [00 for V_AI≤ AD _REFLO; 3FF for V_AI≥ AD _REFHI

]

Table 17. MibADC Recommended Operating Conditions⁽¹⁾

MIN

V_SSAD

MAX

V_CCAD

UNIT

AD_REFHI

AD_REFLO

V_AI

A-to-D high-voltage reference source

V

A-to-D low-voltage reference source

Analog input voltage

V_CCAD

V_SSAD– 0.3

V_CCAD+ 0.3

Analog input clamp current⁽²⁾

(V_AI< V_SSAD– 0.3 or V_AI> V_CCAD+ 0.3)

I_AIC

–2

2

mA

(1) For V_CCADand V_SSADrecommended operating conditions, see the "Device Recommended Operating Conditions" table.

(2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.

Table 18. Operating Characteristics over Full Ranges of Recommended Operating Conditions⁽¹⁾⁽²⁾

PARAMETER

DESCRIPTION/CONDITIONS

See Figure 22.

MIN

TYP

MAX UNIT

500

R_I

C_I

Analog input resistance

250

Ω

Conversion

Sampling

10 pF

30 pF

Analog input capacitance

See Figure 22.

I_AIL

Analog input leakage current

AD_REFHIinput current

See Figure 22.

–1

3

1

5

µA

I_ADREFHI

AD_REFHI= 3.6 V, AD_REFLO= V_SSAD

AD_REFHI- AD_REFLO

mA

Conversion range over which

specified accuracy is maintained

CR

3.6

V

Difference between the actual step width

and the ideal value. See Figure 23.

E_DNL

Differential nonlinearity error

Integral nonlinearity error

±1.5 LSB

±2 LSB

Maximum deviation from the best straight

line through the MibADC. MibADC transfer

characteristics, excluding the quantization

error. See Figure 24.

E_INL

Maximum value of the difference between

an analog value and the ideal midstep

value. See Figure 25.

E _TOT

Total error/Absolute accuracy

±2 LSB

(1) V_CCAD= AD_REFHI

(2) 1 LSB = (AD_REFHI- AD_REFLO)/2¹⁰for the MibADC

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External

MibADC

R_s

R_i

Sample Switch

Input Pin

Sample

Capacitor

Parasitic

Capacitance

R_leak

V_src

C_i

Figure 22. MibADC Input Equivalent Circuit

Table 19. Multi-Buffer ADC Timing Requirements

MIN

0.05

1

NOM

MAX UNIT

t_c(ADCLK)

t_d(SH)

Cycle time, MibADC clock

µs

Delay time, sample and hold time

t_d©)

Delay time, conversion time

0.55

1.55

(1)

t_d(SHC)

Delay time, total sample/hold and conversion time

(1) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for

more details, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).

The differential nonlinearity error shown in Figure 23 (sometimes referred to as differential linearity) is the

difference between an actual step width and the ideal value of 1 LSB.

0 ... 110

0 ... 101

0 ... 100

0 ... 011

DifferentialLinearity

Error(1/2 LSB)

1 LSB

0 ... 010

DifferentialLinearity

Error(- 1/2 LSB)

0 ... 001

1 LSB

0 ... 000

0

1

2

3

4

5

Analog Input Value (LSB)

A. 1 LSB = (AD_REFHI- AD_REFLO)/2¹⁰

Figure 23. Differential Nonlinearity (DNL)

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The integral nonlinearity error shown in Figure 24 (sometimes referred to as linearity error) is the deviation of the

values on the actual transfer function from a straight line.

0 ... 111

0 ... 110

0 ... 101

Ideal

Transition

Actual

Transition

0 ... 100

0 ... 011

At Transition

011/100

(ć 1/2 LSB)

0 ... 010

0 ... 001

End-Point Lin. Error

At Transition

001/010 (ć 1/4 LSB)

0 ... 000

0

1

2

3

4

5

6

7

Analog Input Value (LSB)

A. 1 LSB = (AD_REFHI- AD_REFLO)/2¹⁰

Figure 24. Integral Nonlinearity (INL) Error

The absolute accuracy or total error of an MibADC as shown in Figure 25 is the maximum value of the

difference between an analog value and the ideal midstep value.

0 ... 111

0 ... 110

0 ... 101

0 ... 100

Total Error

At Step 0 ... 101

(-1 1/4 LSB)

0 ... 011

0 ... 010

0 ... 001

0 ... 000

Total Error

At Step 0 ... 001

(1/2 LSB)

0

1

2

3

4

5

6

7

Analog Input Value (LSB)

A. 1 LSB = (AD_REFHI- AD_REFLO)/2¹⁰

Figure 25. Absolute Accuracy (Total) Error

55

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TMS470R1B1M

16/32-Bit RISC Flash Microcontroller

www.ti.com

SPNS109A–SEPTEMBER 2005–REVISED AUGUST 2006

Thermal Resistance Characteristics

PARAMETER

R_{θ JA}

°C/W

43

R_{θ JC}

5

56

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TMS470R1B1M

16/32-Bit RISC Flash Microcontroller

www.ti.com

SPNS109A–SEPTEMBER 2005–REVISED AUGUST 2006

Revision History

This revision history highlights the changes made to the device-specific datasheet SPNS109.

Table 12. Revision History

SPNS109 to SPNS109A

Added note to PORRST Timing Diagram.

Changed T_Arange to –40°C to 85°C on t_wecin "Timing Requirements for Program Flash" table.

Changed t_wecMIN value to 50000 and deleted TYP value in "Timing Requirements for Program Flash" table.

Changed t_{erase(sector)}TYP value to 1.7 in "Timing Requirements for Program Flash" table.

57

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MECHANICAL DATA

MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996

PGE (S-PQFP-G144)

PLASTIC QUAD FLATPACK

108

73

109

72

0,27

M

0,08

0,17

0,50

0,13 NOM

144

37

1

36

Gage Plane

17,50 TYP

20,20

SQ

19,80

0,25

0,05 MIN

22,20

SQ

0°–7°

21,80

0,75

0,45

1,45

1,35

Seating Plane

0,08

1,60 MAX

4040147/C 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

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型号：	TMS470R1B1M_12
厂家：	TEXAS INSTRUMENTS
描述：	16/32-Bit RISC Flash Microcontroller 16位/ 32位RISC闪存微控制器闪存微控制器
文件：	总60页 (文件大小：547K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMS470R1B1M_12 [TI]

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