TMUX1109RSVR [TI]
3pA 导通状态泄漏电流、5V、±2.5V、4:1、2 通道精密多路复用器 | RSV | 16 | -40 to 125;
| 型号： | TMUX1109RSVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3pA 导通状态泄漏电流、5V、±2.5V、4:1、2 通道精密多路复用器 | RSV | 16 | -40 to 125 复用器 |
| 文件： | 总41页 (文件大小：1048K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TMUX1109
SCDS406 –DECEMBER 2018
TMUX1109 5 V, ±2.5 V, Low-Leakage-Current, 4:1, 2-Channel Precision Multiplexer
1 Features
3 Description
The TMUX1109 is a precision complementary metal-
oxide semiconductor (CMOS) multiplexer (MUX). The
TMUX1109 offers differential 4:1 or dual 4:1 single-
ended channels. Wide operating supply of 1.08 V to
5.5 V allows for use in a broad array of applications
from medical equipment to industrial systems. The
device supports bidirectional analog and digital
signals on the source (Sx) and drain (D) pins ranging
from GND to VDD. All logic inputs have 1.8 V logic
compatible thresholds, ensuring both TTL and CMOS
logic compatibility when operating in the valid supply
voltage range. Fail-Safe Logic circuitry allows
voltages on the control pins to be applied before the
supply pin, protecting the device from potential
damage.
1
•
Single Supply Range: 1.08 V to 5.5 V
Dual Supply Range: ±2.75 V
Low Leakage Current: 3 pA
Low Charge Injection: 1 pC
Low On-Resistance: 1.8 Ω
-40°C to +125°C Operating Temperature
1.8 V Logic Compatible
•
•
•
•
•
•
•
•
•
•
•
Fail-Safe Logic
Rail to Rail Operation
Bidirectional Signal Path
Break-Before-Make Switching
ESD Protection HBM: 2000 V
The TMUX1109 is part of the precision switches and
multiplexers family of devices. These devices have
very low on and off leakage currents and low charge
injection, allowing them to be used in high precision
measurement applications. A low supply current of
8nA and small package options enable use in
portable applications.
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
Ultrasound Scanners
Patient Monitoring & Diagnostics
Optical Networking
Optical Test Equipment
Remote Radio Unit
Device Information(1)
Wired Networking
PART NUMBER
PACKAGE
TSSOP (16)
QFN (16)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
2.60 mm x 1.80 mm
ATE Test Equipment
TMUX1109
Factory Automation and Industrial Controls
Programmable Logic Controllers (PLC)
Analog Input Modules
(1) For all available packages, see the package option addendum
at the end of the data sheet.
SONAR Receivers
Motor Drive
Servo Drive Position Feedback
Application Example
Block Diagram
REFby2
TMUX1109
1µF
4 Channels per ADC
REFby2
(2.048V output)
S1A
S2A
S3A
S4A
Cf1 3pF
INN_x
Rg1 1kΩ
Rfil1 30.1Ω
SxA
Rf1 1kΩ
+5V
REFby2
2.048V
DA
Riso1
AINP_A
DA
15pF
15pF
10Ω
4:1
-
Cfil
150pF
Vocm
+
-
ADC_A
Differential
MUX
+
100nF
Riso2
10Ω
AINM_A
DB
Rfil2 30.1Ω
Rf2 1kΩ
SxB
S1B
S2B
S3B
S4B
INP_x
INN_x
Rg2 1kΩ
Cf2 3pF
ADS9224R
Dual,
Simultaneous-
Sampling
Low-Latency
SAR ADC
THS4551 (4x)
DB
TMUX1109
Cf1 3pF
Rg1 1kΩ
Rfil1 30.1Ω
SxA
Rf1 1kΩ
REFby2
2.048V
+5V
Riso1
10Ω
15pF
15pF
AINP_B
DA
4:1
-
1-OF-4
DECODER
Cfil
150pF
Vocm
+
-
Differential
MUX
ADC_B
+
100nF
Riso2
10Ω
DB
AINM_B
Rfil2 30.1Ω
Rf2 1kΩ
SxB
Rg2 1kΩ
Cf2 3pF
INP_x
THS4551 (4x)
A0
A1
EN
TMUX1109
4 Channels per ADC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX1109
SCDS406 –DECEMBER 2018
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 25
Application and Implementation ........................ 26
8.1 Application Information............................................ 26
8.2 Typical Application ................................................. 26
8.3 Design Requirements.............................................. 27
8.4 Detailed Design Procedure ..................................... 27
8.5 Application Curve.................................................... 28
Power Supply Recommendations...................... 28
1
2
3
4
5
6
Features.................................................................. 1
8
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics (VDD = 5 V ±10 %)............ 5
6.6 Electrical Characteristics (VDD = 3.3 V ±10 %)......... 7
9
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Example .................................................... 29
11 Device and Documentation Support ................. 30
11.1 Documentation Support ........................................ 30
11.2 Related Links ........................................................ 30
11.3 Receiving Notification of Documentation Updates 30
11.4 Community Resources.......................................... 30
11.5 Trademarks........................................................... 30
11.6 Electrostatic Discharge Caution............................ 30
11.7 Glossary................................................................ 30
6.7 Electrical Characteristics (VDD = 2.5 V ±10 %), (VSS
=
–2.5 V ±10 %) ............................................................ 9
6.8 Electrical Characteristics (VDD = 1.8 V ±10 %)....... 11
6.9 Electrical Characteristics (VDD = 1.2 V ±10 %)....... 13
6.10 Typical Characteristics.......................................... 15
Detailed Description ............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 23
7.3 Feature Description................................................. 23
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
December 2018
*
Initial release.
2
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SCDS406 –DECEMBER 2018
5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
RSV Package
16-Pin QFN
Top View
A0
EN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A1
GND
VDD
S1B
S2B
S3B
S4B
DB
VSS
S1A
S2A
S3A
S4A
DA
VSS
S1A
S2A
S3A
1
12
11
10
9
VDD
S1B
S2B
S3B
2
3
4
Not to scale
Not to scale
Pin Functions
PIN
TSSOP
1
TYPE(1)
DESCRIPTION
NAME
UQFN
A0
15
I
I
Address line 0. Controls the switch configuration as shown in Table 1.
Active high logic input. When this pin is low, all switches are turned off. When this pin is high,
the A[1:0] address inputs determine which switch is turned on.
EN
2
3
16
1
Negative power supply. This pin is the most negative power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
VSS can be connected to ground for single supply applications.
VSS
P
S1A
S2A
S3A
S4A
DA
4
5
2
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Source pin 1A. Can be an input or output.
Source pin 2A. Can be an input or output.
Source pin 3A. Can be an input or output.
Source pin 4A. Can be an input or output.
Drain pin A. Can be an input or output.
Drain pin B. Can be an input or output.
Source pin 4B. Can be an input or output.
Source pin 3B. Can be an input or output.
Source pin 2B. Can be an input or output.
Source pin 1B. Can be an input or output.
6
4
7
5
8
6
DB
9
7
S4B
S3B
S2B
S1B
10
11
12
13
8
9
10
11
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
14
12
P
GND
A1
15
16
13
14
P
I
Ground (0 V) reference
Address line 1. Controls the switch configuration as shown in Table 1.
(1) I = input, O = output, I/O = input and output, P = power
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SCDS406 –DECEMBER 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
(2) (3)
MIN
–0.5
–0.5
–3.0
–0.5
–30
MAX
UNIT
V
VDD–VSS
6
VDD
Supply voltage
6
0.3
V
VSS
V
VSEL or VEN
ISEL or IEN
VS or VD
IS or ID (CONT)
Tstg
Logic control input pin voltage (EN, A0, A1)
Logic control input pin current (EN, A0, A1)
Source or drain voltage (Sx, Dx)
Source or drain continuous current (Sx, Dx)
Storage temperature
6
V
30
mA
V
–0.5
–30
VDD+0.5
30
mA
°C
°C
–65
150
TJ
Junction temperature
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.08
-2.75
1.08
VSS
NOM
MAX
5.5
0
UNIT
VDD
VSS
Positive power supply voltage (single)
Negative power supply voltage (dual)
V
V
V
V
VDD - VSS Supply rail voltage difference
5.5
VDD
VS or VD
Signal path input/output voltage (source or drain pin) (Sx, Dx)
VSEL or
VEN
Logic control input pin voltage
Ambient temperature
0
5.5
V
TA
–40
125
°C
6.4 Thermal Information
TMUX1109
THERMAL METRIC(1)
PW (TSSOP)
16 PINS
118.9
49.3
RSV (QFN)
16 PINS
134.6
74.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
65.2
62.8
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7.6
4.3
ΨJB
64.6
61.1
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SCDS406 –DECEMBER 2018
6.5 Electrical Characteristics (VDD = 5 V ±10 %)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
1.8
4
4.5
4.9
Ω
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
0.18
0.85
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
On-resistance matching between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
0.4
0.5
Ω
Ω
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
RON
FLAT
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
1.6
1.6
Ω
Ω
VDD = 5 V
Switch Off
VD = 4.5 V / 1.5 V
VS = 1.5 V / 4.5 V
Refer to Off-Leakage Current
–0.08 ±0.005
–0.3
0.08
0.3
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
–40°C to +125°C
–0.9
0.9
nA
VDD = 5 V
Switch Off
VD = 4.5 V / 1.5 V
VS = 1.5 V / 4.5 V
Refer to Off-Leakage Current
25°C
–0.1
±0.01
0.1
nA
nA
–40°C to +85°C
–0.75
0.75
ID(OFF) Drain off leakage current(1)
–40°C to +125°C
–3.5
3.5
nA
VDD = 5 V
Switch On
VD = VS = 2.5 V
Refer to On-Leakage Current
25°C
–0.025 ±0.003
–0.3
0.025
0.3
nA
nA
ID(ON)
–40°C to +85°C
Channel on leakage current
IS(ON)
–40°C to +125°C
–0.75
0.75
nA
VDD = 5 V
Switch On
VD = VS = 4.5 V / 1.5 V
Refer to On-Leakage Current
25°C
–0.1
±0.01
0.1
nA
nA
ID(ON)
–40°C to +85°C
–0.75
0.75
Channel on leakage current
IS(ON)
–40°C to +125°C
–3
3
nA
LOGIC INPUTS (EN, A0, A1)
VIH
VIL
Input logic high
Input logic low
1.49
0
5.5
V
V
–40°C to +125°C
0.87
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.05
2
25°C
1
pF
pF
CIN
Logic input capacitance
–40°C to +125°C
POWER SUPPLY
IDD VDD supply current
25°C
0.008
µA
µA
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
1
(1) When VS is 4.5 V, VD is 1.5 V, and vice versa.
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SCDS406 –DECEMBER 2018
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Electrical Characteristics (VDD = 5 V ±10 %) (continued)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
14
ns
VS = 3 V
tTRAN
Transition time between channels RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
18
19
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Refer to Transition Time
8
12
6
VS = 3 V
tOPEN
(BBM)
Break before make time
RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
1
1
Refer to Break-Before-Make
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
tON(EN) Enable turn-on time
tOFF(EN) Enable turn-off time
–40°C to +85°C
–40°C to +125°C
25°C
19
20
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
–40°C to +85°C
–40°C to +125°C
8
9
VS = 1 V
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
25°C
25°C
25°C
–1
–65
–45
–90
pC
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
25°C
–80
135
dB
Refer to Crosstalk
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
BW
Bandwidth
MHz
CSOFF
CDOFF
Source off capacitance
Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
7.5
32
pF
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
38
pF
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6.6 Electrical Characteristics (VDD = 3.3 V ±10 %)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
4
8.75
9.5
Ω
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
9.75
Ω
0.13
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
On-resistance matching between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
0.4
0.5
Ω
Ω
1.9
2
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
RON
FLAT
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
Ω
2.2
Ω
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
–0.05 ±0.001
–0.1
0.05
0.1
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VS = 1 V / 3 V
Refer to Off-Leakage Current
–40°C to +125°C
–0.5
0.5
nA
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
25°C
–0.1 ±0.005
–0.5
0.1
0.5
nA
nA
–40°C to +85°C
ID(OFF) Drain off leakage current(1)
VS = 1 V / 3 V
Refer to Off-Leakage Current
–40°C to +125°C
–2
2
nA
VDD = 3.3 V
Switch On
VD = VS = 3 V / 1 V
Refer to On-Leakage Current
25°C
–0.1 ±0.005
–0.5
0.1
0.5
nA
nA
ID(ON)
–40°C to +85°C
Channel on leakage current
IS(ON)
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (EN, A0, A1)
VIH
VIL
Input logic high
Input logic low
1.35
0
5.5
0.8
V
V
–40°C to +125°C
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.05
2
25°C
1
pF
pF
CIN
Logic input capacitance
–40°C to +125°C
POWER SUPPLY
25°C
0.006
µA
µA
IDD
VDD supply current
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
1
(1) When VS is 3 V, VD is 1 V, and vice versa.
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Electrical Characteristics (VDD = 3.3 V ±10 %) (continued)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
15
ns
VS = 2 V
tTRAN
Transition time between channels RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
23
23
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Refer to Transition Time
9
14
7
VS = 2 V
tOPEN
(BBM)
Break before make time
RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
1
1
Refer to Break-Before-Make
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
tON(EN) Enable turn-on time
tOFF(EN) Enable turn-off time
–40°C to +85°C
–40°C to +125°C
25°C
25
25
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
–40°C to +85°C
–40°C to +125°C
12
12
VS = 1 V
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
25°C
25°C
25°C
–1
–65
–45
–90
pC
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
25°C
–80
135
dB
Refer to Crosstalk
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
BW
Bandwidth
MHz
CSOFF
CDOFF
Source off capacitance
Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
7
pF
pF
32
CSON
CDON
On capacitance
f = 1 MHz
25°C
38
pF
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6.7 Electrical Characteristics (VDD = 2.5 V ±10 %), (VSS = –2.5 V ±10 %)
at TA = 25°C, VDD = +2.5 V, VSS = –2.5 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
1.8
4
4.5
4.9
Ω
Ω
VS = VSS to VDD
ISD = 10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
0.18
0.85
Ω
VS = VSS to VDD
ISD = 10 mA
Refer to On-Resistance
On-resistance matching between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
0.4
0.5
Ω
Ω
Ω
VS = VSS to VDD
ISD = 10 mA
Refer to On-Resistance
RON
FLAT
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
1.6
1.6
Ω
Ω
VDD = +2.5 V, VSS = –2.5 V
Switch Off
VD = +2 V / –1 V
–0.08 ±0.005
–0.3
0.08
0.3
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VS = –1 V / +2 V
Refer to Off-Leakage Current
–40°C to +125°C
–0.9
0.9
nA
VDD = +2.5 V, VSS = –2.5 V
Switch Off
VD = +2 V / –1 V
VS = –1 V / +2 V
Refer to Off-Leakage Current
25°C
–0.1
±0.01
±0.01
0.1
nA
nA
–40°C to +85°C
–0.75
0.75
ID(OFF) Drain off leakage current(1)
–40°C to +125°C
–3.5
3.5
nA
VDD = +2.5 V, VSS = –2.5 V
Switch On
VD = VS = +2 V / –1 V
Refer to On-Leakage Current
25°C
–0.1
0.1
nA
nA
ID(ON)
–40°C to +85°C
–0.75
0.75
Channel on leakage current
IS(ON)
–40°C to +125°C
–3
3
nA
LOGIC INPUTS (EN, A0, A1)
VIH
VIL
Input logic high
Input logic low
1.2
0
2.75
0.73
V
V
–40°C to +125°C
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
1
µA
µA
IIH
IIL
–40°C to +125°C
±0.05
2
25°C
pF
pF
CIN
Logic input capacitance
–40°C to +125°C
POWER SUPPLY
IDD VDD supply current
25°C
0.008
0.008
µA
µA
µA
µA
Logic inputs = 0 V or 2.75 V
Logic inputs = 0 V or 2.75 V
–40°C to +125°C
25°C
1
1
ISS
VSS supply current
–40°C to +125°C
(1) When VS is positive, VD is negative, and vice versa.
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Electrical Characteristics (VDD = 2.5 V ±10 %), (VSS = –2.5 V ±10 %) (continued)
at TA = 25°C, VDD = +2.5 V, VSS = –2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
14
ns
VS = 1.5 V
tTRAN
Transition time between channels RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
21
21
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Refer to Transition Time
8
14
8
VS = 1.5 V
tOPEN
(BBM)
Break before make time
RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
1
1
Refer to Break-Before-Make
VS = 1.5 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
tON(EN) Enable turn-on time
tOFF(EN) Enable turn-off time
–40°C to +85°C
–40°C to +125°C
25°C
21
22
VS = 1.5 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
–40°C to +85°C
–40°C to +125°C
11
12
VS = –1 V
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
25°C
25°C
25°C
–1
–65
–45
–90
pC
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
25°C
–80
135
dB
Refer to Crosstalk
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
BW
Bandwidth
MHz
CSOFF
CDOFF
Source off capacitance
Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
7
pF
pF
32
CSON
CDON
On capacitance
f = 1 MHz
25°C
38
pF
10
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6.8 Electrical Characteristics (VDD = 1.8 V ±10 %)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
40
Ω
VS = 0 V to VDD
RON
On-resistance
ISD = 10 mA
Refer to On-Resistance
–40°C to +85°C
–40°C to +125°C
25°C
80
80
Ω
Ω
0.4
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
On-resistance matching between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
1.5
1.5
Ω
Ω
VDD = 1.98 V
Switch Off
VD = 1.62 V / 1 V
VS = 1 V / 1.62 V
Refer to Off-Leakage Current
–0.05 ±0.003
–0.1
0.05
0.1
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
–40°C to +125°C
–0.5
0.5
nA
VDD = 1.98 V
Switch Off
VD = 1.62 V / 1 V
VS = 1 V / 1.62 V
Refer to Off-Leakage Current
25°C
–0.1 ±0.005
–0.5
0.1
0.5
nA
nA
–40°C to +85°C
ID(OFF) Drain off leakage current(1)
–40°C to +125°C
–2
2
nA
VDD = 1.98 V
Switch On
VD = VS = 1.62 V / 1 V
Refer to On-Leakage Current
25°C
–0.1 ±0.005
–0.5
0.1
0.5
nA
nA
ID(ON)
–40°C to +85°C
Channel on leakage current
IS(ON)
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (EN, A0, A1)
VIH
VIL
Input logic high
Input logic low
1.07
0
5.5
V
V
–40°C to +125°C
0.68
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.05
2
25°C
1
pF
pF
CIN
Logic input capacitance
–40°C to +125°C
POWER SUPPLY
IDD VDD supply current
25°C
0.001
µA
µA
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
0.85
(1) When VS is 1.62 V, VD is 1 V, and vice versa.
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Electrical Characteristics (VDD = 1.8 V ±10 %) (continued)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
28
ns
VS = 1 V
tTRAN
Transition time between channels RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
48
48
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Refer to Transition Time
16
28
16
VS = 1 V
tOPEN
(BBM)
Break before make time
RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
1
1
Refer to Break-Before-Make
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
tON(EN) Enable turn-on time
tOFF(EN) Enable turn-off time
–40°C to +85°C
–40°C to +125°C
25°C
48
48
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
–40°C to +85°C
–40°C to +125°C
27
27
VS = 1 V
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
25°C
25°C
25°C
–0.5
–65
–45
–90
pC
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
25°C
–80
135
dB
Refer to Crosstalk
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
BW
Bandwidth
MHz
CSOFF
CDOFF
Source off capacitance
Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
7
pF
pF
32
CSON
CDON
On capacitance
f = 1 MHz
25°C
38
pF
12
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SCDS406 –DECEMBER 2018
6.9 Electrical Characteristics (VDD = 1.2 V ±10 %)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
70
Ω
VS = 0 V to VDD
RON
On-resistance
ISD = 10 mA
Refer to On-Resistance
–40°C to +85°C
–40°C to +125°C
25°C
105
105
Ω
Ω
0.4
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
On-resistance matching between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
1.5
1.5
Ω
Ω
VDD = 1.32 V
Switch Off
VD = 1 V / 0.8 V
VS = 0.8 V / 1 V
Refer to Off-Leakage Current
–0.05 ±0.003
–0.1
0.05
0.1
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
–40°C to +125°C
–0.5
0.5
nA
VDD = 1.32 V
Switch Off
VD = 1 V / 0.8 V
VS = 0.8 V / 1 V
Refer to Off-Leakage Current
25°C
–0.1 ±0.005
–0.5
0.1
0.5
nA
nA
–40°C to +85°C
ID(OFF) Drain off leakage current(1)
–40°C to +125°C
–2
2
nA
VDD = 1.32 V
Switch On
VD = VS = 1 V / 0.8 V
Refer to On-Leakage Current
25°C
–0.1 ±0.005
–0.5
0.1
0.5
nA
nA
ID(ON)
–40°C to +85°C
Channel on leakage current
IS(ON)
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (EN, A0, A1)
VIH
VIL
Input logic high
Input logic low
0.96
0
5.5
V
V
–40°C to +125°C
0.36
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.05
2
25°C
1
pF
pF
CIN
Logic input capacitance
–40°C to +125°C
POWER SUPPLY
IDD VDD supply current
25°C
0.001
µA
µA
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
0.7
(1) When VS is 1 V, VD is 0.8 V, and vice versa.
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Electrical Characteristics (VDD = 1.2 V ±10 %) (continued)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
60
ns
VS = 1 V
tTRAN
Transition time between channels RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
210
210
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Refer to Transition Time
28
60
45
VS = 1 V
tOPEN
(BBM)
Break before make time
RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
1
1
Refer to Break-Before-Make
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
tON(EN) Enable turn-on time
tOFF(EN) Enable turn-off time
–40°C to +85°C
–40°C to +125°C
25°C
190
190
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
–40°C to +85°C
–40°C to +125°C
150
150
VS = 1 V
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
25°C
25°C
25°C
–0.5
–65
–45
–90
pC
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
25°C
–80
135
dB
Refer to Crosstalk
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
BW
Bandwidth
MHz
CSOFF
CDOFF
Source off capacitance
Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
7
pF
pF
32
CSON
CDON
On capacitance
f = 1 MHz
25°C
38
pF
14
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6.10 Typical Characteristics
at TA = 25°C, VDD = 5 V (unless otherwise noted)
6
5
4.5
4
VDD = 3 V
5
TA = 85èC
TA = 125èC
3.5
3
VDD = 3.63 V
4
VDD = 4.5 V
3
2.5
2
VDD = 5.5 V
2
1
0
1.5
1
TA = 25èC
TA = -40èC
0.5
0
0
1
2
3
4
5
5.5
0
1
2
3
4
5
Source or Drain Voltage (V)
Source or Drain Voltage (V)
D001
D002
TA = 25°C
VDD = 5 V
Figure 1. On-Resistance vs Source or Drain Voltage
Figure 2. On-Resistance vs Temperature
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
TA = 85èC
TA = 125èC
VDD = 2.25V
VSS = -2.25V
VDD = 2.75 V
VSS = -2.75 V
TA = 25èC
TA = -40èC
1.5
-3
-2
-1
0
1
2
3
0
0.5
1
2
2.5
3
3.5
Source or Drain Voltage (V)
Source or Drain Voltage (V)
D003
D004
TA = 25°C
VDD = 3.3 V
Figure 3. On-Resistance vs Source or Drain Voltage
Figure 4. On-Resistance vs Temperature
40
30
80
70
60
50
40
30
20
10
0
VDD = 1.08 V
20
VDD = 1.98 V
VDD = 1.32 V
VDD = 3.63 V
VDD = 1.32 V
10
0
VDD = 1.62 V
-10
-20
-30
-40
VDD = 1.98 V
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.5
1
1.5
2
2.5
3
3.5
4
Source or Drain Voltage (V)
Source or Drain Voltage (V)
D005
D006
TA = 25°C
TA = 25°C
Figure 5. On-Resistance vs Source or Drain Voltage
Figure 6. On-Leakage vs Source or Drain Voltage
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Typical Characteristics (continued)
400
1
0.75
0.5
300
VDD = 2.5 V
VSS = -2.5 V
200
100
0
VDD = 5 V
VSS = 0 V
IS(OFF)
0.25
0
-100
-200
-300
-400
-0.25
-0.5
-0.75
-1
ID(OFF)
I(ON)
-3
-2
-1
0
1
2
3
4
5
-40
-20
0
20
40
60
80
100
120
Source or Drain Voltage (V)
Temperature (èC)
D007
D008
TA = 25°C
VDD = 3.3 V
Figure 7. On-Leakage vs Source or Drain Voltage
Figure 8. Leakage Current vs Temperature
3.5
2.5
0.4
0.3
0.2
0.1
0
VDD = 5.5 V
1.5
IS(OFF)
VDD = 3.63 V
0.5
-0.5
-1.5
-2.5
-3.5
VDD = 1.8 V
ID(OFF)
ID(ON)
VDD = 1.2 V
-0.1
-40
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D009
Temperature (èC)
D010
VDD = 5 V
VSEL = 5.5 V
Figure 9. Leakage Current vs Temperature
Figure 10. Supply Current vs Temperature
1400
1200
1000
800
600
400
200
0
20
15
10
5
VDD = 3.3 V
VSS = 0 V
VDD = 5 V
VSS = 0 V
0
-5
VDD = 3.3 V
VDD = 5 V
VDD = 2.5 V
VSS = -2.5 V
-10
-15
-20
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-3
-2
-1
0
1
2
3
4
5
Logic Voltage (V)
Source Voltage (V)
D011
D012
TA = 25°C
TA = -40°C to 125°C
Figure 11. Supply Current vs Logic Voltage
Figure 12. Charge Injection vs Source or Drain Voltage
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Typical Characteristics (continued)
5
30
27
24
21
18
15
12
9
3
VDD = 1.2 V
1
TON
-1
VDD = 1.8 V
-3
TOFF
6
-5
3
0
0.5
1
1.5
2
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Source Voltage (V)
Supply Voltage (V)
D013
D014
TA = 25°C
TA = 25°C
Figure 13. Charge Injection vs Source or Drain Voltage
Figure 14. TON (EN) and TOFF (EN) vs Supply Voltage
20
30
25
20
15
10
5
16
12
8
TON
TTRANSITION_FALLING
TOFF
4
TTRANSITION_RISING
0
0
-60
-30
0
30
60
90
120
150
0.5
1.5
2.5
3.5
4.5
5.5
Temperature (èC)
Supply Voltage (V)
D015
D016
VDD = 5 V
TA = 25°C
Figure 15. TON (EN) and TOFF (EN) vs Temperature
Figure 16. TTRANSITION vs Supply Voltage
0
-1
-2
-3
-4
-5
-6
1M
10M
100M
Frequency (Hz)
D018
TA = 25°C
Figure 17. Frequency Response
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7 Detailed Description
7.1 Overview
7.1.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance.
The measurement setup used to measure RON is shown in Figure 18. Voltage (V) and current (ISD) are measured
using this setup, and RON is computed with RON = V / ISD
:
V
ISD
Sx
D
VS
Figure 18. On-Resistance Measurement Setup
7.1.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF)
.
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF)
.
The setup used to measure both off-leakage currents is shown in Figure 19.
VDD
VSS
VDD
VSS
S1A
S4A
S1A
S2A
S3A
S4A
ID (OFF)
DA
DA
A
A
VD
VD
Is (OFF)
VS
VS
Is (OFF)
S1B
S2B
S3B
S4B
S1B
S4B
ID (OFF)
A
DB
DB
A
VS
VD
VD
GND
GND
VS
Figure 19. Off-Leakage Measurement Setup
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Overview (continued)
7.1.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON)
.
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON)
.
Either the source pin or drain pin is left floating during the measurement. Figure 20 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON)
.
VDD
VSS
VDD
VSS
IS (ON)
ID (ON)
S1A
S2A
S3A
S4A
S1A
S2A
S3A
S4A
N.C.
A
DA
DA
N.C.
A
VS
VD
VS
VS
IS (ON)
ID (ON)
S1B
S2B
S3B
S4B
S1B
S2B
S3B
S4B
A
N.C.
DB
DB
N.C.
A
VS
VD
GND
GND
VS
VS
Figure 20. On-Leakage Measurement Setup
7.1.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the address signal
has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of
the device, system level timing can then account for the time constant added from the load resistance and load
capacitance. Figure 21 shows the setup used to measure transition time, denoted by the symbol tTRANSITION
.
VDD
VSS
0.1…F
0.1…F
VDD
VSS
VDD
ADDRESS
DRIVE
S1A
S2A
S3A
S4A
tf < 5ns
tr < 5ns
VS
VIH
OUTPUT
DA
DB
(VSEL
)
VIL
0 V
CL
RL
S1B
S2B
S3B
S4B
VS
tTRANSITION
tTRANSITION
OUTPUT
RL
CL
90%
OUTPUT
A0
A1
VSEL
10%
GND
0 V
Figure 21. Transition-Time Measurement Setup
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Overview (continued)
7.1.5 Break-Before-Make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. Figure 22 shows
the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM)
.
VDD
VSS
0.1…F
0.1…F
VSS
VDD
VDD
S1A
S2A
S3A
S4A
VS
ADDRESS
DRIVE
OUTPUT
DA
DB
tr < 5ns
tf < 5ns
(VSEL
)
CL
RL
0 V
S1B
S2B
S3B
S4B
VS
OUTPUT
RL
90%
Output
CL
tBBM
1
tBBM 2
0 V
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
A0
A1
VSEL
GND
Figure 22. Break-Before-Make Delay Measurement Setup
7.1.6 tON(EN) and tOFF(EN)
Turn-on time is defined as the time taken by the output of the device to rise to 10% after the enable has risen
past the logic threshold. The 10% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. Figure 23 shows
the setup used to measure turn-on time, denoted by the symbol tON(EN)
.
Turn-off time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen
past the logic threshold. The 90% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. Figure 23 shows
the setup used to measure turn-off time, denoted by the symbol tOFF(EN)
.
VDD
VSS
0.1…F
0.1…F
VDD
tf < 5ns
tr < 5ns
VSS
VDD
ENABLE
DRIVE
S1A
S2A
S3A
S4A
VIH
VS
(VEN
)
OUTPUT
DA
DB
VIL
CL
RL
0 V
S1B
S2B
S3B
S4B
VS
OUTPUT
RL
tOFF (EN)
tON
(EN)
CL
90%
EN
OUTPUT
0 V
VEN
GND
10%
Figure 23. Turn-On and Turn-Off Time Measurement Setup
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Overview (continued)
7.1.7 Charge Injection
The TMUX1109 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS
transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.
The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted
by the symbol QC. Figure 24 shows the setup used to measure charge injection from source (Sx) to drain (D).
VDD
VSS
0.1…F
0.1…F
VSS
VDD
S1A
S2A
S3A
S4A
VS
VDD
VEN
OUTPUT
CL
DA
DB
VOUT
0 V
S1B
S2B
S3B
S4B
VS
OUTPUT
Output
VOUT
VOUT
CL
VS
QC = CL
×
VOUT
EN
VEN
GND
Figure 24. Charge-Injection Measurement Setup
7.1.8 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. Figure 25 shows the setup used to measure and the equation used to compute
off isolation.
VDD
VSS
0.1µF
0.1µF
NETWORK
ANALYZER
VSS
VDD
VS
50Q
S
VSIG
D
VOUT
RL
50Q
SX/DX
GND
RL
50Q
Figure 25. Off Isolation Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Off Isolation = 20 ∂ Log
(1)
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Overview (continued)
7.1.9 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. Figure 26 shows the setup used to measure, and the equation used to
compute crosstalk.
VDD
VSS
0.1µF
0.1µF
NETWORK
ANALYZER
VSS
VDD
DA
S1A
VOUT
RL
RL
50Q
50Q
VS
DB
S1B
RL
50Q
50Q
SXA / SX
B
VSIG
RL
50Q
GND
Figure 26. Crosstalk Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Channel-to-Channel Crosstalk = 20 ∂ Log
(2)
7.1.10 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. Figure 27
shows the setup used to measure bandwidth.
VDD
VSS
0.1µF
0.1µF
NETWORK
ANALYZER
VSS
VDD
VS
S
50Q
VSIG
D
VOUT
RL
50Q
GND
Figure 27. Bandwidth Measurement Setup
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7.2 Functional Block Diagram
The TMUX1109 is an 4:1, differential (2-channel), multiplexer. Each switch is turned on or off based on the state
of the address lines and enable pin.
TMUX1109
S1A
S2A
S3A
DA
S4A
S1B
S2B
S3B
DB
S4B
1-OF-4
DECODER
A0
A1
EN
Figure 28. TMUX1109 Functional Block Diagram
7.3 Feature Description
7.3.1 Bidirectional Operation
The TMUX1109 conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each
channel has very similar characteristics in both directions and supports both analog and digital signals.
7.3.2 Rail to Rail Operation
The valid signal path input/output voltage for TMUX1109 ranges from VSS to VDD
.
7.3.3 1.8 V Logic Compatible Inputs
The TMUX1109 has 1.8-V logic compatible control for all logic control inputs. The logic input thresholds scale
with supply but still provide 1.8-V logic control when operating at 5.5 V supply voltage. 1.8-V logic level inputs
allows the TMUX1109 to interface with processors that have lower logic I/O rails and eliminates the need for an
external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations
refer to Simplifying Design with 1.8 V logic Muxes and Switches
7.3.4 Fail-Safe Logic
The TMUX1109 supports Fail-Safe Logic on the control input pins (EN, A0, A1) allowing for operation up to 5.5 V
above VSS, regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied
before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity
by removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic
feature allows the select pins of the TMUX1109 to be ramped to 5.5 V while VDD = 0 V. Additionally, the feature
enables operation of the TMUX1109 with VDD = 1.2 V while allowing the select pins to interface with a logic level
of another device up to 5.5 V.
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Feature Description (continued)
7.3.5 Ultra-low Leakage Current
The TMUX1109 provides extremely low on-leakage and off-leakage currents. The TMUX1109 is capable of
switching signals from high source-impedance inputs into a high input-impedance op amp with minimal offset
error because of the ultralow leakage currents. Figure 29 shows typical leakage currents of the TMUX1109
versus temperature.
3.5
2.5
1.5
IS(OFF)
0.5
-0.5
ID(OFF)
ID(ON)
-1.5
-2.5
-3.5
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
D009
Figure 29. Leakage Current vs Temperature
7.3.6 Ultra-low Charge Injection
The TMUX1109 has a transmission gate topology, as shown in Figure 30. Any mismatch in the stray capacitance
associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.
OFF ON
CGDN
CGSN
D
S
CGSP
CGDP
OFF ON
Figure 30. Transmission Gate Topology
The TMUX1109 has special charge-injection cancellation circuitry that reduces the source-to-drain charge
injection to as low as 1 pC at VS = 1 V as shown in Figure 31.
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Feature Description (continued)
20
15
10
5
VDD = 3.3 V
VSS = 0 V
VDD = 5 V
SS = 0 V
V
0
-5
VDD = 2.5 V
VSS = -2.5 V
-10
-15
-20
-3
-2
-1
0
1
2
3
4
5
Source Voltage (V)
D012
Figure 31. Charge Injection vs Source Voltage
7.4 Device Functional Modes
When the EN pin of the TMUX1109 is pulled high, one of the switches is closed based on the state of the
address lines. When the EN pin is pulled low, all the switches are in an open state regardless of the state of the
address lines.
7.4.1 Truth Tables
Table 1. TMUX1109 Truth Table
EN A1 A0 Selected Input Connected To Drain (DA, DB) Pins
0
1
1
1
1
X(1) X(1)
All channels are off
S1A and S1B
S2A and S2B
S3A and S3B
S4A and S4B
0
0
1
1
0
1
0
1
(1) X denotes don't care.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TMUX11xx family offers ulta-low input/output leakage currents and low charge injection. These devices
operate up to 5.5 V, and offer true rail-to-rail input and output. The TMUX1109 has a low on-capacitance which
allows faster settling time when multiplexing inputs in the time domain. These features make the TMUX11xx
devices a family of precision, robust, high-performance analog multiplexer for low-voltage applications.
8.2 Typical Application
Figure 32 shows a 16-bit, simultaneous-sampling data-acquisition system. This example is typical in industrial
applications that require sampling simultaneous signals such as Optical Modules, Analog Input Modules, and
Motor Drive circuits for position feedback. The circuit uses eight Fully Differential Amplifiers (FDAs), a 16-bit, 3-
MSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along with a two differential
precision multiplexers. Refer to True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC
Circuit for more information.
REFby2
1µF
4 Channels per ADC
REFby2
(2.048V output)
Cf1 3pF
INN_x
Rg1 1kΩ
Rfil1 30.1Ω
SxA
Rf1 1kΩ
REFby2
2.048V
+5V
Riso1
10Ω
AINP_A
DA
15pF
15pF
4:1
-
Cfil
150pF
Vocm
+
-
ADC_A
Differential
MUX
+
Riso2
10Ω
100nF
AINM_A
DB
Rfil2 30.1Ω
Rf2 1kΩ
SxB
INP_x
INN_x
Rg2 1kΩ
Cf2 3pF
ADS9224R
Dual,
Simultaneous-
Sampling
Low-Latency
SAR ADC
THS4551 (4x)
TMUX1109
Cf1 3pF
Rg1 1kΩ
Rfil1 30.1Ω
SxA
Rf1 1kΩ
REFby2
2.048V
+5V
Riso1
10Ω
15pF
15pF
AINP_B
DA
4:1
-
Cfil
150pF
Vocm
+
-
ADC_B
Differential
MUX
+
Riso2
10Ω
100nF
DB
AINM_B
Rfil2 30.1Ω
Rf2 1kΩ
SxB
Rg2 1kΩ
INP_x
Cf2 3pF
THS4551 (4x)
TMUX1109
4 Channels per ADC
Figure 32. Simultaneous-Sampling ADC Circuit
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8.3 Design Requirements
For this design example, use the parameters listed in Table 2.
Table 2. Design Parameters
PARAMETERS
VALUES
5 V
Supply (VDD
)
Vref
4.096 V
Vocm
2.048 V
Max Differential Voltage
Control logic thresholds
3.636 V
1.8 V compatible
8.4 Detailed Design Procedure
The TMUX1109 can be operated without any external components except for the supply decoupling capacitors. If
the device desired power-up state is disabled, the enable pin should have a weak pull-down resistor and be
controlled by the MCU via GPIO. All inputs being muxed to the ADC must fall within the recommend operating
conditions of the TMUX1109 including signal range and continuous current. System level design and component
selection are made according to True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC
Circuit.
1. The ADS9224R was selected because of the dual simultaneous sampling and high throughput (3-MSPS).
2. The TMUX1109 4:1 (2x) multiplexer was selected to support 4 differential inputs for each ADC.
3. Find ADC full-scale range, resolution and common-mode range specifications.
4. Determine the linear range of the FDA (THS4551) based on common-mode and output swing specification.
5. Select COG capacitors for all filter capacitors at the ADC input to minimize distortion.
6. Select the FDA gain resistors RF1,2 , RG1,2. Use 0.1% 20ppm/°C film resistors or better for good accuracy,
low gain drift and to minimize distortion.
7. Introduction to SAR ADC Front-End Component Selection covers the methods for selecting the charge
bucket circuit Rfil1, Rfil1 and Cfil. These component values are dependent on the amplifier bandwidth, data
converter sampling rare, and data converter design. The values shown here will give good settling and AC
performance for the amplifier and data converter in this example. If the design is modified, a different RC
filter must be selected.
8. The THS4551 is commonly used in high-speed precision fully differential SAR applications as it has sufficient
bandwidth to settle to charge kickback transients from the ADC input sampling, and multiplexer charge
injection and provides the common-mode level shifting to the voltage range of the SAR ADC.
9. The TMUX1109 is used in high-speed precision fully differential SAR applications as it has sufficient
bandwidth, low charge injection, and low on-resistance and capacitance. Low capacitance supports fast
switching between channels and allows the system to settle within required precision in the specified timing.
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8.5 Application Curve
Charge injection impacts system performance and settling characteristics of the charge bucket circuit. A
multiplexer with low charge injection and a flat response across input voltage allows the system to settle to the
required precision during the ADC acquisition period. Figure 33 shows the flat charge injection of the TMUX1109
at multiple supply voltages.
20
15
10
5
VDD = 3.3 V
VSS = 0 V
VDD = 5 V
SS = 0 V
V
0
-5
VDD = 2.5 V
VSS = -2.5 V
-10
-15
-20
-3
-2
-1
0
1
2
3
4
5
Source Voltage (V)
D012
TA = 25°C
Figure 33. Charge Injection vs Source Voltage
9 Power Supply Recommendations
The TMUX1109 operates across a wide supply range of 1.08 V to 5.5 V, or ±2.5 V. Do not exceed the absolute
maximum ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD and
SS
supplies to other components. Good power-supply decoupling is important to achieve optimum performance. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD and
VSS to ground. Place the bypass capacitors as close to the power supply pins of the device as possible using
low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low
equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes.
For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting
the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers
the overall inductance and is beneficial for connections to ground planes.
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10 Layout
10.1 Layout Guidelines
10.1.1 Layout Information
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners.Figure 34 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
1W min.
W
Figure 34. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, through-
hole pins are not recommended at high frequencies.
Figure 35 illustrates an example of a PCB layout with the TMUX1109. Some key considerations are:
•
Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
•
•
•
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
10.2 Layout Example
Via to GND plane
A1
A0
C
C
Wide (low inductance)
trace for power
Wide (low inductance)
trace for power
GND
VDD
S1B
S2B
EN
VSS
S1A
S2A
TMUX1109
S3B
S4B
DB
S3A
S4A
DA
Figure 35. TMUX1109 Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit.
Texas Instruments, Improve Stability Issues with Low CON Multiplexers.
Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.
Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches.
Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers.
Texas Instruments, QFN/SON PCB Attachment.
Texas Instruments, Quad Flatpack No-Lead Logic Packages.
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX1109PWR
TMUX1109RSVR
ACTIVE
ACTIVE
TSSOP
UQFN
PW
16
16
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
TM1109
1D1
RSV
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX1109PWR
TMUX1109RSVR
TSSOP
UQFN
PW
16
16
2000
3000
330.0
178.0
12.4
13.5
6.9
2.1
5.6
2.9
1.6
8.0
4.0
12.0
12.0
Q1
Q1
RSV
0.75
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMUX1109PWR
TMUX1109RSVR
TSSOP
UQFN
PW
16
16
2000
3000
356.0
189.0
356.0
185.0
35.0
36.0
RSV
Pack Materials-Page 2
PACKAGE OUTLINE
RSV0016A
UQFN - 0.55 mm max height
S
C
A
L
E
5
.
0
0
0
ULTRA THIN QUAD FLATPACK - NO LEAD
1.85
1.75
A
B
PIN 1 INDEX AREA
2.65
2.55
C
0.55
0.45
SEATING PLANE
0.05 C
0.05
0.00
2X 1.2
SYMM
℄
(0.13) TYP
5
8
0.45
0.35
15X
4
9
SYMM
℄
2X 1.2
12X 0.4
1
0.25
16X
12
0.15
0.07
0.05
C A B
13
16
0.55
0.45
PIN 1 ID
(45° X 0.1)
4220314/C 02/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
SYMM
℄
(0.7)
16
SEE SOLDER MASK
DETAIL
13
12
16X (0.2)
1
SYMM
℄
12X (0.4)
(2.4)
(R0.05) TYP
9
4
15X (0.6)
5
8
(1.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220314/C 02/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
(0.7)
16
13
16X (0.2)
1
12
SYMM
℄
12X (0.4)
(2.4)
(R0.05) TYP
4
9
15X (0.6)
5
8
SYMM
℄
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 25X
4220314/C 02/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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