TMUX1113PWR [TI]
3pA、5V、1:1 (SPST)、4 通道精密开关（2 个低电平有效，2 个高电平有效） | PW | 16 | -40 to 125;
| 型号： | TMUX1113PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3pA、5V、1:1 (SPST)、4 通道精密开关（2 个低电平有效，2 个高电平有效） | PW | 16 | -40 to 125 开关 |
| 文件： | 总42页 (文件大小：1315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TMUX1111, TMUX1112, TMUX1113
ZHCSJE1B –FEBRUARY 2019–REVISED AUGUST 2019
TMUX111x 5V、低泄漏电流、1:1 (SPST)、4 通道精密开关
1 特性
3 说明
1
•
宽电源电压范围：1.08V 至 5.5V
低泄漏电流：3pA
TMUX1111、TMUX1112 和 TMUX1113 是精密互补
金属氧化物半导体 (CMOS) 器件，具有四个独立的可
选 1:1、单极单投 (SPST) 开关。1.08V 至 5.5V 的宽
电源电压工作范围 可支持 医疗设备到工业系统的大量
应用。该器件可在源极 (Sx) 和漏极 (Dx) 引脚上支持从
GND 到 VDD 范围的双向模拟和数字信号。
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低电荷注入：-1.5pC
低导通电阻：2Ω
-40°C 至 +125°C 工作温度
1.8V 逻辑兼容
失效防护逻辑
TMUX1111 的开关可通过逻辑 0 在恰当的逻辑控制输
入下打开，而要打开 TMUX1112 中的开关，则需逻辑
1。TMUX1113 的四个通道通过两个支持逻辑 0 的开
关分开，而另外两个开关则支持逻辑 1。TMUX1113
具有先断后合开关，因此该器件可用于交叉点开关 应
用。
轨至轨运行
双向信号路径
先断后合开关
ESD 保护 HBM：2000V
2 应用
TMUX111x 器件是精密开关和多路复用器器件系列中
的一部分。这些器件具有非常低的导通和关断泄漏电流
以及较低的电荷注入，因此可用于高精度测量 应用。
8nA 的低电源电流和小型封装选项使其可用于便携式
应用标准。
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采样保持电路
反馈增益开关
信号隔离
现场变送器
可编程逻辑控制器 (PLC)
工厂自动化和控制
超声波扫描仪
器件信息(1)
器件型号
TMUX1111
封装
封装尺寸（标称值）
患者监护和诊断
心电图 (ECG)
TSSOP (16) (PW)
5.00mm × 4.40mm
TMUX1112
TMUX1113
UQFN (16) (RSV)
2.60mm x 1.80mm
数据采集系统 (DAQ)
ATE 测试设备
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
电池测试设备
仪表：实验室、分析、便携
智能仪表：水表和燃气表
光纤网络
光学测试设备
TMUX111x 方框图
CHANNEL 1
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
S1
D1
D2
D3
D4
S1
S2
S3
S4
D1
D2
D3
D4
S1
S2
S3
S4
D1
D2
D3
D4
CHANNEL 2
S2
CHANNEL 3
S3
CHANNEL 4
S4
SEL1
SEL1
SEL2
SEL3
SEL4
SEL1
SEL2
SEL3
SEL4
SEL2
SEL3
SEL4
TMUX1111
TMUX1112
ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT
TMUX1113
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS408
TMUX1111, TMUX1112, TMUX1113
ZHCSJE1B –FEBRUARY 2019–REVISED AUGUST 2019
www.ti.com.cn
目录
9.1 Overview ................................................................. 21
9.2 Functional Block Diagram ....................................... 21
9.3 Feature Description................................................. 21
9.4 Device Functional Modes........................................ 23
9.5 Truth Tables............................................................ 23
10 Application and Implementation........................ 24
10.1 Application Information.......................................... 24
10.2 Typical Application - Sample-and-Hold Circuit .... 24
10.3 Design Requirements............................................ 25
10.4 Detailed Design Procedure ................................... 25
10.5 Application Curve.................................................. 26
10.6 Typical Application - Switched Gain Amplifier ..... 26
10.7 Design Requirements............................................ 27
10.8 Detailed Design Procedure ................................... 27
10.9 Application Curve.................................................. 27
11 Power Supply Recommendations ..................... 28
12 Layout................................................................... 28
12.1 Layout Guidelines ................................................. 28
12.2 Layout Example .................................................... 29
13 器件和文档支持 ..................................................... 30
13.1 文档支持................................................................ 30
13.2 相关链接................................................................ 30
13.3 接收文档更新通知 ................................................. 30
13.4 社区资源................................................................ 30
13.5 商标....................................................................... 30
13.6 静电放电警告......................................................... 30
13.7 Glossary................................................................ 30
14 机械、封装和可订购信息....................................... 31
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics (VDD = 5 V ±10 %)............ 5
7.6 Electrical Characteristics (VDD = 3.3 V ±10 %)......... 7
7.7 Electrical Characteristics (VDD = 1.8 V ±10 %)......... 9
7.8 Electrical Characteristics (VDD = 1.2 V ±10 %)....... 11
7.9 Typical Characteristics............................................ 13
Parameter Measurement Information ................ 16
8.1 On-resistance.......................................................... 16
8.2 Off-leakage current ................................................. 16
8.3 On-leakage current ................................................. 17
8.4 Transition time......................................................... 17
8.5 Break-before-make ................................................. 18
8.6 Charge injection ...................................................... 18
8.7 Off isolation ............................................................. 19
8.8 Channel-to-Channel Crosstalk................................ 19
8.9 Bandwidth ............................................................... 20
Detailed Description ............................................ 21
8
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (June 2019) to Revision B
Page
•
•
•
•
从器件信息 表中的 TMUX1113、TMUX1112 和 RSV 封装中删除了产品预览 说明 .............................................................. 1
Deleted the Product Preview note from: TMUX1113, TMUX1112 in the Device Comparison Table table............................ 3
Deleted the Product Preview note from:the RSV package in the Pin Configuration and Functions secton .......................... 3
Added RSV (UQFN) thermal values to Thermal Information ................................................................................................. 4
Changes from Original (February 2019) to Revision A
Page
•
将文档从预告信息 更改为混合状态。 ..................................................................................................................................... 1
2
Copyright © 2019, Texas Instruments Incorporated
TMUX1111, TMUX1112, TMUX1113
www.ti.com.cn
ZHCSJE1B –FEBRUARY 2019–REVISED AUGUST 2019
5 Device Comparison Table
PRODUCT
DESCRIPTION
TMUX1111
TMUX1112
TMUX1113
Low-Leakage-Current, Precision, 4-Channel, 1:1 (SPST) Switches (Normally Closed)
Low-Leakage-Current, Precision, 4-Channel, 1:1 (SPST) Switches (Normally Open)
Low-Leakage-Current, Precision, 4-Channel, 1:1 (SPST) Switches (Dual Open + Dual Closed)
6 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
RSV Package
16-Pin UQFN
Top View
SEL1
D1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL2
D2
S1
S2
S1
N.C.
GND
S4
1
12
11
10
9
S2
N.C.
GND
S4
VDD
N.C.
S3
2
3
4
VDD
N.C.
S3
D4
D3
SEL4
SEL3
Not to scale
Not to scale
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
SEL1
D1
TSSOP
UQFN
1
2
15
16
1
I
Logic control input 1. Controls channel 1 state as shown in Truth Tables.
Drain pin 1. Can be an input or output.
I/O
I/O
-
S1
3
Source pin 1. Can be an input or output.
No internal connection.
N.C.
GND
S4
4
2
5
3
P
Ground (0 V) reference
6
4
I/O
I/O
I
Source pin 4. Can be an input or output.
Drain pin 4. Can be an input or output.
D4
7
5
SEL4
SEL3
D3
8
6
Logic control input 4. Controls channel 4 state as shown in Truth Tables.
Logic control input 3. Controls channel 3 state as shown in Truth Tables.
Drain pin 3. Can be an input or output.
9
7
I
10
11
12
8
I/O
I/O
-
S3
9
Source pin 3. Can be an input or output.
No internal connection.
N.C.
10
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
13
11
P
S2
14
15
16
12
13
14
I/O
I/O
I
Source pin 2. Can be an input or output.
D2
Drain pin 2. Can be an input or output.
SEL2
Logic control input 2. Controls channel 2 state as shown in Truth Tables.
(1) I = input, O = output, I/O = input and output, P = power
Copyright © 2019, Texas Instruments Incorporated
3
TMUX1111, TMUX1112, TMUX1113
ZHCSJE1B –FEBRUARY 2019–REVISED AUGUST 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2) (3)
MIN
–0.5
–0.5
–30
–0.5
–30
–65
MAX
UNIT
V
VDD
Supply voltage
6
6
VSEL
Logic control input pin voltage (SELx)
Logic control input pin current (SELx)
Source or drain voltage (Sx, Dx)
Source or drain continuous current (Sx, Dx)
Storage temperature
V
ISEL
30
mA
V
VS or VD
IS or ID (CONT)
Tstg
VDD+0.5
30
mA
°C
°C
150
TJ
Junction temperature
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101
or ANSI/ESDA/JEDEC JS-002, all pins(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.08
0
NOM
MAX
5.5
UNIT
VDD
Positive power supply voltage
V
V
VS or VD
VSEL
TA
Signal path input/output voltage (source or drain pin) (Sx, Dx)
Logic control input pin voltage (SELx)
Ambient temperature
VDD
5.5
0
V
–40
125
°C
7.4 Thermal Information
TMUX1111 / TMUX1112 / TMUX1113
THERMAL METRIC(1)
PW (TSSOP)
16 PINS
124.7
54.8
RSV (QFN)
16 PINS
146.8
83.5
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
70.9
75.5
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
10.8
9.0
ΨJB
70.3
73.4
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2019, Texas Instruments Incorporated
TMUX1111, TMUX1112, TMUX1113
www.ti.com.cn
ZHCSJE1B –FEBRUARY 2019–REVISED AUGUST 2019
7.5 Electrical Characteristics (VDD = 5 V ±10 %)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
2
4
4.5
4.9
Ω
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
0.13
0.85
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
On-resistance matching between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
0.4
0.5
Ω
Ω
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
RON
FLAT
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
1.6
1.6
Ω
Ω
VDD = 5 V
Switch Off
VD = 4.5 V / 1.5 V
VS = 1.5 V / 4.5 V
Refer to Off-leakage current
–0.08 ±0.005
–0.3
0.08
0.3
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
–40°C to +125°C
–0.9
0.9
nA
VDD = 5 V
Switch Off
VD = 4.5 V / 1.5 V
VS = 1.5 V / 4.5 V
Refer to Off-leakage current
25°C
–0.08 ±0.005
–0.3
0.08
0.3
nA
nA
–40°C to +85°C
ID(OFF) Drain off leakage current(1)
–40°C to +125°C
–0.9
0.9
nA
VDD = 5 V
Switch On
VD = VS = 2.5 V
Refer to On-leakage current
25°C
–0.025 ±0.003
–0.2
0.025
0.2
nA
nA
ID(ON)
–40°C to +85°C
Channel on leakage current
IS(ON)
–40°C to +125°C
–0.95
0.95
nA
VDD = 5 V
Switch On
VD = VS = 4.5 V / 1.5 V
Refer to On-leakage current
25°C
–0.1
±0.01
0.1
nA
nA
ID(ON)
–40°C to +85°C
–0.35
0.35
Channel on leakage current
IS(ON)
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (SELx)
VIH
VIL
Input logic high
Input logic low
–40°C to +125°C
–40°C to +125°C
1.49
0
5.5
V
V
0.87
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.06
2
CIN
CIN
Logic input capacitance
Logic input capacitance
25°C
1
pF
pF
–40°C to +125°C
POWER SUPPLY
25°C
0.008
µA
µA
IDD VDD supply current
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
1
(1) When VS is 4.5 V, VD is 1.5 V or when VS is 1.5 V, VD is 4.5 V.
Copyright © 2019, Texas Instruments Incorporated
5
TMUX1111, TMUX1112, TMUX1113
ZHCSJE1B –FEBRUARY 2019–REVISED AUGUST 2019
www.ti.com.cn
Electrical Characteristics (VDD = 5 V ±10 %) (continued)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
12
ns
VS = 3 V
tTRAN
Transition time between channels RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
18
19
ns
ns
ns
ns
ns
Refer to Transition time
8
VS = 3 V
Break before make time
tOPEN
(BBM)
RL = 200 Ω, CL = 15 pF
Refer to Break-before-make
–40°C to +85°C
–40°C to +125°C
1
1
(TMUX1113 Only)
VS = 1 V
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to Charge injection
25°C
25°C
25°C
–1.5
–62
–40
pC
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off isolation
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off isolation
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Channel-to-Channel
Crosstalk
25°C
–100
dB
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
25°C
–90
300
dB
Refer to Channel-to-Channel
Crosstalk
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
BW
Bandwidth
MHz
CSOFF
CDOFF
Source off capacitance
Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
7
pF
pF
10
CSON
CDON
On capacitance
f = 1 MHz
25°C
17
pF
6
Copyright © 2019, Texas Instruments Incorporated
TMUX1111, TMUX1112, TMUX1113
www.ti.com.cn
ZHCSJE1B –FEBRUARY 2019–REVISED AUGUST 2019
7.6 Electrical Characteristics (VDD = 3.3 V ±10 %)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
3.7
8.8
9.5
9.8
Ω
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
0.13
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
On-resistance matching between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
0.4
0.5
Ω
Ω
1.9
2
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
RON
FLAT
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
Ω
2.2
Ω
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
–0.05 ±0.001
–0.2
0.05
0.2
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VS = 1 V / 3 V
Refer to Off-leakage current
–40°C to +125°C
–0.9
0.9
nA
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
25°C
–0.05 ±0.001
–0.2
0.05
0.2
nA
nA
–40°C to +85°C
ID(OFF) Drain off leakage current(1)
VS = 1 V / 3 V
Refer to Off-leakage current
–40°C to +125°C
–0.9
0.9
nA
VDD = 3.3 V
Switch On
VD = VS = 3 V / 1 V
Refer to On-leakage current
25°C
–0.1 ±0.005
–0.35
0.1
nA
nA
ID(ON)
–40°C to +85°C
0.35
Channel on leakage current
IS(ON)
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (SELx)
VIH
VIL
Input logic high
Input logic low
–40°C to +125°C
–40°C to +125°C
1.35
0
5.5
0.8
V
V
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.05
2
CIN
CIN
Logic input capacitance
Logic input capacitance
25°C
1
pF
pF
–40°C to +125°C
POWER SUPPLY
25°C
0.005
µA
µA
IDD VDD supply current
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
1
(1) When VS is 3 V, VD is 1 V or when VS is 1 V, VD is 3 V.
Copyright © 2019, Texas Instruments Incorporated
7
TMUX1111, TMUX1112, TMUX1113
ZHCSJE1B –FEBRUARY 2019–REVISED AUGUST 2019
www.ti.com.cn
Electrical Characteristics (VDD = 3.3 V ±10 %) (continued)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
14
ns
VS = 2 V
tTRAN
Transition time between channels RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
20
22
ns
ns
ns
ns
ns
Refer to Transition time
9
VS = 2 V
Break before make time
tOPEN
(BBM)
RL = 200 Ω, CL = 15 pF
Refer to Break-before-make
–40°C to +85°C
–40°C to +125°C
1
1
(TMUX1113 Only)
VS = 1 V
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to Charge injection
25°C
25°C
25°C
–1.5
–62
–40
pC
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off isolation
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off isolation
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Channel-to-Channel
Crosstalk
25°C
–100
dB
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
25°C
–90
300
dB
Refer to Channel-to-Channel
Crosstalk
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
BW
Bandwidth
MHz
CSOFF
CDOFF
Source off capacitance
Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
7
pF
pF
10
CSON
CDON
On capacitance
f = 1 MHz
25°C
17
pF
8
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ZHCSJE1B –FEBRUARY 2019–REVISED AUGUST 2019
7.7 Electrical Characteristics (VDD = 1.8 V ±10 %)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
40
Ω
VS = 0 V to VDD
RON
On-resistance
ISD = 10 mA
Refer to On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
80
80
Ω
Ω
0.4
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
On-resistance matching between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
1.5
1.5
Ω
Ω
VDD = 1.98 V
Switch Off
VD = 1.62 V / 1 V
VS = 1 V / 1.62 V
Refer to Off-leakage current
–0.05 ±0.001
–0.2
0.05
0.2
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
–40°C to +125°C
–0.9
0.9
nA
VDD = 1.98 V
Switch Off
VD = 1.62 V / 1 V
VS = 1 V / 1.62 V
Refer to Off-leakage current
25°C
–0.05 ±0.001
–0.2
0.05
0.2
nA
nA
–40°C to +85°C
ID(OFF) Drain off leakage current(1)
–40°C to +125°C
–0.9
0.9
nA
VDD = 1.98 V
Switch On
VD = VS = 1.62 V / 1 V
Refer to On-leakage current
25°C
–0.1 ±0.005
–0.35
0.1
nA
nA
ID(ON)
–40°C to +85°C
0.35
Channel on leakage current
IS(ON)
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (SELx)
VIH
VIL
Input logic high
Input logic low
–40°C to +125°C
–40°C to +125°C
1.07
0
5.5
V
V
0.68
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.05
2
CIN
CIN
Logic input capacitance
Logic input capacitance
25°C
1
pF
pF
–40°C to +125°C
POWER SUPPLY
25°C
0.001
µA
µA
IDD VDD supply current
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
0.85
(1) When VS is 1.62 V, VD is 1 V or when VS is 1 V, VD is 1.62 V.
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Electrical Characteristics (VDD = 1.8 V ±10 %) (continued)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
25
ns
VS = 1 V
tTRAN
Transition time between channels RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
44
44
ns
ns
ns
ns
ns
Refer to Transition time
17
VS = 1 V
Break before make time
tOPEN
(BBM)
RL = 200 Ω, CL = 15 pF
Refer to Break-before-make
–40°C to +85°C
–40°C to +125°C
1
1
(TMUX1113 Only)
VS = 1 V
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to Charge injection
25°C
25°C
25°C
–0.5
–62
–40
pC
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off isolation
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off isolation
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Channel-to-Channel
Crosstalk
25°C
–100
dB
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
25°C
–90
300
dB
Refer to Channel-to-Channel
Crosstalk
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
BW
Bandwidth
MHz
CSOFF
CDOFF
Source off capacitance
Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
7
pF
pF
10
CSON
CDON
On capacitance
f = 1 MHz
25°C
17
pF
10
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ZHCSJE1B –FEBRUARY 2019–REVISED AUGUST 2019
7.8 Electrical Characteristics (VDD = 1.2 V ±10 %)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
70
Ω
VS = 0 V to VDD
RON
On-resistance
ISD = 10 mA
Refer to On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
105
105
Ω
Ω
0.4
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
On-resistance matching between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
1.5
1.5
Ω
Ω
VDD = 1.32 V
Switch Off
VD = 1 V / 0.8 V
VS = 0.8 V / 1 V
Refer to Off-leakage current
–0.05 ±0.001
–0.2
0.05
0.2
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
–40°C to +125°C
–0.9
0.9
nA
VDD = 1.32 V
Switch Off
VD = 1 V / 0.8 V
VS = 0.8 V / 1 V
Refer to Off-leakage current
25°C
–0.05 ±0.001
–0.2
0.05
0.2
nA
nA
–40°C to +85°C
ID(OFF) Drain off leakage current(1)
–40°C to +125°C
–0.9
0.9
nA
VDD = 1.32 V
Switch On
VD = VS = 1 V / 0.8 V
Refer to On-leakage current
25°C
–0.1 ±0.005
–0.35
0.1
nA
nA
ID(ON)
–40°C to +85°C
0.35
Channel on leakage current
IS(ON)
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (SELx)
VIH
VIL
Input logic high
Input logic low
–40°C to +125°C
–40°C to +125°C
0.96
0
5.5
V
V
0.36
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.05
2
CIN
CIN
Logic input capacitance
Logic input capacitance
25°C
1
pF
pF
–40°C to +125°C
POWER SUPPLY
25°C
0.001
µA
µA
IDD VDD supply current
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
0.7
(1) When VS is 1 V, VD is 0.8 V or when VS is 0.8 V, VD is 1 V.
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Electrical Characteristics (VDD = 1.2 V ±10 %) (continued)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
55
ns
VS = 1 V
tTRAN
Transition time between channels RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
25°C
190
190
ns
ns
ns
ns
ns
Refer to Transition time
28
VS = 1 V
Break before make time
tOPEN
(BBM)
RL = 200 Ω, CL = 15 pF
Refer to Break-before-make
–40°C to +85°C
–40°C to +125°C
1
1
(TMUX1113 Only)
VS = 1 V
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to Charge injection
25°C
25°C
25°C
–0.5
–62
–40
pC
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off isolation
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off isolation
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Channel-to-Channel
Crosstalk
25°C
–100
dB
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
25°C
–90
300
dB
Refer to Channel-to-Channel
Crosstalk
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
BW
Bandwidth
MHz
CSOFF
CDOFF
Source off capacitance
Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
8
pF
pF
11
CSON
CDON
On capacitance
f = 1 MHz
25°C
18
pF
12
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7.9 Typical Characteristics
at TA = 25°C, VDD = 5 V (unless otherwise noted)
6
5
4.5
4
VDD = 3 V
5
TA = 85èC
TA = 125èC
VDD = 3.63 V
3.5
3
4
VDD = 4.5 V
3
2.5
2
VDD = 5.5 V
2
1
0
1.5
1
TA = -40èC
TA = 25èC
0.5
0
0
1
2
VS or VD - Source or Drain Voltage (V)
3
4
5
5.5
0
0
0
1
2
VS or VD - Source or Drain Voltage (V)
3
4
5
D001
D002
TA = 25°C
VDD = 5 V
图 1. On-Resistance vs Source or Drain Voltage
图 2. On-Resistance vs Temperature
8
7
6
5
4
3
2
1
0
80
70
60
50
40
30
20
10
0
VDD = 1.08 V
TA = 85èC
TA = 125èC
VDD = 1.32 V
VDD = 1.62 V
VDD = 1.98 V
TA = -40èC
TA = 25èC
2.5
VS or VD - Source or Drain Voltage (V)
0
0.5
1
1.5
2
3
3.5
0.2 0.4 0.6 0.8 1
VS or VD - Source or Drain Voltage (V)
1.2 1.4 1.6 1.8
2
D003
D004
VDD = 3.3 V
TA = 25°C
图 3. On-Resistance vs Temperature
图 4. On-Resistance vs Source or Drain Voltage
20
15
10
5
80
60
40
VDD = 3.63 V
VDD = 1.98 V
VDD = 1.32 V
20
0
0
-5
-20
-40
-60
-80
-10
-15
-20
0
0.5
1
VS or VD - Source or Drain Voltage (V)
1.5
2
2.5
3
3.5
4
1
VS or VD - Source or Drain Voltage (V)
2
3
4
5
D005
D006
TA = 25°C
VDD = 5 V
图 5. On-Leakage vs Source or Drain Voltage
图 6. On-Leakage vs Source or Drain Voltage
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Typical Characteristics (接下页)
1
3
2
0.75
0.5
IS(OFF)
IS(OFF)
1
0.25
0
0
-0.25
-0.5
-1
-2
-3
IS(ON)
IS(ON)
-0.75
-1
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D007
D008
VDD = 3.3 V
VDD = 5 V
图 7. Leakage Current vs Temperature
图 8. Leakage Current vs Temperature
1400
1200
1000
800
600
400
200
0
0.5
0.4
0.3
0.2
0.1
0
VDD = 5 V
VDD = 3.3 V
VDD = 1.8 V
VDD = 1.2 V
VDD = 5 V
VDD = 3.3 V
VDD = 1.8 V
VDD = 1.2 V
-0.1
0
0.5
1
1.5
2
2.5
3
Logic Voltage (V)
3.5
4
4.5
5
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D010
D009
TA = 25°C
VSEL = 5.5 V
图 9. Supply Current vs Temperature
图 10. Supply Current vs Logic Voltage
20
8
6
15
10
5
4
VDD = 1.2 V
VDD = 3.3 V
2
VDD = 5 V
0
0
-5
-2
-4
-6
VDD = 1.8 V
-10
-15
-20
-8
0
0
1
2
VS - Source Voltage (V)
3
4
5
0.25
0.5
0.75
1
Source Voltage (V)
1.25
1.5
1.75
2
D011
D012
TA = -40°C to 125°C
TA = -40°C to 125°C
图 11. Charge Injection vs Source Voltage
图 12. Charge Injection vs Source Voltage
14
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Typical Characteristics (接下页)
30
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
25
Off-Isolation
Rising
20
15
10
5
Crosstalk
Falling
0
0.5
1.5
2.5 3.5
VDD - Supply Voltage (V)
4.5
5.5
100k
1M
10M
Frequency (Hz)
100M
D013
D014
TA = -40°C to +125°C
TA = -40°C to +125°C
图 13. Output TTRANSITION vs Supply Voltage
图 14. Xtalk and Off-Isolation vs Frequency
0
-1
-2
-3
-4
-5
-6
1M
10M
Frequency (Hz)
100M
D015
TA = -40°C to +125°C
图 15. On Response vs Frequency
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8 Parameter Measurement Information
8.1 On-resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (Dx) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance.
The measurement setup used to measure RON is shown in 图 16. Voltage (V) and current (ISD) are measured
using this setup, and RON is computed with RON = V / ISD
:
V
ISD
Sx
Dx
VS
图 16. On-Resistance measurement setup
8.2 Off-leakage current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF)
.
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF)
.
The setup used to measure both off-leakage currents is shown in 图 17.
VDD
VDD
VDD
VDD
IS (OFF)
A
ID (OFF)
A
S1
D1
D1
S1
VS
VD
VD
VS
IS (OFF)
A
ID (OFF)
A
S4
D4
D4
S4
VS
VD
VD
VS
GND
GND
图 17. Off-leakage measurement setup
16
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8.3 On-leakage current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON)
.
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON)
.
Either the source pin or drain pin is left floating during the measurement. 图 18 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON)
.
VDD
VDD
VDD
VDD
IS (ON)
A
ID (ON)
S1
D1
D1
S1
N.C.
N.C.
A
VS
VD
IS (ON)
A
ID (ON)
A
S4
D4
D4
S4
N.C.
N.C.
VS
VD
GND
GND
图 18. On-leakage measurement setup
8.4 Transition time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the address signal
has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of
the device. System level timing can then account for the time constant added from the load resistance and load
capacitance. 图 19 shows the setup used to measure transition time, denoted by the symbol tTRANSITION
.
VDD
0.1ꢀF
VDD
VDD
ADDRESS
DRIVE
(VSEL
tf < 5ns
tr < 5ns
VIH
)
VIL
OUTPUT
RL
S1
D1
0 V
VS
CL
tTRANSITION
tTRANSITION
OUTPUT
RL
S4
D4
VS
90%
CL
SEL1 - SEL4
OUTPUT
VSEL
GND
10%
0 V
图 19. Transition-time measurement setup
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8.5 Break-before-make
The TMUX1113 has break-before-make delay which allows the device to be used in cross-point switching
application. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. 图 20 shows the
setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM)
.
VDD
0.1ꢀF
VDD
VDD
VSEL
VIH
VIL
0 V
OUTPUT 1
CL
S1, S4
D1, D4
VS
90%
90%
RL
Output 2
0 V
OUTPUT 2
CL
S2, S3
D2, D3
VS
90%
90%
Output 1
tBBM2
RL
tBBM1
SEL1 - SEL4
0 V
VSEL
GND
tBBM= min (tBBM1, tBBM2
)
图 20. Break-before-make delay measurement setup
8.6 Charge injection
The TMUX111x devices have a transmission-gate topology. Any mismatch in capacitance between the NMOS
and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the
gate signal. The amount of charge injected into the source or drain of the device is known as charge injection,
and is denoted by the symbol QC. 图 21 shows the setup used to measure charge injection from source (Sx) to
drain (Dx).
VDD
0.1ꢀF
VDD
VDD
VSEL
OUTPUT
S1
D1
VOUT
CL
VS
0 V
Output
VS
OUTPUT
VOUT
S4
D4
VOUT
CL
VS
QC = CL
×
VOUT
SEL1 - SEL4
VSEL
GND
图 21. Charge-injection measurement setup
18
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8.7 Off isolation
Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the
source pin (Sx) of an off-channel. The characteristic impedance, Z0, for the measurement is 50 Ω. 图 22 shows
the setup used to measure off isolation. Use off isolation equation to compute off isolation.
0.1µF
NETWORK
VDD
ANALYZER
VS
S
D
50Ω
VSIG
VOUT
RL
50Ω
SX/DX
GND
RL
50Ω
图 22. Off isolation measurement setup
≈
∆
«
’
÷
◊
VOUT
VS
Off Isolation = 20 ∂ Log
(1)
8.8 Channel-to-Channel Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (Dx) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. The characteristic impedance, Z0, for the measurement is 50 Ω. 图 23
shows the setup used to measure, and the equation used to compute crosstalk.
VDD
0.1µF
NETWORK
VDD
ANALYZER
D1
D2
S1
S2
VOUT
RL
RL
50Ω
50Ω
VS
RL
50Ω
50Ω
SX / DX
VSIG = 200 mVpp
VBIAS = VDD / 2
RL
50Ω
GND
图 23. Channel-to-Channel Crosstalk Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Channel-to-Channel Crosstalk = 20 ∂ Log
(2)
19
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8.9 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx) of the device. The
characteristic impedance, Z0, for the measurement is 50 Ω. 图 24 shows the setup used to measure bandwidth.
VDD
0.1µF
NETWORK
VDD
ANALYZER
VS
S
D
50Ω
VSIG
VOUT
RL
50Ω
GND
图 24. Bandwidth measurement setup
20
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9 Detailed Description
9.1 Overview
The TMUX1111, TMUX1112, and TMUX1113 are 1:1 (SPST), 4-Channel switches. The devices have four
independently selectable single-pole, single-throw switches that are turned-on or turned-off based on the state of
the corresponding select pin.
9.2 Functional Block Diagram
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
S1
S2
S3
S4
D1
D2
D3
D4
S1
S2
S3
S4
D1
D2
D3
D4
S1
S2
S3
S4
D1
D2
D3
D4
SEL1
SEL2
SEL3
SEL4
SEL1
SEL2
SEL3
SEL4
SEL1
SEL2
SEL3
SEL4
TMUX1111
TMUX1112
ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT
TMUX1113
图 25. TMUX111x Functional Block Diagram
9.3 Feature Description
9.3.1 Bidirectional operation
The TMUX111x conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each
channel has very similar characteristics in both directions and supports both analog and digital signals.
9.3.2 Rail to rail operation
The valid signal path input/output voltage for TMUX111x ranges from GND to VDD
.
9.3.3 1.8 V Logic compatible inputs
The TMUX111x devices have 1.8-V logic compatible control for all logic control inputs. The logic input thresholds
scale with supply but still provide 1.8-V logic control when operating at 5.5 V supply voltage. 1.8-V logic level
inputs allows the TMUX111x devices to interface with processors that have lower logic I/O rails and eliminates
the need for an external translator, which saves both space and BOM cost. The current consumption of the
TMUX111x devices increase when using 1.8V logic with higher supply voltage as shown in 图 10. For more
information on 1.8 V logic implementations refer to Simplifying Design with 1.8 V logic Muxes and Switches
9.3.4 Fail-safe logic
The TMUX111x supports Fail-Safe Logic on the control input pins (EN, A0, A1) allowing for operation up to 5.5
V, regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied before
the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by
removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic
feature allows the select pins of the TMUX111x to be ramped to 5.5 V while VDD = 0 V. Additionally, the feature
enables operation of the TMUX111x with VDD = 1.2 V while allowing the select pins to interface with a logic level
of another device up to 5.5 V.
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Feature Description (接下页)
9.3.5 Ultra-low Leakage Current
The TMUX111x devices provide extremely low on-leakage and off-leakage currents. The TMUX111x devices are
capable of switching signals from high source-impedance inputs into a high input-impedance op amp with
minimal offset error because of the ultra-low leakage currents. 图 26 shows typical leakage currents of the
TMUX111x devices versus temperature at VDD = 5V.
3
2
IS(OFF)
1
0
-1
IS(ON)
-2
-3
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
D008
图 26. Leakage Current vs Temperature
9.3.6 Ultra-low Charge Injection
The TMUX111x devices have a transmission gate topology, as shown in 图 27. Any mismatch in the stray
capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is
opened or closed.
The TMUX111x devices have special charge-injection cancellation circuitry that reduces the source-to-drain
charge injection to -1.5 pC at VS = 1 V as shown in 图 28.
20
OFF ON
15
10
5
CGDN
CGSN
VDD = 3.3 V
VDD = 5 V
0
D
S
-5
-10
-15
-20
CGSP
CGDP
0
1
2
3
VS - Source Voltage (V)
4
5
OFF ON
D011
图 28. Charge Injection vs Source Voltage
图 27. Transmission Gate Topology
22
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ZHCSJE1B –FEBRUARY 2019–REVISED AUGUST 2019
9.4 Device Functional Modes
The TMUX111x devices have four independently selectable single-pole, single-throw switches that are turned-on
or turned-off based on the state of the corresponding select pin. The control pins can be as high as 5.5 V.
The TMUX111x devices can be operated without any external components except for the supply decoupling
capacitors. Unused logic control pins should be tied to GND or VDD in order to ensure the device does not
consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path
inputs (Sx or Dx) should be connection to GND.
9.5 Truth Tables
表 1, 表 2, and 表 3 show the truth tables for the TMUX1111, TMUX1112, and TMUX1113, respectively.
表 1. TMUX1111 Truth table(1)
SEL x
CHANNEL x
Channel x ON
Channel x OFF
0
1
(1) x denotes 1, 2, 3 , or 4 for the corresponding channel.
表 2. TMUX1112 Truth table(1)
SEL x
CHANNEL x
Channel x OFF
Channel x ON
0
1
(1) x denotes 1, 2, 3 , or 4 for the corresponding channel.
表 3. TMUX1113 Truth table(1)
SEL1
SEL2
SEL3
SEL4
ON / OFF CHANNELS
CHANNEL 1 OFF
CHANNEL 1 ON
CHANNEL 2 ON
CHANNEL 2 OFF
CHANNEL 3 ON
CHANNEL 3 OFF
CHANNEL 4 OFF
CHANNEL 4 ON
0
1
X
X
0
X
X
X
X
0
X
X
X
X
X
X
0
X
X
X
X
X
X
1
X
X
X
X
1
X
X
1
(1) X denotes don't care.
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TMUX11xx family offers ulta-low input/output leakage currents and low charge injection. These devices
operate up to 5.5 V, and offer true rail-to-rail input and output of both analog and digital signals. The TMUX111x
have a low on-capacitance which allows faster settling time when multiplexing inputs in the time domain. These
features make the TMUX11xx devices a family of precision, high-performance switches and multiplexers for low-
voltage applications.
10.2 Typical Application - Sample-and-Hold Circuit
One useful application to take advantage of the TMUX1111, TMUX1112, and TMUX1113's performance is the
sample-and-hold circuit. A sample-and-hold circuit can be useful for an analog to digital converter (ADC) to
sample a varying input voltage with improved reliability and stability. It can also be used to store the output
samples from a single digital-to-analog converter (DAC) in a multi-output application. A simple sample-and-hold
circuit can be realized using an analog switch such as the TMUX1111, TMUX1112, and TMUX1113 analog
switches. 图 29 shows a single channel sample-and hold circuit using only 1 of 4 channels in the TMUX111x
devices.
TMUX111x
DAC
+
OP AMP
+
RL
VOUT
CL
œ
OP AMP
CH
SEL1
œ
4 Channels
(1.8V Capable Control Logic)
SEL4
图 29. Single Channel Sample-and-Hold Circuit Example
An optional op amp is used before the switch since buffered DACs typically have limitations in driving capacitive
loads. The additional buffer stage is included following the DAC to prevent potential stability problems from
driving a large capacitive load.
Ideally, the switch delivers only the input signals to the holding capacitors. However, when the switch gets
toggled, some amount of charge also gets transferred to the switch output in the form of charge injection,
resulting in a pedestal sampling error. The TMUX1111, TMUX1112, and TMUX1113 switches have excellent
charge injection performance of only -1.5 pC, making them ideal choices for this implementation to minimize
sampling error. The pedestal error voltage is indirectly related to the size of the capacitance on the output, for
better precision a larger capacitor is required due to charge injection. Larger capacitance limits the system
settling time which may not be acceptable in some applications. 图 30 shows a TMUX111x device configured for
a 2-channel sample-and-hold circuit with pedestal error compensation.
24
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Typical Application - Sample-and-Hold Circuit (接下页)
5V
CH
VDD
5V
5V
œ
SW1
RL
5V
CC
RC
VOUT1
VIN1
OPA2192
DAC9881
+
SW2
CL
+
OPA2192
0V
œ
SEL1/
SEL2
CH
CH
0V
5V
SEL3/
SEL4
œ
5V
5V
+
OPA2192
SW3
SW4
RL
RC
CC
VIN2
VOUT2
DAC9881
+
OPA2192
0V
CL
œ
0V
CH
TMUX111x
图 30. 2-Channel Sample-and-Hold Circuit with Pedestal Error Compensation
10.3 Design Requirements
The purpose of this precision design is to implement an optimized 2-output sample-and-hold circuit using a 4-
channel SPST switch. The sample and hold circuit needs to be capable of supporting high accuracy with
minimized pedestal error and fast settling time..
10.4 Detailed Design Procedure
10.4.1 Detailed Design Procedure
The TMUX1111, TMUX1112, or TMUX1113 switch is used in conjunction with the voltage holding capacitors
(CH) to implement the sample-and-hold circuit. The basic operation is:
1. When the switch (SW2 or SW3) is closed, it samples the input voltage and charges the holding capacitors
(CH) to the input voltages values.
2. When the switch (SW2 or SW3) is open, the holding capacitors (CH) holds its previous value, maintaining
stable voltage at the amplifier output (VOUT).
Due to switch and capacitor leakage current, as well as amplifier bias current, the voltage on the hold capacitors
droops with time. The TMUX1111, TMUX1112, or TMUX1113 minimize the droops due to its ultra-low leakage
performance. At 25°C, the TMUX1111, TMUX1112, andTMUX1113 have extremely low leakage current at 3pA
typical.
A second switch SW1 (or SW4) is also included to operate in parallel with SW2 (or SW3) to reduce pedestal
error during switch toggling. Because both switches are driven at the same potential, they act as common-mode
signal to the op-amp, thereby minimizing the charge injection effects caused by the switch toggling action.
Compensation network consisting of RC and CC is also added to further reduce the pedestal error, whiling
reducing the hold-time glitch and improving the settling time of the circuit. Refer to Sample & Hold Glitch
Reduction for Precision Outputs Reference Design for more information on sample-and-hold circuits.
版权 © 2019, Texas Instruments Incorporated
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TMUX1111, TMUX1112, TMUX1113
ZHCSJE1B –FEBRUARY 2019–REVISED AUGUST 2019
www.ti.com.cn
10.5 Application Curve
TMUX1111, TMUX1112, andTMUX1113 have excellent charge injection performance and ultra-low leakage
current, making them ideal choices to minimize sampling error for the sample and hold application.
20
15
10
5
80
60
40
VDD = 3.3 V
20
VDD = 5 V
0
0
-20
-40
-60
-80
-5
-10
-15
-20
0
1
2
3
VS or VD - Source or Drain Voltage (V)
4
5
0
1
2
3
VS - Source Voltage (V)
4
5
D006
D011
VDD= 5 V
TA = -40°C to +125°C
图 31. Charge Injection vs Source Voltage
图 32. On-Leakage vs Source or Drain Voltage
10.6 Typical Application - Switched Gain Amplifier
Switches and multiplexers are commonly used in the feedback path of amplifier circuits to provide configurable
gain control. By using various resistor values on each switch path the TMUX111x allows the system to have
multiple gain settings. An external resistor, or utilizing 1 channel always being closed, ensures the amplifier isn't
operating in an open loop configuration. A transimpedance amplifier (TIA) for photodiode inputs is a common
circuit that requires gain control using a multi-channel switch to convert the output current of the photodiode into
a voltage for the MCU or processor. The leakage current, capacitance, and charge injection performance of the
TMUX111x are key specifications to evaluate when selecting a device for gain control.
VI/O
VDD
VDD
0.1µF
Processor
SEL1
SEL2
SEL3
SEL4
1.8V Logic I/O
RF_1
RF_2
RF_3
RF_4
Digital Processing
VDD
VDD
-
OP
AMP
Gain / Filter
Network
ADC
IPD
+
图 33. Switching Gain Settings of a TIA circuit
26
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ZHCSJE1B –FEBRUARY 2019–REVISED AUGUST 2019
10.7 Design Requirements
For this design example, use the parameters listed in 表 4.
表 4. Design parameters
PARAMETERS
Supply (VDD
VALUES
3.3 V
)
Input / Output signal range
Control logic thresholds
0 µA to 10 µA
1.8 V compatible
10.8 Detailed Design Procedure
The TMUX111x devices can be operated without any external components except for the supply decoupling
capacitors. All inputs signals passing through the switch must fall within the recommend operating conditions of
the TMUX111x including signal range and continuous current. For this design example, with a supply of 3.3 V,
the signals can range from 0 V to 3.3 V when the device is powered. The max continuous current can be 30 mA.
Photodiodes commonly have a current output that ranges from a few hundred picoamps to tens of microamps
based on the amount of light being absorbed. The TMUX111x have a typical On-leakage current of less than 10
pA which would lead to an accuracy well within 1% of a full scale 10 µA signal. The low ON and OFF
capacitance of the TMUX111x improves system stability by minimizing the total capacitance on the output of the
amplifier. Lower capacitance leads to less overshoot and ringing in the system which can cause the amplifier
circuit to go unstable if the phase margin is not at least 45°. Refer to Improve Stability Issues with Low CON
Multiplexers for more information on calculating the phase margin vs. percent overshoot.
10.9 Application Curve
The TMUX1111 is capable of switching signals from high source-impedance inputs into a high input-impedance
op amp with minimal offset error because of the ultra-low leakage currents.
20
15
10
VDD = 3.63 V
VDD = 1.98 V
VDD = 1.32 V
5
0
-5
-10
-15
-20
0
0.5
1
1.5
2
2.5
3
VS or VD - Source or Drain Voltage (V)
3.5
4
D005
TA = 25°C
图 34. On-Leakage vs Source or Drain Voltage
版权 © 2019, Texas Instruments Incorporated
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TMUX1111, TMUX1112, TMUX1113
ZHCSJE1B –FEBRUARY 2019–REVISED AUGUST 2019
www.ti.com.cn
11 Power Supply Recommendations
The TMUX111x operate across a wide supply range of 1.08 V to 5.5 V. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply to
other components. Good power-supply decoupling is important to achieve optimum performance. For improved
supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to ground.
Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance
connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series
resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive
systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to
the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall
inductance and is beneficial for connections to ground planes.
12 Layout
12.1 Layout Guidelines
12.1.1 Layout Information
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners.图 35 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
1W min.
W
图 35. Trace example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, through-
hole pins are not recommended at high frequencies.
28
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TMUX1111, TMUX1112, TMUX1113
www.ti.com.cn
ZHCSJE1B –FEBRUARY 2019–REVISED AUGUST 2019
Layout Guidelines (接下页)
图 36 illustrates an example of a PCB layout with the TMUX111x. Some key considerations are:
•
Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
•
•
•
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
12.2 Layout Example
Via to GND plane
SEL1
SEL2
D2
D1
S1
C
Wide (low inductance)
trace for power
S2
N.C.
GND
VDD
TMUX111x
N.C.
S3
S4
D4
D3
SEL4
SEL3
图 36. TMUX111x Layout example
版权 © 2019, Texas Instruments Incorporated
29
TMUX1111, TMUX1112, TMUX1113
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www.ti.com.cn
13 器件和文档支持
13.1 文档支持
13.1.1 相关文档
德州仪器 (TI)，《通过采样保持减少干扰实现精密输出的参考设计》。
德州仪器 (TI)，《真差分 4 x 2 多路复用器、模拟前端、同步采样 ADC 电路》。
德州仪器 (TI)，《使用低 CON 多路复用器改善稳定性问题》。
德州仪器 (TI)，《使用 1.8V 逻辑多路复用器和开关简化设计》。
德州仪器 (TI)，《利用关断保护信号开关消除电源排序》。
德州仪器 (TI)，《高电压模拟多路复用器的系统级保护》。
德州仪器 (TI)，《QFN/SON PCB 连接》。
德州仪器 (TI)，《四方扁平封装无引线逻辑封装》。
13.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 5. 相关链接
器件
产品文件夹
单击此处
单击此处
单击此处
立即订购
单击此处
单击此处
单击此处
技术文档
单击此处
单击此处
单击此处
工具与软件
单击此处
单击此处
单击此处
支持和社区
单击此处
单击此处
单击此处
TMUX1111
TMUX1112
TMUX1113
13.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 商标
E2E is a trademark of Texas Instruments.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
30
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14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
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31
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX1111PWR
TMUX1111RSVR
TMUX1112PWR
TMUX1112RSVR
TMUX1113PWR
TMUX1113RSVR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
UQFN
TSSOP
UQFN
TSSOP
UQFN
PW
RSV
PW
16
16
16
16
16
16
2000 RoHS & Green
3000 RoHS & Green
2000 RoHS & Green
3000 RoHS & Green
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TM1111
NIPDAUAG
NIPDAU
1FC
TM1112
1FD
RSV
PW
NIPDAUAG
NIPDAU
TM1113
1FE
RSV
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX1111PWR
TMUX1111RSVR
TMUX1112PWR
TMUX1112RSVR
TMUX1113PWR
TMUX1113RSVR
TSSOP
UQFN
TSSOP
UQFN
TSSOP
UQFN
PW
RSV
PW
16
16
16
16
16
16
2000
3000
2000
3000
2000
3000
330.0
178.0
330.0
178.0
330.0
178.0
12.4
13.5
12.4
13.5
12.4
13.5
6.9
2.1
6.9
2.1
6.9
2.1
5.6
2.9
5.6
2.9
5.6
2.9
1.6
0.75
1.6
8.0
4.0
8.0
4.0
8.0
4.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
RSV
PW
0.75
1.6
RSV
0.75
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMUX1111PWR
TMUX1111RSVR
TMUX1112PWR
TMUX1112RSVR
TMUX1113PWR
TMUX1113RSVR
TSSOP
UQFN
TSSOP
UQFN
TSSOP
UQFN
PW
RSV
PW
16
16
16
16
16
16
2000
3000
2000
3000
2000
3000
356.0
189.0
356.0
189.0
356.0
189.0
356.0
185.0
356.0
185.0
356.0
185.0
35.0
36.0
35.0
36.0
35.0
36.0
RSV
PW
RSV
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
RSV0016A
UQFN - 0.55 mm max height
S
C
A
L
E
5
.
0
0
0
ULTRA THIN QUAD FLATPACK - NO LEAD
1.85
1.75
A
B
PIN 1 INDEX AREA
2.65
2.55
C
0.55
0.45
SEATING PLANE
0.05 C
0.05
0.00
2X 1.2
SYMM
℄
(0.13) TYP
5
8
0.45
0.35
15X
4
9
SYMM
℄
2X 1.2
12X 0.4
1
0.25
16X
12
0.15
0.07
0.05
C A B
13
16
0.55
0.45
PIN 1 ID
(45° X 0.1)
4220314/C 02/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
SYMM
℄
(0.7)
16
SEE SOLDER MASK
DETAIL
13
12
16X (0.2)
1
SYMM
℄
12X (0.4)
(2.4)
(R0.05) TYP
9
4
15X (0.6)
5
8
(1.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220314/C 02/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
(0.7)
16
13
16X (0.2)
1
12
SYMM
℄
12X (0.4)
(2.4)
(R0.05) TYP
4
9
15X (0.6)
5
8
SYMM
℄
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 25X
4220314/C 02/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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