TMUX1208 [TI]
具有 1.8V 输入逻辑的 5V、8:1、单通道通用模拟多路复用器;
| 型号： | TMUX1208 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 1.8V 输入逻辑的 5V、8:1、单通道通用模拟多路复用器 复用器 |
| 文件： | 总36页 (文件大小：1280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TMUX1208, TMUX1209
ZHCSIN2C –AUGUST 2018–REVISED DECEMBER 2018
TMUX1208 5V 双向 8:1、单通道多路复用器
TMUX1209 5V 双向 4:1、双通道多路复用器
1 特性
3 说明
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轨至轨运行
TMUX1208 和 TMUX1209 为通用互补金属氧化物半
导体 (CMOS) 多路复用器 (MUX)。TMUX1208 提供
8:1 单端通道，而 TMUX1209 提供差动 4:1 或双 4:1
单端通道。1.08V 至 5.5V 的宽电源电压工作范围 可支
持 的各种 应用中运行。该器件可在源极 (Sx) 和漏极
(D) 引脚上支持从 GND 到 VDD 范围的双向模拟和数字
信号。
双向信号路径
低导通电阻：5Ω
宽电源电压范围：1.08V 至 5.5V
-40°C 至 +125°C 运行温度
兼容 1.8V 逻辑
失效防护逻辑
低电源电流：10nA
转换时间：14ns
所有逻辑输入均具有兼容 1.8V 逻辑的阈值，当器件在
有效电源电压范围内运行时，这些阈值可确保 TTL 和
CMOS 逻辑兼容性。失效防护逻辑 电路允许在电源引
脚之前的控制引脚上施加电压，从而保护器件免受潜在
的损害。
先断后合开关
ESD 保护 HBM：2000V
行业标准 TSSOP 和 QFN 封装
器件信息(1)
2 应用
器件型号
TMUX1208
封装
TSSOP (16)
QFN (16)
封装尺寸（标称值）
5.00mm × 4.40mm
2.60mm x 1.80mm
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模拟和数字多路复用/多路信号分离
HVAC：取暖、通风和空调
烟雾探测器
TMUX1209
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
视频监控
电子销售终端
电池供电类设备
电器
空白
消费类音频
应用示例
TMUX1208、TMUX1209 方框图
VDD
TMUX1208
TMUX1209
VDD
VI/O
VDD
S1A
S2A
S3A
S4A
S1
S2
S3
S4
S5
S6
S7
S8
LDO #1
DA
DB
EN
MCU
S1
S2
S3
S4
S5
S6
S7
S8
LDO #2
LDO #3
D
S1B
S2B
S3B
S4B
RAM
FLASH
D
Integrated
12-bit ADC
LM20
Analog Temp.
Sensor
1-OF-8
DECODER
1-OF-4
DECODER
LM20
Analog Temp.
Sensor
A0
A1
EN
A0 A1 A2 EN
Port I/O
TIMERS
A2
A1
LM20
Analog Temp.
Sensor
A0
GND
1.8V Logic
I/O
System Inputs &
Sensors
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS389
TMUX1208, TMUX1209
ZHCSIN2C –AUGUST 2018–REVISED DECEMBER 2018
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics (VDD = 5 V ±10 %)............ 6
7.6 Electrical Characteristics (VDD = 3.3 V ±10 %)......... 8
7.7 Electrical Characteristics (VDD = 1.8 V ±10 %)....... 10
7.8 Electrical Characteristics (VDD = 1.2 V ±10 %)....... 12
7.9 Typical Characteristics............................................ 14
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 20
8.3 Feature Description................................................. 20
9
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application ................................................. 22
9.3 Design Requirements.............................................. 22
9.4 Detailed Design Procedure ..................................... 23
9.5 Application Curve.................................................... 23
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 器件和文档支持 ..................................................... 25
12.1 文档支持................................................................ 25
12.2 相关链接................................................................ 25
12.3 接收文档更新通知 ................................................. 25
12.4 社区资源................................................................ 25
12.5 商标....................................................................... 25
12.6 静电放电警告......................................................... 25
12.7 术语表 ................................................................... 25
13 机械、封装和可订购信息....................................... 25
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (November 2018) to Revision C
Page
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向数据表添加了 TMUX1209 器件 ........................................................................................................................................... 1
Changes from Revision A (September 2018) to Revision B
Page
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Added RSV (QFN) thermal information to Thermal Information: table................................................................................... 5
Added footnote to clarify test conditions ................................................................................................................................ 8
Changes from Original (August 2018) to Revision A
Page
•
将文件状态从预告信息 更改为生产数据.................................................................................................................................. 1
2
Copyright © 2018, Texas Instruments Incorporated
TMUX1208, TMUX1209
www.ti.com.cn
ZHCSIN2C –AUGUST 2018–REVISED DECEMBER 2018
5 Device Comparison Table
PRODUCT
TMUX1208
TMUX1209
DESCRIPTION
8:1, 1-Channel, single-ended multiplexer
4:1, 2-Channel, differential multiplexer
6 Pin Configuration and Functions
TMUX1208: PW Package
16-Pin TSSOP
TMUX1208: RSV Package
16-Pin QFN
Top View
Top View
A0
EN
N.C.
S1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A1
A2
GND
VDD
S5
N.C.
S1
1
12
11
10
9
GND
VDD
S5
S2
2
3
4
S3
S6
S2
S4
S7
S3
S6
S8
D
Not to scale
Not to scale
Pin Functions TMUX1208
PIN
TSSOP
1
TYPE(1)
DESCRIPTION
NAME
UQFN
A0
15
I
I
Address line 0. Controls the switch configuration as shown in 表 1.
Active high logic input. When this pin is low, all switches are turned off. When this pin is high,
the A[2:0] address inputs determine which switch is turned on.
EN
2
16
N.C.
S1
S2
S3
S4
D
3
4
1
2
Not Connected
Not Connected
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Source pin 1. Can be an input or output.
Source pin 2. Can be an input or output.
Source pin 3. Can be an input or output.
Source pin 4. Can be an input or output.
Drain pin. Can be an input or output.
Source pin 8. Can be an input or output.
Source pin 7. Can be an input or output.
Source pin 6. Can be an input or output.
Source pin 5. Can be an input or output.
5
3
6
4
7
5
8
6
S8
S7
S6
S5
9
7
10
11
12
8
9
10
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
13
11
P
GND
A2
14
15
16
12
13
14
P
I
Ground (0 V) reference
Address line 2. Controls the switch configuration as shown in 表 1.
Address line 1. Controls the switch configuration as shown in 表 1.
A1
I
(1) I = input, O = output, I/O = input and output, P = power
Copyright © 2018, Texas Instruments Incorporated
3
TMUX1208, TMUX1209
ZHCSIN2C –AUGUST 2018–REVISED DECEMBER 2018
www.ti.com.cn
TMUX1209: PW Package
16-Pin TSSOP
TMUX1209: RSV Package
16-Pin QFN
Top View
Top View
A0
EN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A1
GND
VDD
S1B
S2B
S3B
S4B
DB
N.C.
S1A
S2A
S3A
S4A
DA
N.C.
S1A
S2A
S3A
1
12
11
10
9
VDD
S1B
S2B
S3B
2
3
4
Not to scale
Not to scale
Pin Functions TMUX1209
PIN
TSSOP
1
TYPE(1)
DESCRIPTION
NAME
UQFN
A0
15
I
I
Address line 0. Controls the switch configuration as shown in 表 2.
Active high logic input. When this pin is low, all switches are turned off. When this pin is high,
the A[1:0] address inputs determine which switch is turned on.
EN
2
16
N.C.
S1A
S2A
S3A
S4A
DA
3
4
1
2
Not Connected
Not Connected
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Source pin 1A. Can be an input or output.
Source pin 2A. Can be an input or output.
Source pin 3A. Can be an input or output.
Source pin 4A. Can be an input or output.
Drain pin A. Can be an input or output.
Drain pin B. Can be an input or output.
Source pin 4B. Can be an input or output.
Source pin 3B. Can be an input or output.
Source pin 2B. Can be an input or output.
Source pin 1B. Can be an input or output.
5
3
6
4
7
5
8
6
DB
9
7
S4B
S3B
S2B
S1B
10
11
12
13
8
9
10
11
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
14
12
P
GND
A1
15
16
13
14
P
I
Ground (0 V) reference
Address line 1. Controls the switch configuration as shown in 表 2.
(1) I = input, O = output, I/O = input and output, P = power
4
Copyright © 2018, Texas Instruments Incorporated
TMUX1208, TMUX1209
www.ti.com.cn
ZHCSIN2C –AUGUST 2018–REVISED DECEMBER 2018
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
(2) (3)
MIN
–0.3
–0.3
–30
–0.5
–30
–65
MAX
UNIT
V
VDD
Supply voltage
6
6
VSEL or VEN
ISEL or IEN
VS or VD
IS or ID (CONT)
Tstg
Logic control input pin voltage (EN, A0, A1, A2)
Logic control input pin current (EN, A0, A1, A2)
Source or drain voltage (Sx, D)
Source or drain continuous current (Sx, D)
Storage temperature
V
30
mA
V
VDD+0.5
30
mA
°C
°C
150
TJ
Junction temperature
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.08
0
NOM
MAX
5.5
UNIT
V
VDD
Supply voltage
VS or VD
Signal path input/output voltage (source or drain pin) (Sx, D)
VDD
V
VSEL or
VEN
Logic control input pin voltage (EN, A0, A1, A2)
Ambient temperature
0
5.5
V
TA
–40
125
°C
7.4 Thermal Information
TMUX1208 / TMUX1209
THERMAL METRIC
PW (TSSOP)
RSV (QFN)
16 PINS
134.6
74.3
UNIT
16 PINS
118.9
49.3
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
65.2
62.8
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7.6
4.3
ΨJB
64.6
61.1
RθJC(bot)
N/A
N/A
Copyright © 2018, Texas Instruments Incorporated
5
TMUX1208, TMUX1209
ZHCSIN2C –AUGUST 2018–REVISED DECEMBER 2018
www.ti.com.cn
7.5 Electrical Characteristics (VDD = 5 V ±10 %)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
5
Ω
VS = 0 V to VDD
RON
On-resistance
ISD = 10 mA
Refer to On-Resistance
–40°C to +85°C
–40°C to +125°C
25°C
7
9
Ω
Ω
0.15
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
On-resistance matching between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
1
1
Ω
Ω
1.5
2
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
RON
FLAT
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
Ω
3
Ω
VDD = 5 V
Switch Off
VD = 4.5 V / 1 V
VS = 1 V / 4.5 V
Refer to Off-Leakage Current
±75
nA
nA
–40°C to +85°C
-150
-175
150
175
IS(OFF)
Source off leakage current(1)
–40°C to +125°C
nA
VDD = 5 V
Switch Off
VD = 4.5 V / 1 V
VS = 1 V / 4.5 V
Refer to Off-Leakage Current
25°C
±200
±200
nA
nA
–40°C to +85°C
-500
-750
500
750
ID(OFF) Drain off leakage current(1)
–40°C to +125°C
nA
VDD = 5 V
Switch On
VD = VS = 4.5 V / 1 V
Refer to On-Leakage Current
25°C
nA
nA
ID(ON)
–40°C to +85°C
-500
-750
500
750
Channel on leakage current
IS(ON)
–40°C to +125°C
nA
LOGIC INPUTS (EN, A0, A1, A2)
VIH
VIL
Input logic high
Input logic low
-40°C to 125°C
-40°C to 125°C
1.49
0
5.5
V
V
0.87
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.10
2
CIN
CIN
Logic input capacitance
Logic input capacitance
25°C
1
pF
pF
–40°C to +125°C
POWER SUPPLY
25°C
0.02
µA
µA
IDD
VDD supply current
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
2.7
(1) When VS is 4.5 V, VD is 1 V, and vice versa.
6
Copyright © 2018, Texas Instruments Incorporated
TMUX1208, TMUX1209
www.ti.com.cn
ZHCSIN2C –AUGUST 2018–REVISED DECEMBER 2018
Electrical Characteristics (VDD = 5 V ±10 %) (continued)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
14
ns
VS = 3 V
tTRAN
Transition time between channels
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
–40°C to +85°C
–40°C to +125°C
25°C
33
33
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
14
5
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
tOPEN
(BBM)
Break before make time
–40°C to +85°C
–40°C to +125°C
25°C
1
1
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
tON(EN) Enable turn-on time
tOFF(EN) Enable turn-off time
–40°C to +85°C
–40°C to +125°C
25°C
20
20
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
–40°C to +85°C
–40°C to +125°C
20
20
VS = VDD/2
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
25°C
25°C
25°C
25°C
±9
-62
-42
-62
-42
pC
dB
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
Bandwidth - TMUX1208
25°C
25°C
65
MHz
MHz
BW
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
Bandwidth - TMUX1209
Source off capacitance
125
CSOFF
CDOFF
f = 1 MHz
25°C
25°C
25°C
25°C
25°C
13
76
38
85
42
pF
pF
pF
pF
pF
Drain off capacitance - TMUX1208 f = 1 MHz
Drain off capacitance - TMUX1209 f = 1 MHz
On capacitance - TMUX1208
On capacitance - TMUX1209
f = 1 MHz
f = 1 MHz
CSON
CDON
Copyright © 2018, Texas Instruments Incorporated
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TMUX1208, TMUX1209
ZHCSIN2C –AUGUST 2018–REVISED DECEMBER 2018
www.ti.com.cn
7.6 Electrical Characteristics (VDD = 3.3 V ±10 %)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
9
Ω
VS = 0 V to VDD
RON
On-resistance
ISD = 10 mA
Refer to On-Resistance
–40°C to +85°C
–40°C to +125°C
25°C
15
17
Ω
Ω
0.15
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
On-resistance matching between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
1
1
Ω
Ω
3
5
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
RON
FLAT
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
Ω
6
Ω
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
VS = 1 V / 3 V
±75
nA
nA
–40°C to +85°C
-150
-175
150
175
IS(OFF)
Source off leakage current(1)
–40°C to +125°C
nA
Refer to Off-Leakage Current
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
VS = 1 V / 3 V
25°C
±200
±200
nA
nA
–40°C to +85°C
-500
-750
500
750
ID(OFF) Drain off leakage current(1)
–40°C to +125°C
nA
Refer to Off-Leakage Current
VDD = 3.3 V
Switch On
VD = VS = 3 V / 1 V
Refer to On-Leakage Current
25°C
nA
nA
ID(ON)
–40°C to +85°C
-500
-750
500
750
Channel on leakage current
IS(ON)
–40°C to +125°C
nA
LOGIC INPUTS (EN, A0, A1, A2)
VIH
VIL
Input logic high
Input logic low
-40°C to 125°C
-40°C to 125°C
1.35
0
5.5
0.8
V
V
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.10
2
CIN
CIN
Logic input capacitance
Logic input capacitance
25°C
1
pF
pF
–40°C to +125°C
POWER SUPPLY
25°C
0.01
µA
µA
IDD
VDD supply current
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
1.5
(1) When VS is 3 V, VD is 1 V, and vice versa.
8
Copyright © 2018, Texas Instruments Incorporated
TMUX1208, TMUX1209
www.ti.com.cn
ZHCSIN2C –AUGUST 2018–REVISED DECEMBER 2018
Electrical Characteristics (VDD = 3.3 V ±10 %) (continued)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
14
ns
VS = 2 V
tTRAN
Transition time between channels
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
–40°C to +85°C
–40°C to +125°C
25°C
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
14
7
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
tOPEN
(BBM)
Break before make time
–40°C to +85°C
–40°C to +125°C
25°C
1
1
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
tON(EN) Enable turn-on time
tOFF(EN) Enable turn-off time
–40°C to +85°C
–40°C to +125°C
25°C
25
25
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
–40°C to +85°C
–40°C to +125°C
13
13
VS = VDD/2
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
25°C
25°C
25°C
25°C
±7
-62
-42
-62
-42
pC
dB
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
Bandwidth - TMUX1208
25°C
25°C
65
MHz
MHz
BW
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
Bandwidth - TMUX1209
Source off capacitance
125
CSOFF
CDOFF
f = 1 MHz
25°C
25°C
25°C
25°C
25°C
13
76
38
85
42
pF
pF
pF
pF
pF
Drain off capacitance - TMUX1208 f = 1 MHz
Drain off capacitance - TMUX1209 f = 1 MHz
On capacitance - TMUX1208
On capacitance - TMUX1209
f = 1 MHz
f = 1 MHz
CSON
CDON
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www.ti.com.cn
7.7 Electrical Characteristics (VDD = 1.8 V ±10 %)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
40
Ω
VS = 0 V to VDD
RON
On-resistance
ISD = 10 mA
Refer to On-Resistance
–40°C to +85°C
–40°C to +125°C
25°C
80
80
Ω
Ω
0.15
±75
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
On-resistance matching between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
1.5
1.5
Ω
Ω
VDD = 1.98 V
Switch Off
VD = 1.8 V / 1 V
VS = 1 V / 1.8 V
Refer to Off-Leakage Current
nA
nA
–40°C to +85°C
-150
-175
150
175
IS(OFF)
Source off leakage current(1)
–40°C to +125°C
nA
VDD = 1.98 V
Switch Off
VD = 1.8 V / 1 V
VS = 1 V / 1.8 V
Refer to Off-Leakage Current
25°C
±200
±200
nA
nA
–40°C to +85°C
-500
-750
500
750
ID(OFF) Drain off leakage current(1)
–40°C to +125°C
nA
VDD = 1.98 V
Switch On
VD = VS = 1.8 V / 1 V
Refer to On-Leakage Current
25°C
nA
nA
ID(ON)
–40°C to +85°C
-500
-750
500
750
Channel on leakage current
IS(ON)
–40°C to +125°C
nA
LOGIC INPUTS (EN, A0, A1, A2)
VIH
VIL
Input logic high
Input logic low
–40°C to +125°C
–40°C to +125°C
1.07
0
5.5
V
V
0.68
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.10
2
25°C
1
pF
pF
CIN
Logic input capacitance
–40°C to +125°C
POWER SUPPLY
25°C
0.006
µA
µA
IDD
VDD supply current
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
0.95
(1) When VS is 1.8 V, VD is 1 V, and vice versa.
10
Copyright © 2018, Texas Instruments Incorporated
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ZHCSIN2C –AUGUST 2018–REVISED DECEMBER 2018
Electrical Characteristics (VDD = 1.8 V ±10 %) (continued)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
28
ns
VS = 1 V
tTRAN
Transition time between channels
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
–40°C to +85°C
–40°C to +125°C
25°C
48
48
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16
28
16
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
tOPEN
(BBM)
Break before make time
–40°C to +85°C
–40°C to +125°C
25°C
1
1
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
tON(EN) Enable turn-on time
tOFF(EN) Enable turn-off time
–40°C to +85°C
–40°C to +125°C
25°C
48
48
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
–40°C to +85°C
–40°C to +125°C
27
27
VS = VDD/2
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
25°C
25°C
25°C
25°C
-2
-62
-42
-62
-42
pC
dB
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
Bandwidth - TMUX1208
25°C
25°C
65
MHz
MHz
BW
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
Bandwidth - TMUX1209
Source off capacitance
125
CSOFF
CDOFF
f = 1 MHz
25°C
25°C
25°C
25°C
25°C
13
76
38
85
42
pF
pF
pF
pF
pF
Drain off capacitance - TMUX1208 f = 1 MHz
Drain off capacitance - TMUX1209 f = 1 MHz
On capacitance - TMUX1208
On capacitance - TMUX1209
f = 1 MHz
f = 1 MHz
CSON
CDON
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7.8 Electrical Characteristics (VDD = 1.2 V ±10 %)
at TA = 25°C, VDD = 1.2 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
70
Ω
VS = 0 V to VDD
RON
On-resistance
ISD = 10 mA
Refer to On-Resistance
–40°C to +85°C
–40°C to +125°C
25°C
105
105
Ω
Ω
0.15
±75
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
On-resistance matching between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
1.5
1.5
Ω
Ω
VDD = 1.32 V
Switch Off
VD = 1.2 V / 1 V
VS = 1 V / 1.2 V
Refer to Off-Leakage Current
nA
nA
–40°C to +85°C
-150
-175
150
175
IS(OFF)
Source off leakage current(1)
–40°C to +125°C
nA
VDD = 1.32 V
Switch Off
VD = 1.2 V / 1 V
VS = 1 V / 1.2 V
Refer to Off-Leakage Current
25°C
±200
±200
nA
nA
–40°C to +85°C
-500
-750
500
750
ID(OFF) Drain off leakage current(1)
–40°C to +125°C
nA
VDD = 1.32 V
Switch On
VD = VS = 1.2 V / 1 V
Refer to On-Leakage Current
25°C
nA
nA
ID(ON)
–40°C to +85°C
-500
-750
500
750
Channel on leakage current
IS(ON)
–40°C to +125°C
nA
LOGIC INPUTS (EN, A0, A1, A2)
VIH
VIL
Input logic high
Input logic low
–40°C to +125°C
–40°C to +125°C
0.96
0
5.5
V
V
0.36
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.10
2
25°C
1
pF
pF
CIN
Logic input capacitance
–40°C to +125°C
POWER SUPPLY
25°C
0.005
µA
µA
IDD
VDD supply current
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
0.8
(1) When VS is 1.2 V, VD is 1 V, and vice versa.
12
Copyright © 2018, Texas Instruments Incorporated
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ZHCSIN2C –AUGUST 2018–REVISED DECEMBER 2018
Electrical Characteristics (VDD = 1.2 V ±10 %) (continued)
at TA = 25°C, VDD = 1.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
60
ns
VS = 1 V
tTRAN
Transition time between channels
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
–40°C to +85°C
–40°C to +125°C
25°C
210
210
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
28
60
45
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
tOPEN
(BBM)
Break before make time
–40°C to +85°C
–40°C to +125°C
25°C
1
1
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
tON(EN) Enable turn-on time
tOFF(EN) Enable turn-off time
–40°C to +85°C
–40°C to +125°C
25°C
190
190
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
–40°C to +85°C
–40°C to +125°C
150
150
VS = VDD/2
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
25°C
25°C
25°C
25°C
±2
-62
-42
-62
-42
pC
dB
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
Bandwidth - TMUX1208
25°C
25°C
65
MHz
MHz
BW
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
Bandwidth - TMUX1209
Source off capacitance
125
CSOFF
CDOFF
f = 1 MHz
25°C
25°C
25°C
25°C
25°C
13
76
38
85
42
pF
pF
pF
pF
pF
Drain off capacitance - TMUX1208 f = 1 MHz
Drain off capacitance - TMUX1209 f = 1 MHz
On capacitance - TMUX1208
On capacitance - TMUX1209
f = 1 MHz
f = 1 MHz
CSON
CDON
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www.ti.com.cn
7.9 Typical Characteristics
at TA = 25°C, VDD = 5 V (unless otherwise noted)
80
10
8
VDD= 1.08V
60
TA = +125èC
TA = +85èC
6
40
4
VDD= 1.62V
20
2
VDD= 3V
VDD= 4.5V
4.5
TA = -40èC
TA = +25èC
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
5
0
0.5
1
1.5
2
2.5
3
3.5
Source or Drain Voltage (V)
Source or Drain Voltage (V)
D001
D002
TA = 25°C
VDD= 3 V
图 1. On-Resistance vs Source or Drain Voltage
图 2. On-Resistance vs Source or Drain Voltage
30
27
24
21
18
15
12
9
20
16
12
8
TON
TON
TOFF
4
TOFF
6
3
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-60
-30
0
30
60
90
120
150
VDD - Supply Voltage (V)
TA - Temperature (èC)
D003
D004
TA = 25°C
VDD= 3.3 V
图 3. TON (EN) and TOFF (EN) vs Supply Voltage
图 4. TON (EN) and TOFF (EN) vs Temperature
0
30
-10
25
20
15
10
5
-20
-30
-40
-50
-60
-70
-80
-90
-100
TTRANSITION_FALLING
TTRANSITION_RISING
TMUX1208 Bandwidth
TMUX1209 Bandwidth
Off-Isolation
0
100k
1M
10M
100M
0.5
1.5
2.5
3.5
4.5
5.5
Frequency (Hz)
VDD - Supply Voltage (V)
D006
D005
TA = 25°C
TA = 25°C
图 6. Frequency Response
图 5. TTRANSITION vs Supply Voltage
14
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ZHCSIN2C –AUGUST 2018–REVISED DECEMBER 2018
8 Detailed Description
8.1 Overview
8.1.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance.
The measurement setup used to measure RON is shown below. Voltage (V) and current (ISD) are measured using
this setup, and RON is computed as shown in 图 7 with RON = V / ISD
:
V
ISD
Sx
D
VS
图 7. On-Resistance Measurement Setup
8.1.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF)
.
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF)
.
The setup used to measure both off-leakage currents is shown in 图 8.
VDD
VDD
VDD
VDD
Is (OFF)
S1
S2
S1
A
ID (OFF)
S2
D
D
A
VS
S8
S8
VS
VD
VD
GND
GND
图 8. Off-Leakage Measurement Setup
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Overview (接下页)
8.1.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON)
.
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON)
.
Either the source pin or drain pin is left floating during the measurement. 图 9 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON)
.
VDD
VDD
VDD
VDD
IS (ON)
S1
S1
S2
A
N.C.
ID (ON)
S2
D
D
A
N.C.
S8
S8
Vs
VS
VS
VD
GND
GND
图 9. On-Leakage Measurement Setup
8.1.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the address signal
has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of
the device, system level timing can then account for the time constant added from the load resistance and load
capacitance. 图 10 shows the setup used to measure transition time, denoted by the symbol tTRANSITION
.
VDD
0.1…F
VDD
VDD
ADDRESS
tf < 5ns
tr < 5ns
DRIVE
(VSEL
VIH
S1
)
VS
OUTPUT
VIL
D
0 V
S2
S8
RL
CL
tTRANSITION
tTRANSITION
A0
A1
A2
90%
OUTPUT
VSEL
10%
GND
0 V
图 10. Transition-Time Measurement Setup
16
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ZHCSIN2C –AUGUST 2018–REVISED DECEMBER 2018
Overview (接下页)
8.1.5 Break-Before-Make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. 图 11 shows the
setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM)
.
VDD
0.1…F
VDD
VDD
S1
ADDRESS
DRIVE
VS
OUTPUT
D
tr < 5ns
tf < 5ns
(VSEL
)
S2-S7
0 V
RL
CL
S8
90%
Output
A0
A1
A2
tBBM
1
tBBM 2
0 V
VSEL
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
GND
图 11. Break-Before-Make Delay Measurement Setup
8.1.6 tON(EN) and tOFF(EN)
Turn-on time is defined as the time taken by the output of the device to rise to 10% after the enable has risen
past the logic threshold. The 10% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. 图 12 shows the
setup used to measure transition time, denoted by the symbol tON(EN)
.
Turn-off time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen
past the logic threshold. The 90% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. 图 12 shows the
setup used to measure transition time, denoted by the symbol tOFF(EN)
.
VDD
0.1…F
VDD
VDD
tf < 5ns
tr < 5ns
ENABLE
DRIVE
S1
VS
OUTPUT
VIH
(VEN
)
D
VIL
S2
S8
0 V
RL
CL
tOFF
tON
(EN)
(EN)
A0
A1
A2
EN
90%
OUTPUT
0 V
VEN
10%
GND
图 12. Turn-On and Turn-Off Time Measurement Setup
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Overview (接下页)
8.1.7 Charge Injection
The TMUX1208 and TMUX1209 have a transmission-gate topology. Any mismatch in capacitance between the
NMOS and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge
of the gate signal. The amount of charge injected into the source or drain of the device is known as charge
injection, and is denoted by the symbol QC. 图 13 shows the setup used to measure charge injection from source
(Sx) to drain (D).
VDD
0.1…F
VDD
VDD
S1
VS
OUTPUT
D
VOUT
CL
0 V
S2
S8
Output
VOUT
VS
QC = CL
×
VOUT
A0
EN
A1
A2
VEN
GND
图 13. Charge-Injection Measurement Setup
8.1.8 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. 图 14 shows the setup used to measure, and the equation to compute off
isolation.
0.1µF
NETWORK
VDD
ANALYZER
VS
S
50Q
VSIG
D
VOUT
RL
50Q
SX/DX
GND
RL
50Q
图 14. Off Isolation Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Off Isolation = 20 ∂ Log
(1)
18
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Overview (接下页)
8.1.9 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. 图 15 shows the setup used to measure, and the equation used to
compute crosstalk.
0.1µF
NETWORK
VDD
ANALYZER
S1
VOUT
RL
D
50Q
VS
RL
S2
50Q
50Q
VSIG
SX
RL
GND
50Q
图 15. Channel-to-Channel Crosstalk Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Channel-to-Channel Crosstalk = 20 ∂ Log
(2)
8.1.10 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. 图 16
shows the setup used to measure bandwidth.
0.1µF
NETWORK
VDD
ANALYZER
VS
S
50Q
VSIG
D
VOUT
RL
50Q
GND
图 16. Bandwidth Measurement Setup
≈
∆
«
’
÷
◊
V2
Attenuation = 20 ∂ Log
V
1
(3)
19
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www.ti.com.cn
8.2 Functional Block Diagram
The TMUX1208 is an 8:1, single-ended (1-ch.), mux. The TMUX1209 is an 4:1, differential (2-ch.), mux. Each
channel is turned on or turned off based on the state of the address lines and enable pin.
TMUX1208
TMUX1209
S1A
S2A
S3A
S4A
S1
S2
S3
S4
S5
S6
S7
S8
DA
DB
D
S1B
S2B
S3B
S4B
1-OF-8
1-OF-4
DECODER
DECODER
A0
A1
EN
A0 A1 A2 EN
图 17. TMUX1208, TMUX1209 Functional Block Diagrams
8.3 Feature Description
8.3.1 Bidirectional Operation
The TMUX1208 and TMUX1209 conduct equally well from source (Sx) to drain (D) or from drain (D) to source
(Sx). Each channel has very similar characteristics in both directions and supports both analog and digital
signals.
8.3.2 Rail to Rail Operation
The valid signal path input/output voltage for TMUX1208 and TMUX1209 ranges from GND to VDD
.
8.3.3 1.8 V Logic Compatible Inputs
The TMUX1208 and TMUX1209 has 1.8-V logic compatible control for all logic control inputs. The logic input
thresholds scale with supply but still provide 1.8-V logic control when operating at 5.5 V supply voltage. 1.8-V
logic level inputs allows the multiplexers to interface with processors that have lower logic I/O rails and eliminates
the need for an external translator, which saves both space and BOM cost. For more information on 1.8 V logic
implementations refer to Simplifying Design with 1.8 V logic Muxes and Switches
8.3.4 Fail-Safe Logic
The TMUX1208 and TMUX1209 have Fail-Safe Logic on the control input pins (EN, A0. A1, A2) allowing for
operation up to 5.5 V, regardless of the state of the supply pin. This feature allows voltages on the control pins to
be applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system
complexity by removing the need for power supply sequencing on the logic control pins. For example, the Fail-
Safe Logic feature allows the select pins of the TMUX1208 or TMUX1209 to be ramped to 5.5 V while VDD = 0 V.
Additionally, the feature enables operation of the multiplexers with VDD = 1.2 V while allowing the select pins to
interface with a logic level of another device up to 5.5 V.
20
版权 © 2018, Texas Instruments Incorporated
TMUX1208, TMUX1209
www.ti.com.cn
ZHCSIN2C –AUGUST 2018–REVISED DECEMBER 2018
Feature Description (接下页)
8.3.5 Device Functional Modes
When the EN pin of the TMUX1208 is pulled high, one of the switches is closed based on the state of the
address lines. Similarly, when the EN pin of the TMUX1209 is pulled high, two of the switches are closed based
on the state of the address lines. When the EN pin is pulled low, all the switches are in an open state regardless
of the state of the address lines.
8.3.6 Truth Tables
表 1 and 表 2 show the truth tables for the TMUX1208 and TMUX1209, respectively.
表 1. TMUX1208 Truth Table
EN A2 A1 A0
Selected Inputs Connected To Drain (D) Pin
0
1
1
1
1
1
1
1
1
X(1) X(1) X(1)
All channels are off
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
S1
S2
S3
S4
S5
S6
S7
S8
(1) X denotes don't care.
表 2. TMUX1209 Truth Table
EN A1 A0 Selected Input Connected To Drain (DA, DB) Pins
0
1
1
1
1
X(1) X(1)
All channels are off
S1A and S1B
S2A and S2B
S3A and S3B
S4A and S4B
0
0
1
1
0
1
0
1
(1) X denotes don't care.
版权 © 2018, Texas Instruments Incorporated
21
TMUX1208, TMUX1209
ZHCSIN2C –AUGUST 2018–REVISED DECEMBER 2018
www.ti.com.cn
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TMUX12xx family offers good system performance across a wide operating supply (1.08V to 5.5V). These
devices include 1.8V logic compatible control input pins that enable operation in systems with 1.8V I/O rails.
Additionally, the control input pins support Fail-Safe Logic which allows for operation up to 5.5V, regardless of
the state of the supply pin. This protection stops the logic pins from back-powering the supply rail. These
features make the TMUX12xx a family of general purpose multiplexers and switches that can reduce system
complexity, board size, and overall system cost.
9.2 Typical Application
One useful application to take advantage of the TMUX1208 features is multiplexing various signals into an ADC
that is integrated into a MCU. Utilizing an integrated ADC in a MCU allows a system to minimize cost with a
potential tradeoff of system performance when compared to an external ADC. The multiplexer allows for multiple
inputs/sensors to be monitored with a single ADC pin of the device, which is critical in systems with limited I/O.
The TMUX1209 is suitable for similar design example using differential signals, or as two 4:1 multiplexers.
VDD
VDD
VI/O
VDD
EN
LDO #1
MCU
S1
S2
S3
S4
S5
S6
S7
S8
LDO #2
LDO #3
RAM
FLASH
D
Integrated
12-bit ADC
LM20
Analog Temp.
Sensor
LM20
Analog Temp.
Sensor
Port I/O
TIMERS
A2
A1
LM20
Analog Temp.
Sensor
A0
GND
1.8V Logic
I/O
System Inputs &
Sensors
图 18. Multiplexing Signals to Integrated ADC
9.3 Design Requirements
For this design example, use the parameters listed in 表 3.
表 3. Design Parameters
PARAMETERS
Supply (VDD
VALUES
5.0 V
)
I/O signal range
0 V to VDD (Rail to Rail)
1.8 V compatible
Control logic thresholds
22
版权 © 2018, Texas Instruments Incorporated
TMUX1208, TMUX1209
www.ti.com.cn
ZHCSIN2C –AUGUST 2018–REVISED DECEMBER 2018
9.4 Detailed Design Procedure
The TMUX1208 and TMUX1209 can be operated without any external components except for the supply
decoupling capacitors. If the parts desired power-up state is disabled, the enable pin should have a weak pull-
down resistor and be controlled by the MCU via GPIO. All inputs being muxed to the ADC of the MCU must fall
within the recommend operating conditions of the TMUX1208 and TMUX1209 including signal range and
continuous current. For this design with a supply of 5 V the signal range can be 0 V to 5 V and the max
continuous current can be 30 mA.
9.5 Application Curve
80
VDD= 1.08V
60
40
VDD= 1.62V
20
VDD= 3V
VDD= 4.5V
4.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
5
Source or Drain Voltage (V)
D001
TA = 25°C
图 19. On-Resistance vs Source or Drain Voltage
10 Power Supply Recommendations
The TMUX1208 and TMUX1209 operate across a wide supply range of 1.08 V to 5.5 V. Do not exceed the
absolute maximum ratings because stresses beyond the listed ratings can cause permanent damage to the
devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply to
other components. Good power-supply decoupling is important to achieve optimum performance. For improved
supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to ground.
Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance
connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series
resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive
systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to
the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall
inductance and is beneficial for connections to ground planes.
版权 © 2018, Texas Instruments Incorporated
23
TMUX1208, TMUX1209
ZHCSIN2C –AUGUST 2018–REVISED DECEMBER 2018
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
11.1.1 Layout Information
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. 图 20 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
1W min.
W
图 20. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, through-
hole pins are not recommended at high frequencies.
图 21 illustrates an example of a PCB layout with the TMUX1208. Some key considerations are:
•
Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
•
•
•
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
Via to
ground plane
A0
EN
A1
A2
Wide (low inductance)
trace for power
C
GND
VDD
N.C.
Via to
ground plane
S1
S2
S3
S4
D
S5
S6
S7
S8
TMUX1208
图 21. TMUX1208 Layout Example
24
版权 © 2018, Texas Instruments Incorporated
TMUX1208, TMUX1209
www.ti.com.cn
ZHCSIN2C –AUGUST 2018–REVISED DECEMBER 2018
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
德州仪器 (TI)，《使用 1.8V 逻辑多路复用器和开关简化设计》。
德州仪器 (TI)，《QFN/SON PCB 连接》。
Texas Instruments, 《四方扁平封装无引线逻辑封装》。
12.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 4. 相关链接
器件
产品文件夹
单击此处
单击此处
立即订购
单击此处
单击此处
技术文档
单击此处
单击此处
工具与软件
单击此处
单击此处
支持和社区
单击此处
单击此处
TMUX1208
TMUX1209
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.5 商标
E2E is a trademark of Texas Instruments.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2018, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX1208PWR
TMUX1208RSVR
TMUX1209PWR
TMUX1209RSVR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
UQFN
TSSOP
UQFN
PW
RSV
PW
16
16
16
16
2000 RoHS & Green
3000 RoHS & Green
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TM1208
NIPDAUAG
NIPDAU
1B4
TM1209
1D2
RSV
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX1208PWR
TMUX1208RSVR
TMUX1209PWR
TMUX1209RSVR
TSSOP
UQFN
TSSOP
UQFN
PW
RSV
PW
16
16
16
16
2000
3000
2000
3000
330.0
178.0
330.0
178.0
12.4
13.5
12.4
13.5
6.9
2.1
6.9
2.1
5.6
2.9
5.6
2.9
1.6
0.75
1.6
8.0
4.0
8.0
4.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
RSV
0.75
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMUX1208PWR
TMUX1208RSVR
TMUX1209PWR
TMUX1209RSVR
TSSOP
UQFN
TSSOP
UQFN
PW
RSV
PW
16
16
16
16
2000
3000
2000
3000
356.0
189.0
356.0
189.0
356.0
185.0
356.0
185.0
35.0
36.0
35.0
36.0
RSV
Pack Materials-Page 2
PACKAGE OUTLINE
RSV0016A
UQFN - 0.55 mm max height
S
C
A
L
E
5
.
0
0
0
ULTRA THIN QUAD FLATPACK - NO LEAD
1.85
1.75
A
B
PIN 1 INDEX AREA
2.65
2.55
C
0.55
0.45
SEATING PLANE
0.05 C
0.05
0.00
2X 1.2
SYMM
℄
(0.13) TYP
5
8
0.45
0.35
15X
4
9
SYMM
℄
2X 1.2
12X 0.4
1
0.25
16X
12
0.15
0.07
0.05
C A B
13
16
0.55
0.45
PIN 1 ID
(45° X 0.1)
4220314/C 02/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
SYMM
℄
(0.7)
16
SEE SOLDER MASK
DETAIL
13
12
16X (0.2)
1
SYMM
℄
12X (0.4)
(2.4)
(R0.05) TYP
9
4
15X (0.6)
5
8
(1.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220314/C 02/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
(0.7)
16
13
16X (0.2)
1
12
SYMM
℄
12X (0.4)
(2.4)
(R0.05) TYP
4
9
15X (0.6)
5
8
SYMM
℄
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 25X
4220314/C 02/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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