TMUX1309QPWRQ1 [TI]
TMUX13xx-Q1 5-V, Bidirectional 8:1, 1-Channel and 4:1, 2-Channel Multiplexers with Injection Current Control;
| 型号： | TMUX1309QPWRQ1 |
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TEXAS INSTRUMENTS |
| 描述： | TMUX13xx-Q1 5-V, Bidirectional 8:1, 1-Channel and 4:1, 2-Channel Multiplexers with Injection Current Control |
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TMUX1308-Q1,TMUX1309-Q1
SCDS414C – DECEMBER 2019 – REVISED AUGUST 2020
TMUX13xx-Q1 5-V, Bidirectional 8:1, 1-Channel and 4:1, 2-Channel
Multiplexers with Injection Current Control
1 Features
3 Description
•
AEC-Q100 Qualified for Automotive Applications
The TMUX1308-Q1 and TMUX1309-Q1 are general
purpose complementary metal-oxide semiconductor
(CMOS) multiplexers (MUX). The TMUX1308-Q1 is
an 8:1, 1-channel (single-ended) mux, while the
TMUX1309-Q1 is a 4:1, 2-channel (differential) mux.
The devices support bidirectional analog and digital
signals on the source (Sx) and drain (Dx) pins ranging
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature
Injection Current Control
•
•
Back-powering Protection
– No ESD Diode Path to VDD
Wide Supply Range: 1.62 V to 5.5 V
Low Capacitance
Bidirectional Signal Path
Rail-to-Rail Operation
1.8 V Logic Compatible
Fail-safe Logic
Break-before-make Switching
Functional Safety-Capable
– Documentation Available to Aid Functional
Safety System Design
•
•
•
•
•
•
•
•
from GND to VDD
.
The TMUX13xx-Q1 devices have an internal injection
current control feature which eliminates the need for
external diode and resistor networks typically used to
protect the switch and keep the input signals within
the supply voltage. The internal injection current
control circuitry allows signals on disabled signal
paths to exceed the supply voltage without affecting
the signal of the enabled signal path. Additionally, the
TMUX13xx-Q1 devices do not have any internal diode
path to the supply pin, which eliminates the risk of
damaging components connected to the supply pin, or
providing unintended power to the supply rail.
•
•
TMUX1308-Q1 - Pin Compatible with:
– Industry Standard 4051 and 4851 Multiplexers
TMUX1309-Q1 - Pin Compatible with:
– Industry Standard 4052 and 4852 Multiplexers
All logic inputs have 1.8 V logic compatible
thresholds, ensuring both TTL and CMOS logic
compatibility when operating with a valid supply
voltage. Fail-Safe Logic circuitry allows voltages on
the control pins to be applied before the supply pin,
protecting the device from potential damage.
2 Applications
•
•
•
•
•
•
•
•
Analog and Digital Multiplexing and Demultiplexing
Diagnostics and Monitoring
Body Control Modules
Battery Management Systems (BMS)
HVAC Control Module
Automotive Head Unit
Telematics
On-board (OBC) and Wireless Charging
Device Information
PART NUMBER(1)
PACKAGE
BODY SIZE (NOM)
5.00 mm × 4.40 mm
4.20 mm x 2.00 mm
3.50 mm x 2.50 mm
TSSOP (16)
TMUX1308-Q1
TMUX1309-Q1
SOT-23-THIN (16)
WQFN (16)
(1) For all available packages, see the package option
addendum at the end of the data sheet.
TMUX1308-Q1
TMUX1309-Q1
S0A
S1A
S2A
S3A
S0
S1
S2
S3
S4
S5
S6
S7
DA
DB
D
S0B
S1B
S2B
S3B
1-OF-8
1-OF-4
DECODER
DECODER
A0
A1
EN
A0 A1 A2 EN
TMUX1308-Q1 and TMUX1309-Q1 Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX1308-Q1, TMUX1309-Q1
SCDS414C – DECEMBER 2019 – REVISED AUGUST 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
Pin Functions TMUX1308-Q1 ..........................................4
Pin Functions TMUX1309-Q1 ..........................................6
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings........................................ 7
7.2 ESD Ratings............................................................... 7
7.3 Recommended Operating Conditions.........................7
7.4 Thermal Information: TMUX1308-Q1..........................8
7.5 Thermal Information: TMUX1309-Q1..........................8
7.6 Electrical Characteristics.............................................9
7.7 Logic and Dynamic Characteristics...........................10
7.8 Timing Characteristics...............................................11
7.9 Injection Current Coupling........................................ 12
7.10 Typical Characteristics............................................13
8 Detailed Description......................................................16
8.1 Overview...................................................................16
8.2 Functional Block Diagram.........................................22
8.3 Feature Description...................................................22
9 Application and Implementation..................................27
9.1 Application Information............................................. 27
9.2 Typical Application.................................................... 27
9.3 Design Requirements............................................... 28
9.4 Detailed Design Procedure.......................................28
10 Power Supply Recommendations..............................29
11 Layout...........................................................................29
11.1 Layout Guidelines................................................... 29
11.2 Layout Example...................................................... 30
12 Device and Documentation Support..........................31
12.1 Documentation Support.......................................... 31
12.2 Related Links.......................................................... 31
12.3 Receiving Notification of Documentation Updates..31
12.4 Support Resources................................................. 31
12.5 Trademarks.............................................................31
12.6 Electrostatic Discharge Caution..............................31
12.7 Glossary..................................................................31
13 Mechanical, Packaging, and Orderable
Information.................................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (July 2020) to Revision C (August 2020)
Page
•
•
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Added the Typical Characteristics.................................................................................................................... 13
Changes from Revision A (June 2020) to Revision B (July 2020)
Page
•
Added thermal information for TMUX1309-Q1................................................................................................... 8
Changes from Revision * (December 2019) to Revision A (June 2020)
Page
•
Changed status From: Advanced Information To: Production Data ...................................................................1
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SCDS414C – DECEMBER 2019 – REVISED AUGUST 2020
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5 Device Comparison Table
PRODUCT
DESCRIPTION
TMUX1308-Q1
TMUX1309-Q1
8:1, 1-Channel, single-ended multiplexer
4:1, 2-Channel, differential multiplexer
6 Pin Configuration and Functions
S4
S6
D
1
16
15
14
13
12
11
10
9
VDD
S2
S1
S0
S3
A0
A1
A2
S4
S6
D
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
S2
S1
S0
S3
A0
A1
A2
2
3
S7
S5
4
S7
S5
5
6
N.C.
7
N.C.
GND
8
Not to scale
GND
Figure 6-2. TMUX1308-Q1: DYY Package 16-Pin
SOT-23-THIN Top View
Not to scale
Figure 6-1. TMUX1308-Q1: PW Package 16-Pin
TSSOP Top View
S6
D
2
3
4
5
6
7
15
14
13
12
11
10
S2
S1
S0
S3
A0
A1
Thermal
Pad
S7
S5
N.C.
Not to scale
Figure 6-3. TMUX1308-Q1: BQB Package 16-Pin WQFN Top View
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SCDS414C – DECEMBER 2019 – REVISED AUGUST 2020
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Pin Functions TMUX1308-Q1
PIN
TYPE(1)
DESCRIPTION(2)
Source pin 4. Signal path can be an input or output.
NAME
S4
NO.
1
I/O
I/O
I/O
I/O
I/O
S6
2
Source pin 6. Signal path can be an input or output.
Drain pin (common). Signal path can be an input or output.
Source pin 7. Signal path can be an input or output.
Source pin 5. Signal path can be an input or output.
D
3
S7
4
S5
5
Active low logic input. When this pin is high, all switches are turned off. When this pin is low, the A[2:0]
address inputs determine which switch is turned on as shown in Table 8-1.
EN
6
I
N.C.
GND
A2
7
Not Connected
Not Connected.
8
P
I
Ground (0 V) reference
9
Address line 2. Controls the switch configuration as shown in Table 8-1.
Address line 1. Controls the switch configuration as shown in Table 8-1.
Address line 0. Controls the switch configuration as shown in Table 8-1.
Source pin 3. Signal path can be an input or output.
Source pin 0. Signal path can be an input or output.
Source pin 1. Signal path can be an input or output.
Source pin 2. Signal path can be an input or output.
A1
10
11
12
13
14
15
I
A0
I
S3
I/O
I/O
I/O
I/O
S0
S1
S2
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
16
—
P
Exposed thermal pad. No requirement to solder this pad, if connected it should be left floating or tied to
GND.
Thermal pad
Not Connected
(1) I = input, O = output, I/O = input and output, P = power.
(2) Refer to Section 8.3.6 for what to do with unused pins.
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S0B
S2B
DB
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
S2A
S1A
DA
S0B
S2B
DB
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
S2A
S1A
DA
S3B
S1B
S3B
S1B
S0A
S3A
A0
S0A
S3A
A0
N.C.
N.C.
GND
A1
GND
A1
Not to scale
Figure 6-5. TMUX1309-Q1: DYY Package 16-Pin
SOT-23-THIN Top View
Not to scale
Figure 6-4. TMUX1309-Q1: PW Package 16-Pin
TSSOP Top View
S2B
DB
2
3
4
5
6
7
15
14
13
12
11
10
S2A
S1A
DA
Thermal
Pad
S3B
S1B
S0A
S3A
A0
N.C.
Not to scale
Figure 6-6. TMUX1309-Q1: BQB Package 16-Pin WQFN Top View
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SCDS414C – DECEMBER 2019 – REVISED AUGUST 2020
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Pin Functions TMUX1309-Q1
PIN
TYPE(1)
DESCRIPTION(1)
Source pin 0 of mux B. Can be an input or output.
NAME
S0B
S2B
DB
NO.
1
I/O
I/O
I/O
I/O
I/O
2
Source pin 2 of mux B. Can be an input or output.
Drain pin (Common) of mux B. Can be an input or output.
Source pin 3 of mux B. Can be an input or output.
Source pin 1 of mux B. Can be an input or output.
3
S3B
S1B
4
5
Active low logic input. When this pin is high, all switches are turned off. When this pin is low, the A[1:0]
address inputs determine which switch is turned on.
EN
6
I
N.C.
GND
A1
7
Not Connected
Not Connected.
8
P
I
Ground (0 V) reference
9
Address line 1. Controls the switch configuration as shown in Table 8-2.
Address line 0. Controls the switch configuration as shown in Table 8-2.
Source pin 3 of mux A. Can be an input or output.
Source pin 0 of mux A. Can be an input or output.
Drain pin (Common) of mux A. Can be an input or output.
Source pin 1 of mux A. Can be an input or output.
Source pin 3 of mux A. Can be an input or output.
A0
10
11
12
13
14
15
I
S3A
S0A
DA
I/O
I/O
I/O
I/O
I/O
S1A
S2A
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
16
—
P
Exposed thermal pad. No requirement to solder this pad, if connected it should be left floating or tied to
GND.
Thermal pad
Not Connected
(1) Refer to Section 8.3.6 for what to do with unused pins.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
MIN
–0.5
–0.5
–0.5
–30
MAX
6
UNIT
VDD
Supply voltage
VSEL or VEN
VS or VD
ISEL or IEN
IS or ID (CONT)
IS or ID (CONT)
IGND
Logic control input pin voltage (EN, A0, A1, A2)
Source or drain voltage (Sx, D)
6
V
VDD+0.5
30
Logic control input pin current (EN, A0, A1, A2)
Continuous current through switch (Sx, D pins) –40°C to +85°C
Continuous current through switch (Sx, D pins) –40°C to +125°C
Continuous current through GND
–50
50
mA
–25
25
–100
100
500
150
150
Ptot
Total power dissipation(4)
mW
°C
Tstg
Storage temperature
–65
TJ
Junction temperature
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
(4) For TSSOP package: Ptot derates linearily above TA = 80°C by 7.2mW/°C.
For SOT-23-THIN package: Ptot derates linearily above TA = 66°C by 6mW/°C.
7.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per
All pins
All pins
±2000
±750
AEC Q100-002(1)
V(ESD) Electrostatic discharge
V
Charged device model (CDM), per
AEC Q100-011
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX
UNIT
V
VDD
Supply voltage
1.62
0
5.5
VDD
5.5
50
VS or VD
Signal path input/output voltage (source or drain pin) (Sx, D)
Logic control input pin voltage (EN, A0, A1, A2)
Continuous current through switch (Sx, D pins) –40°C to +85°C
Continuous current through switch (Sx, D pins) –40°C to +125°C
V
VSEL or VEN
IS or ID (CONT)
IS or ID (CONT)
0
V
–50
–25
mA
mA
25
Current per input into source or drain pins when singal voltage exceeds
recommended operating voltage (1)
IOK
–50
50
mA
IINJ
Injected current into single off switch input
Total injected current into all off switch inputs combined
Ambient temperature
–50
–100
–40
50
100
125
mA
mA
°C
IINJ_ALL
TA
(1) If source or drain voltage exceeds VDD, or goes below GND, the pin will be shunted to GND through an internal FET, the current must
be limited within the specified value. If Vsignal > VDD or if Vsignal < GND.
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UNIT
SCDS414C – DECEMBER 2019 – REVISED AUGUST 2020
7.4 Thermal Information: TMUX1308-Q1
TMUX1308-Q1
DYY (SOT)
PINS
THERMAL METRIC(1)
PW (TSSOP)
PINS
139.6
77.2
BQB (WQFN)
PINS
94.8
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
167.1
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
106.3
92.6
84.2
90.0
64.5
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
26.5
17.2
13.3
ΨJB
83.8
90.0
64.4
RθJC(bot)
N/A
N/A
42.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information: TMUX1309-Q1
TMUX1309-Q1
THERMAL METRIC(1)
PW (TSSOP)
PINS
139.6
77.2
DYY (SOT)
PINS
172.4
107.0
96.1
BQB (WQFN)
PINS
94.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
92.6
84.2
64.5
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
26.5
19.7
13.3
ΨJB
83.8
95.9
64.4
RθJC(bot)
N/A
N/A
42.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.6 Electrical Characteristics
At specified VDD ±10%
Typical values measured at nominal VDD
Operating free-air temperature (TA)
–40°C to 85°C –40°C to 125°C
MIN TYP MAX
PARAMETER
TEST CONDITIONS
VDD
25°C
TYP MAX
UNIT
MIN
MIN
TYP MAX
ANALOG SWITCH
On-state
1.8 V
2.5 V
3.3 V
5 V
650 1500
1700
670
350
220
21
1700
670
370
270
22
VS = 0 V to VDD
ISD = 0.5 mA
Refer to On-Resistance
230
120
75
10
3
600
330
195
19
RON
switch
Ω
Ω
resistance
On-state
switch
1.8 V
2.5 V
3.3 V
10
12
16
VS = 0 V to VDD
ISD = 0.5 mA
Refer to On-Resistance
resistance
matching
between
inputs
ΔRON
2
8
11
15
5 V
1
7
10
14
1.8 V
2.5 V
3.3 V
5 V
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
2
–25
–25
–25
–25
–45
–45
–45
–45
–45
–45
–45
–45
25 –800
25 –800
25 –800
25 –800
45 –800
45 –800
45 –800
45 –800
45 –800
45 –800
45 –800
45 –800
14
800
800
800
800
800
800
800
800
800
800
800
800
14
Switch Off
Source off-
IS(OFF) state leakage
current
VD = 0.8 x VDD/ 0.2 x VDD
VS = 0.2 x VDD/ 0.8 x VDD
Refer to Off-Leakage
nA
nA
nA
pF
pF
pF
1.8 V
2.5 V
3.3 V
5 V
Drain off-state
leakage
ID(OFF) current
(common
Switch Off
VD = 0.8 x VDD/ 0.2 x VDD
VS = 0.2 x VDD/ 0.8 x VDD
Refer to Off-Leakage
drain pin)
1.8 V
2.5 V
3.3 V
5 V
Switch On
Channel on-
ID(ON)
VD = VS = 0.8 x VDD or
VD = VS = 0.2 x VDD
Refer to On-Leakage
state leakage
IS(ON)
current
1.8 V
2.5 V
3.3 V
5 V
14
14
14
14
37
37
37
37
40
40
40
40
2
14
14
Source off
CSOFF
VS = VDD / 2
f = 1 MHz
capacitance
2
14
14
2
14
14
1.8 V
2.5 V
3.3 V
5 V
7
37
37
7
37
37
Drain off
CDOFF
VS = VDD / 2
f = 1 MHz
capacitance
7
37
37
7
37
37
1.8 V
2.5 V
3.3 V
5 V
11
11
11
11
40
40
40
40
CSON
CDON
On
capacitance
VS = VDD / 2
f = 1 MHz
40
40
40
40
POWER SUPPLY
1.8 V
2.5 V
3.3 V
5 V
1
1
1
1
1
1
1.2
1.5
2
VDD supply
current
IDD
Logic inputs = 0 V or VDD
µA
1
1.5
3
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7.7 Logic and Dynamic Characteristics
At specified VDD ±10%
Typical values measured at nominal VDD and TA = 25°C.
Operating free-air
temperature (TA)
PARAMETER
TEST CONDITIONS
VDD
UNIT
–40°C to 125°C
MIN
TYP
MAX
LOGIC INPUTS (EN, A0, A1, A2)
1.8 V
0.95
1.1
1.15
1.25
0
5.5
5.5
5.5
5.5
0.6
0.7
0.8
0.95
1
2.5 V
3.3 V
5 V
VIH
Input logic high
V
V
1.8 V
2.5 V
3.3 V
5 V
0
VIL
Input logic low
0
0
IIH
IIL
Logic high input leakage current VLOGIC = 1.8 V or VDD
All
uA
uA
Logic low input leakage current
Logic input capacitance
VLOGIC = 0 V
All
–1
VLOGIC = 0 V, 1.8 V, VDD
f = 1 MHz
CIN
All
1
2
pF
DYNAMIC CHARACTERISTICS
1.8 V
2.5 V
3.3 V
5 V
–0.5
–0.5
–1
VS = VDD / 2
RS = 0 Ω, CL = 100 pF
Refer to Charge Injection
QINJ
Charge Injection
Off Isolation
Off Isolation
Crosstalk
pC
–6.5
–110
–110
–110
–110
–90
1.8 V
2.5 V
3.3 V
5 V
VBIAS = VDD / 2
VS = 200 mVpp
RL = 50 Ω, CL = 5 pF
f = 100 kHz
OISO
OISO
XTALK
XTALK
BW
dB
dB
Refer to Off Isolation
1.8 V
2.5 V
3.3 V
5 V
VBIAS = VDD / 2
VS = 200 mVpp
RL = 50 Ω, CL = 5 pF
f = 1 MHz
–90
–90
Refer to Off Isolation
–90
1.8 V
2.5 V
3.3 V
5 V
–110
–110
–110
–110
–90
VBIAS = VDD / 2
VS = 200 mVpp
RL = 50 Ω, CL = 5 pF
f = 100 kHz
dB
Refer to Crosstalk
1.8 V
2.5 V
3.3 V
5 V
VBIAS = VDD / 2
VS = 200 mVpp
RL = 50 Ω, CL = 5 pF
f = 1 MHz
–90
Crosstalk
dB
–90
Refer to Crosstalk
–90
1.8 V
2.5 V
3.3 V
5 V
350
VBIAS = VDD / 2
VS = 200 mVpp
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
450
Bandwidth
MHz
500
500
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7.8 Timing Characteristics
At specified VDD ±10%
Typical values measured at nominal VDD
.
Operating free-air temperature (TA)
PARAMETER
TEST CONDITIONS
VDD
25°C
–40°C to 85°C
–40°C to 125°C
UNIT
MIN TYP MAX
MIN TYP MAX
MIN TYP MAX
SWITCHING CHARACTERISTICS
1.8 V
2.5 V
3.3 V
5 V
15
8
30
15
11
9
30
30
20
20
CL = 50 pF
Sx to D, D to Sx
tPD
Propagation delay
5
15
15 ns
4
10
10
5
CL = 15 pF
5 V
1.5
44
30
23
18
15
39
30
26
24
22
58
21
15
11
8
4
5
1.8 V
2.5 V
3.3 V
5 V
94
63
51
43
39
64
45
38
32
31
80
70
65
40
15
103
103
67
RL = 10 kΩ, CL = 50 pF
Ax to D, Ax to Sx
Refer to Transition Time
67
Transition-time
between inputs
tTRAN
54
54 ns
46
46
43
75
50
RL = 10 kΩ, CL = 15 pF 5 V
43
1.8 V
75
RL = 10 kΩ, CL = 50 pF
EN to D, EN to Sx
Refer to Turn-On and
Turn-Off Time
2.5 V
3.3 V
5 V
50
Turnon-time from
enable
tON(EN)
42
42 ns
37
37
RL = 10 kΩ, CL = 15 pF 5 V
35
35
1.8 V
85
85
RL = 10 kΩ, CL = 50 pF
EN to D, EN to Sx
Refer to Turn-On and
Turn-Off Time
2.5 V
3.3 V
5 V
72
72
Turnoff time from
enable
tOFF(EN)
70
70 ns
45
45
RL = 10 kΩ, CL = 15 pF 5 V
20
20
1.8 V
1
1
1
1
16
22
24
33
1
1
1
1
1
1
1
1
RL = 10 kΩ, CL = 15 pF
Sx to D, D to Sx
Refer to Break-Before-
Make
2.5 V
3.3 V
5 V
Break before make
time
tBBM
ns
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7.9 Injection Current Coupling
At specified VDD ±10%
Typical values measured at nominal VDD and TA = 25°C.
-40°C to 125°C
PARAMETER
VDD
TEST CONDITIONS
UNIT
MIN
TYP
MAX
INJECTION CURRENT COUPLING
1.8 V
0.01
0.05
0.1
1
1
3.3 V
5 V
RS ≤ 3.9 kΩ IINJ ≤ 1 mA
1
1.8 V
3.3 V
5 V
0.01
0.3
2
IINJ ≤ 10
RS ≤ 3.9 kΩ
mA
3
0.06
0.05
0.05
0.1
4
Maximum shift of output voltage
of enabled analog input
ΔVOUT
mV
1.8 V
3.3 V
5 V
2
RS ≤ 20 kΩ IINJ ≤ 1 mA
2
2
1.8 V
3.3 V
5 V
0.05
0.05
0.02
15
15
15
IINJ ≤ 10
RS ≤ 20 kΩ
mA
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7.10 Typical Characteristics
at TA = 25°C, VDD = 5 V (unless otherwise noted)
270
370
320
270
220
170
120
70
TA = 125èC
TA = 85èC
TA = 25èC
TA = -40èC
TA = 125èC
TA = 85èC
TA = 25èC
TA = -40èC
220
170
120
70
20
20
0
0.5
1
1.5
2
2.5
VS or VD - Source or Drain Voltage (V)
3
3.5
0
1
2
3
VS or VD - Source or Drain Voltage (V)
4
5
D002
D001
VDD = 3.3 V
VDD = 5 V
Figure 7-2. On-Resistance vs Temperature
Figure 7-1. On-Resistance vs Temperature
530
700
TA = 125èC
VDD = 5 V
650
600
550
500
450
400
350
300
250
200
150
100
50
480
TA = 85èC
VDD = 3.3 V
VDD = 2.5 V
VDD = 1.8 V
TA = 25èC
TA = -40èC
430
380
330
280
230
180
130
80
30
0
0.5
1
VS or VD - Source or Drain Voltage (V)
1.5
2
2.5
0
0.5
1
1.5
2
2.5
VS or VD - Source or Drain Voltage (V)
3
3.5
4
4.5
5
D003
D005
VDD = 2.5 V
TA = 25°C
Figure 7-3. On-Resistance vs Temperature
Figure 7-4. On-Resistance vs Source or Drain
Voltage
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1100
1000
900
800
700
600
500
400
300
200
100
0
15
14
13
12
11
10
9
VDD = 5.5 V
VDD = 5 V
VDD = 3.3 V
VDD = 1.8 V
CON
CSOFF
CDOFF
8
7
6
5
4
3
2
1
0
0.3
0
0.5
1
1.5
2
2.5
3
Logic Voltage (V)
3.5
4
4.5
5
5.5
0.6
0.9
1.2
1.5
1.8
2.1
VS or VD - Source or Drain Voltage (V)
2.4
2.7
3
D006
D013
Figure 7-5. Supply Current vs Logic Voltage
VDD = 3.3 V
Figure 7-6. Capacitance vs Source Voltage
80
VDD = 5.5 V
VDD = 5 V
VDD = 3.3 V
VDD = 1.8 V
TON(EN)
TOFF(EN)
100m
70
10m
1m
60
50
40
30
20
10
100m
10m
1m
100n
100
1k
10k 100k
Frequency (Hz)
1M
10M
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D012
D007
TA = 25°C
VDD = 3.3 V
Figure 7-7. Supply Current vs Input Switching
Frequency
Figure 7-8. TON(EN) and TOFF(EN) vs Temperature
50
40
Transiton_Falling
Transiton_Rising
Transiton_Falling
Transiton_Rising
45
40
35
30
25
20
15
10
35
30
25
20
15
1.5
2
2.5
3
Supply Voltage (V)
3.5
4
4.5
5
5.5
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D008
D009
TA = 25°C
TA = 25°C
Figure 7-9. TTRANSITION vs Supply Voltage
Figure 7-10. TTRANSITION vs Temperature
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-4
-20
-30
-40
-5
-6
-7
-8
-50
-60
-70
-80
-90
-100
-110
-120
-9
100k
10k
100k
1M 10M
Frequency (Hz)
100M
1G
1M
10M
Frequency (Hz)
100M
D00114
D010
TA = 25°C , VDD = 3.3 V
TA = 25°C
Figure 7-12. Xtalk and Off-Isolation vs Frequency
Figure 7-11. On Response vs Frequency
16
14
12
10
8
VDD = 5 V
VDD = 3.3 V
VDD = 1.8 V
6
4
2
0
-2
0
5
10
15
20
25
Current (mA)
30
35
40
45
50
D011
D011
VS = (VDD/2), TA = 25°C
Figure 7-13. Injection Current vs Maximum Output Voltage shift
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8 Detailed Description
8.1 Overview
8.1.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-
resistance. The measurement setup used to measure RON is shown below. Voltage (V) and current (ISD) are
measured using this setup, and RON is computed as shown in Figure 8-1 with RON = V / ISD
:
V
ISD
Sx
D
VS
Figure 8-1. On-Resistance Measurement Setup
8.1.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current.
2. Drain off-leakage current.
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF)
.
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF)
.
The setup used to measure both off-leakage currents is shown in Figure 8-2.
VDD
VDD
VDD
VDD
Is (OFF)
S0
S0
A
ID (OFF)
D
D
S6
S7
A
S6
S7
VS
VS
VD
VD
GND
GND
Figure 8-2. Off-Leakage Measurement Setup
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8.1.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON)
.
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON)
.
Either the source pin or drain pin is left floating during the measurement. Figure 8-3 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON)
.
VDD
VDD
VDD
VDD
IS (ON)
S0
S0
S1
A
N.C.
ID (ON)
S1
D
D
A
N.C.
S7
S7
Vs
VS
VS
VD
GND
GND
Figure 8-3. On-Leakage Measurement Setup
8.1.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 50% after the address signal
has risen or fallen past the 50% threshold. Figure 8-4 shows the setup used to measure transition time, denoted
by the symbol tTRANSITION
.
VDD
0.1…F
VDD
S0
S1
50%
50%
VSEL
tr < 5ns
tf < 5ns
VDD
OUTPUT
D
0 V
tTRAN_HIGH
tTRAN_LOW
RL
CL
S7
Output
50%
50%
A0
A1
0 V
tTRAN = max ( tTRAN_HGH, tTRAN_LOW
)
EN
VSEL
A2
GND
Figure 8-4. Transition-Time Measurement Setup
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8.1.5 Break-Before-Make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. Figure 8-5 shows
the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM)
.
VDD
0.1…F
VDD
S0
Input Select
(VSEL
VDD
tr < 5ns
tf < 5ns
OUTPUT
)
D
S1-S6
S7
0 V
RL
CL
90%
Output
0 V
tBBM_1
tBBM_2
A0
A1
tBBM = min ( tBBM_1, tBBM_2
)
EN
VSEL
A2
GND
Figure 8-5. Break-Before-Make Delay Measurement Setup
8.1.6 tON(EN) and tOFF(EN)
Turn-on time is defined as the time taken by the output of the device to rise to 10% after the enable has risen
past the 50% threshold. The 10% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. Figure 8-6 shows
the setup used to measure transition time, denoted by the symbol tON(EN)
.
Turn-off time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen
past the 50% threshold. The 90% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. Figure 8-6 shows
the setup used to measure transition time, denoted by the symbol tOFF(EN)
.
VDD
0.1…F
VDD
tf < 5ns
50%
50%
tr < 5ns
VEN
S0
S1
VDD
OUTPUT
D
0 V
RL
CL
S7
tON
tOFF
(EN)
(EN)
90%
A0
A1
EN
OUTPUT
0 V
VEN
A2
10%
GND
Figure 8-6. Turn-On and Turn-Off Time Measurement Setup
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8.1.7 Charge Injection
The TMUX1308-Q1 and TMUX1309-Q1 device have a transmission-gate topology. Any mismatch in capacitance
between the NMOS and PMOS transistors results in a charge injected into the drain or source during the falling
or rising edge of the gate signal. The amount of charge injected into the source or drain of the device is known
as charge injection, and is denoted by the symbol QC. Figure 8-7 shows the setup used to measure charge
injection from source (Sx) to drain (D).
VDD
0.1…F
VDD
VDD
S0
VS
VEN
S5
S6
S7
OUTPUT
D
0 V
VOUT
CL
Output
VOUT
VS
QC = CL
×
VOUT
EN
A0
A1
VEN
A2
GND
Figure 8-7. Charge-Injection Measurement Setup
8.1.8 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. Figure 8-8 shows the setup used to measure, and the equation to compute off
isolation.
0.1µF
NETWORK
VDD
ANALYZER
VS
50Q
S
VSIG
D
VOUT
RL
SX
50Q
GND
RL
50Q
Figure 8-8. Off Isolation Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Off Isolation = 20 ∂ Log
(1)
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8.1.9 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. Figure 8-9 shows the setup used to measure, and the equation used to
compute crosstalk.
0.1µF
NETWORK
VDD
ANALYZER
S1
VOUT
RL
D
50Q
VS
RL
S2
50Q
50Q
VSIG
SX
RL
GND
50Q
Figure 8-9. Channel-to-Channel Crosstalk Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Channel-to-Channel Crosstalk = 20 ∂ Log
(2)
8.1.10 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. Figure
8-10 shows the setup used to measure bandwidth.
0.1µF
NETWORK
VDD
ANALYZER
VS
S
50Q
VSIG
D
VOUT
RL
50Q
SX
GND
RL
50Q
Figure 8-10. Bandwidth Measurement Setup
≈
∆
«
’
÷
◊
V2
Attenuation = 20 ∂ Log
V
1
(3)
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8.1.11 Injection Current Control
Injection current is measured at the change in output of the enabled signal path when an current is injected into
a disabled signal path. Figure 8-11 shows the setup used to measure Injection current control.
VDD
Any OFF input
VINPUT_2 < GND or
VINPUT_2 > VDD
VINPUT_2
S0
S1
S2
S3
S4
S5
S6
IINJ
VOUT = VINPUT_1 ûVOUT
D
VOUT
VINPUT_1
S7
RS
VS
EN
A0 A1 A2
Figure 8-11. Injection current Measurement Setup
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8.2 Functional Block Diagram
The TMUX1308-Q1 is an 8:1, single-ended (1-channel), mux. The TMUX1309-Q1 is a 4:1, differential (2-
channel) mux. Each channel is turned on or turned off based on the state of the address lines and enable pin.
TMUX1308-Q1
TMUX1309-Q1
S0A
S1A
S2A
S3A
S0
S1
S2
S3
S4
S5
S6
S7
DA
DB
D
S0B
S1B
S2B
S3B
1-OF-8
1-OF-4
DECODER
DECODER
A0
A1
EN
A0 A1 A2 EN
Figure 8-12. TMUX1308-Q1 and TMUX1309-Q1 Functional Block Diagram
8.3 Feature Description
8.3.1 Bidirectional Operation
The TMUX1308-Q1 and TMUX1309-Q1 devices conduct equally well from source (Sx) to drain (Dx) or from
drain (Dx) to source (Sx). Each signal path has very similar characteristics in both directions so they can be used
as both multiplexers and demultiplexer to supports both analog and digital signals.
8.3.2 Rail-to-Rail Operation
The valid signal path input and output voltage for the TMUX1308-Q1 and TMUX1309-Q1 ranges from GND to
VDD
.
8.3.3 1.8 V Logic Compatible Inputs
The TMUX1308-Q1 and TMUX1309-Q1 support 1.8-V logic compatible control for all logic control inputs. The
logic input thresholds scale with supply but still provide 1.8-V logic control when operating at 5.5-V supply
voltage. 1.8-V logic level inputs allows the multiplexers to interface with processors that have lower logic I/O rails
and eliminates the need for an external voltage translator, which saves both space and BOM cost. The current
consumption of the TMUX1308-Q1 and TMUX1309-Q1 devices increase when using 1.8-V logic with higher
supply voltage. For more information on 1.8-V logic implementations refer to Simplifying Design with 1.8 V logic
Muxes and Switches.
8.3.4 Fail-Safe Logic
The TMUX1308-Q1 and TMUX1309-Q1 device have Fail-Safe Logic on the control input pins (EN, A0, A1, and
A2) allowing for operation up to 5.5-V, regardless of the state of the supply pin. This feature allows voltages on
the control pins to be applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic
minimizes system complexity by removing the need for power supply sequencing on the logic control pins. For
example, the Fail-Safe Logic feature allows the select pins of the TMUX1308-Q1 and TMUX1309-Q1 to be
ramped to 5.5-V while VDD = 0-V. Additionally, the feature enables operation of the multiplexers with VDD = 1.8-V
while allowing the select pins to interface with a logic level of another device up to 5.5-V, eliminating the potential
need for an external voltage translator.
8.3.5 Injection Current Control
Injection current is the current that is being forced into a pin by an input voltage (VIN) higher than the positive
supply (VDD + ∆V) or lower than ground (VSS). The current flows through the input protection diodes into
whichever supply of the device potentially compromising the accuracy and reliability of the system. Injected
currents can come from various sources depending on the application.
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•
•
Harsh environments and applications with long cabling, such as in factory automation and automotive
systems, may be susceptible to injected currents from switching or transient events
Other self-contained systems can also be subject to injected current if the input signal is coming from various
sensors or current sources
Injected Current Impact: Typical CMOS switches have ESD protection diodes on the inputs and outputs. These
diodes not only serve as ESD protection but also provide a voltage clamp to prevent the inputs or outputs going
above VDD or below GND/VSS. When current is injected into the pin of a disabled signal path, a small amount of
current goes thorough the ESD diode but most of the current goes through conduction to the Drain. If forward
diode voltage of the ESD diode (VF) is greater than the PMOS threshold voltage (VT), the PMOS of all OFF
switches turns ON and there would be undesirable subthreshold leakage between the source and the drain that
can lift the OFF source pins up also. Figure 8-13 shows a simplified diagram of typical CMOS switch and
associated injected current path:
Logic D ecode
Block
Injected current into
unselected switch input
n
S0
Som ec urrent goes
through ESD
M ost c urrent goes through
as conduc ti on
p
ESD
S1
S2
S3
Drain voltage
VDD + VF (ESD)
D
S4
ESD
S5
S6
Logic D ecode
Block
n
S7
Selected switch input
p
ESD
VDD (PMOS gate voltage)
Figure 8-13. Simplified diagram of typical CMOS switch and Associated Injected Current Path
It is quite difficult to cut off these current paths. The drain pin can never be allowed to exceed the voltage above
VDD by more than a VT. Analog pins can be protected against current injection by adding external components
like Schottky diode from Drain pin to ground to clamp the drain voltage at < VDD + VT to cut off the current path.
Change in RON due to Current Injection: Because the ON resistance of the enabled FET switch is impacted by
the change in the supply rail, when the drain pin voltage exceeds the supply voltage by more than a VT, an error
in the output signal voltage can be expected. This undesired change in the output can cause issues related to
false trigger events and incorrect measurement readings, potentially compromising the accuracy and reliability of
the system. As shown in Figure 8-14, S2 is the enabled signal path that is conducting a signal from S2 pin to D
pin. Because there is an injected current at the disabled S1 pin, the voltage at that pin increases above the
supply voltage and the ESD protection diode is forward biased, shifting the power supply rail. This shift in supply
voltage alters the RON of the internal FET switches, causing a ∆V error on the output at the D pin.
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VDD
+ûV error
VD
VS2
II/O
OFF
S1
D
-ûV error
ON
S2
VS2
Figure 8-14. Injected Current Impact on RON
To avoid the complications of added external protection to your system, the TMUX1308-Q1 and TMUX1309-Q1
devices have an internal injection current control feature which eliminates the need for external diode/resistor
networks typically used to protect the switch and keep the input signals within the supply voltage. The internal
injection current control circuitry allows signals on disabled signal paths to exceed the supply voltage without
affecting the signal of the enabled signal path. The injection current control circuitry also protects the TMUX13xx-
Q1 from currents injected into disabled signal paths without impacting the enabled signal path, which typical
CMOS switches do not support. Additionally, the TMUX1308-Q1 and TMUX1309-Q1 do not have any internal
diode paths to the supply pin, which eliminates the risk of damaging components connected to the supply pin, or
providing unintended power to the system supply rail. Figure 8-12 shows a simplified diagram of one signal path
for the TMUX13xx-Q1 devices and the associated injection current circuit.
Logic D ecode
Block
n
Control
Control
p
ESD
ESD
Circuitry
Circuitry
Simplified injection curr ent circuitry
Simplified injection curr ent circuitry
Figure 8-15. Simplified Diagram of Injection Current Control
The injection current control circuitry is independently controlled for each source or drain pin (Sx, D). The control
circuitry for a particular pin is enabled when that input is disabled by the logic pins and the injected current
causes the voltage at the pin to be above VDD or below GND. The injection current circuit includes a FET to
shunt undesired current to GND in the case of overvoltage or injected current events. Each injection current
circuit is rated to handle up to 50 mA, however the device can support a maximum current of 100 mA at any
given time. Depending on the system application, a series limiting resistor may be needed and must be sized
appropriately. Figure 8-15 shows the TMUX13xx-Q1 protection circuitry with an injected current at an input pin.
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Logic D ecode
Block
Injected current into
unselected switch input
n
Control
Circuitry
Control
Circuitry
p
ESD
ESD
IIN J
Simplified injection curr ent circuitry
Simplified injection curr ent circuitry
Figure 8-16. Injected Current at Input Pin
Figure 8-17 shows an example of using a series limiting resistor in the case of an overvoltage event.
Logic D ecode
Block
VIN PU T > VDD or
VIN PU T < GND
n
RLIM
Control
Control
p
VIN PU T
ESD
ESD
Circuitry
Circuitry
Simplified injection curr ent circuitry
Simplified injection curr ent circuitry
Figure 8-17. Over-voltage Event with Series Resistor
If the voltage at the source or drain pins is greater than VDD, or less than GND, the protection FET will be turned
on for any disabled signal path and shunt the pin the GND. In this event, a series resistor is needed to limit the
total current injected into the device to be less than 100 mA. Two example scenarios are:
8.3.5.1 TMUX13xx-Q1 is Powered and the Input Signal is Greater Than VDD (VDD = 5 V, VINPUT = 5.5 V).
A typical CMOS switch would have an internal ESD diode to the supply pin rated for about ≈30 mA that would be
turned on and a series limited resistor would be needed. However, any conducted current would be injected into
the supply rail potentially damaging the system, unexpectedly turning on other devices on the same supply rail,
or requiring additional components for protection. The TMUX13xx-Q1 implementation also handles this scenario
with a series limiting resistor, however, the current path is now to GND which doesn’t have the same issues as
the current injected into the supply rail.
8.3.5.2 TMUX13xx-Q1 is Unpowered and the Input Signal has a Voltage Present (VDD = 0 V, VINPUT = 3 V)
Many CMOS switches are unable to support a voltage at the input without a valid supply voltage present
otherwise the voltage will be coupled from input to output and could damage downstream devices or impact
power-sequencing. The TMUX13xx-Q1 circuitry can handle an input signal present without a supply voltage
while minimizing power transfer from the input to output of the switch. By limiting the output voltage coupling to
400 mV the TMUX1308-Q1 and TMUX1309-Q1 help reduce the chance of conduction through any downstream
ESD diodes.
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8.3.6 Device Functional Modes
When the EN pin of the TMUX1308-Q1 is pulled low, one of the switches is closed based on the state of the
address lines. Similarly, when the EN pin of the TMUX1309-Q1 is pulled low, two of the switches are closed
based on the state of the address lines. When the EN pin is pulled high, all the switches are in an open state
regardless of the state of the address lines.
Unused logic control pins must be tied to GND or VDD in order to ensure the device does not consume additional
current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (Sx and Dx)
should be connected to GND.
8.3.7 Truth Tables
Table 8-1 and Table 8-2 show the truth tables for the TMUX1308-Q1 and TMUX1309-Q1 respectively.
Table 8-1. TMUX1308-Q1 Truth Table
Selected Signal Path Connected To Drain
EN A2 A1 A0
(D) Pin
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
S0
S1
S2
S3
S4
S5
S6
S7
X(1) X(1) X(1)
All channels are off
(1) X denotes don't care.
Table 8-2. TMUX1309-Q1 Truth Table
Selected Signal Path Connected To Drain (DA
EN A1 A0
and DB) Pins
S0A to DA
S0B to DB
0
0
0
0
0
1
1
0
1
0
1
S1A to DA
S1B to DB
S2A to DA
S2B to DB
S3A to DA
S3B to DB
0
1
X(1) X(1)
All channels are off
(1) X denotes don't care.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TMUX13xx-Q1 family offers protection against injection current invents across a wide operating supply
range (1.62 V to 5.5 V). These devices include 1.8 V logic compatible control input pins that enable operation in
systems with 1.8 V I/O rails. Additionally, the control input pins support Fail-Safe Logic which allows for operation
up to 5.5 V, regardless of the state of the supply pin. This feature stops the logic pins from back-powering the
supply rail while the injection current circuitry prevents the signal path from back-powering the supply. These
features make the TMUX13xx-Q1 a family of general purpose multiplexers and switches that can reduce system
complexity, board size, and overall system cost.
9.2 Typical Application
One useful application to take advantage of the TMUX13xx-Q1 features is multiplexing various physical switches
in a body control module (BCM) or electronic control unit (ECU). Automotive BCMs are complex systems
designed to manage numerous functions such as lighting, door locks, windows, wipers, turn signals and many
more inputs. The BCM monitors these physical switches and controls power to various loads within the vehicle.
A CMOS multiplexer can be used to multiplex the inputs and minimize the number of GPIO or ADC inputs
needed by an onboard MCU. Figure 9-1 shows a typical BCM system using the TMUX1308-Q1 to multiplex
system inputs.
D1
Electronic Control Unit (ECU)
VBAT
V
CBUFF
CVBAT
Wetting Current
Control Circuity
FET
FET
RWETT
R1
R2
DX
CX
…C
S1
Rx
Rx
Logic x3
DX
S8
CX
Figure 9-1. Multiplexing BCM Inputs
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9.3 Design Requirements
For this design example, use the parameters listed in Table 9-1.
Table 9-1. Design Parameters
PARAMETERS
Supply (VDD
VALUES
5.0 V
)
I/O signal range
Control logic thresholds
Switch inputs
0 V to VDD (Rail to Rail)
1.8 V compatible
Eight
9.4 Detailed Design Procedure
The TMUX1308-Q1 has an internal injection current control feature which eliminates the need for external diode/
resistor networks typically used to protect the switch and keep the input signals within the supply voltage. The
internal injection current control circuitry allows signals on disabled signal paths to exceed the supply voltage
without affecting the signal of the enabled signal path. Injected currents can come from various sources such as
from long cabling in automotive systems that may be susceptible to induced currents from switching or transient
events. Another momentary source of injected currents in BCMs are wetting currents, which are small currents
used to prevent oxidation on metal switch contacts or wires. A switch without injection current control can have
the measured output of the enabled signal path impacted if a current is injected into a disabled signal path. This
undesired change in the output can cause issues related to false trigger events and incorrect measurement
readings which can compromise the accuracy and reliability of the BCM system. Figure 9-2 shows a detailed
BCM application.
DBATT
VBATT
12 kO
VBAT
12V
V
10 kO
CBUFF
CVBAT
2.7 nF
RWETT
1.2 kO
1.2 kO
20 kO
S0
D1
15 kO
…C
10 nF
10 nF
S1
S8
D
20 kO
A2
S7
A0
A1
D8
15 kO
Figure 9-2. Detailed BCM Application
The BCM uses the 12 V battery voltage to provide a wetting current to each switch when the associated control
circuitry is enabled by the micro controller. The wetting current is sized by the RWETT and the required value may
vary depending on the type physical switch being monitoried. The 20 kΩ and 15 kΩ resistors are used in addition
to the wetting resistor to create a voltage divider before the input of the multiplexer incase of a short to battery
condition. The resistor values are selected to maintain the voltage at the switch signal path below VDD. The 20
kΩ series resistor also limits the amount of injected current into the switch if an overvotlage event occurs. Diodes
D1 through D8 are used to prevent back flow of current in case a secondary system is monitoring the same
physical switches for backup or redundancy reasons. The 10 nF capacitors are used for initial ESD protection in
the system and must be sized based on system level requirements.
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The logic address pins are controlled by the micro controller to cycle between the eight switch inputs in the
system. If the parts desired power-up state is disabled, the enable pin should have a weak pull-up resistor and
be controlled by the MCU through the GPIO.
10 Power Supply Recommendations
The TMUX1308-Q1 and TMUX1309-Q1 devices operate across a wide supply range of 1.62 V to 5.5 V. Note: do
not exceed the absolute maximum ratings because stresses beyond the listed ratings can cause permanent
damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply
to other components. Good power-supply decoupling is important to achieve optimum performance. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to
ground. Place the bypass capacitors as close to the power supply pins of the device as possible using low-
impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low
equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes.
For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting
the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers
the overall inductance and is beneficial for connections to ground planes.
11 Layout
11.1 Layout Guidelines
11.1.1 Layout Information
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight; therefore, some traces must turn
corners. Figure 11-1 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
2W
1W min.
W
Figure 11-1. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance
changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via
introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference
from the other layers of the board. Be careful when designing test points, through-hole pins are not
recommended at high frequencies.
Figure 11-2 illustrates an example of a PCB layout with the TMUX1308-Q1 and TMUX1309-Q1. Some key
considerations are:
•
Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
•
•
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
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•
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
Via to GND plane
Wide (low inductance)
trace for power
Wide (low inductance)
trace for power
C
C
S4
S0B
VDD
S2
S1
S0
S3
A0
A1
A2
VDD
S6
D
S2B
DB
S2A
S1A
DA
S7
S3B
S1B
TMUX1308-Q1
TMUX1309-Q1
S5
S0A
S3A
A0
EN
EN
N.C.
N.C.
GND
GND
A1
Figure 11-2. TMUX1308-Q1 and TMUX1309-Q1 Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.
Texas Instruments, QFN/SON PCB Attachment.
Texas Instruments, Quad Flatpack No-Lead Logic Packages.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 12-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TMUX1308-Q1
TMUX1309-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Aug-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTMUX1308QBQBRQ1
TMUX1308QBQBRQ1
ACTIVE
WQFN
WQFN
BQB
BQB
16
16
3000
3000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
PREVIEW
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
1308Q
TMUX1308QDYYRQ1
TMUX1308QPWRQ1
TMUX1309QBQBRQ1
TMUX1309QDYYRQ1
TMUX1309QPWRQ1
ACTIVE SOT-23-THN
DYY
PW
16
16
16
16
16
3000
2000
3000
3000
2000
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TMUX1308Q
TM1308Q
1309Q
ACTIVE
TSSOP
WQFN
Green (RoHS
& no Sb/Br)
PREVIEW
BQB
DYY
PW
Green (RoHS
& no Sb/Br)
PREVIEW SOT-23-THN
PREVIEW TSSOP
Green (RoHS
& no Sb/Br)
TMUX1309Q
TM1309Q
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Aug-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TMUX1308-Q1, TMUX1309-Q1 :
Catalog: TMUX1308, TMUX1309
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Aug-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX1308QDYYRQ1
TMUX1308QPWRQ1
SOT-
23-THN
DYY
PW
16
16
3000
2000
330.0
12.4
4.8
3.6
1.6
8.0
12.0
Q3
TSSOP
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Aug-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMUX1308QDYYRQ1
TMUX1308QPWRQ1
SOT-23-THN
TSSOP
DYY
PW
16
16
3000
2000
336.6
367.0
336.6
367.0
31.8
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0016A
C
3.36
3.16
SEATING PLANE
PIN 1 INDEX
AREA
A
0.1 C
14X 0.5
16
1
4.3
4.1
NOTE 3
2X
3.5
8
9
0.31
16X
0.11
0.1
C A
B
1.1 MAX
2.1
1.9
B
0.2
0.08
TYP
SEE DETAIL A
0.25
GAUGE PLANE
0°- 8°
0.1
0.0
0.63
0.33
DETAIL A
TYP
4224642/A 11/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
www.ti.com
EXAMPLE BOARD LAYOUT
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0016A
16X (1.05)
SYMM
16
1
16X (0.3)
SYMM
14X (0.5)
9
8
(R0.05) TYP
(3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224642/A 11/2018
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0016A
16X (1.05)
SYMM
16
1
16X (0.3)
SYMM
14X (0.5)
9
8
(R0.05) TYP
(3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 20X
4224642/A 11/2018
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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