TMUX6111 [TI]
5pA、±16.5V、1:1 (SPST)、4 通道精密模拟开关（低电平有效）;
| 型号： | TMUX6111 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 5pA、±16.5V、1:1 (SPST)、4 通道精密模拟开关（低电平有效） 开关 |
| 文件： | 总37页 (文件大小：1699K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TMUX6111, TMUX6112, TMUX6113
ZHCSIN7E –AUGUST 2018–REVISED DECEMBER 2019
TMUX611x ±17V 低电容、低泄漏电流、
精密四通道 SPST 开关
1 特性
3 说明
1
•
宽电源电压范围：±5V 至 ±17V（双电源），
TMUX6111、TMUX6112 和 TMUX6113 器件是现代
10V 至 17V（但电源）
化的互补金属氧化物半导体 (CMOS) 器件，具有四个
独立的可选单刀单掷 (SPST) 开关。这些器件在双电源
（±5V 至 ±17V）、单电源（10V 至 17V）或非对称电
源供电时均能正常运行。所有数字输入均具有兼容晶体
管-晶体管逻辑 (TTL) 的阈值，从而确保 TTL/CMOS
逻辑兼容性。
•
所有引脚的闩锁性都能达到 100mA，符合 JESD78
II 类 A 级要求
•
•
•
•
•
•
•
•
•
•
低导通电容：4.2pF
低输入泄漏：0.5pA
低电荷注入：0.6pC
轨至轨运行
逻辑 0 会打开 TMUX6111 中数字控制输入上的开关。
要打开 TMUX6112 中的开关，则需要逻辑 1。
TMUX6113 有两个开关的数字控制逻辑与 TMUX6111
类似，而另外两个开关上的逻辑则与之相反。
TMUX6113 具有先断后合开关，因此可用于交叉点开
关应用。
低导通电阻：120Ω
快速开关开启时间：66ns
先断后合开关 (TMUX6113)
EN 引脚可连接至 VDD
低电源电流：17µA
人体放电模型 (HBM) ESD 保护：针对所有引脚提
供 ±2kV 保护
TMUX611x 器件是德州仪器 (TI) 精密开关和多路复用
器系列的一部分。这些器件具有非常低的泄漏电流和电
荷注入，因此可用于高精度测量 应用中的数字输入 D
类音频放大器。这些器件的电源电流低至 17μA，因此
可用于便携式 应用供电的出色器件。
•
行业标准 TSSOP 封装和较小的 WQFN 封装
2 应用
•
•
•
•
•
工厂自动化和工业过程控制
可编程逻辑控制器 (PLC)
模拟输入模块
器件信息(1)
器件型号
TMUX6111
封装
封装尺寸（标称值）
半导体测试设备
电池测试设备
TSSOP (16)
5.00mm × 4.40mm
TMUX6112
TMUX6113
WQFN (16)
3.00mm x 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化原理图
VDD
SW
VSS
VDD
VSS
VDD
SW
VSS
SW
S1
D1
D2
D3
D4
S1
S2
S3
S4
D1
D2
D3
D4
S1
S2
S3
S4
D1
D2
D3
D4
SW
SW
SW
S2
S3
S4
SW
SW
SW
SW
SW
SW
SEL1
SEL2
SEL3
SEL4
SEL1
SEL2
SEL3
SEL4
SEL1
SEL2
SEL3
SEL4
TMUX6111
TMUX6112
TMUX6113
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS383
TMUX6111, TMUX6112, TMUX6113
ZHCSIN7E –AUGUST 2018–REVISED DECEMBER 2019
www.ti.com.cn
目录
9.2 Functional Block Diagram ....................................... 18
9.3 Feature Description................................................. 18
9.4 Device Functional Modes........................................ 19
10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
10.2 Typical Application ............................................... 20
10.3 Application Curves ................................................ 21
11 Power Supply Recommendations ..................... 22
12 Layout................................................................... 23
12.1 Layout Guidelines ................................................. 23
12.2 Layout Example .................................................... 23
13 器件和文档支持 ..................................................... 24
13.1 文档支持................................................................ 24
13.2 相关链接................................................................ 24
13.3 接收文档更新通知 ................................................. 24
13.4 支持资源................................................................ 24
13.5 商标....................................................................... 24
13.6 静电放电警告......................................................... 24
13.7 Glossary................................................................ 24
14 机械、封装和可订购信息....................................... 25
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 4
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Thermal Information.................................................. 5
7.4 Recommended Operating Conditions....................... 5
7.5 Electrical Characteristics (Dual Supplies: ±15 V) ..... 6
7.6 Switching Characteristics (Dual Supplies: ±15 V)..... 7
7.7 Electrical Characteristics (Single Supply: 12 V)........ 7
7.8 Switching Characteristics (Single Supply: 12 V)....... 8
7.9 Typical Characteristics.............................................. 9
Parameter Measurement Information ................ 12
8.1 Truth Tables............................................................ 12
Detailed Description ............................................ 13
9.1 Overview ................................................................. 13
8
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision D (January 2019) to Revision E
Page
•
•
将标题 中的“TMUX611x ±16.5V”更改成了“TMUX611x ±17V”................................................................................................ 1
将特性 中的“宽电源电压范围：±5V 至 ±16.5V（双电源），10V 至 16.5V（单电源）”更改成了“宽电源电压范围：±5V
至 ±17V（双电源），10V 至 17V（单电源）” ....................................................................................................................... 1
•
将说明 中的“双电源（±5V 至 ±16.5V）、单电源（10V 至 16.5V）”更改成了“双电源（±5V 至 ±17V）、单电源（10V
至 17V）”................................................................................................................................................................................ 1
•
•
•
•
•
Changed ±16.5-V to ±17.5-V in the Description of the Device Comparison Table................................................................ 4
Changed recommended power supply voltage differential from 33 V to 34 V....................................................................... 5
Changed recommended single supply voltage from 16.5 V to 17 V ...................................................................................... 5
Changed positive and negative power supply voltage to +17 V and -17V............................................................................. 5
The Overview From: dual supplies (±5 V to ±16.5 V) or single supply (10 V to 16.5 V) To: dual supplies (±5 V to ±17
V) or single supply (10 V to 17 V) ........................................................................................................................................ 13
•
•
Changed the Application Information From: 16.5 V (single supply) To: 17 V (single supply) ............................................. 20
The Power Supply Recommendations From: wide supply range of of ±5 V to ±16.5 V (10 V to 16.5 V in single-
supply mode) To: wide supply range of of ±5 V to ±17 V (10 V to 17 V in single-supply mode)......................................... 22
Changes from Revision C (December 2018) to Revision D
Page
•
•
Changed descriptions in the Device Comparison Table to match the data sheet title........................................................... 4
已更改 图 30 to correct Op-Amp terminal polarities. ........................................................................................................... 20
Changes from Revision B (November 2018) to Revision C
Page
•
Changed units for channel current and ambient temperature................................................................................................ 6
2
版权 © 2018–2019, Texas Instruments Incorporated
TMUX6111, TMUX6112, TMUX6113
www.ti.com.cn
ZHCSIN7E –AUGUST 2018–REVISED DECEMBER 2019
Changes from Revision A (November 2018) to Revision B
Page
•
针对 TMUX6111 和 TMUX6113 将文档状态从产品预览 更改成了生产数据........................................................................... 1
Changes from Original (August 2018) to Revision A
Page
•
针对 TMUX6112 将文档状态从预告信息 更改成了生产数据 .................................................................................................. 1
Copyright © 2018–2019, Texas Instruments Incorporated
3
TMUX6111, TMUX6112, TMUX6113
ZHCSIN7E –AUGUST 2018–REVISED DECEMBER 2019
www.ti.com.cn
5 Device Comparison Table
PRODUCT
DESCRIPTION
TMUX6111
TMUX6112
TMUX6113
±17-V, Low-Capacitance, Low-Leakage-Current, Precision, Quad SPST Switches (Normally Closed)
±17-V, Low-Capacitance, Low-Leakage-Current, Precision, Quad SPST Switches (Normally Open)
±17-V, Low-Capacitance, Low-Leakage-Current, Precision, Quad SPST Switches (Dual Open + Dual Closed)
6 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
RTE Package
16-Pin WQFN
Top View
SEL1
D1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL2
D2
S1
S2
S1
VSS
GND
S4
1
2
3
4
12
11
10
9
S2
VSS
GND
S4
VDD
NC
VDD
NC
S3
Thermal
Pad
S3
D4
D3
SEL4
SEL3
Not to scale
Not to scale
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
TSSOP
WQFN
SEL1
D1
1
2
3
15
16
1
I
Logic control input 1.
I/O
I/O
Drain pin 1. Can be an input or output.
Source pin 1. Can be an input or output.
S1
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
VSS
4
2
P
GND
S4
5
6
3
4
P
I/O
I/O
I
Ground (0 V) reference
Source pin 4. Can be an input or output.
Drain pin 4. Can be an input or output.
Logic control input 4.
D4
7
5
SEL4
SEL3
D3
8
6
9
7
I
Logic control input 3.
10
11
12
8
I/O
I/O
–
Drain pin 3. Can be an input or output.
Source pin 3. Can be an input or output.
No internal connection.
S3
9
NC
10
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
13
11
P
S2
14
15
16
12
13
14
I/O
I/O
I
Source pin 2. Can be an input or output.
Drain pin 2. Can be an input or output.
Logic control input 2.
D2
SEL2
Exposed Pad. The exposed pad is electrically connected to VSS internally. Connect EP to VSS to
achieve rated thermal and ESD performance.
–
-
EP
–
(1) I = input, O = output, I/O = input and output, P = power
4
Copyright © 2018–2019, Texas Instruments Incorporated
TMUX6111, TMUX6112, TMUX6113
www.ti.com.cn
ZHCSIN7E –AUGUST 2018–REVISED DECEMBER 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
36
UNIT
V
VDD to VSS
VDD to GND
VSS to GND
VDIG
Supply voltage
–0.3
–18
18
V
0.3
V
Digital input pin (SEL1, SEL2, SEL3, SEL4) voltage
Digital input pin (SEL1, SEL2, SEL3, SEL4) current
Analog input pin (Sx) voltage
Analog input pin (Sx) current
Analog output pin (D) voltage
Analog output pin (D) current
Ambient temperature
GND –0.3
–30
VDD+0.3
30
V
IDIG
mA
V
VANA_IN
IANA_IN
VANA_OUT
IANA_OUT
TA
VSS–0.3
–30
VDD+0.3
30
mA
V
VSS–0.3
–30
VDD+0.3
30
mA
°C
°C
°C
–55
140
TJ
Junction temperature
150
Tstg
Storage temperature
–65
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Thermal Information
TMUX6111/ TMUX6112/ TMUX6113
THERMAL METRIC
PW (TSSOP)
16 PINS
111.0
41.7
RTE (QFN)
16 PINS
51.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
53.3
57.2
26.6
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.1
1.7
ΨJB
56.6
26.6
RθJC(bot)
N/A
11.6
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
10
NOM
MAX
34
UNIT
(1)
VDD to VSS
VDD to GND
VDD to GND
VSS to GND
Power supply voltage differential
V
V
V
V
V
Positive power supply voltage (singlle supply, VSS = 0 V)
Positive power supply voltage (dual supply)
Negative power supply voltage (dual supply)
Source pins voltage
10
17
5
17
–5
–17
VDD
(2)
VS
VSS
(1) VDD and VSS can be any value as long as 10 V ≤ (VDD – VSS) ≤ 34 V.
(2) VS is the voltage on all the S pins.
Copyright © 2018–2019, Texas Instruments Incorporated
5
TMUX6111, TMUX6112, TMUX6113
ZHCSIN7E –AUGUST 2018–REVISED DECEMBER 2019
www.ti.com.cn
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
VSS
0
NOM
MAX
UNIT
V
VD
Drain pin voltage
VDD
VDD
25
VDIG
ICH
TA
Digital input pin (SEL1, SEL2, SEL3, SEL4) voltage
Channel current (TA = 25°C )
Ambient temperature
V
–25
–40
mA
°C
125
7.5 Electrical Characteristics (Dual Supplies: ±15 V)
at TA = 25°C, VDD = 15 V, and VSS = -15 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
MIN
TYP
MAX UNIT
VA
Analog signal range
TA = –40°C to +125°C
VSS
VDD
135
160
210
245
6
V
Ω
VS = 0 V, IS = 1 mA
120
140
Ω
RON
On-resistance
VS = ±10 V, IS = 1 mA
TA = –40°C to +85°C
TA = –40°C to +125°C
Ω
Ω
2.5
23
Ω
On-resistance mismatch
between channels
ΔRON
VS = ±10 V, IS = 1 mA
TA = –40°C to +85°C
TA = –40°C to +125°C
9
Ω
11
Ω
33
Ω
VS = –10 V, 0 V, +10 V, IS
= 1 mA
RON_FLAT
On-resistance flatness
TA = –40°C to +85°C
TA = –40°C to +125°C
37
Ω
38
Ω
RON_DRIFT On-resistance drift
VS = 0 V
0.52
%/°C
nA
nA
nA
nA
nA
nA
nA
nA
nA
–0.02
-0.14
–1.3
0.005
0.02
0.05
0.25
0.02
0.05
0.25
0.04
0.1
Switch state is off, VS
+10 V/ –10 V, VD = –10
V/ + 10 V
=
IS(OFF)
ID(OFF)
ID(ON)
Source off leakage current(1)
TA = –40°C to +85°C
TA = –40°C to +125°C
–0.02
–0.14
–1.3
0.005
0.01
Switch state is off, VS
+10 V/ –10 V, VD = –10
V/ +10 V
=
Drain off leakage current(1)
Drain on leakage current
TA = –40°C to +85°C
TA = –40°C to +125°C
–0.04
–0.25
–1.8
Switch state is on, VS
+10 V/ –10 V, VD = –10
V/ +10 V
=
TA = –40°C to +85°C
TA = –40°C to +125°C
0.5
DIGITAL INPUT (SELx pins)
VIH
VIL
Logic voltage high
Logic voltage low
2
V
V
0.8
Pull-down resistance on SELx
pins
RPD(IN)
6
MΩ
POWER SUPPLY
17
21
22
23
10
11
12
µA
µA
µA
µA
µA
µA
VA = 0 V or 3.3 V, VS = 0
V
IDD
VDD supply current
TA = –40°C to +85°C
TA = –40°C to +125°C
8
VA = 0 V or 3.3 V, VS = 0
V
ISS
VSS supply current
TA = –40°C to +85°C
TA = –40°C to +125°C
(1) When VS is positive, VD is negative, and vice versa.
6
Copyright © 2018–2019, Texas Instruments Incorporated
TMUX6111, TMUX6112, TMUX6113
www.ti.com.cn
ZHCSIN7E –AUGUST 2018–REVISED DECEMBER 2019
7.6 Switching Characteristics (Dual Supplies: ±15 V)
at TA = 25°C, VDD = 15 V, and VSS = -15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VS = ±10 V, RL = 300 Ω , CL = 35 pF
66
78
ns
VS = ±10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
107
ns
tON
Enable turn-on time
VS = ±10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
117
68
ns
ns
ns
VS = ±10 V, RL = 300 Ω , CL = 35 pF
56
40
VS = ±10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
77
tOFF
Enable turn-off time
VS = ±10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
81
ns
ns
Break-before-make time delay
(TMUX6113 Only)
VS = 10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
tBBM
8
QJ
Charge injection
Off-isolation
VS = 0 V, RS = 0 Ω , CL = 1 nF
0.6
–85
pC
dB
dB
OISO
RL = 50 Ω , CL = 5 pF, f = 1 MHz
RL = 50 Ω , CL = 5 pF, f = 1 MHz, adjacent channel
–100
XTALK
IL
Channel-to-channel crosstalk
Insertion loss
RL = 50 Ω , CL = 5 pF, f = 1 MHz, non-
adjacentchannel
–115
–7.0
–59
dB
dB
dB
RL = 50 Ω , CL = 5 pF, f = 1 MHz
RL = 10 kΩ , CL = 5 pF, VPP= 0.62 V on VDD, f= 1
MHz
AC Power Supply Rejection
Ratio
ACPSRR
RL = 10 kΩ , CL = 5 pF, VPP= 0.62 V on VSS, f= 1
MHz
–59
800
dB
MHz
%
BW
THD
CIN
-3dB Bandwidth
RL = 50 Ω , CL = 5 pF
Total harmonic distortion +
noise
RL = 10k Ω , CL = 5 pF, f= 20Hz to 20kHz
0.08
Digital input capacitance
Source off-capacitance
Drain off-capacitance
VIN = 0 V or VDD
1.5
1.9
2.5
2.4
pF
pF
pF
pF
VS = 0 V, f = 1 MHz (PW package)
VS = 0 V, f = 1 MHz (RTE package)
VS = 0 V, f = 1 MHz
3.0
3.6
3.1
CS(OFF)
CD(OFF)
CS(ON),
CD(ON)
Source and drain on-
capacitance
VS = 0 V, f = 1 MHz
4.2
6.0
pF
7.7 Electrical Characteristics (Single Supply: 12 V)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
MIN
TYP
230
5
MAX UNIT
VA
Analog signal range
TA = –40°C to +125°C
VS = 10 V, IS = 1 mA
VSS
VDD
265
355
405
12
V
Ω
RON
On-resistance
TA = –40°C to +85°C
TA = –40°C to +125°C
Ω
Ω
Ω
On-resistance mismatch
between channels
ΔRON
VS = 10 V, IS = 1 mA
TA = –40°C to +85°C
TA = –40°C to +125°C
19
Ω
23
Ω
RON_DRIFT On-resistance drift
Source off leakage current(1)
VS = 0 V
0.5
%/°C
nA
nA
nA
–0.02
–0.1
-1
0.005
0.02
0.04
0.2
Switch state is off, VS
10 V/ 1 V, VD = 1 V/ 10 V
=
IS(OFF)
TA = –40°C to +85°C
TA = –40°C to +125°C
(1) When VS is positive, VD is negative, and vice versa.
Copyright © 2018–2019, Texas Instruments Incorporated
7
TMUX6111, TMUX6112, TMUX6113
ZHCSIN7E –AUGUST 2018–REVISED DECEMBER 2019
www.ti.com.cn
MAX UNIT
Electrical Characteristics (Single Supply: 12 V) (continued)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
–0.02
–0.1
TYP
0.005
0.02
0.04
0.2
nA
nA
nA
nA
nA
nA
Switch state is off, VS
10 V/ 1 V, VD = 1 V/ 10 V
=
ID(OFF)
Drain off leakage current(1)
TA = –40°C to +85°C
TA = –40°C to +125°C
–1
–0.04
–0.16
–1.4
0.01
0.04
0.08
0.4
Switch state is on, VS
floating, VD = 1 V/ 10 V
=
ID(ON)
Drain on leakage current
TA = –40°C to +85°C
TA = –40°C to +125°C
DIGITAL INPUT (SELx pins)
VIH
VIL
Logic voltage high
Logic voltage low
2
V
V
0.8
Pull-down resistance on SELx
pins
RPD(EN)
6
MΩ
POWER SUPPLY
13
16
17
18
µA
µA
µA
VA = 0 V or 3.3 V, VS = 0
V
IDD
VDD supply current
TA = –40°C to +85°C
TA = –40°C to +125°C
7.8 Switching Characteristics (Single Supply: 12 V)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VS = 8 V, RL = 300 Ω , CL = 35 pF
72
84
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
117
ns
tON
Enable turn-on time
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
128
66
ns
ns
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF
57
47
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
78
tOFF
Enable turn-off time
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
84
ns
ns
Break-before-make time delay
(TMUX6113 only)
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
tBBM
17
QJ
Charge injection
Off-isolation
VS = 0 V to 12 V, RS = 0 Ω , CL = 1 nF
RL = 50 Ω , CL = 5 pF, f = 1 MHz
0.6
–86
–98
pC
dB
dB
OISO
RL = 50 Ω , CL = 5 pF, f = 1 MHz, adjacent channel
XTALK
Channel-to-channel crosstalk
Insertion loss
RL = 50 Ω , CL = 5 pF, f = 1 MHz, non-adjacent
channel
–117
-14
dB
dB
dB
IL
RL = 50 Ω , CL = 5 pF, f = 1 MHz
AC Power Supply Rejection
Ratio
ACPSRR
RL = 10 kΩ , CL = 5 pF, VPP= 0.62 V, f= 1 MHz
–59
BW
CIN
-3dB Bandwidth
RL = 50 Ω , CL = 5 pF
750
1.6
2.2
2.9
2.8
MHz
pF
Digital input capacitance
VIN = 0 V or VDD
VS = 6 V, f = 1 MHz (PW package)
VS = 6 V, f = 1 MHz (RTE package)
VS = 6 V, f = 1 MHz
3.1
4.0
3.5
pF
CS(OFF)
Source off-capacitance
pF
CD(OFF)
CS(ON)
CD(ON)
Drain off-capacitance
pF
,
Source and drain on-
capacitance
VS = 6 V, f = 1 MHz
4.6
6.3
pF
8
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7.9 Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
250
650
600
550
500
450
400
350
300
250
200
150
100
VDD= 12V
VSS = -12V
200
150
100
50
VDD= 13.5V
VSS = -13.5V
VDD= 10V
VSS = 0V
VDD= 12V
VSS = 0V
VDD= 15V
VSS = -15V
VDD= 16.5V
VSS = -16.5V
VDD= 14V
VSS = 0V
0
-20
-15
-10
-5
Source or Drain Voltage (V)
0
5
10
15
20
0
2
4
Source or Drain Voltage (V)
6
8
10
12
14
D001
D002
Dual Supply Operation (TA = 25°C)
Single Supply Operation (TA = 25°C)
图 1. On-Resistance vs Source or Drain Voltage
图 2. On-Resistance vs Source or Drain Voltage
250
200
150
100
50
700
600
500
400
300
200
100
0
TA = 125èC
TA = 85èC
TA = 125èC
TA = 85èC
TA = 25èC
TA = -40èC
TA = -40èC
TA = 25èC
0
-15
-10
-5
Source or Drain Voltage (V)
0
5
10
15
0
2
4
Source or Drain Voltage (V)
6
8
10
12
D003
D004
VDD = 15 V, VSS = –15 V
VDD = 12 V, VSS = 0 V
图 3. On-Resistance vs Source or Drain Voltage
图 4. On-Resistance vs Source or Drain Voltage
400
200
0
400
200
0
ID(OFF)-
ID(OFF)_1V
IS(OFF)+
ID(OFF)_10V
ID(ON)+
ID(ON)_10V
IS(OFF)+
IS(OFF)-
-200
-400
-600
-800
-200
-400
-600
IS(OFF)_1V
ID(ON)_10V
ID(ON)_1V
100 125
ID(ON)-
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
150
Ambient Temperature (èC)
Ambient Temperature (èC)
D005
D006
VDD = 15 V, VSS = –15 V
图 5. Leakage Current vs Temperature
VDD = 12 V, VSS = 0 V
图 6. Leakage Current vs Temperature
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Typical Characteristics (接下页)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
4
9
6
VDD= 10V
VSS = -10V
VDD= 10V
VSS = -10V
2
0
VDD= 15V
VSS = -15V
3
0
-3
-6
-9
-2
VDD= 12V
VSS = 0V
VDD= 12V
VSS = 0V
VDD= 15V
VSS = -15V
-4
-15
-10
-5 0
Source Voltage (V)
5
10
15
-15
-10
-5
0
Drain Voltage (V)
5
10
15
D007
D008
TA = 25°C
TA = 25°C
图 7. Charge Injection vs Source Voltage
图 8. Charge Injection vs Drain Voltage
120
90
60
30
0
0
-20
tON (VDD= 12V, VSS= 0V)
VDD= 15V
VSS = -15V
tON (VDD= 15V, VSS= -15V)
-40
-60
-80
tOFF (VDD= 12V, VSS= 0V)
-100
-120
-140
VDD= 12V
VSS = 0V
tOFF (VDD= 15V, VSS= -15V)
-50
-25
0
25
50
75
100
125
150
1E+5
1E+6
1E+7
Frequency (Hz)
1E+8
5E+8
Ambient Temperature (èC)
D009
D001
TA = 25°C
图 9. Turn-On and Turn-Off Times vs Temperature
图 10. Off Isolation vs Frequency
0
100
50
-20
-40
20
10
5
VDD= 5V
VSS = -5V
Adjacent Channels
VDD= 15V
VSS = -15V
2
1
-60
-80
0.5
0.2
0.1
-100
-120
-140
Non-Adjacent Channels
0.05
0.02
0.01
1E+5
1E+6
1E+7
Frequency (Hz)
1E+8
5E+8
1E+1
1E+2
1E+3
Frequency (Hz)
1E+4
1E+5
D001
D001
VDD = 15 V, VSS = –15 V, TA = 25°C
TA = 25°C
图 11. Crosstalk vs Frequency
图 12. THD+N vs Frequency
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Typical Characteristics (接下页)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
-5
0
-20
-40
-10
-15
-20
-60
-80
-100
-120
-140
1E+5
1E+6
1E+7
Frequency(Hz)
1E+8
1E+9
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
1E+7
D001
D001
VDD = 15 V, VSS = –15 V, TA = 25°C
VDD = 15 V, VSS = –15 V, VPP= 0.62 V, TA = 25°C
图 13. On Response vs Frequency
图 14. ACPSRR vs Frequency
8
8
6
4
2
CD(ON), CS(ON)
6
4
2
0
CS(ON), CD(ON)
CD(OFF)
CD(OFF)
CS(OFF)
CS(OFF)
0
0
-15 -12
-9
-6
-3
Source Voltage (V)
0
3
6
9
12
15
2
4
6
Source Voltage (V)
8
10
12
D001
D001
VDD = 15 V, VSS = –15 V, TA = 25°C
图 15. Capacitance vs Source Voltage
VDD = 12 V, VSS = 0 V, TA = 25°C
图 16. Capacitance vs Source Voltage
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8 Parameter Measurement Information
8.1 Truth Tables
表 1, 表 2, 表 3and show the truth tables for the TMUX6111, TMUX6112, and TMUX6113, respectively.
表 1. TMUX6111 Truth Table
SELx
STATE
0
1
All Switch ON
All Switch OFF
表 2. TMUX6112 Truth Table
SELx
STATE
0
1
All Switch OFF
All Switch ON
表 3. TUMUX6113 Truth Table
SELx
STATE
Switch 1, 4 OFF
Switch 2, 3 ON
0
Switch 1, 4 ON
Switch 2, 3 OFF
1
12
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9 Detailed Description
9.1 Overview
The TMUX6111, TMUX6112, and TMUX6113 are 4-channel single-pole/ single-throw (SPDT) switches that
supports dual supplies (±5 V to ±17 V) or single supply (10 V to 17 V) operation. Each channel of the switch is
turned on or turned off based on the state of its corresponding SELx pin. The Functional Block Diagram section
provides a top-level block diagram of the switches.
9.1.1 On-Resistance
The on-resistance of the TMUX6111, TMUX6112, and TMUX6113 is the ohmic resistance across the source (Sx)
and drain (Dx) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol
RON is used to denote on-resistance. The measurement setup used to measure RON is shown in 图 17. Voltage
(V) and current (ICH) are measured using this setup, and RON is computed as shown in 公式 1:
V
S
D
ICH
VS
图 17. On-Resistance Measurement Setup
RON = V / ICH
(1)
9.1.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF)
.
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF)
.
The setup used to measure both off-leakage currents is shown in 图 18
Is (OFF)
ID (OFF)
A
S
D
A
VS
VD
图 18. Off-Leakage Measurement Setup
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Overview (接下页)
9.1.3 On-Leakage Current
On-leakage current is defined as the leakage current that flows into or out of the drain pin when the switch is in
the on state. The source pin is left floating during the measurement. 图 19 shows the circuit used for measuring
the on-leakage current, denoted by ID(ON)
.
ID (ON)
S
D
NC
A
NC = No Connection
VD
图 19. On-Leakage Measurement Setup
9.1.4 Break-Before-Make Delay
The break-before-make delay is a safety feature of the TMUX6113 switch. The TMUX6113's ON switches first
break the connection before the OFF switches make connection. The time delay between the break and the
make is known as break-before-make delay. 图 20 shows the setup used to measure break-before-make delay,
denoted by the symbol tBBM
.
VDD
VSS
3 V
TMUX6113
50%
50%
VIN
VDD
VSS
VS
VS
0 V
VS
S1
S2
D1
D2
Output 1
Output 2
300 Ω
35 pF
0.9 VS
0.9 VS
35 pF
Output 2
300 Ω
SEL1,
SEL2
0 V
VS
0.9 VS
0.9 VS
tBBM2
GND
VIN
Output 1
0 V
tBBM1
tBBM= min (tBBM2, tBBM2
)
图 20. Break-Before-Make Delay Measurement Setup
9.1.5 Turn-On and Turn-Off Time
Turn-on time is defined as the time taken by the output of the TMUX6111, TMUX6112, and TMUX6113 to rise to
a 90% final value after the SELx signal has risen (for NC switches) or fallen (for NO switches) to a 50% final
value. 图 21 shows the setup used to measure turn-on time. Turn-on time is denoted by the symbol tON
.
Turn off time is defined as the time taken by the output of the TMUX6111, TMUX6112, and TMUX6113 to fall to
a 10% initial value after the SELx signal has fallen (for NC switches) or risen (for NO switches) to a 50% initial
value. 图 21 shows the setup used to measure turn-off time. Turn-off time is denoted by the symbol tOFF
.
14
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Overview (接下页)
VDD
VSS
3 V
50%
50%
50%
50%
TMUX6111 VIN
VDD
VSS
0 V
3 V
Output
VS
Sx
Dx
TMUX6112
VIN
SELx
300 Ω
35 pF
0 V
VS
0.9 VS
tON
VIN
GND
tOFF
Output
0.1 VS
图 21. Turn-On and Turn-Off Time Measurement Setup
9.1.6 Charge Injection
The TMUX6111, TMUX6112, and TMUX6113 have a simple transmission-gate topology. Any mismatch in
capacitance between the NMOS and PMOS transistors results in a charge injected into the drain or source
during the falling or rising edge of the gate signal. The amount of charge injected into the source or drain of the
device is known as charge injection, and is denoted by the symbol QINJ. 图 22 shows the setup used to measure
charge injection.
VDD
VSS
3 V
TMUX6111 VIN
VDD
VSS
0 V
3 V
Output
Sx
Dx
RS
VS
TMUX6112
VIN
1 nF
SELx
0 V
VS
VIN
GND
VOUT
Output
QINJ = CL
×
VOUT
图 22. Charge-Injection Measurement Setup
9.1.7 Off Isolation
Off isolation is defined as the voltage at the drain pin (Dx) of the TMUX6111, TMUX6112, and TMUX6113 when
a 1-VRMS signal is applied to the source pin (Sx) of an OFF switch. 图 23 shows the setup used to measure off
isolation. Use 公式 2 to compute off isolation.
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Overview (接下页)
VDD
VSS
VDD
VSS
Network Analyzer
Sx
Dx
VOUT
SELx
VS
50 Ω
50 Ω
VIN
GND
图 23. Off Isolation Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Off Isolation = 20 ∂ Log
(2)
9.1.8 Channel-to-Channel Crosstalk
Channel-to-channel crosstalk is defined as the voltage at the source pin (Sx) of an off-channel, when a 1-VRMS
signal is applied at the source pin of an on-channel. 图 24 shows the setup used to measure, and 公式 3 is the
equation used to compute, channel-to-channel crosstalk.
VDD
VSS
VDD
VSS
Network Analyzer
S1
S2
D1
D2
VOUT
50 Ω
50 Ω
VS
SELx
50 Ω
VIN
GND
图 24. Channel-to-Channel Crosstalk Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Channel-to-Channel Crosstalk = 20 ∂ Log
(3)
9.1.9 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to the
source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx) of the TMUX6111,
TMUX6112, and TMUX6113. 图 25 shows the setup used to measure bandwidth of the switch. Use 公式 4 to
compute the attenuation.
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Overview (接下页)
VDD
VSS
VDD
VSS
Network Analyzer
Sx
Dx
VOUT
SELx
VS
50 Ω
VIN
GND
图 25. Bandwidth Measurement Setup
≈
∆
«
’
÷
◊
V2
Attenuation = 20 ∂ Log
V
1
(4)
9.1.10 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as the
ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the mux
output. The on-resistance of the TMUX6111, TMUX6112, and TMUX6113 varies with the amplitude of the input
signal and results in distortion when the drain pin is connected to a low-impedance load. Total harmonic
distortion plus noise is denoted as THD+N. 图 26 shows the setup used to measure THD+N of the TMUX6111,
TMUX6112, and TMUX6113.
VDD
VSS
VDD
VSS
Audio Precision
Sx
Dx
RS
VOUT
SELx
VS
10k Ω
VIN
GND
图 26. THD+N Measurement Setup
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9.2 Functional Block Diagram
VDD
SW
VSS
VDD
SW
VSS
VDD
SW
VSS
S1
S2
S3
S4
D1
D2
D3
D4
S1
S2
S3
S4
D1
D2
D3
D4
S1
S2
S3
S4
D1
D2
SW
SW
SW
SW
SW
SW
D3
SW
SW
SW
D4
SEL1
SEL2
SEL3
SEL4
SEL1
SEL2
SEL3
SEL4
SEL1
SEL2
SEL3
SEL4
TMUX6111
TMUX6112
TMUX6113
9.3 Feature Description
9.3.1 Ultra-low Leakage Current
The TMUX6111, TMUX6112, and TMUX6113 provide extremely low on- and off-leakage currents. The devices
are capable of switching signals from high source-impedance inputs into a high input-impedance op amp with
minimal offset error because of the ultralow leakage currents. 图 27 shows typical leakage currents of the
devices versus temperature.
400
ID(OFF)-
200
IS(OFF)+
ID(ON)+
0
IS(OFF)+
IS(OFF)-
-200
-400
-600
-800
ID(ON)-
-50
-25
0
25
50
75
100
125
150
Ambient Temperature (èC)
D005
图 27. Leakage Current vs Temperature
9.3.2 Ultra-low Charge Injection
The TMUX6111, TMUX6112, and TMUX6113 are implemented with simple transmission gate topology, as
shown in 图 28. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output
level change whenever the switch is opened or closed. The devices utilize special charge-injection cancellation
circuitry that reduces the source (Sx)-to-drain (Dx) charge injection to as low as 0.6 pC at VS = 0 V, as shown in
图 29.
18
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Feature Description (接下页)
OFF ON
CGDN
CGSN
D
S
CGSP
CGDP
OFF ON
图 28. Transmission Gate Topology
4
VDD= 10V
VSS = -10V
2
0
VDD= 15V
VSS = -15V
-2
VDD= 12V
VSS = 0V
-4
-15
-10
-5 0
Source Voltage (V)
5
10
15
D007
图 29. Source-to-Drain Charge Injection vs Source or Drain Voltage
9.3.3 Bidirectional and Rail-to-Rail Operation
The TMUX6111, TMUX6112, and TMUX6113 conduct equally well from source (Sx) to drain (Dx) or from drain
(Dx) to source (Sx). Each channel of the switches has very similar characteristics in both directions. The input
signal to the devices swings from VSS to VDD without any significant degradation in performance. The on-
resistance of these devices varies with input signal.
9.4 Device Functional Modes
Each channel of the TMUX6111, TMUX6112, and TMUX6113 is turned on or turned off based on the state of its
corresponding SELx pin. The SELx pins are weakly pulled-down through an internal 6 MΩ resistor, allowing the
switches to stay in a determined state when power is applies to the devices. The SELx pins can be connected to
VDD
.
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TMUX6111, TMUX6112, and TMUX6113 offer outstanding input/output leakage currents and ultralow charge
injection. These devices operate up to 34 (dual supply) or 17 V (single supply), and offer true rail-to-rail input and
output. The on-capacitance of the TMUX6111, TMUX6112, and TMUX6113 is low. These features makes the
TMUX6111, TMUX6112, and TMUX6113 a family of precision, robust, high-performance analog multiplexer for
high-voltage, industrial applications.
10.2 Typical Application
One useful application to take advantage of TMUX6111, TMUX6112, and TMUX6113's precision performance is
the sample and hold circuit. A sample and hold circuit can be useful for an analog to digital converter (ADC) to
sample a varying input voltage with improved reliability and stability. It can also be used to store the output
samples from a single digital-to-analog converter (DAC) in a multi-output application. A simple sample and hold
circuit can be realized using an analog switch like one of the TMUX6111, TMUX6112, and TMUX6113 analog
switches.
+15V
VDD
-15V
VSS
CH
+15V
œ
SW1
+15V
CC
RC
VIN1
+
OPA2192
VOUT1
OPA2192
+
SW2
-15V
œ
SEL1/
SEL2
CH
CH
-15V
SEL3/
SEL4
GND
+15V
œ
+15V
+
OPA2192
SW3
SW4
RC
CC
VIN2
VOUT2
+
OPA2192
-15V
œ
-15V
CH
TMUX611x
图 30. A 2-output Sample and Hold Circuit Realized Using the TMUX611x Analog Switch
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ZHCSIN7E –AUGUST 2018–REVISED DECEMBER 2019
Typical Application (接下页)
10.2.1 Design Requirements
The purpose of this precision design is to implement an optimized 2-output sample and hold circuit using a 4-
channel SPST switch. The sample and hold circuit needs to be capable of supporting high voltage output swing
up to ± 15V with minimized pedestal error and fast settling time. The overall system block diagram is illustrated in
图 30.
10.2.2 Detailed Design Procedure
The TMUX6111, TMUX6112, or TMUX6113 switch is used in conjunction with the voltage holding capacitors
(CH) to implement the sample and hold circuit. The basic operation is:
1. When the switch (SW2 or SW3) is closed, it samples the input voltage and charges the holding capacitors
(CH) to the input voltages values.
2. When the switch (SW2 or SW3) is open, the holding capacitors (CH) holds its previous value, maintaining
stable voltage at the amplifier output (VOUT).
Ideally, the switch delivers only the input signals to the holding capacitors. However, when the switch gets
toggled, some amount of charge also gets transferred to the switch output in the form of charge injection,
resulting slight sampling error. The TMUX6111, TMUX6112, and TMUX6113 switches have excellent charge
injection performance of only 0.6 pC, making them ideal choices for this implementation to minimize sampling
error.
Due to switch and capacitor leakage current, the voltage on the hold capacitors droops with time. The
TMUX6111, TMUX6112, and TMUX6113 minimize the droops due to its ultra-low leakage performance. At 25°C,
the TMUX6111, TMUX6112, and TMUX6113 have extremely tiny leakage current at 1 pA typical and 20 pA max.
The TMUX6111, TMUX6112, and TMUX6113 devices also support high voltage capability. The devices support
up to ± 17 V dual supply operation, making it an ideal solution in this high voltage sample and hold application.
A second switch SW1 (or SW4) is also included to operate in parallel with SW2 (or SW3) to reduce pedestal
error during switch toggling. Because both switches are driven at the same potential, they act as common-mode
signal to the op-amp, thereby minimizing the charge injection effects caused by the switch toggling action.
Compensation network consisting of RC and CC is also added to further reduce the pedestal error, whiling
reducing the hold-time glitch and improving the settling time of the circuit.
10.3 Application Curves
TMUX6111, TMUX6112, and TMUX6113 have excellent charge injection performance of only 0.6 pC (typical),
making them ideal choices to minimize sampling error for the sample and hold application. 图 31 shows the plot
for the charge injection vs. source input voltage for TMUX6111, TMUX6112, and TMUX6113.
4
VDD= 10V
VSS = -10V
2
0
VDD= 15V
VSS = -15V
-2
VDD= 12V
VSS = 0V
-4
-15
-10
-5 0
Source Voltage (V)
5
10
15
D007
图 31. Charge injection vs. Source Voltage for TMUX6111, TMUX6112 and TMUX6113
版权 © 2018–2019, Texas Instruments Incorporated
21
TMUX6111, TMUX6112, TMUX6113
ZHCSIN7E –AUGUST 2018–REVISED DECEMBER 2019
www.ti.com.cn
11 Power Supply Recommendations
The TMUX6111, TMUX6112, and TMUX6113 operate across a wide supply range of ±5 V to ±17 V (10 V to 17 V
in single-supply mode). They also perform well with asymmetrical supplies such as VDD = 12 V and VSS= –5 V.
For improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 µF to 10 µF at both the
VDD and VSS pins to ground. Always ensure the ground (GND) connection is established before supplies are
ramped. As a best practice, it is recommended to ramp VSS first before VDD in dual or asymmetrical supply
applications.
The on-resistance of the devices varies with supply voltage, as illustrated in 图 32
250
VDD= 12V
VSS = -12V
200
150
100
50
VDD= 13.5V
VSS = -13.5V
VDD= 15V
VSS = -15V
VDD= 16.5V
VSS = -16.5V
0
-20
-15
-10
-5
0
5
Source or Drain Voltage (V)
10
15
20
D001
图 32. On-Resistance Variation With Supply and Input Voltage
22
版权 © 2018–2019, Texas Instruments Incorporated
TMUX6111, TMUX6112, TMUX6113
www.ti.com.cn
ZHCSIN7E –AUGUST 2018–REVISED DECEMBER 2019
12 Layout
12.1 Layout Guidelines
图 33 illustrates an example of a PCB layout with the TMUX6112PW. Some key considerations are:
•
Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure
that the capacitor voltage rating is sufficient for the VDD and VSS supplies.
•
•
•
Keep the input lines as short as possible.
Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
12.2 Layout Example
Via to
ground plane
SEL1
D1
SEL2
D2
C
S2
S1
VDD
NC
VSS
GND
S4
TMUX6112
C
S3
D4
D3
SEL4
SEL3
Via to
ground plane
图 33. TMUX6112PW Layout Example
版权 © 2018–2019, Texas Instruments Incorporated
23
TMUX6111, TMUX6112, TMUX6113
ZHCSIN7E –AUGUST 2018–REVISED DECEMBER 2019
www.ti.com.cn
13 器件和文档支持
13.1 文档支持
13.1.1 相关文档
•
《采用 e-trim™ 技术的 OPAx192 36V、精密、轨到轨输入/输出、低偏移电压、低输入偏置电流运算放大器》
(SBOS620E)
13.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 4. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
TMUX6111
TMUX6112
TMUX6113
13.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 商标
E2E is a trademark of Texas Instruments.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
24
版权 © 2018–2019, Texas Instruments Incorporated
TMUX6111, TMUX6112, TMUX6113
www.ti.com.cn
ZHCSIN7E –AUGUST 2018–REVISED DECEMBER 2019
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2018–2019, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX6111PWR
TMUX6111RTER
TMUX6112PWR
TMUX6112RTER
TMUX6113PWR
TMUX6113RTER
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
WQFN
TSSOP
WQFN
TSSOP
WQFN
PW
RTE
PW
16
16
16
16
16
16
2000 RoHS & Green
3000 RoHS & Green
2000 RoHS & Green
3000 RoHS & Green
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
MUX6111
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TM6111
MUX6112
TM6112
MUX6113
TM6113
RTE
PW
RTE
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX6111PWR
TMUX6111RTER
TMUX6112PWR
TMUX6112RTER
TMUX6113PWR
TMUX6113RTER
TSSOP
WQFN
TSSOP
WQFN
TSSOP
WQFN
PW
RTE
PW
16
16
16
16
16
16
2000
3000
2000
3000
2000
3000
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
6.9
3.3
6.9
3.3
6.9
3.3
5.6
3.3
5.6
3.3
5.6
3.3
1.6
1.1
1.6
1.1
1.6
1.1
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q2
Q1
Q2
Q1
Q2
RTE
PW
RTE
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMUX6111PWR
TMUX6111RTER
TMUX6112PWR
TMUX6112RTER
TMUX6113PWR
TMUX6113RTER
TSSOP
WQFN
TSSOP
WQFN
TSSOP
WQFN
PW
RTE
PW
16
16
16
16
16
16
2000
3000
2000
3000
2000
3000
356.0
367.0
356.0
367.0
367.0
367.0
356.0
367.0
356.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
RTE
PW
RTE
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016C
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
17
1.5
1
12
0.30
16X
0.18
PIN 1 ID
(OPTIONAL)
13
16
0.1
C A B
SYMM
0.05
0.5
0.3
16X
4219117/B 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
17
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
8
(R0.05)
ALL PAD CORNERS
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219117/B 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219117/B 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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