TMUX6121 [TI]
5pA、±16.5V、1:1 (SPST)、2 通道精密模拟开关(高电平有效);型号: | TMUX6121 |
厂家: | TEXAS INSTRUMENTS |
描述: | 5pA、±16.5V、1:1 (SPST)、2 通道精密模拟开关(高电平有效) 开关 |
文件: | 总32页 (文件大小:1651K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TMUX6121, TMUX6122, TMUX6123
ZHCSJ87A –DECEMBER 2018 –REVISED JULY 2022
TMUX612x ±16.5V、低电容、低漏电流、
精密双路SPST 开关
1 特性
3 说明
• 宽电源电压范围:±5V 至±16.5V(双电源)或10V
至16.5V(单电源)
• 所有引脚的闩锁性能都达到100mA,符合JESD78
II 类A 级要求
TMUX6121、TMUX6122 和TMUX6123 是现代化的互
补金属氧化物半导体 (CMOS) 器件,具有两个独立的
可选单刀单掷 (SPST) 开关。该器件在双电源(±5V 至
±16.5V)、单电源(10V 至 16.5V)或非对称电源供
电时均能正常运行。所有数字输入均具有兼容晶体管到
晶体管逻辑 (TTL) 的阈值,这些阈值可确保 TTL 和
CMOS 逻辑兼容性。
• 低导通电容:4.2pF
• 低输入泄漏电流:0.5pA
• 低电荷注入:0.51 pC
• 轨到轨运行
逻辑 1 会打开 TMUX6121 中数字控制输入上的开关。
要打开 TMUX6122 中的开关, 则需要逻辑 0。
TMUX6123 有一个开关的数字控制逻辑与 TMUX6121
类似, 而另外一个开关上的逻辑则与之相反。
TMUX6123 具有先断后合开关,因此可用于交叉点开
关应用。
• 低导通电阻:120Ω
• 快速开关导通时间:68ns
• 先断后合开关(TMUX6123)
• SELx 引脚可连接至带集成下拉电阻器的VDD
• 逻辑电平:2V 至VDD
• 低电源电流:16µA
TMUX6121、TMUX6122、TMUX6123 是精密开关和
多路复用器器件系列的一部分。这些器件具有非常低的
漏电流和低电荷注入,因此可用于高精度测量应用。由
于具有 16µA 的低电源电流,因此这些器件可用于便携
式应用。
• 人体放电模型(HBM) ESD 保护:所有引脚上均为
±2kV
• 业界通用的VSSOP 封装
2 应用
• 工厂自动化和工业过程控制
• 可编程逻辑控制器(PLC)
• 模拟输入模块
• ATE 测试设备
• 数字万用表
• 电池监控系统
器件信息(1)
封装尺寸(标称值)
器件型号
TMUX6121
封装
TMUX6122
TMUX6123
VSSOP (10)
3.00mm × 3.00mm
(1) 要了解所有可用封装,请参见数据表末尾的封装选项附录。
VDD
VSS
VDD
VSS
VDD
VSS
SW
SW
SW
S1
S2
D1
D2
S1
S2
D1
D2
S1
S2
D1
D2
SW
SW
SW
SEL1
SEL2
SEL1
SEL2
SEL1
SEL2
TMUX6121
TMUX6122
TMUX6123
ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT
简化版原理图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SCDS398
TMUX6121, TMUX6122, TMUX6123
ZHCSJ87A –DECEMBER 2018 –REVISED JULY 2022
www.ti.com.cn
Table of Contents
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................20
9 Application and Implementation..................................21
9.1 Application Information............................................. 21
9.2 Typical Application.................................................... 21
10 Power Supply Recommendations..............................23
11 Layout...........................................................................23
11.1 Layout Guidelines................................................... 23
11.2 Layout Example...................................................... 23
12 Device and Documentation Support..........................24
12.1 Documentation Support.......................................... 24
12.2 接收文档更新通知................................................... 24
12.3 支持资源..................................................................24
12.4 Trademarks.............................................................24
12.5 Electrostatic Discharge Caution..............................24
12.6 术语表..................................................................... 24
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Thermal Information....................................................4
6.4 Recommended Operating Conditions.........................5
6.5 Electrical Characteristics (Dual Supplies: ±15 V)........5
6.6 Switching Characteristics (Dual Supplies: ±15 V).......6
6.7 Electrical Characteristics (Single Supply: 12 V)..........6
6.8 Switching Characteristics (Single Supply: 12 V).........7
7 Parameter Measurement Information..........................12
7.1 Truth Tables.............................................................. 12
8 Detailed Description......................................................13
8.1 Overview...................................................................13
8.2 Functional Block Diagram.........................................18
Information.................................................................... 24
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2018) to Revision A (July 2022)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
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5 Pin Configuration and Functions
SEL1
S1
1
2
3
4
5
10
9
SEL2
VDD
GND
NC
D1
8
D2
7
S2
6
VSS
Not to scale
图5-1. DGS Package, 10-Pin VSSOP (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
SEL1
S1
NO.
1
I
Logic control input 1.
2
I/O
I/O
I/O
I/O
Source pin 1. Can be an input or output.
Drain pin 1. Can be an input or output.
Drain pin 2. Can be an input or output.
Source pin 2. Can be an input or output.
D1
3
D2
4
S2
5
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a
decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
VSS
6
P
NC
7
8
No Connect
P
No internal connection.
Ground (0 V) reference.
GND
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and
GND.
VDD
9
P
I
SEL2
10
Logic control input 2.
(1) I = input, O = output, P = power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
36
UNIT
V
VDD to VSS
VDD to GND
VSS to GND
VDIG
18
V
Supply voltage
–0.3
–18
0.3
V
Digital input pin (SEL1, SEL2) voltage
Digital input pin (SEL1, SEL2) current
Analog input pin (Sx) voltage
Analog input pin (Sx) current
Analog output pin (Dx) voltage
Analog output pin (Dx) current
Ambient temperature
VDD+0.3
30
V
GND –0.3
–30
IDIG
mA
V
VANA_IN
IANA_IN
VANA_OUT
IANA_OUT
TA
VDD+0.3
30
VSS–0.3
–30
mA
V
VDD+0.3
30
VSS–0.3
–30
mA
°C
°C
°C
140
–55
TJ
Junction temperature
150
Tstg
Storage temperature
150
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Thermal Information
TMUX6121/ TMUX6122/
TMUX6123
THERMAL METRIC(1)
DGS (VSSOP)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
180.7
66.2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
103.2
11.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJT
101.3
N/A
ΨJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
10
NOM
MAX
33
UNIT
V
(1)
VDD to VSS
VDD to GND
VDD to GND
VSS to GND
VS
Power supply voltage differential
Positive power supply voltage (singlle supply, VSS = 0 V)
Positive power supply voltage (dual supply)
Negative power supply voltage (dual supply)
Source pins voltage(2)
10
16.5
16.5
–5
VDD
VDD
VDD
25
V
5
V
V
–16.5
VSS
VSS
VSS
–25
–40
V
VD
Drain pin voltage
V
VSEL
Select pin (SEL1, SEL2) voltage
Channel current (TA = 25°C )
V
ICH
mA
°C
TA
Ambient temperature
125
(1) VDD and VSS can be any value as long as 10 V ≤(VDD –VSS) ≤33 V.
(2) VS is the voltage on both S pins.
6.5 Electrical Characteristics (Dual Supplies: ±15 V)
at TA = 25°C, VDD = 15 V, and VSS = −15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG SWITCH
VA
Analog signal range
On-resistance
VSS
VDD
135
165
210
245
6
V
TA = –40°C to +125°C
TA = –40°C to +125°C
VS = 0 V, IS = 1 mA
120
140
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
RON
VS = ±10 V, IS = 1 mA
VS = ±10 V, IS = 1 mA
TA = –40°C to +85°C
TA = –40°C to +125°C
2.4
22
On-resistance mismatch
between channels
9
TA = –40°C to +85°C
TA = –40°C to +125°C
ΔRON
11
45
VS = –10 V, 0 V, +10 V, IS
= 1 mA
47
RON_FLAT
On-resistance flatness
TA = –40°C to +85°C
TA = –40°C to +125°C
49
Ω
%/°C
nA
RON_DRIFT On-resistance drift
VS = 0 V
0.5
0.005
0.02
0.05
0.2
–0.02
–0.12
–1
Switch state is off, VS =
+10 V/ –10 V, VD = –10 TA = –40°C to +85°C
V/ + 10 V
IS(OFF)
ID(OFF)
ID(ON)
Source off leakage current(1)
nA
nA
nA
nA
nA
nA
nA
nA
TA = –40°C to +125°C
0.005
0.01
0.02
0.05
0.2
–0.02
–0.12
–1
Switch state is off, VS =
+10 V/ –10 V, VD = –10 TA = –40°C to +85°C
V/ +10 V
Drain off leakage current(1)
Drain on leakage current
TA = –40°C to +125°C
0.04
0.1
–0.04
–0.25
–1.8
Switch state is on, VS
=
+10 V/ –10 V, VD = –10 TA = –40°C to +85°C
V/ +10 V
0.4
TA = –40°C to +125°C
DIGITAL INPUT (SELx pins)
VIH
VIL
Logic voltage high
Logic voltage low
2
V
V
0.8
Pull-down resistance on INx
pins
RPD(IN)
6
MΩ
POWER SUPPLY
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MAX UNIT
6.5 Electrical Characteristics (Dual Supplies: ±15 V) (continued)
at TA = 25°C, VDD = 15 V, and VSS = −15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
16
21
22
23
10
11
12
µA
µA
µA
µA
µA
µA
IDD
VDD supply current
VA = 0 V or 3.3 V, VS = 0 V TA = –40°C to +85°C
TA = –40°C to +125°C
7
ISS
VSS supply current
VA = 0 V or 3.3 V, VS = 0 V TA = –40°C to +85°C
TA = –40°C to +125°C
(1) When VS is positive, VD is negative, and vice versa.
6.6 Switching Characteristics (Dual Supplies: ±15 V)
at TA = 25°C, VDD = 15 V, and VSS = −15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
68
86
ns
ns
VS = ±10 V, RL = 300 Ω, CL = 35 pF
VS = ±10 V, RL = 300 Ω, CL = 35 pF, TA = –40°C to
+85°C
110
tON
Switch turn-on time
VS = ±10 V, RL = 300 Ω, CL = 35 pF, TA = –40°C to
+125°C
121
76
ns
ns
ns
57
VS = ±10 V, RL = 300 Ω, CL = 35 pF
VS = ±10 V, RL = 300 Ω, CL = 35 pF, TA = –40°C to
+85°C
82
tOFF
Switch turn-off time
VS = ±10 V, RL = 300 Ω, CL = 35 pF, TA = –40°C to
+125°C
85
ns
ns
Break-before-make time delay
(TMUX6123 Only)
VS = 10 V, RL = 300 Ω, CL = 35 pF, TA = –40°C to
+125°C
tBBM
20
40
QJ
Charge injection
Off-isolation
0.51
pC
dB
dB
dB
dB
dB
MHz
%
VS = 0 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 10 kΩ, CL = 5 pF, VPP= 0.62 V on VDD, f= 1 MHz
RL = 10 kΩ, CL = 5 pF, VPP= 0.62 V on VSS, f= 1 MHz
RL = 50 Ω, CL = 5 pF
OISO
XTALK
IL
–85
–110
–7.7
–61
–61
630
Channel-to-channel crosstalk
Insertion loss
AC Power Supply Rejection
Ratio
ACPSRR
BW
−3 dB Bandwidth
THD
Total harmonic distortion + noise
Digital input capacitance
Source off-capacitance
Drain off-capacitance
0.08
1.2
RL = 10 kΩ, CL = 5 pF, f= 20 Hz to 20 kHz
VSELx = 0 V or VDD
CIN
pF
CS(OFF)
CD(OFF)
VS = 0 V, f = 1 MHz
1.9
2.5
2.6
pF
VS = 0 V, f = 1 MHz
2.2
pF
CS(ON),
CD(ON)
Source and drain on-
capacitance
VS = 0 V, f = 1 MHz
4.2
5
pF
6.7 Electrical Characteristics (Single Supply: 12 V)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG SWITCH
VA
Analog signal range
VSS
VDD
V
TA = –40°C to +125°C
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6.7 Electrical Characteristics (Single Supply: 12 V) (continued)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
230
265
355
405
9
Ω
Ω
Ω
Ω
Ω
RON
On-resistance
VS = 10 V, IS = 1 mA
TA = –40°C to +85°C
TA = –40°C to +125°C
1
On-resistance mismatch
between channels
12
VS = 10 V, IS = 1 mA
VS = 0 V
TA = –40°C to +85°C
TA = –40°C to +125°C
ΔRON
14
Ω
%/°C
nA
RON_DRIFT On-resistance drift
0.48
0.005
0.02
0.04
0.13
0.02
0.04
0.13
0.04
0.08
0.25
–0.02
–0.08
–0.75
–0.02
–0.08
–0.75
–0.04
–0.16
–1.5
Switch state is off, VS = 10
V/ 1 V, VD = 1 V/ 10 V
IS(OFF)
ID(OFF)
ID(ON)
Source off leakage current(1)
nA
nA
nA
nA
nA
nA
nA
nA
TA = –40°C to +85°C
TA = –40°C to +125°C
0.005
0.01
Switch state is off, VS = 10
V/ 1 V, VD = 1 V/ 10 V
Drain off leakage current(1)
Drain on leakage current
TA = –40°C to +85°C
TA = –40°C to +125°C
Switch state is on, VS
=
TA = –40°C to +85°C
TA = –40°C to +125°C
floating, VD = 1 V/ 10 V
DIGITAL INPUT (SELx pins)
VIH
VIL
Logic voltage high
Logic voltage low
2
V
V
0.8
Pull-down resistance on INx
pins
RPD(IN)
6
MΩ
POWER SUPPLY
VA = 0 V or 3.3 V, VS = 0 V
11
14
16
17
µA
µA
µA
IDD
VDD supply current
VA = 0 V or 3.3 V, VS = 0 V VA = 0 V or 3.3 V, VS = 0 V
VA = 0 V or 3.3 V, VS = 0 V
(1) When VS is positive, VD is negative, and vice versa.
6.8 Switching Characteristics (Single Supply: 12 V)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
74
82
89
ns
ns
VS = 8 V, RL = 300 Ω, CL = 35 pF
VS = 8 V, RL = 300 Ω, CL = 35 pF, TA = –40°C to
+85°C
tON
Switch turn-on time
VS = 8 V, RL = 300 Ω, CL = 35 pF, TA = –40°C to
+125°C
93
75
83
ns
ns
ns
56
VS = 8 V, RL = 300 Ω, CL = 35 pF
VS = 8 V, RL = 300 Ω, CL = 35 pF, TA = –40°C to
+85°C
tOFF
Switch turn-off time
VS = 8 V, RL = 300 Ω, CL = 35 pF, TA = –40°C to
+125°C
85
ns
ns
Break-before-make time delay
(TMUX6123 only)
VS = 8 V, RL = 300 Ω, CL = 35 pF, TA = –40°C to
+125°C
tBBM
20
37
QJ
Charge injection
0.14
-85
pC
dB
dB
VS = 6 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz
OISO
XTALK
Off-isolation
Channel-to-channel crosstalk
–115
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6.8 Switching Characteristics (Single Supply: 12 V) (continued)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IL
Insertion loss
dB
RL = 50 Ω, CL = 5 pF, f = 1 MHz
–15
AC Power Supply Rejection
Ratio
ACPSRR
dB
RL = 10 kΩ, CL = 5 pF, VPP= 0.62 V, f= 1 MHz
–61
BW
-3dB Bandwidth
500
1.3
2.2
2.5
MHz
pF
RL = 50 Ω, CL = 5 pF
VIN = 0 V or VDD
CIN
Digital input capacitance
Source off-capacitance
Drain off-capacitance
CS(OFF)
CD(OFF)
CS(ON)
CD(ON)
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
2.8
2.8
pF
pF
,
Source and drain on-
capacitance
VS = 6 V, f = 1 MHz
4.8
6.1
pF
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Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
250
200
150
100
50
700
650
600
550
500
450
400
350
300
250
200
150
100
VDD= 13.6V
VSS = -13.5V
VDD= 12V
VSS = -12V
VDD= 14V
VSS = 0V
VDD= 12V
VSS = 0V
VDD= 15V
VSS = -15V
VDD= 16.5V
VSS = -16.5V
VDD= 10V
VSS = 0V
0
0
2
4
6
8
10
Source or Drain Voltage (V)
12
14
-20
-15
-10
-5
0
5
Source or Drain Voltage (V)
10
15
20
D002
D001
Dual Supply Operation (TA = 25°C)
图6-2. On-Resistance vs Source or Drain Voltage
Dual Supply Operation (TA = 25°C)
图6-1. On-Resistance vs Source or Drain Voltage
250
700
TA = 125èC
TA = 85èC
600
500
400
300
200
100
0
TA = 125èC
200
150
100
50
TA = 85èC
TA = 25èC
TA = -40èC
TA = -40èC
TA = 25èC
0
-15
-10
-5
Source or Drain Voltage (V)
0
5
10
15
0
2
4
Source or Drain Voltage (V)
6
8
10
12
D003
D004
VDD = 12 V, VSS = 0 V
VDD = 15 V, VSS = –15 V
图6-4. On-Resistance vs Source or Drain Voltage
图6-3. On-Resistance vs Source or Drain Voltage
400
400
ID(OFF)+
IS(OFF)+
IS(ON)_10V
ID(OFF)_1V
200
0
200
0
ID(ON)+
ID(OFF)_10V
-200
-400
-600
-800
ID(OFF)-
IS(OFF)_10V
-200
-400
-600
IS(OFF)-
ID(ON)-
IS(OFF)_1V
ID(ON)_1V
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Ambient Temperature (èC)
Ambient Temperature (èC)
D005
D006
VDD = 12 V, VSS = 0 V
VDD = 15 V, VSS = –15 V
图6-5. Leakage Current vs Temperature
图6-6. Leakage Current vs Temperature
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Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
2
7
5
VDD= 15V
VSS = -15V
VDD= 15V
SS = -15V
VDD= 12V
VSS = 0V
V
1
0
3
VDD= 10V
VSS = -10V
1
-1
-3
-5
-7
VDD= 10V
VSS = -10V
-1
VDD= 12V
VSS = 0V
-2
-15
-10
-5 0
Source Voltage (V)
5
10
15
-15
-10
-5
0
Drain Voltage (V)
5
10
15
D007
D008
TA = 25°C
TA = 25°C
图6-7. Charge Injection vs Source Voltage
图6-8. Charge Injection vs Drain Voltage
150
120
90
60
30
0
0
-20
tON(VDD= 12V, VSS= 0V)
VDD= 12V, VSS= 0V
-40
tON(VDD= 15V, VSS= -15V)
-60
-80
VDD= 15V, VSS= -15V
-100
-120
-140
tOFF(VDD= 15V, VSS= -15V)
tOFF(VDD= 12V, VSS= 0V)
1E+5
1E+6
1E+7
Frequency (Hz)
1E+8
5E+8
-50
-25
0
25
50
75
100
125
150
Ambient Temperature (èC)
D010
D009
TA = 25°C
.
图6-10. Off Isolation vs Frequency
图6-9. Turn-On and Turn-Off Times vs Temperature
0
100
50
-20
20
10
5
VDD= 5V, VSS= -5V
VDD= 12V, VSS= 0V
-40
VDD= 15V, VSS= -15V
2
1
-60
-80
0.5
0.2
0.1
-100
0.05
-120
-140
VDD= 15V, VSS= -15V
1E+8
0.02
0.01
1E+1
1E+2
1E+3
Frequency (Hz)
1E+4
1E+5
1E+5
1E+6
1E+7
Frequency (Hz)
5E+8
D012
D011
TA = 25°C
VDD = 15 V, VSS = –15 V, TA = 25°C
图6-11. Crosstalk vs Frequency
图6-12. THD+N vs Frequency
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Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
-5
0
-20
-40
-60
-80
-10
-15
-20
-25
VDD= 12V, VSS= 0V
VDD= 15V, VSS= -15V
-100
1E+5
-30
1E+5
2E+53E+5 5E+5
1E+6
Frequency (Hz)
2E+63E+6 5E+6
1E+7
1E+6
1E+7
Frequency(Hz)
1E+8
1E+9
D016
D013
VDD = 15 V, VSS = –15 V, VPP= 0.62 V, TA = 25°C
图6-14. ACPSRR vs Frequency
VDD = 15 V, VSS = –15 V, TA = 25°C
图6-13. On Response vs Frequency
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
CD(ON), CS(ON)
CS(ON), CD(ON)
CD(OFF)
CD(OFF)
CS(OFF)
CS(OFF)
0
0
-15 -12
-9
-6
-3
Source Voltage (V)
0
3
6
9
12
15
2
4
6
Source Voltage (V)
8
10
12
D014
D015
VDD = 12 V, VSS = 0 V, TA = 25°C
图6-16. Capacitance vs Source Voltage
VDD = 15 V, VSS = –15 V, TA = 25°C
图6-15. Capacitance vs Source Voltage
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7 Parameter Measurement Information
7.1 Truth Tables
表7-1, 表7-2, and 表7-3 show the truth tables for the TMUX6121, TMUX6122, and TMUX6123, respectively.
表7-1. TMUX6121 Truth Table
SELx
STATE
0
1
All Switch OFF
All Switch ON
表7-2. TMUX6122 Truth Table
SELx
STATE
0
1
All Switch ON
All Switch OFF
表7-3. TMUX6123 Truth Table
SELx
STATE
Switch 1 OFF
Switch 2 ON
0
Switch 1 ON
Switch 2 OFF
1
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8 Detailed Description
8.1 Overview
The TMUX6121, TMUX6122, and TMUX6123 are 2-channel single-pole/ single-throw (SPDT) switches that
support dual supplies (±5 V to ±16.5 V) or single supply (10 V to 16.5 V) operation. Each channel of the switch is
turned on or turned off based on the state of its corresponding SELx pin. 节 8.2 provides a top-level block
diagram of the switches.
8.1.1 On-Resistance
The on-resistance of the TMUX6121, TMUX6122, and TMUX6123 is the ohmic resistance across the source
(Sx) and drain (D) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol
RON is used to denote on-resistance. The measurement setup used to measure RON is shown in 图 8-1. Voltage
(V) and current (ICH) are measured using this setup, and RON is computed as shown in 方程式1:
V
S
D
ICH
VS
图8-1. On-Resistance Measurement Setup
RON = V / ICH
(1)
8.1.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF)
.
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF)
.
The setup used to measure both off-leakage currents is shown in 图8-2.
Is (OFF)
ID (OFF)
A
S
D
A
VS
VD
图8-2. Off-Leakage Measurement Setup
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8.1.3 On-Leakage Current
On-leakage current is defined as the leakage current that flows into or out of the drain pin when the switch is in
the on state. The source pin is left floating during the measurement. 图 8-3 shows the circuit used for measuring
the on-leakage current, denoted by ID(ON)
.
ID (ON)
S
D
NC
A
NC = No Connection
VD
图8-3. On-Leakage Measurement Setup
8.1.4 Turn-On and Turn-Off Time
Turn-on time is defined as the time taken by the output of the TMUX6121, TMUX6122, and TMUX6123 to rise to
a 90% final value after the SELx signal has risen (for NO switches) or fallen (for NC switches) to a 50% final
value. 图8-4 shows the setup used to measure turn-on time. Turn-on time is denoted by the symbol tON
.
Turn off time is defined as the time taken by the output of the TMUX6121, TMUX6122, and TMUX6123 to fall to
a 10% initial value after the SELx signal has fallen (for NO switches) or risen (for NC switches) to a 50% initial
value. 图8-4 shows the setup used to measure turn-off time. Turn-off time is denoted by the symbol tOFF
.
VDD
VSS
3 V
50%
50%
50%
50%
TMUX6122 VIN
VDD
VSS
0 V
3 V
Output
VS
Sx
Dx
TMUX6121
VIN
SELx
300 Ω
35 pF
0 V
VS
0.9 VS
tON
VIN
GND
tOFF
Output
0.1 VS
图8-4. Transition-Time Measurement Setup
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8.1.5 Break-Before-Make Delay
The break-before-make delay is a safety feature of the TMUX6123 switch. The TMUX6123's ON switches first
break the connection before the OFF switches make connection. The time delay between the break and the
make is known as break-before-make delay. 图 8-5 shows the setup used to measure break-before-make delay,
denoted by the symbol tBBM
.
VDD
VSS
3 V
TMUX6123
50%
50%
VIN
VDD
VSS
VS
VS
0 V
VS
S1
S2
D1
D2
Output 1
Output 2
300 Ω
35 pF
0.9 VS
0.9 VS
35 pF
Output 2
300 Ω
SEL1,
SEL2
0 V
VS
0.9 VS
0.9 VS
tBBM2
GND
VIN
Output 1
0 V
tBBM1
tBBM= min (tBBM2, tBBM2
)
图8-5. Break-Before-Make Delay Measurement Setup
8.1.6 Charge Injection
The TMUX6121, TMUX6122, and TMUX6123 have a simple transmission-gate topology. Any mismatch in
capacitance between the NMOS and PMOS transistors results in a charge injected into the drain or source
during the falling or rising edge of the gate signal. The amount of charge injected into the source or drain of the
device is known as charge injection, and is denoted by the symbol QINJ. 图 8-6 shows the setup used to
measure charge injection.
VDD
VSS
3 V
TMUX6122 VIN
VDD
VSS
0 V
3 V
Output
Sx
Dx
RS
VS
TMUX6121
VIN
1 nF
SELx
0 V
VS
VIN
GND
VOUT
Output
QINJ = CL ×
VOUT
图8-6. Charge-Injection Measurement Setup
8.1.7 Off Isolation
Off isolation is defined as the voltage at the drain pin (Dx) of the TMUX6121, TMUX6122, and TMUX6123 when
a 1-VRMS signal is applied to the source pin (Sx) of an OFF switch. 图 8-7 shows the setup used to measure off
isolation. Use 方程式2 to compute off isolation.
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VDD
VSS
VDD
VSS
Network Analyzer
Sx
Dx
VOUT
SELx
VS
50 Ω
50 Ω
VIN
GND
图8-7. Off Isolation Measurement Setup
≈
∆
«
’
VOUT
Off Isolation = 20 ∂ Log
÷
◊
VS
(2)
8.1.8 Channel-to-Channel Crosstalk
Channel-to-channel crosstalk is defined as the voltage at the source pin (Sx) of an off-channel, when a 1-VRMS
signal is applied at the source pin (Sx) of an on-channel. 图 8-8 shows the setup used to measure, and 方程式 3
is the equation used to compute, channel-to-channel crosstalk.
VDD
VSS
VDD
VSS
Network Analyzer
S1
S2
D1
D2
VOUT
50 Ω
50 Ω
VS
SELx
50 Ω
VIN
GND
图8-8. Channel-to-Channel Crosstalk Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Channel-to-Channel Crosstalk = 20 ∂ Log
(3)
8.1.9 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to the
source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the TMUX6121, TMUX6122,
and TMUX6123. 图8-9 shows the setup used to measure bandwidth of the switch. Use 方程式 4 to compute the
attenuation.
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VDD
VSS
VDD
VSS
Network Analyzer
Sx
Dx
VOUT
SELx
VS
50 Ω
VIN
GND
图8-9. Bandwidth Measurement Setup
≈
∆
«
’
÷
◊
V2
Attenuation = 20 ∂ Log
V
1
(4)
8.1.10 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as
the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the
mux output. The on-resistance of the TMUX6121, TMUX6122, and TMUX6123 varies with the amplitude of the
input signal and results in distortion when the drain pin is connected to a low-impedance load. Total harmonic
distortion plus noise is denoted as THD+N. 图8-10 shows the setup used to measure THD+N of the TMUX6121,
TMUX6122, and TMUX6123.
VDD
VSS
VDD
VSS
Audio Precision
Sx
Dx
RS
VOUT
SELx
VS
10k Ω
VIN
GND
图8-10. THD+N Measurement Setup
8.1.11 AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply
voltage pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a
sine wave of 620 mVPP. The ratio of the amplitude of signal on the output to the amplitude of the modulated
signal is the AC PSRR. 图 8-11 shows the setup used to measure ACPSRR of the TMUX6121, TMUX6122, and
TMUX6123.
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VDD
Network Analyzer
DC Bias
Injector
VSS
VDD
VSS
620 mVPP
VIN
VBIAS
SW
Sx
VOUT
Dx
VSEL
10k Ω
5 pF
SELx
50 Ω
GND
VBIAS = 0 V
ACPSRR= 20 × Log (VOUT/ VIN
)
图8-11. AC PSRR Measurement Setup
节 8.2 provides a top-level block diagram of the TMUX6121, TMUX6122, and TMUX6123. The devices are 2-
channel, single-ended, analog switches. Each channel is turned on or turned off based on the state of the
address lines and enable pin.
8.2 Functional Block Diagram
VDD
VSS
VDD
VSS
VDD
VSS
SW
SW
SW
S1
S2
D1
D2
S1
S2
D1
D2
S1
S2
D1
D2
SW
SW
SW
SEL1
SEL2
SEL1
SEL2
SEL1
SEL2
TMUX6121
TMUX6122
TMUX6123
ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT
8.3 Feature Description
8.3.1 Ultralow Leakage Current
The TMUX6121, TMUX6122, and TMUX6123 provide extremely low on- and off-leakage currents. The devices
are capable of switching signals from high source-impedance inputs into a high input-impedance op amp with
minimal offset error because of the ultralow leakage currents. 图 8-12 shows typical leakage currents of the
devices versus temperature.
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400
200
0
ID(OFF)+
IS(OFF)+
ID(ON)+
-200
-400
-600
-800
ID(OFF)-
IS(OFF)-
ID(ON)-
-50
-25
0
25
50
75
100
125
150
Ambient Temperature (èC)
D005
图8-12. Leakage Current vs Temperature
8.3.2 Ultralow Charge Injection
The TMUX6121 is implemented with simple transmission gate topology, as shown in 图 8-13. Any mismatch in
the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch
is opened or closed.
OFF ON
CGDN
CGSN
D
S
CGSP
CGDP
OFF ON
图8-13. Transmission Gate Topology
The devices utilize special charge-injection cancellation circuitry that reduces the source (Sx)-to-drain (Dx)
charge injection to as low as 0.51 pC at VS = 0 V, as shown in 图8-14.
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2
VDD= 15V
VSS = -15V
VDD= 12V
VSS = 0V
1
0
VDD= 10V
VSS = -10V
-1
-2
-15
-10
-5 0
Source Voltage (V)
5
10
15
D007
图8-14. Source-to-Drain Charge Injection vs Source or Drain Voltage
8.3.3 Bidirectional and Rail-to-Rail Operation
The TMUX6121, TMUX6122, and TMUX6123 conduct equally well from source (Sx) to drain (Dx) or from drain
(Dx) to source (Sx). Each channel of the switches has very similar characteristics in both directions. The input
signal to the devices swings from VSS to VDD without any significant degradation in performance. The on
resistance of these devices varies with input signal.
8.4 Device Functional Modes
Each channel of the TMUX6121, TMUX6122, and TMUX6123 is turned on or turned off based on the state of its
corresponding SELx pin. The SELx pins are weakly pulled-down through an internal 6 MΩ resistor, allowing the
switches to stay in a determined state when power is applies to the devices. The SELx pins can be connected to
VDD
.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
9.1 Application Information
The TMUX6121, TMUX6122, and TMUX6123 offer outstanding input/output leakage currents and ultralow
charge injection. These devices operate up to 33 (dual supply) or 16.5 V (single supply), and offer true rail-to-rail
input and output. The on-capacitance of the TMUX6121, TMUX6122, and TMUX6123 is low. These features
makes the TMUX6121, TMUX6122, and TMUX6123 a family of precision, robust, high-performance analog
multiplexer for high-voltage, industrial applications.
9.2 Typical Application
One useful application to take advantage of TMUX6121, TMUX6122, and TMUX6123's precision performance is
the sample and hold circuit. A sample and hold circuit can be useful for an analog to digital converter (ADC) to
sample a varying input voltage with improved reliability and stability. It can also be used to store the output
samples from a single digital-to-analog converter (DAC) in a multi-output application. A simple sample and hold
circuit can be realized using an analog switch like one of the TMUX6121, TMUX6122, and TMUX6123 analog
switches.
+15V
VDD
-15V
VSS
CH
+15V
+
SW1
+15V
CC
RC
VIN1
+
OPA2192
VOUT
œ
OPA2192
SW2
-15V
œ
SEL1/
SEL2
CH
-15V
GND
TMUX612x
图9-1. A Sample and Hold Circuit Realized Using the TMUX611x Analog Switch
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9.2.1 Design Requirements
The purpose of this precision design is to implement an optimized 2-output sample and hold circuit using a 4-
channel SPST switch. The sample and hold circuit needs to be capable of supporting high voltage output swing
up to ± 15 V with minimized pedestal error and fast settling time. The overall system block diagram is shown in
图9-1.
9.2.2 Detailed Design Procedure
The TMUX6121, TMUX6122, or TMUX6123 switch is used in conjunction with the voltage holding capacitors
(CH) to implement the sample and hold circuit. The basic operation is:
1. When the switch SW2 is closed, it samples the input voltage and charges the holding capacitors (CH) to the
input voltages values.
2. When the switch SW2 is open, the holding capacitors (CH) holds its previous value, maintaining stable
voltage at the amplifier output (VOUT
)
Ideally, the switch delivers only the input signals to the holding capacitors. However, when the switch gets
toggled, some amount of charge also gets transferred to the switch output in the form of charge injection,
resulting slight sampling error. The TMUX6121, TMUX6122, and TMUX6123 switches have excellent charge
injection performance of only 0.51 pC, making them ideal choices for this implementation to minimize sampling
error. Due to switch and capacitor leakage current, the voltage on the hold capacitors droops with time. The
TMUX6121, TMUX6122, and TMUX6123 minimize the droops due to its ultra-low leakage performance. At 25°C,
the TMUX6111, TMUX6112, and TMUX6113 have extremely tiny leakage current at 0.5 pA typical and 20 pA
maximum. The TMUX6121, TMUX6122, and TMUX6123 devices also support high voltage capability. The
devices support up to ± 16.5 V dual supply operation, making it an ideal solution in this high voltage sample and
hold application.
A second switch SW1 is also included to operate in parallel with SW2 to reduce pedestal error during switch
toggling. Because both switches are driven at the same potential, they act as common-mode signal to the op-
amp, thereby minimizing the charge injection effects caused by the switch toggling action. Compensation
network consisting of RC and CC is also added to further reduce the pedestal error, whiling reducing the hold-
time glitch and improving the settling time of the circuit.
9.2.3 Application Curve
TMUX6121, TMUX6122, and TMUX6123 have excellent charge injection performance of only 0.51 pC (typical),
making them ideal choices to minimize sampling error for the sample and hold application. 图 9-2 shows the plot
for the charge injection versus source input voltage for TMUX6121, TMUX6122, and TMUX6123.
2
VDD= 15V
VSS = -15V
VDD= 12V
VSS = 0V
1
0
VDD= 10V
VSS = -10V
-1
-2
-15
-10
-5 0
Source Voltage (V)
5
10
15
D007
图9-2. Charge Injection vs. Source Voltage for TMUX6121, TMUX6122 and TMUX6123
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TMUX6121, TMUX6122, TMUX6123
ZHCSJ87A –DECEMBER 2018 –REVISED JULY 2022
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10 Power Supply Recommendations
The TMUX6121, TMUX6122, and TMUX6123 operate across a wide supply range of ±5 V to ±16.5 V (10 V to
16.5 V in single-supply mode). They also perform well with asymmetrical supplies such as VDD = 12 V and VSS
=
–5 V. For improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 µF to 10 µF at
both the VDD and VSS pins to ground. Always ensure the ground (GND) connection is established before
supplies are ramped. As a best practice, it is recommended to ramp VSS first before VDD in dual or asymmetrical
supply applications.
The on-resistance of the TMUX6121, TMUX6122, and TMUX6123 varies with supply voltage, as shown in 图
10-1
250
VDD= 13.6V
VSS = -13.5V
VDD= 12V
VSS = -12V
200
150
100
VDD= 15V
VSS = -15V
50
VDD= 16.5V
VSS = -16.5V
0
-20
-15
-10
-5
0
5
Source or Drain Voltage (V)
10
15
20
D001
图10-1. On-Resistance Variation With Supply and Input Voltage
11 Layout
11.1 Layout Guidelines
图11-1 shows an example of a PCB layout with the TMUX6121, TMUX6122, and TMUX6123.
Some key considerations are:
1. Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure
that the capacitor voltage rating is sufficient for the VDD and VSS supplies.
2. Keep the input lines as short as possible.
3. Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
4. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
SEL1
S1
SEL2
VDD
GND
NC
C
C
TMUX6121
TMUX6122
TMUX6123
Via to
ground plane
D1
D2
S2
VSS
图11-1. TMUX6121 Layout Example
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TMUX6121, TMUX6122, TMUX6123
ZHCSJ87A –DECEMBER 2018 –REVISED JULY 2022
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, OPAx192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias
Current Op Amp with e-trim™
12.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX6121DGSR
TMUX6122DGSR
TMUX6123DGSR
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
DGS
DGS
DGS
10
10
10
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
1Q16
1Q26
1Q36
Samples
Samples
Samples
NIPDAUAG
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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3-Jun-2022
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX6121DGSR
TMUX6122DGSR
TMUX6123DGSR
VSSOP
VSSOP
VSSOP
DGS
DGS
DGS
10
10
10
2500
2500
2500
330.0
330.0
330.0
12.4
12.4
12.4
5.3
5.3
5.3
3.4
3.4
3.4
1.4
1.4
1.4
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMUX6121DGSR
TMUX6122DGSR
TMUX6123DGSR
VSSOP
VSSOP
VSSOP
DGS
DGS
DGS
10
10
10
2500
2500
2500
366.0
366.0
366.0
364.0
364.0
364.0
50.0
50.0
50.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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