TMUX7308F_V01 [TI]
TMUX730xF ±60-V Fault-Protected, 8:1 and Dual 4:1 Multiplexers with 1.8-V Logic;
| 型号： | TMUX7308F_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TMUX730xF ±60-V Fault-Protected, 8:1 and Dual 4:1 Multiplexers with 1.8-V Logic |
| 文件： | 总40页 (文件大小：1597K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
TMUX730xF ±60-V Fault-Protected, 8:1 and Dual 4:1 Multiplexers with 1.8-V Logic
1 Features
3 Description
•
Wide supply range:
The TMUX7308F and TMUX7309F are modern
complementary metal-oxide semiconductor (CMOS)
analog multiplexers in 8:1 (single ended) and 4:1
(differential) configurations. The devices work well
with dual supplies (±5 V to ±22 V), a single supply
(8 V to 44 V), or asymmetric supplies. All control
inputs support logic levels from 1.8 V to 44 V, enabling
system level flexibility for controlling the multiplexer.
– Dual supply: ±5 V to ±22 V
– Single supply: 8 V to 44 V
Integrated fault protection:
•
– Overvoltage protection,
source to supplies or to Ddrain: ±85 V
– Overvoltage protection: ±60 V
– Powered-off protection: ±60 V
– Non-fault channels continue to operate with low
leakage currents
– Known state without digital inputs present
– Output clamped to the supply in overvoltage
condition
Latch-up immunity by device construction
Break-before-make switching action
Logic levels: 1.8 V to VDD
Industry standard TSSOP and
smaller WQFN packages
When no power supplies are present, the switch
channels remain in the OFF state regardless of
switch input conditions and logic control status. Under
normal operation conditions, if the analog input signal
level on any Sx pin exceeds the supply voltage (VDD
or VSS) by a threshold voltage (VT), the channel turns
OFF and the Sx pin becomes high impedance. When
the fault channel is selected, the drain pin (D or Dx) is
pulled to the supply (VDD or VSS) that was exceeded.
The device blocks fault voltage up to +60 V or –60
V relative to ground in both powered and powered-off
conditions.
•
•
•
•
2 Applications
•
•
•
•
•
•
•
Factory automation and control
Programmable logic controllers (PLC)
Analog input modules
Semiconductor test equipment
Battery test equipment
The low capacitance, low charge injection, and
integrated fault protection enable the TMUX7308F
and TMUX7309F devices to be used in front end
data acquisition applications where high performance
and high robustness are both critical. The devices are
available in a standard TSSOP package and smaller
WQFN package (ideal if PCB space is limited).
Servo drive control module
Data acquisition systems (DAQ)
VDD
VSS
VDD
VSS
Device Information(1)
SW
SW
SW
PART NUMBER
PACKAGE
TSSOP (16)
WQFN (16)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
4.00 mm × 4.00 mm
S1
S2
S1A
DA
DB
TMUX7308F
TMUX7309F
SW
SW
S4A
S1B
D
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SW
SW
S4B
S8
A1
A2
A3
EN
A1
A2
EN
Fault Detection/
Switch Driver/
Logic Decoder
Fault Detection/
Switch Driver/
Logic Decoder
TMUX7308F
TMUX7309F
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Thermal Information ...................................................5
6.4 Recommended Operating Conditions ........................6
6.5 Electrical Characteristics (Global) ..............................6
6.6 ±15 V Dual Supply: Electrical Characteristics ............7
6.7 ±20 V Dual Supply: Electrical Characteristics ..........10
6.8 12 V Single Supply: Electrical Characteristics ......... 13
7 Parameter Measurement Information..........................16
7.1 Truth Tables.............................................................. 16
7.2 On-Resistance.......................................................... 17
7.3 Off-Leakage Current................................................. 17
7.4 On-Leakage Current................................................. 18
7.5 Break-Before-Make Delay.........................................18
7.6 Enable Delay Time....................................................19
7.7 Transition Time......................................................... 19
7.8 Charge Injection........................................................20
7.9 Crosstalk...................................................................21
7.10 Bandwidth............................................................... 22
8 Detailed Description......................................................23
8.1 Overview...................................................................23
8.2 Functional Block Diagram.........................................23
8.3 Feature Description...................................................23
8.4 Device Functional Modes..........................................25
9 Application and Implementation..................................26
9.1 Application Information............................................. 26
9.2 Typical Application.................................................... 26
10 Power Supply Recommendations..............................27
11 Layout...........................................................................28
11.1 Layout Guidelines................................................... 28
11.2 Layout Example...................................................... 28
12 Device and Documentation Support..........................29
12.1 Documentation Support.......................................... 29
12.2 Receiving Notification of Documentation Updates..29
12.3 Support Resources................................................. 29
12.4 Trademarks.............................................................29
12.5 Electrostatic Discharge Caution..............................29
12.6 Glossary..................................................................29
13 Mechanical, Packaging, and Orderable
Information.................................................................... 29
13.1 Tape and Reel Information......................................36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (February 2021) to Revision A (October 2021)
Page
•
•
Added package details....................................................................................................................................... 1
Added Thermal information for TSSOP package............................................................................................... 5
Copyright © 2021 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
Device Comparison Table
PRODUCT
DESCRIPTION
TMUX7308F
TMUX7309F
+60 V/ –60 V Tolerant, Fault-protected, Latch-up Immune, Single-Ended 8:1 Multiplexer
+60 V/ –60 V Tolerant, Fault-protected, Latch-up Immune, 4:1, 2-Channel Multiplexer
5 Pin Configuration and Functions
A0
EN
VSS
S1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A1
A2
GND
VDD
S5
VSS
S1
1
2
3
4
12
11
10
9
GND
VDD
S5
Thermal
Pad
S2
S2
S3
S6
S3
S6
S4
S7
D
S8
Not to scale
Not to scale
Figure 5-1. PW Package 16-Pin TSSOP Top View
Figure 5-2. RRP Package 16-Pin WQFN Top View
Table 5-1. Pin Functions: TMUX7308F
PIN
TYPE(1)
DESCRIPTION
NAME
A0
TSSOP
WQFN
15
1
16
15
8
I
I
Logic control input address 0 (A0).
A1
14
Logic control input address 1 (A1).
Logic control input address 2 (A2).
Drain pin. Can be an input or output.
A2
13
I
D
6
I/O
Active high digital enable (EN) pin. The device is disabled and all switches become high
impedance when the pin is low. When the pin is high, the Ax logic inputs determine individual
switch states.
EN
2
16
I
GND
S1
S2
S3
S4
S5
S6
S7
S8
14
4
12
2
P
Ground (0 V) reference
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Source pin 1. Can be an input or output.
Source pin 2. Can be an input or output.
Source pin 3. Can be an input or output.
Source pin 4. Can be an input or output.
Source pin 5. Can be an input or output.
Source pin 6. Can be an input or output.
Source pin 7. Can be an input or output.
Source pin 8. Can be an input or output.
5
3
6
4
7
5
12
11
10
9
10
9
8
7
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and
GND.
VDD
13
11
P
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
VSS
3
1
P
P
Thermal
Pad
The thermal pad is not connected internally. No requirement to solder this pad. For best
performance, it is recommended that the pad be tied to GND or VSS.
—
—
(1) I = input, O = output, I/O = input and output, P = power
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
A0
EN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A1
GND
VDD
S1B
S2B
S3B
S4B
DB
VSS
S1A
S2A
S3A
S4A
DA
VSS
S1A
S2A
S3A
1
2
3
4
12
11
10
9
VDD
S1B
S2B
S3B
Thermal
Pad
Not to scale
Not to scale
Figure 5-4. RRP Package 16-Pin WQFN Top View
Figure 5-3. PW Package 16-Pin TSSOP Top View
Table 5-2. Pin Functions: TMUX7309F
PIN
TYPE(1)
DESCRIPTION
NAME
A0
TSSOP
WQFN
1
16
8
15
14
6
I
Logic control input address 0 (A0).
A1
I
Logic control input address 1 (A1).
DA
I/O
I/O
Drain terminal A. Can be an input or output.
Drain terminal B. Can be an input or output.
DB
9
7
Active high digital enable (EN) pin. The device is disabled and all switches become high
impedance when the pin is low. When the pin is high, the Ax logic inputs determine individual
switch states.
EN
2
16
I
GND
S1A
S1B
S2A
S2B
S3A
S3B
S4A
S4B
15
4
13
2
P
Ground (0 V) reference
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Source pin 1A. Can be an input or output.
Source pin 1B. Can be an input or output.
Source pin 2A. Can be an input or output.
Source pin 2B. Can be an input or output.
Source pin 3A. Can be an input or output.
Source pin 3B. Can be an input or output.
Source pin 4A. Can be an input or output.
Source pin 4B. Can be an input or output.
13
5
11
3
12
6
10
4
11
7
9
5
10
8
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and
GND.
VDD
14
12
P
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
VSS
3
1
P
P
Thermal
Pad
The thermal pad is not connected internally. No requirement to solder this pad. For best
performance, it is recommended that the pad be tied to GND or VSS.
—
—
(1) I = input, O = output, I/O = input and output, P = power
Copyright © 2021 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
48
UNIT
V
VDD to VSS
VDD to GND
VSS to GND
VS to GND
VS to VDD
VS to VSS
VD
Supply voltage
–0.3
–48
–60
–85
48
V
0.3
60
V
Source input pin (Sx) voltage to GND
Source input pin (Sx) voltage to VDD
Source input pin (Sx) voltage to VSS
Drain pin (D or Dx) voltage
V
V
85
V
VSS–0.7
GND –0.7
–30
VDD+0.7
V
VSEL or VEN
ISEL or IEN
IS or ID (CONT)
Tstg
Logic control input pin voltage (EN, A0, A1, A2)(2)
Logic control input pin current (EN, A0, A1, A2)(2)
Source or drain continuous current (Sx or D)
Storage temperature
48
V
30
IDC ± 10 %(3)
150
mA
mA
°C
°C
°C
IDC ± 10 %(3)
–65
TA
Ambient temperature
–55
150
TJ
Junction temperature
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Stresses have to be kept at or below both voltage and current ratings at all time.
(3) Refer to Recommended Operating Conditions for IDC ratings.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
±2000
V
Electrostatic
discharge
V(ESD)
Charged device model (CDM), per JEDEC
All pins
±500
V
specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Thermal Information
TMUX7308F/ TMUX7309F
THERMAL METRIC(1)
PW (TSSOP)
16 PINS
100.2
31.2
RRP (QFN)
16 PINS
43.0
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
28.8
46.3
17.9
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.7
0.4
ΨJB
45.7
17.9
RθJC(bot)
N/A
4.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
(1)
VDD – VSS
VDD
Power supply voltage differential
8
5
22
44
V
V
V
V
V
V
Positive power supply voltage
VS
Source pin (Sx) voltage (non-fault condition)
Source pin (Sx) voltage (fault condition)
Drain pin (D, Dx) voltage
VSS
–60
VSS
0
VDD
60
(2)
VS_FAULT
VD
VDD
44
VSEL of VEN
TA
Logic control input pin voltage (EN, A0, A1, A2)
Ambient temperature
–40
125 °C
13 mA
Continuous current through switch, WQFN package, 25°C
Continuous current through switch, WQFN package, 125°C
IDC
TMUX7308F
8
mA
(1) VDD and VSS can be any value as long as 8 V ≤ (VDD – VSS) ≤ 44 V, and the minimum VDD is met.
(2) Source pin voltage (Sx) under a fault condition may not exceed 85 V from supply pins (VDD and VSS.) or drain pins (D, Dx).
6.5 Electrical Characteristics (Global)
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
Threshold voltage for fault
detector
VT
25°C
0.7
V
DIGITAL INPUT/ OUTPUT
VIH
High-level input voltage
EN, Ax pins
EN, Ax pins
–40°C to +125°C
–40°C to +125°C
1.3
0
44
V
V
VIL
Low-level input voltage
0.8
POWER SUPPLY
Undervoltage lockout (UVLO)
Rising edge, single supply configuration
only
VUVLO
VUVLO
–40°C to +125°C
–40°C to +125°C
5
5
6
6.5
6.5
V
V
threshold voltage (VDD – VSS
)
Undervoltage lockout (UVLO)
Falling edge, single supply configuration
only
5.8
threshold voltage (VDD – VSS
)
Copyright © 2021 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
6.6 ±15 V Dual Supply: Electrical Characteristics
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VS = –10 V to +10 V, IS = –1 mA
VS = –10 V to +10 V, IS = –1 mA
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
250
300
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
330
390
6
Ω
Ω
2.5
1.5
0.1
0.1
0.3
On-resistance mismatch between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
12
13
3.5
4
RFLAT
On-resistance flatness
VS = –10 V to +10 V, IS = –1 mA
–40°C to +85°C
–40°C to +125°C
25°C
Ω
4
–1
–2
1
Switch state is off, VS = +10 V/ –10 V, VD
–10 V/ + 10 V, VDD = 16.5 V, VSS = –16.5 V
=
IS(OFF)
ID(OFF)
IS(ON), I,D(ON)
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage current
–40°C to +85°C
–40°C to +125°C
25°C
2
nA
nA
nA
–8
8
–2
2
Switch state is off, VS = +10 V/ –10 V, VD
–10 V/ + 10 V, VDD = 16.5 V, VSS = –16.5 V
=
–40°C to +85°C
–40°C to +125°C
25°C
–5
5
–15
–2
15
2
Switch state is on, VS = floating, VD = –
10 V/ +10 V, or VS = –10 V/ +10 V, VD
floating, VDD = 16.5 V, VSS = –16.5 V
=
–40°C to +85°C
–40°C to +125°C
–20
–25
20
25
FAULT CONDITION
25°C
±90
±95
VS = ± 60 V, GND = 0V, VDD = 16.5 V, VSS
= –16.5 V
–40°C to +85°C
–40°C to +125°C
25°C
µA
µA
µA
±100
±120
±125
±130
±120
±125
±130
Input leakage current
under overvoltage
VS = ± 60 V, GND = 0V, VDD = VSS = 0 V,
VEN = VAx = 0 V or floating
IS(FA)
–40°C to +85°C
–40°C to +125°C
25°C
VS = ± 60 V, GND = 0V, VDD = VSS
floating, VEN = VAx = 0 V or floating
=
–40°C to +85°C
–40°C to +125°C
LOGIC INPUT/ OUTPUT
IIH High-level input current
25°C
–2
–2
–2
–2
± 0.6
± 0.6
160
2
2
2
2
VEN = VAx = VDD
VEN = VAx = 0 V
µA
µA
–40°C to +125°C
25°C
IIL
Low-level input current
–40°C to +125°C
25°C
tTRAN
VS = 10 V, RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
380
400
ns
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TMUX7308F
TMUX7308F
www.ti.com
MAX UNIT
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
6.6 ±15 V Dual Supply: Electrical Characteristics (continued)
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VS = 10 V, RL = 4 kΩ, CL= 12 pF
VS = 10 V, RL = 4 kΩ, CL= 12 pF
RL = 4 kΩ, CL= 12 pF
TA
MIN
TYP
SWITCHING CHARACTERISTICS
25°C
150
tON (EN)
Enable turn-on time
Enable turn-off time
Fault response time
Fault recovery time
–40°C to +85°C
–40°C to +125°C
25°C
300
400
ns
ns
ns
µs
120
90
tOFF (EN)
–40°C to +85°C
–40°C to +125°C
25°C
300
400
tRESPONSE
–40°C to +85°C
–40°C to +125°C
25°C
200
300
0.7
tRECOVERY
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
2
2.5
tBBM
QINJ
Break-before-make time delay
Charge injection
VS = 10 V, RL = 4 kΩ, CL= 12 pF
VS = 0 V, CL = 1 nF, RS = 0 Ω
50
120
–13
ns
pC
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200m VRMS, VBIAS = 0 V, f = 1 MHz
=
=
=
=
=
=
OFFISO
Off-isolation
25°C
25°C
25°C
25°C
25°C
–65
–60
–75
100
150
dB
dB
Intra-channel
crosstalk (TMUX7308F)
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200m VRMS, VBIAS = 0 V, f = 1 MHz
XTALK
Inter-channel crosstalk
(TMUX7309F)
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200m VRMS, VBIAS = 0 V, f = 1 MHz
dB
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200m VRMS, VBIAS = 0 V
–3 dB bandwidth (TMUX7308F)
–3 dB bandwidth (TMUX7309F)
MHz
MHz
BW
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200m VRMS, VBIAS = 0 V
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200m VRMS, VBIAS = 0 V, f = 1 MHz
IL
Insertion loss
25°C
25°C
25°C
–10
5
dB
pF
pF
CS(OFF)
Input off-capacitance
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
Output off-capacitance
(TMUX7308F)
40
CD(OFF)
Output off-capacitance
(TMUX7309F)
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
25°C
25°C
25°C
20
40
20
pF
pF
pF
Input/Output on-capacitance
(TMUX7308F)
CS(ON), CD(ON)
Input/Output on-capacitance
(TMUX7309F)
Copyright © 2021 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
6.6 ±15 V Dual Supply: Electrical Characteristics (continued)
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
POWER SUPPLY
25°C
0.25
1
VDD = 16.5 V, VSS = –16.5 V, VAx = 0 V, 5
V, or VDD, VEN = 5 V or VDD, VS = 0 V
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
1
1
mA
0.15
0.5
0.6
0.7
VDD = 16.5 V, VSS = –16.5 V, VAx = 0 V, 5
V, or VDD, VEN = 5 V or VDD, VS = 0 V
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
mA
mA
mA
VDD = 16.5 V, VSS = –16.5 V, VAx = 0 V, 5
V, or VDD, VEN = 5 V or VDD, VS = 0 V
IGND
GND current
25°C
0.1
25°C
0.25
1
1
VS = ± 60 V, VDD = 16.5 V, VSS = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IDD(FA)
VDD supply current under fault
–40°C to +85°C
–40°C to +125°C
25°C
1
0.15
0.5
0.6
0.7
VS = ± 60 V, VDD = 16.5 V, VSS = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
ISS(FA)
VSS supply current under fault
GND current under fault
–40°C to +85°C
–40°C to +125°C
mA
mA
mA
VS = ± 60 V, VDD = 16.5 V, VSS = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IGND(FA)
25°C
0.2
25°C
0.13
1
1
VDD = 16.5 V, VSS = –16.5 V, VAx = 0 V, 5
V, or VDD, VEN = 0 V, VS = 0 V
IDD(DISABLE)
VDD supply current (disable mode)
–40°C to +85°C
–40°C to +125°C
25°C
1
0.1
0.4
0.5
0.6
VDD = 16.5 V, VSS = –16.5 V, VAx = 0 V, 5
V, or VDD, VEN = 0 V, VS = 0 V
ISS(DISABLE)
VSS supply current (disable mode)
–40°C to +85°C
–40°C to +125°C
mA
(1) When VS is positive,VD is negative, and vice versa.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
6.7 ±20 V Dual Supply: Electrical Characteristics
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VS = –15 V to +15 V, IS = –1 mA
VS = –15 V to +15 V, IS = –1 mA
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
180
270
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
340
400
6
Ω
Ω
2.5
1.5
On-resistance mismatch between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
12
13
3.5
4
RFLAT
On-resistance flatness
On-resistance drift
VS = –15 V to +15 V, IS = –1 mA
VS = 0 V, IS = –1 mA
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
Ω
4
RON_DRIFT
0.05
0.1
%/°C
nA
–1
–2
1
2
Switch state is off, VS = +15 V/ –15 V, VD
–15 V/ + 15 V, VDD = 22 V, VSS = –22 V
=
=
IS(OFF)
Source off leakage current(1)
–40°C to +85°C
–40°C to +125°C
25°C
–8
8
–2
0.1
0.3
2
Switch state is off, VS = +15 V/ –15 V, VD
–15 V/ + 15 V, VDD = 22 V, VSS = –22 V
ID(OFF)
Drain off leakage current(1)
Channel on leakage current
–40°C to +85°C
–40°C to +125°C
25°C
–5
5
nA
nA
–15
–2
15
2
Switch state is on, VS = floating, VD = –
IS(ON), I,D(ON)
15 V/ +15 V, or VS = –15 V/ +15 V, VD
floating, VDD = 22 V, VSS = –22 V
=
–40°C to +85°C
–40°C to +125°C
–20
–25
20
25
FAULT CONDITION
25°C
±90
±95
VS = ± 60 V, GND = 0V, VDD = 22 V, VSS
–22 V
=
–40°C to +85°C
–40°C to +125°C
25°C
µA
µA
µA
±100
±120
±125
±130
±120
±125
±130
Input leakage current
under overvoltage
VS = ± 60 V, GND = 0V, VDD = VSS = 0 V,
VEN = VAx = 0 V or floating
IS(FA)
–40°C to +85°C
–40°C to +125°C
25°C
VS = ± 60 V, GND = 0V, VDD = VSS
floating, VEN = VAx = 0 V or floating
=
–40°C to +85°C
–40°C to +125°C
LOGIC INPUT/ OUTPUT
IIH High-level input current
25°C
–2
–2
–2
–2
± 0.6
± 0.6
160
2
2
2
2
VEN = VAx = VDD
VEN = VAx = 0 V
µA
µA
–40°C to +125°C
25°C
IIL
Low-level input current
Transition time
–40°C to +125°C
25°C
tTRAN
VS = 10 V, RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
380
400
ns
Copyright © 2021 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
6.7 ±20 V Dual Supply: Electrical Characteristics (continued)
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VS = 10 V, RL = 4 kΩ, CL= 12 pF
VS = 10 V, RL = 4 kΩ, CL= 12 pF
RL = 4 kΩ, CL= 12 pF
TA
MIN
TYP
MAX UNIT
SWITCHING CHARACTERISTICS
25°C
150
tON (EN)
Enable turn-on time
Enable turn-off time
Fault response time
Fault recovery time
–40°C to +85°C
–40°C to +125°C
25°C
300
400
ns
ns
ns
µs
120
90
tOFF (EN)
–40°C to +85°C
–40°C to +125°C
25°C
300
400
tRESPONSE
–40°C to +85°C
–40°C to +125°C
25°C
200
300
0.7
tRECOVERY
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
2
2.5
tBBM
QINJ
Break-before-make time delay
Charge injection
VS = 10 V, RL = 4 kΩ, CL= 12 pF
VS = 0 V, CL = 1 nF, RS = 0 Ω
50
120
–13
ns
pC
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200m VRMS, VBIAS = 0 V, f = 1 MHz
=
=
=
=
=
=
OFFISO
Off-isolation
25°C
25°C
25°C
25°C
25°C
–65
–60
–75
100
150
dB
dB
Intra-channel
crosstalk (TMUX7308F)
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200m VRMS, VBIAS = 0 V, f = 1 MHz
XTALK
Inter-channel crosstalk
(TMUX7309F)
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200m VRMS, VBIAS = 0 V, f = 1 MHz
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200m VRMS, VBIAS = 0 V
–3 dB bandwidth (TMUX7308F)
–3 dB bandwidth (TMUX7309F)
BW
MHz
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200m VRMS, VBIAS = 0 V
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200m VRMS, VBIAS = 0 V, f = 1 MHz
IL
Insertion loss
25°C
25°C
25°C
–10
5
dB
pF
CS(OFF)
Input off-capacitance
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
Output off-capacitance
(TMUX7308F)
40
CD(OFF)
pF
pF
Output off-capacitance
(TMUX7309F)
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
25°C
25°C
25°C
20
40
20
Input/Output on-capacitance
(TMUX7308F)
CS(ON), CD(ON)
Input/Output on-capacitance
(TMUX7309F)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
6.7 ±20 V Dual Supply: Electrical Characteristics (continued)
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
POWER SUPPLY
25°C
0.25
1
VDD = 22 V, VSS = –22 V, VEN/ VAx = 0V,
5V, or VDD, VS = 0 V
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
1
1
mA
0.15
0.5
0.6
0.7
VDD = 22 V, VSS = –22 V, VEN/ VAx = 0V,
5V, or VDD, VS = 0 V
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
mA
mA
mA
VDD = 22 V, VSS = –22 V, VEN/ VAx = 0V,
5V, or VDD, VS = 0 V
IGND
GND current
25°C
0.1
25°C
0.25
1
1
VS = ± 60 V, VDD = 22 V, VSS = –22 V, VEN
VAx = 0V, 5V, or VDD
/
/
IDD(FA)
VDD supply current under fault
–40°C to +85°C
–40°C to +125°C
25°C
1
0.15
0.5
0.6
0.7
VS = ± 60 V, VDD = 22 V, VSS = –22 V, VEN
VAx = 0V, 5V, or VDD
ISS(FA)
VSS supply current under fault
GND current under fault
–40°C to +85°C
–40°C to +125°C
mA
mA
VS = ± 60 V, VDD = 22 V, VSS = –22 V,
VEN/ VAx = 0V, 5V, or VDD
IGND(FA)
25°C
0.2
25°C
0.13
1
1
mA
mA
mA
mA
mA
mA
VDD = 22 V, VSS = –22 V, VAx = 0 V, 5 V, or
VDD, VEN = 0 V, VS = 0 V
IDD(DISABLE)
VDD supply current (disable mode)
–40°C to +85°C
–40°C to +125°C
25°C
1
0.1
0.4
0.5
0.6
VDD = 22 V, VSS = –22 V, VAx = 0 V, 5 V, or
VDD, VEN = 0 V, VS = 0 V
ISS(DISABLE)
VSS supply current (disable mode)
–40°C to +85°C
–40°C to +125°C
(1) When VS is positive,VD is negative, and vice versa.
Copyright © 2021 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
6.8 12 V Single Supply: Electrical Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG SWITCH
RON
RON
RON
On-resistance
On-resistance
On-resistance
VS = 0 V to 7.8 V, IS = –1 mA
VS = 0 V to 7.8 V, IS = –1 mA
VS = 0 V to 7.8 V, IS = –1 mA
25°C
190
320
330
400
6
Ω
Ω
Ω
–40°C to +85°C
–40°C to +125°C
25°C
2.5
20
On-resistance mismatch between
channels
ΔRON
VS = 0 V to 7.8 V, IS = –1 mA
VS = 0 V to 7.8 V, IS = –1 mA
–40°C to +85°C
–40°C to +125°C
25°C
12
13
25
27
27
1
Ω
Ω
RFLAT
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
–1
–2
0.1
0.1
0.3
Switch state is off, VS = 1 V/ 10 V, VD = 10
V/ 1 V, VDD = 13.2 V
IS(OFF)
Source off leakage current(1)
Drain off leakage current(1)
Output on leakage current(1)
–40°C to +85°C
–40°C to +125°C
25°C
2
nA
nA
nA
–8
8
–2
2
Switch state is off, VS = 1 V/ 10 V, VD = 10
V/ 1 V, VDD = 13.2 V
ID(OFF)
–40°C to +85°C
–40°C to +125°C
25°C
–5
5
–15
–2
15
2
Switch state is on, VS = floating, VD = 1 V/
10 V, VDD = 13.2
IS(ON), I,D(ON)
–40°C to +85°C
–40°C to +125°C
–20
–25
20
25
FAULT CONDITION
25°C
±90
±95
VS = ± 60 V, GND = 0V, VDD = 13.2 V, VSS
= 0 V
–40°C to +85°C
–40°C to +125°C
25°C
µA
µA
µA
±100
±120
±125
±130
±120
±125
±130
Input leakage current
under overvoltage
VS = ± 60 V, GND = 0V, VDD = VSS = 0 V,
VEN = VAx = 0 V or floating
IS(FA)
–40°C to +85°C
–40°C to +125°C
25°C
VS = ± 60 V, GND = 0V, VDD = VSS
floating, VEN = VAx = 0 V or floating
=
–40°C to +85°C
–40°C to +125°C
LOGIC INPUT/ OUTPUT
IIH High-level input current
25°C
–2
–2
–2
–2
± 0.6
± 0.6
160
2
2
2
2
µA
µA
VEN = VAx = VDD
VEN = VAx = 0 V
–40°C to +125°C
25°C
IIL
Low-level input current
Transition time
µA
–40°C to +125°C
25°C
tTRAN
VS = 8 V, RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
380
400
ns
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TMUX7308F
TMUX7308F
www.ti.com
MAX UNIT
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
6.8 12 V Single Supply: Electrical Characteristics (continued)
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
SWITCHING CHARACTERISTICS
25°C
150
tON (EN)
Enable turn-on time
Enable turn-off time
Fault response time
Fault recovery time
VS = 8 V, RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
25°C
300
400
ns
ns
ns
µs
120
90
tOFF (EN)
VS = 8 V, RL = 4 kΩ, CL= 12 pF
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
25°C
300
400
tRESPONSE
–40°C to +85°C
–40°C to +125°C
25°C
200
300
0.7
tRECOVERY
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
25°C
2
2.5
QJ
Charge injection
Off-isolation
VS = 6 V, CL = 1 nF, RS = 0 Ω
–13
–65
pC
dB
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200m VRMS, VBIAS = 6 V, f = 1 MHz
=
=
=
=
=
=
OFFISO
25°C
25°C
25°C
25°C
25°C
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200m VRMS, VBIAS = 6 V, f = 1 MHz
XTALK
XTALK
Intra-channel crosstalk
–60
–75
100
150
dB
dB
Inter-channel crosstalk
(TMUX7309F)
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200m VRMS, VBIAS = 6 V, f = 1 MHz
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200m VRMS, VBIAS = 6 V
–3 dB bandwidth (TMUX7308F)
–3 dB bandwidth (TMUX7309F)
BW
MHz
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200m VRMS, VBIAS = 6 V
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200m VRMS, VBIAS = 6 V, f = 1 MHz
IL
Insertion loss
25°C
25°C
25°C
–10
5
dB
pF
CS(OFF)
Input off-capacitance
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
Output off-capacitance
(TMUX7308F)
40
CD(OFF)
pF
pF
Output off-capacitance
(TMUX7309F)
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
25°C
25°C
25°C
20
40
20
Input/Output on-capacitance
(TMUX7308F)
CS(ON), CD(ON)
Input/Output on-capacitance
(TMUX7309F)
Copyright © 2021 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
6.8 12 V Single Supply: Electrical Characteristics (continued)
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLY
25°C
0.25
1
VDD = 13.2 V, VSS = 0 V, VEN/ VAx = 0V, 5V,
or VDD, VS = 6 V
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
1
1
mA
0.15
0.5
0.6
0.7
VDD = 13.2 V, VSS = 0 V, VEN/ VAx = 0V, 5V,
or VDD, VS = 6 V
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
mA
mA
mA
VDD = 13.2 V, VSS = 0 V, VEN/ VAx = 0V, 5V,
or VDD, VS = 6 V
IGND
GND current
25°C
0.1
25°C
0.25
1
1
VS = ± 60 V, VDD = 13.2 V, VSS = 0 V, VEN
/
IDD(FA)
VDD supply current under fault
–40°C to +85°C
–40°C to +125°C
25°C
VAx = 0V, 5V, or VDD
1
0.15
0.5
0.6
0.7
VS = ± 60 V, VDD = 13.2 V, VSS = 0 V, VEN
VAx = 0V, 5V, or VDD
/
/
ISS(FA)
VSS supply current under fault
GND current under fault
–40°C to +85°C
–40°C to +125°C
mA
mA
mA
VS = ± 60 V, VDD = 13.2 V, VSS = 0 V, VEN
VAx = 0V, 5V, or VDD
IGND(FA)
25°C
0.2
25°C
0.13
1
1
VDD = 13.2 V, VSS = 0 V, VAx = 0 V, 5 V, or
VDD, VEN = 0 V, VS = 0 V
IDD(DISABLE)
VDD supply current (disable mode)
–40°C to +85°C
–40°C to +125°C
25°C
1
0.1
0.4
0.5
0.6
VDD = 13.2 V, VSS = 0 V, VAx = 0 V, 5 V, or
VDD, VEN = 0 V, VS = 0 V
ISS(DISABLE)
VSS supply current (disable mode)
–40°C to +85°C
–40°C to +125°C
mA
(1) When VS is 10 V,VD is 1 V, and vice versa.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
7 Parameter Measurement Information
7.1 Truth Tables
Table 7-1 shows the truth tables for the TMUX7308F.
Table 7-1. TMUX7308F Truth Table
Selected Source Connected to Drain Pin
(D)
EN
A2
A1
A0
0
X(1)
X(1)
X(1)
All sources are off (HI-Z)
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
S1
S2
S3
S4
S5
S6
S7
S8
(1) "X" means "do not care."
Table 7-2 shows the truth tables for the TMUX7309F.
Table 7-2. TMUX7309F Truth Table
EN
A1
A0
Selected Source Connected to Drain Pins (DA, DB)
0
X(1)
X(1)
All sources are off (HI-Z)
1
1
1
1
0
0
1
1
0
1
0
1
S1A and S1B
S2A and S2B
S3A and S3B
S4A and S4B
(1) "X" means "do not care."
Copyright © 2021 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
7.2 On-Resistance
The on-resistance of the TMUX7308F and TMUX7309F is the ohmic resistance across the source (Sx) and drain
(Dx) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol RON is used
to denote on-resistance. Figure 7-1 shows the measurement setup used to measure RON. ΔRON represents the
difference between the RON of any two channels, while RON_FLAT denotes the flatness that is defined as the
difference between the maximum and minimum value of the on-resistance measured over the specified analog
signal range.
V
VDD
VSS
8
410
=
+
5
VDD
VSS
IS
SW
Sx
Dx
VS
GND
Figure 7-1. On-Resistance Measurement Setup
7.3 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state, which follows:
1. Source off-leakage current IS(OFF): the leakage current flowing into or out of the source pin when the switch
is off.
2. Drain off-leakage current ID(OFF): the leakage current flowing into or out of the drain pin when the switch is
off.
Figure 7-2 shows the setup used to measure both off-leakage currents.
VDD
VSS
VDD
VSS
Is (OFF)
A
SW
SW
SW
SW
S1
S2
S1
S2
ID (OFF)
VS
D
D
A
GND
VD
SW
SW
S8
S8
VD
GND
VS
GND
GND
GND
GND
IS(OFF)
ID(OFF)
Figure 7-2. Off-Leakage Measurement Setup
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
7.4 On-Leakage Current
Source on-leakage current (IS(ON)) and drain on-leakage current (ID(ON)) denote the channel leakage currents
when the switch is in the on state. IS(ON) is measured with the drain floating, while ID(ON) is measured with the
source floating. Figure 7-3 shows the circuit used for measuring the on-leakage currents.
VDD
VSS
VDD
VSS
IS(ON)
A
SW
SW
SW
SW
S1
S2
S1
S2
N.C.
ID(ON)
A
D
D
VS
GND
N.C.
SW
SW
VD
S8
S8
GND
VS
VS
GND
GND
GND
GND
IS(ON)
ID(ON)
Figure 7-3. On-Leakage Measurement Setup
7.5 Break-Before-Make Delay
The break-before-make delay is a safety feature of the TMUX7308F and TMUX7309F. The ON switches first
break the connection before the OFF switches make connection. The time delay between the break and the
make is known as break-before-make delay. Figure 7-4 shows the setup used to measure break-before-make
delay, denoted by the symbol tBBM
.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
SW
SW
S1
S2
3 V
D
tr < 20 ns
VA
tf < 20 ns
0 V
CL
RL
GND
GND
SW
SW
S7
S8
GND
VS
0.8 VS
Output
A0
A1
tBBM
1
tBBM 2
VS
EN
0 V
Decoder
tBBM = min ( tBBM 1, tBBM 2)
A2
GND
VEN
VA
GND
GND
GND
Figure 7-4. Break-Before-Make Delay Measurement Setup
Copyright © 2021 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
7.6 Enable Delay Time
tON(EN) time is defined as the time taken by the output of the TMUX7308F and TMUX7309F to rise to a 90% final
value after the EN signal has risen to a 50% final value. tOFF(EN) is defined as the time taken by the output of the
TMUX7308F and TMUX7309F to fall to a 10% initial value after the EN signal has fallen to a 50% initial value.
Figure 7-5 shows the setup used to measure the enable delay time.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
SW
SW
S1
S2
3 V
VS
D
tr < 20 ns
tf < 20 ns
50%
50%
VEN
GND
0 V
VS
RL
GND
CL
SW
S8
0.9 VS
tON(EN)
GND
tOFF(EN)
0.1 VS
GND
Output
A0
A1
EN
Decoder
A2
VEN
GND
GND
GND
Figure 7-5. Enable Delay Measurement Setup
7.7 Transition Time
Transition time is defined as the time taken by the output of the device to rise (to 90% of the transition) or fall (to
10% of the transition) after the address signal (Ax) has fallen or risen to 50% of the transition. Figure 7-6 shows
the setup used to measure transition time, denoted by the symbol tTRAN
.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
SW
SW
S1
S2
3 V
0 V
tr < 20 ns
tf < 20 ns
50%
50%
VA
VS
D
GND
RL
GND
0.9 VS
tTRAN
CL
SW
S8
Output
VS
tTRAN
1
2
GND
0.1 VS
GND
tTRAN = max ( tTRAN 1, tTRAN 2)
A0
A1
EN
Decoder
A2
VEN
VA
GND
GND
GND
Figure 7-6. Transition Time Measurement Setup
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
7.8 Charge Injection
Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during
switching and is denoted by the symbol QINJ. Figure 7-7 shows the setup used to measure charge injection from
the source to drain.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
SW
SW
S1
S2
Output
VS
D
3 V
VEN
0 V
GND
CL
SW
S8
tr < 20 ns
tf < 20 ns
GND
GND
A0
A1
Output
VS
EN
VOUT
QINJ = CL ×
VOUT
Decoder
A2
VEN
GND
GND
GND
Figure 7-7. Charge-Injection Measurement Setup
Copyright © 2021 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
7.9 Crosstalk
The following are two types of crosstalk that can be defined for the devices:
1. Intra-channel crosstalk (XTALK(INTRA)): the voltage at the source pin (Sx) of an off-switch input, when a
1-VRMS signal is applied at the source pin of an on-switch input in the same channel, as shown in Figure 7-8.
2. Inter-channel crosstalk (XTALK(INTER)): the voltage at the source pin (Sx) of an on-switch input, when a
1-VRMS signal is applied at the source pin of an on-switch input in a different channel, as shown in Figure
7-9. Inter-channel crosstalk applies only to the TMUX7309F device.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
Network Analyzer
SW
SW
S1/S1X
D/ DX
VOUT
S2/S2X
RS
RL
Other
Sx/ Dx
Pins
50Ω
SW
VS
N.C.
Ax, EN
GND
VAX
VEN
8176
+JPN= F ?D=JJAH %NKOOP=HG = 20 × .KC
8
5
Figure 7-8. Intra-channel Crosstalk Measurement Setup
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
Network Analyzer
SW
SxA
DA
Other
SxA Pins
SW
SW
N.C.
N.C.
RS
RL
VOUT
SxB
DB
Other
SxB Pins
SW
50Ω
RL
VS
Ax, EN
GND
VAX
VEN
8176
+JPAN F ?D=JJAH %NKOOP=HG = 20 × .KC
8
5
Figure 7-9. Inter-channel Crosstalk Measurement Setup
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
7.10 Bandwidth
Bandwidth (BW) is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to
the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D or Dx) of the TMUX730xF.
Figure 7-10 shows the setup used to measure bandwidth of the switch.
VDD
VSS
0.1 µF
GND
0.1 µF
VDD
VSS
Network Analyzer
GND
SW
SW
SX
N.C.
N.C.
Other
Sx/ Dx
Pins
RS
SW
VOUT
D/ DX
VS
50Ω
Ax, EN
VAX
VEN
GND
8176
$=J@SE@PD = 20 × .KC
8
5
Figure 7-10. Bandwidth Measurement Setup
Copyright © 2021 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
8 Detailed Description
8.1 Overview
The TMUX7308F and TMUX7309F are a modern complementary metal-oxide semiconductor (CMOS) analog
multiplexers in 8:1 (single ended) and 4:1 (differential) configurations. The devices work well with dual supplies
(±5 V to ±22 V), a single supply (8 V to 44 V), or asymmetric supplies (such as VDD = 15 V, VSS = –5 V). The
devices have an overvoltage protection feature on the source pins under powered and powered-off conditions,
allowing them to be used in harsh industrial environments.
8.2 Functional Block Diagram
VDD
VSS
VDD
VSS
SW
SW
SW
S1
S2
S1A
DA
DB
SW
SW
S4A
S1B
D
SW
SW
S4B
S8
A1
A2
A3
EN
A1
A2
EN
Fault Detection/
Switch Driver/
Logic Decoder
Fault Detection/
Switch Driver/
Logic Decoder
TMUX7308F
TMUX7309F
8.3 Feature Description
8.3.1 Flat On – Resistance
The TMUX7308F and TMUX7309F are designed with a special switch architecture to produce ultra-flat on-
resistance (RON) across most of the switch input operation region. The flat RON response allows the device to
be used in precision sensor applications since the RON is controlled regardless of the signals sampled. The
architecture is implemented without a charge pump so no unwanted noise is produced from the device to affect
sampling accuracy.
8.3.2 Protection Features
The TMUX7308F and TMUX7309F offer a number of protection features to enable robust system
implementations.
8.3.2.1 Input Voltage Tolerance
The maximum voltage that can be applied to any source input pin is +60 V or -60 V, allowing the device to
handle typical voltage fault conditions in industrial applications. It shall be cautioned that the device is rated to
handle maximum stress of 85 V across different pins, such as the following:
1. Between the source pins and supply rails:
For example, if the device is powered by VDD supply of 20 V, then the maximum negative signal level on any
source pin is –60 V to maintain the 60 V maximum rating on any source pin. If the device is powered by VDD
supply of 40 V, then the maximum negative signal level on any source pin is reduced to –45 V to maintain
the 85 V maximum rating across the source pin and the supply.
2. Between the source pins and one or more drain pins:
For example, if channel S1 is ON and the voltage on S1(A) pin is 40 V. In this case, the drain voltage is
also 40 V. The maximum negative voltage on any of the other source pins is –45 V to maintain the 85 V
maximum rating across the source pin and the drain pin.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
8.3.2.2 Powered-Off Protection
When the supplies of TMUX7308F and TMUX7309F are removed (VDD/ VSS = 0 V or floating), the source
(Sx) pins of the device remain in the high impedance (Hi-Z) state, and the device performance remains within
the leakage performance mentioned in the Electrical Specifications. Powered-off protection minimizes system
complexity by removing the need to control power supply sequencing of the system. The feature prevents errant
voltages on the input source pins from reaching the rest of the system and maintains isolation when the system
is powering up. Without powered-off protection, signal on the input source pins can back-power the supply rails
through internal ESD diodes and cause potential damage to the system.
The switch remains OFF regardless of whether the VDD and VSS supplies are 0 V or floating. A GND reference
must always be present to ensure proper operation. Source and drain voltage levels of up to ±60 V are blocked
in the powered-off condition.
8.3.2.3 Fail-Safe Logic
Fail-safe logic circuitry allows voltages on the digital control pins to be applied before the supply pins, protecting
the device from potential damage. The switch is specified to be in the OFF state, regardless of the state of the
digital logic signals. The digital inputs are protected against positive faults of up to +44 V in the powered-off
condition, but do not offer protection against the negative overvoltage condition.
8.3.2.4 Overvoltage Protection and Detection
The TMUX7308F and TMUX7309F detect overvoltage inputs by comparing the voltage on a source pin (Sx) with
the supplies (VDD and VSS). A signal is considered overvoltage if it exceeds the supply voltages by the threshold
voltage (VT).
When an overvoltage is detected, the switch automatically turns OFF regardless of the digital logic controls. The
source pin becomes high impedance and ensures only small leakage current flows through the switch. When
the fault channel is selected by the digital logic control, the drain pin (D or Dx) is pulled to the supply that was
exceeded. For example, if the source voltage exceeds VDD, the drain output is pulled to VDD. If the source
voltage exceeds VSS, the drain output is pulled to VSS. The pull-up impedance is approximately 40 kΩ, and as a
result, the drain current is limited to roughly 1 mA during a shorted load (to GND) condition. Figure depicts the
protection structure of the device.
8.3.2.5 Latch-Up Immunity
Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition
is caused by a trigger (current injection or overvoltage); but once activated, the low impedance path remains
even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic
damage due to the excessive current levels. The latch-up condition typically requires a power cycle to eliminate
the low impedance path.
In the TMUX7308F and TMUX7309F devices, an insulating oxide layer is placed on top of the silicon substrate
to prevent any parasitic junctions from forming. As a result, the devices are latch-up immune under all
circumstances by device construction.
8.3.2.6 EMC Protection
The TMUX7308F and TMUX7309F are not intended for standalone electromagnetic compatibility (EMC)
protection in industrial applications. There are three common high voltage transient specifications that govern
industrial high voltage transient specification: IEC61000-4-2 (ESD), IEC61000-4-4 (EFT), and IEC61000-4-5
(surge immunity). A transient voltage suppressor (TVS), along with some low-value series current limiting
resistor, are required to prevent source input voltages from going above the rated ±60 V limits.
When selecting a TVS protection device, it is critical to ensure that the maximum working voltage is greater than
both the normal operating range of the input source pins to be protected and any known system common-mode
overvoltage that may be present due to incorrect wiring, loss of power, or short circuit. Figure 8-1 shows one
example of the proper design window when selecting a TVS device.
Copyright © 2021 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
Region 1 denotes the normal operation region of TMUX7308F and TMUX7309F where the input source voltages
stay below the fault supplies VFP and VFN. Region 2 represents the range of possible persistent DC (or long
duration AC overvoltage fault) presented on the source input pins. Region 3 represents the margin between
any known DC overvoltage level and the absolute maximum rating of the TMUX7308F and TMUX7309F. The
selected TVS breakdown voltage must be less than the absolute maximum rating of the TMUX730xF but
greater than any known possible persistent DC or long duration AC overvoltage fault to avoid triggering the
TVS inadvertently. Region 4 represents the margin that system designers must impose when selecting the TVS
protection device to prevent accidental triggering of the ESD cells of the TMUX7308F and TMUX7309F devices.
Internal ESD
Trigger Voltage
4
Device Absolute
Max Rating
TVS
Breakdown
Voltage
3
2
System
Overvoltage
Overvoltage
Protection Window
Positive Supply
VDD
0 V
1
Normal Operation
Negative Supply
VSS
2
3
4
System
Overvoltage
Overvoltage
Protection Window
TVS
Breakdown
Voltage
Device Absolute
Max Rating
Internal ESD
Trigger Voltage
Figure 8-1. System Operation Regions and Proper Region of Selecting a TVS Protection Device
8.3.3 Bidirectional and Rail-to-Rail Operation
The TMUX7308F and TMUX7309F conducts equally well from source (Sx) to drain (D or Dx) or from drain (D or
Dx) to source (Sx). Each signal path has very similar characteristics in both directions. However, take note that
the overvoltage protection is implemented only on the source (Sx) side. The voltage on the drain is only allowed
to swing between VDD and VSS and no overvoltage protection is available on the drain side.
8.4 Device Functional Modes
The TMUX7308F and TMUX7309F offers two modes of operation (Normal mode and Fault mode) depending on
whether any of the input pins experience an overvoltage condition.
8.4.1 Normal Mode
In Normal mode operation, signals of up to VDD and VSS can be passed through the switch from source (Sx) to
drain (D or Dx) or from drain (D or Dx) to source (Sx). The address (Ax) pins and the enable (EN) pin determines
which switch path to turn on, according to Table 7-1 and Table 7-2. The following conditions must be satisfied for
the switch to stay in the ON condition:
•
The difference between the primary supplies (VDD – VSS) must be higher or equal to 8 V. With a minimum
VDD of 5 V.
•
•
The input signals on the source (Sx) or the drain (D or Dx) must be be between VFP+ VT and VFN – VT.
The digital logic control (Ax and EN) must have selected the switch.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
8.4.2 Fault Mode
The TMUX7308F and TMUX7309F enter into the Fault mode when any of the input signals on the source
(Sx) pins exceed VDD or VSS by a threshold voltage VT. Under the overvoltage condition, the switch input
experiencing the fault automatically turns OFF regardless of the digital logic status, and the source pin becomes
high impedance with a negligible amount of leakage current flowing through the switch. When the fault channel
is selected by the digital logic control, the drain pin (D or Dx) is pulled to the supply that was exceeded through a
40 kΩ internal resistor.
The overvoltage protection is provided only for the source (Sx) input pins. The drain (D or Dx) pin, if used as a
signal input, must stay in between VDD and VSS at all times since no overvoltage protection is implemented on
the drain pin.
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TMUX7308F and TMUX7309F are part of the fault protected switches and multiplexers family of devices.
The abilty to protect downstream components from overvoltage events up to ±60 V makes these switches and
multiplexers suitable for harsh environments.
9.2 Typical Application
In analog input programmable logic controllers (PLC) a multiplexer is often used to switch multiple sensors
to a single ADC. By using a multiplexer, the number of components in the system can be reduced to save
system cost and size. In a PLC module a ±10 V input signal range is common for interfacing with external field
transmitters and sensors; however, there are a number of fault cases that may occur that can be damaging
to many of the integrated circuits. Such fault conditions may include, but are not limited to, human error from
wiring connections incorrectly, component failure or wire shorts, electromagnetic interference (EMI) or transient
disturbances, and so forth.
Copyright © 2021 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
Supply
GND
Power Module
VDD
VSS
PLC Analog
Input Module
Bridge Sensor
TMUX7308F
S1
S2
S3
S4
S5
S6
S7
S8
5V
REF5025
Thermocouple
Current Sensing
D
Gain / Filter
Network
Fault
Protected
Mux Inputs
Signal
Processing
ISO77xx
ADS125H01
Photo
LED
A2
A1
V
Detector
A0
GND
1.8V Logic
Signals
Optical Sensor
Sensors
Figure 9-1. Typical Application
Table 9-1. Design Parameters
9.2.1 Design Requirements
PARAMETER
VALUE
+15 V
-15 V
Positive supply (VDD) mux and ADC
Negative supply (VSS) mux and ADC
Power board supply voltage
Input / output signal range non-faulted
Overvoltage protection levels
24 V
-15 V to 15 V
-60 V to 60 V
Control logic thresholds
Temperature range
1.8 V compatible, up to 44 V
-40°C to +125°C
9.2.2 Detailed Design Procedure
The image shows the case where an incorrect wiring condition occurred and one of the input connectors has
been short to the power board supply voltage. If the board supply voltage is higher than the power supply of
the multiplexer, then the TMUX7308F or TMUX7309F will disconnect the source input from passing the signal to
protect the downstream ADC. The drain pin of the mux will be pulled up to the supply voltage VDD through a 40
kΩ resistor to allow the ADC to determine a fault condition has occurred.
10 Power Supply Recommendations
The TMUX7308F and TMUX7309F operate across a wide supply range of ±5 V to ±22 V (8 V to 44 V in
single-supply mode). They also perform well with asymmetrical supplies such as VDD = 15 V and VSS= –5 V. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 1 µF to 10 µF at both the VDD
and VSS pins to ground. Always ensure the ground (GND) connection is established before supplies are ramped.
As a best practice, it is recommended to ramp VSS first before VDD in dual or asymmetrical supply applications.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
11 Layout
11.1 Layout Guidelines
The image below illustrates an example of a PCB layout with the TMUX7308F and TMUX7309F. Some key
considerations are:
•
Decouple the VDD and VSS pins with a 1-µF capacitor, placed as close to the pin as possible. Make sure that
the capacitor voltage rating is sufficient for the VDD and VSS supplies.
•
•
•
Keep the input lines as short as possible.
Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
Via to
ground plane
Via to
ground plane
A0
EN
VSS
A1
A2
Wide (low inductance)
trace for power
C
Wide (low inductance)
trace for power
C
GND
VDD
S5
Via to
ground plane
S1
S2
S3
S4
D
TMUX7308F
S6
S7
S8
Figure 11-1. TMUX7308F Layout Example
Copyright © 2021 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
•
•
•
Texas Instruments, ADS8664 12-Bit, 500-kSPS, 4- and 8-Channel, Single-Supply, SAR ADCs with Bipolar
Input Ranges data sheet
Texas Instruments, OPA140 High-Precision, Low-Noise, Rail-to-Rail Output, 11-MHz JFET Op Amp data
sheet
Texas Instruments, OPA192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias
Current Op Amp with e-Trim™ data sheet
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
32
Submit Document Feedback
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
PACKAGE OUTLINE
RRP0016A
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
PIN 1 INDEX AREA
4.1
3.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.95
SYMM
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
4
9
2X 1.95
SYMM
17
2.6 0.1
12X 0.65
1
12
0.35
0.25
PIN 1 ID
16X
13
16
0.1
C A B
0.45
0.35
0.05
16X
4224816/A 02/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
EXAMPLE BOARD LAYOUT
RRP0016A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.6)
SYMM
SEE SOLDER MASK
DETAIL
13
16
16X (0.6)
1
12
16X (0.3)
17
SYMM
12X (0.65)
(3.8)
(1.05)
4
9
(R0.05) TYP
(
0.2) TYP
VIA
5
8
(1.05)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DEFINED
SOLDER MASK DETAILS
4224816/A 02/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
34
Submit Document Feedback
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
EXAMPLE STENCIL DESIGN
RRP0016A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.675) TYP
13
16
16X (0.6)
1
12
16X (0.3)
(0.675) TYP
(3.8)
17
SYMM
12X (0.65)
4X ( 1.15)
9
4
(R0.05) TYP
8
5
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 17
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224816/A 02/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
13.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
P1 Pitch between successive cavity centers
W
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
TMUX7308FRRPR
TMUX7308FPWR
WQFN
RRP
PW
16
16
3000
2000
330
330
12.4
12.4
4.25
6.9
4.25
5.6
1.15
1.6
8
8
12
12
Q2
Q1
TSSOP
Copyright © 2021 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: TMUX7308F
TMUX7308F
SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021
www.ti.com
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
SPQ
3000
2000
Length (mm) Width (mm)
Height (mm)
TMUX7308FRRPR
TMUX7308FPWR
WQFN
RRP
PW
16
16
367
367
367
367
35
35
TSSOP
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: TMUX7308F
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTMUX7308FPWR
PTMUX7308FRRPR
ACTIVE
ACTIVE
TSSOP
WQFN
PW
16
16
2000
3000
TBD
TBD
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
RRP
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
相关型号：
TMUX7308F_V02
TMUX730xF ±60-V Fault-Protected, 8:1 and Dual 4:1 Multiplexers with Latch-Up Immunity and 1.8-V Logic
TI
TMUX7309F
TMUX730xF ±60-V Fault-Protected, 8:1 and Dual 4:1 Multiplexers with Latch-Up Immunity and 1.8-V Logic
TI
TMUX7309FRRPR
TMUX730xF ±60-V Fault-Protected, 8:1 and Dual 4:1 Multiplexers with Latch-Up Immunity and 1.8-V Logic
TI
TMUX730XF
TMUX730xF ±60-V Fault-Protected, 8:1 and Dual 4:1 Multiplexers with Latch-Up Immunity and 1.8-V Logic
TI
TMUX7411F
TMUX741xF ±60 V Fault-Protected, 1:1 (SPST), 4-Channel Switches with Latch-Up Immunity and 1.8-V Logic
TI
TMUX7411F_V01
TMUX741xF ±60 V Fault-Protected, 1:1 (SPST), 4-Channel Switches with Latch-Up Immunity and 1.8-V Logic
TI
TMUX7412F
TMUX741xF ±60 V Fault-Protected, 1:1 (SPST), 4-Channel Switches with Latch-Up Immunity and 1.8-V Logic
TI
©2020 ICPDF网 联系我们和版权申明