TMUX7308F [TI]
TMUX730xF ±60-V Fault-Protected, 8:1 and Dual 4:1 Multiplexers with Latch-Up Immunity and 1.8-V Logic;
| 型号： | TMUX7308F |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TMUX730xF ±60-V Fault-Protected, 8:1 and Dual 4:1 Multiplexers with Latch-Up Immunity and 1.8-V Logic |
| 文件： | 总54页 (文件大小：2618K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMUX7308F, TMUX7309F
SCDS403B – FEBRUARY 2021 – REVISED DECEMBER 2021
TMUX730xF ±60-V Fault-Protected, 8:1 and Dual 4:1 Multiplexers with Latch-Up
Immunity and 1.8-V Logic
1 Features
3 Description
•
Wide supply range:
The TMUX7308F and TMUX7309F are modern
complementary metal-oxide semiconductor (CMOS)
analog multiplexers in 8:1 (single ended) and 4:1
(differential) configurations. The devices work well
with dual supplies (±5 V to ±22 V), a single supply (8
V to 44 V), or asymmetric supplies (such as VDD = 12
V, VSS = –5 V). The overvoltage protection is available
in powered and powered-off conditions, making the
TMUX7308F and TMUX7309F devices suitable for
applications where power supply sequencing cannot
be precisely controlled.
– Dual supply: ±5 V to ±22 V
– Single supply: 8 V to 44 V
Integrated fault protection:
– Overvoltage protection, source to supplies or
source to drain: ±85 V
– Overvoltage protection: ±60 V
– Powered-off protection: ±60 V
– Non-fault channels continue to operate
– Known state without logic inputs present
– Output clamped to the supply in overvoltage
condition
•
The device blocks fault voltage up to +60 V or –60
V relative to ground in both powered and powered-off
conditions. When no power supplies are present, the
switch channels remain in the OFF state regardless of
switch input conditions and logic control status. Under
normal operation conditions, if the analog input signal
level on any Sx pin exceeds the supply voltage (VDD
or VSS) by a threshold voltage (VT), the channel turns
OFF and the Sx pin becomes high impedance. When
the fault channel is selected, the drain pin (D or Dx) is
pulled to the supply (VDD or VSS) that was exceeded.
•
•
•
•
•
•
Latch-up immune
1.8-V Logic capable
Fail-safe logic: up to 44 V independent of supply
Integrated pull-down resistor on logic pins
Break-before-make switching
Industry standard TSSOP and
smaller WQFN packages
2 Applications
•
•
•
•
•
•
•
Factory automation and control
Programmable logic controllers (PLC)
Analog input modules
Semiconductor test equipment
Battery test equipment
The low capacitance, low charge injection, and
integrated fault protection enables the TMUX7308F
and TMUX7309F devices to be used in front end
data acquisition applications where high performance
and high robustness are both critical. The devices are
available in a standard TSSOP package and smaller
WQFN package (ideal if PCB space is limited).
Servo drive control module
Data acquisition systems (DAQ)
VDD
VSS
VDD
VSS
SW
SW
SW
Device Information(1)
S1
S2
S1A
DA
DB
PART NUMBER
PACKAGE
TSSOP (16)(2)
WQFN (16)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
4.00 mm × 4.00 mm
SW
SW
S4A
S1B
TMUX7308F
TMUX7309F
D
SW
SW
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
S4B
S8
(2) Preview package for TMUX7309F.
A0
A1
A2
EN
A0
A1
EN
Fault Detection/
Switch Driver/
Logic Decoder
Fault Detection/
Switch Driver/
Logic Decoder
TMUX7308F
TMUX7309F
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX7308F, TMUX7309F
SCDS403B – FEBRUARY 2021 – REVISED DECEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Thermal Information....................................................6
7.4 Recommended Operating Conditions.........................6
7.5 Electrical Characteristics (Global)...............................6
7.6 ±15 V Dual Supply: Electrical Characteristics.............7
7.7 ±20 V Dual Supply: Electrical Characteristics...........10
7.8 12 V Single Supply: Electrical Characteristics.......... 13
7.9 36 V Single Supply: Electrical Characteristics.......... 16
7.10 Typical Characteristics............................................19
8 Parameter Measurement Information..........................26
8.1 On-Resistance.......................................................... 26
8.2 Off-Leakage Current................................................. 26
8.3 On-Leakage Current................................................. 27
8.4 Input and Output Leakage Current Under
8.9 Fault Recovery Time.................................................30
8.10 Charge Injection......................................................31
8.11 Off Isolation............................................................. 31
8.12 Crosstalk.................................................................32
8.13 Bandwidth............................................................... 33
8.14 THD + Noise........................................................... 33
9 Detailed Description......................................................34
9.1 Overview...................................................................34
9.2 Functional Block Diagram.........................................34
9.3 Feature Description...................................................34
9.4 Device Functional Modes..........................................37
10 Application and Implementation................................39
10.1 Application Information........................................... 39
10.2 Typical Application.................................................. 39
11 Power Supply Recommendations..............................40
12 Layout...........................................................................41
12.1 Layout Guidelines................................................... 41
12.2 Layout Example...................................................... 41
13 Device and Documentation Support..........................43
13.1 Documentation Support.......................................... 43
13.2 Receiving Notification of Documentation Updates..43
13.3 Support Resources................................................. 43
13.4 Trademarks.............................................................43
13.5 Electrostatic Discharge Caution..............................43
13.6 Glossary..................................................................43
14 Mechanical, Packaging, and Orderable
Overvoltage Fault........................................................27
8.5 Break-Before-Make Delay.........................................28
8.6 Enable Delay Time....................................................29
8.7 Transition Time......................................................... 29
8.8 Fault Response Time................................................30
Information.................................................................... 43
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2021) to Revision B (December 2021)
Page
•
Changed the status of the data sheet from: Advanced Information to: Production Data ...................................1
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5 Device Comparison Table
PRODUCT
DESCRIPTION
TMUX7308F
TMUX7309F
+60 V/ –60 V Tolerant, Fault-protected, Latch-up Immune, Single-Ended 8:1 Multiplexer
+60 V/ –60 V Tolerant, Fault-protected, Latch-up Immune, 4:1, 2-Channel Multiplexer
6 Pin Configuration and Functions
A0
EN
VSS
S1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A1
A2
GND
VDD
S5
VSS
S1
1
2
3
4
12
11
10
9
GND
VDD
S5
Thermal
Pad
S2
S2
S3
S6
S3
S6
S4
S7
D
S8
Not to scale
Not to scale
Figure 6-1. PW Package
16-Pin TSSOP, Top View
Figure 6-2. RRP Package
16-Pin WQFN, Top View
Table 6-1. Pin Functions: TMUX7308F
PIN
TYPE(1)
DESCRIPTION
NAME
TSSOP
WQFN
Logic control input address 0 (A0), has internal 4 MΩ pull-down resistor. Controls switch state
as shown in Section 9.4.3.
A0
1
2
15
I
I
Active high logic enable (EN) pin, has internal 4 MΩ pull-down resistor. The device is disabled
and all switches become high impedance when the pin is low. When the pin is high, the Ax
logic inputs determine individual switch states as shown in Section 9.4.3.
EN
16
1
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
VSS
3
P
S1
S2
S3
S4
D
4
5
2
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Overvoltage protected source pin 1. Can be an input or output.
Overvoltage protected source pin 2. Can be an input or output.
Overvoltage protected source pin 3. Can be an input or output.
Overvoltage protected source pin 4. Can be an input or output.
Drain pin. Can be an input or output. The drain pin is not overvoltage protected.
Overvoltage protected source pin 8. Can be an input or output.
Overvoltage protected source pin 7. Can be an input or output.
Overvoltage protected source pin 6. Can be an input or output.
Overvoltage protected source pin 5. Can be an input or output.
6
4
7
5
8
6
S8
S7
S6
S5
9
7
10
11
12
8
9
10
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and
GND.
VDD
13
11
P
GND
A2
14
15
12
13
P
I
Ground (0 V) reference
Logic control input address 2 (A2), has internal 4 MΩ pull-down resistor. Controls switch state
as shown in Section 9.4.3.
Logic control input address 1 (A1), has internal 4 MΩ pull-down resistor. Controls switch state
as shown in Section 9.4.3.
A1
16
14
I
The thermal pad is not connected internally. It is recommended that the pad be tied to GND or
VSS for best performance.
Thermal Pad
P
(1) I = input, O = output, I/O = input and output, P = power
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A0
EN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A1
GND
VDD
S1B
S2B
S3B
S4B
DB
VSS
S1A
S2A
S3A
S4A
DA
VSS
S1A
S2A
S3A
1
2
3
4
12
11
10
9
VDD
S1B
S2B
S3B
Thermal
Pad
Not to scale
Not to scale
Figure 6-4. RRP Package
16-Pin WQFN, Top View
Figure 6-3. (Preview) PW Package
16-Pin TSSOP, Top View
Table 6-2. Pin Functions: TMUX7309F
PIN
TYPE(1)
DESCRIPTION
NAME
TSSOP(2)
WQFN
Logic control input address 0 (A0), has internal 4 MΩ pull-down resistor. Controls switch state
as shown in Section 9.4.3.
A0
1
2
15
I
Active high logic enable (EN) pin, has internal 4 MΩ pull-down resistor. The device is disabled
and all switches become high impedance when the pin is low. When the pin is high, the Ax
logic inputs determine individual switch states as shown in Section 9.4.3.
EN
16
1
I
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
VSS
3
P
S1A
S2A
S3A
S4A
DA
4
5
2
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Overvoltage protected source pin 1A. Can be an input or output.
Overvoltage protected source pin 2A. Can be an input or output.
Overvoltage protected source pin 3A. Can be an input or output.
Overvoltage protected source pin 4A. Can be an input or output.
Drain terminal A. Can be an input or output. The drain pin is not overvoltage protected.
Drain terminal B. Can be an input or output. The drain pin is not overvoltage protected.
Overvoltage protected source pin 4B. Can be an input or output.
Overvoltage protected source pin 3B. Can be an input or output.
Overvoltage protected source pin 2B. Can be an input or output.
Overvoltage protected source pin 1B. Can be an input or output.
6
4
7
5
8
6
DB
9
7
S4B
S3B
S2B
S1B
10
11
12
13
8
9
10
11
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and
GND.
VDD
14
12
P
GND
A1
15
16
13
14
P
I
Ground (0 V) reference
Logic control input address 1 (A1), has internal 4 MΩ pull-down resistor. Controls switch state
as shown in Section 9.4.3.
The thermal pad is not connected internally. It is recommended that the pad be tied to GND or
VSS for best performance.
Thermal Pad
P
(1) I = input, O = output, I/O = input and output, P = power
(2) Preview package
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
48
UNIT
V
VDD to VSS
VDD to GND
VSS to GND
VS to GND
VS to VDD
VS to VSS
VD
Supply voltage
–0.3
–48
–65
–90
48
V
0.3
65
V
Source input pin (Sx) voltage to GND
Source input pin (Sx) voltage to VDD
Source input pin (Sx) voltage to VSS
Drain pin (D or Dx) voltage
V
V
90
VDD+0.7
48
V
VSS–0.7
GND –0.7
–30
V
VEN or VAx
IEN or IAx
IS or ID (CONT)
Tstg
Logic control input pin voltage (EN, A0, A1, A2)(2)
Logic control input pin current (EN, A0, A1, A2)(2)
Source or drain continuous current (Sx or D)
Storage temperature
V
30
mA
mA
°C
°C
°C
mW
mW
IDC ± 10 %(3)
IDC ± 10 %(3)
–65
150
TA
Ambient temperature
–55
150
TJ
Junction temperature
150
(4)
Ptot
Total power dissipation (QFN)
1600
(5)
Ptot
Total power dissipation (TSSOP)
650
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) Stresses have to be kept at or below both voltage and current ratings at all time.
(3) Refer to Recommended Operating Conditions for IDC ratings.
(4) For QFN package: Ptot derates linearly above TA = 70°C by 23.5 mW/°C
(5) For TSSOP package: Ptot derates linearly above TA = 70°C by 10.1 mW/°C
7.2 ESD Ratings
VALUE
UNIT
Electrostatic
discharge
V(ESD)
V(ESD)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±3500
V
Electrostatic
discharge
Charged device model (CDM), per JEDEC specification JESD22-
C101 or ANSI/ESDA/JEDEC JS-002(2)
±750
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible if necessary precautions are taken.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible if necessary precautions are taken.
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UNIT
SCDS403B – FEBRUARY 2021 – REVISED DECEMBER 2021
7.3 Thermal Information
TMUX7308F/ TMUX7309F
THERMAL METRIC(1)
PW (TSSOP)
RRP (QFN)
16 PINS
43.0
16 PINS
100.4
31.3
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
28.8
46.4
17.9
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.7
0.4
ΨJB
45.8
17.9
RθJC(bot)
N/A
4.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
(1)
VDD – VSS
VDD
Power supply voltage differential
8
5
44
44
V
V
V
V
Positive power supply voltage
VS
Source pin (Sx) voltage (non-fault condition)
Source pin (Sx) voltage to GND (fault condition)
Source pin (Sx) voltage to VDD or VD (fault condition)
Source pin (Sx) voltage to VSS or VD (fault condition)
Drain pin (D, Dx) voltage
VSS
–60
–85
VDD
60
VS to GND
(2)
VS to VDD
VS to VSS
VD
(2)
85
VDD
44
VSS
0
V
V
VEN or VAx
TA
Logic control input pin voltage (EN, A0, A1, A2)
Ambient temperature
–40
125 °C
TA = 25°C
TA = 85°C
TA = 125°C
9
IDC
Continuous current through switch
6.5 mA
5
(1) VDD and VSS can be any value as long as 8 V ≤ (VDD – VSS) ≤ 44 V, and the minimum VDD is met.
(2) Under a fault condition, the potential difference between source pin (Sx) and supply pins (VDD and VSS.) or source pin (Sx) and drain
pins (D, Dx) may not exceed 85 V.
7.5 Electrical Characteristics (Global)
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
Threshold voltage for fault
detector
VT
25°C
0.7
V
LOGIC INPUT/ OUTPUT
VIH
High-level input voltage
EN, Ax pins
EN, Ax pins
–40°C to +125°C
–40°C to +125°C
1.3
0
44
V
V
VIL
Low-level input voltage
0.8
POWER SUPPLY
Undervoltage lockout (UVLO)
Rising edge, single supply
Falling edge, single supply
Single supply
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
5.1
5
6
6.4
6.3
V
V
threshold voltage (VDD – VSS
)
VUVLO
Undervoltage lockout (UVLO)
5.8
threshold voltage (VDD – VSS
)
VDD Undervoltage
lockout (UVLO) hysteresis
VHYS
0.2
40
V
RD(OVP)
Drain resistance to supply rail during overvoltage event on selected source pin 25°C
kΩ
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7.6 ±15 V Dual Supply: Electrical Characteristics
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VS = –10 V to +10 V, IS = –1 mA
VS = –10 V to +10 V, IS = –1 mA
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
180
250
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
330
390
8
Ω
Ω
2.5
1.5
On-resistance mismatch between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
12
13
3.5
4
RFLAT
On-resistance flatness
On-resistance drift
VS = –10 V to +10 V, IS = –1 mA
VS = 0 V, IS = –1 mA
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
Ω
4
RON_DRIFT
1
Ω/°C
nA
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
–1
–1
0.1
1
1
IS(OFF)
Source off leakage current(1)
–40°C to +85°C
–40°C to +125°C
25°C
VD = –10 V / + 10 V
–4
4
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
–1
0.1
0.3
1
ID(OFF)
Drain off leakage current(1)
Output on leakage current(2)
–40°C to +85°C
–40°C to +125°C
25°C
–3
3
nA
nA
VD = –10 V / + 10 V
–14
–1.5
–5
14
1.5
5
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
–22
22
FAULT CONDITION
Input leakage current
durring overvoltage
VS = ± 60 V, GND = 0 V,
VDD = 16.5 V, VSS = –16.5 V
IS(FA)
–40°C to +125°C
–40°C to +125°C
±110
±135
µA
µA
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V
VDD = VSS = 0 V
IS(FA) Grounded
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = floating
IS(FA) Floating
–40°C to +125°C
±135
±10
µA
nA
25°C
–50
–70
50
70
VS = ± 60 V, GND = 0 V,
VDD = 16.5 V, VSS = –16.5 V, –15.5V ≤
VD ≤ 16.5V
Output leakage current
during overvoltage
ID(FA)
–40°C to +85°C
–40°C to +125°C
25°C
–90
90
–50
±1
50
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = 0 V
ID(FA) Grounded
–40°C to +85°C
–40°C to +125°C
25°C
–100
–500
100
500
nA
µA
±3
±5
±8
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = floating
ID(FA) Floating
–40°C to +85°C
–40°C to +125°C
LOGIC INPUT/ OUTPUT
IIH High-level input current
25°C
–2
–2
± 0.6
± 0.6
2
2
VEN = VAx = VDD
VEN = VAx = 0 V
µA
µA
–40°C to +125°C
25°C
–1.1
–1.2
1.1
1.2
IIL
Low-level input current
–40°C to +125°C
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7.6 ±15 V Dual Supply: Electrical Characteristics (continued)
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
SWITCHING CHARACTERISTICS
25°C
165
265
VS = 10 V,
RL = 4 kΩ, CL= 12 pF
tON (EN)
tOFF (EN)
tTRAN
Enable turn-on time
Enable turn-off time
Transition time
–40°C to +85°C
–40°C to +125°C
25°C
285
300
400
400
420
225
245
260
ns
ns
ns
350
170
VS = 10 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
25°C
VS = 10 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
25°C
tRESPONSE
tRECOVERY
tBBM
Fault response time
Fault recovery time
RL = 4 kΩ, CL= 12 pF
300
1.2
ns
µs
ns
pC
RL = 4 kΩ, CL= 12 pF
25°C
Break-before-make time delay
Charge injection
VS = 10 V, RL = 4 kΩ, CL= 12 pF
VS = 0 V, CL = 1 nF
–40°C to +125°C
25°C
50
120
–15
QINJ
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
OISO
Off-isolation
25°C
25°C
25°C
–82
–95
dB
dB
dB
Intra-channel crosstalk
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
XTALK
Inter-channel crosstalk
(TMUX7309F)
–103
–3 dB bandwidth (TMUX7308F)
–3 dB bandwidth (TMUX7309F)
25°C
25°C
150
280
MHz
MHz
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V
BW
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
ILOSS
Insertion loss
25°C
–9
dB
Total harmonic distortion plus
noise
RS = 40 Ω, RL = 10k Ω, VS = 15 VPP, VBIAS
= 0 V, f = 20 Hz to 20k Hz
THD+N
CS(OFF)
25°C
25°C
25°C
0.0015
3.5
%
pF
pF
Input off-capacitance
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
Output off-capacitance
(TMUX7308F)
28
CD(OFF)
Output off-capacitance
(TMUX7309F)
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
25°C
25°C
25°C
15
30
17
pF
pF
pF
Input/Output on-capacitance
(TMUX7308F)
CS(ON)
CD(ON)
Input/Output on-capacitance
(TMUX7309F)
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7.6 ±15 V Dual Supply: Electrical Characteristics (continued)
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
POWER SUPPLY
25°C
0.25
0.5
VDD = 16.5 V, VSS = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
0.5
0.5
0.4
0.4
0.4
mA
0.15
VDD = 16.5 V, VSS = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
mA
mA
mA
VDD = 16.5 V, VSS = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IGND
GND current
25°C
0.075
0.25
25°C
1
1
VS = ± 60 V,
VDD = 16.5 V, VSS = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IDD(FA)
VDD supply current under fault
–40°C to +85°C
–40°C to +125°C
25°C
1
0.15
0.5
0.5
0.5
VS = ± 60 V,
VDD = 16.5 V, VSS = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
ISS(FA)
VSS supply current under fault
GND current under fault
–40°C to +85°C
–40°C to +125°C
mA
mA
mA
VS = ± 60 V,
VDD = 16.5 V, VSS = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IGND(FA)
25°C
0.15
0.15
25°C
0.5
0.5
0.5
0.4
0.4
0.4
VDD = 16.5 V, VSS = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
IDD(DISABLE)
VDD supply current (disable mode)
–40°C to +85°C
–40°C to +125°C
25°C
0.1
VDD = 16.5 V, VSS = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
ISS(DISABLE)
VSS supply current (disable mode)
–40°C to +85°C
–40°C to +125°C
mA
(1) When VS is positive,VD is negative. And when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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7.7 ±20 V Dual Supply: Electrical Characteristics
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VS = –15 V to +15 V, IS = –1 mA
VS = –15 V to +15 V, IS = –1 mA
VS = –15 V to +15 V, IS = –1 mA
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
180
250
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
330
390
8
Ω
Ω
Ω
2.5
8
On-resistance mismatch between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
12
13
10
12
12
3.5
4
RFLAT
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
1.5
RFLAT
On-resistance flatness
On-resistance drift
VS = –13.5 V to +13.5 V, IS = –1 mA
VS = 0 V, IS = –1 mA
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
Ω
4
RON_DRIFT
1
Ω/°C
nA
VDD = 22 V, VSS = –22 V
Switch state is off
VS = +15 V / –15 V
VD = –15 V / + 15 V
–1
–1
0.1
1
1
IS(OFF)
Source off leakage current(1)
–40°C to +85°C
–40°C to +125°C
25°C
–4
4
VDD = 22 V, VSS = –22 V
Switch state is off
VS = +15 V / –15 V
VD = –15 V / + 15 V
–1
0.1
0.3
1
ID(OFF)
Drain off leakage current(1)
Output on leakage current(2)
–40°C to +85°C
–40°C to +125°C
25°C
–3
3
nA
nA
–14
–1.5
–5
14
1.5
5
VDD = 22 V, VSS = –22 V
Switch state is on
VS = VD = ±15 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
–22
22
FAULT CONDITION
Input leakage current
durring overvoltage
VS = ± 60 V, GND = 0 V,
VDD = 22 V, VSS = –22 V
IS(FA)
–40°C to +125°C
–40°C to +125°C
±95
µA
µA
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = 0 V
IS(FA) Grounded
±135
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = floating
IS(FA) Floating
–40°C to +125°C
±135
±10
µA
nA
25°C
–50
–70
50
70
VS = ± 60 V, GND = 0V,
VDD = 22 V, VSS = –22 V,
–21V ≤ VD ≤ 22V
Output leakage current
during overvoltage
ID(FA)
–40°C to +85°C
–40°C to +125°C
25°C
–90
90
–50
±1
50
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = 0 V
ID(FA) Grounded
–40°C to +85°C
–40°C to +125°C
25°C
–100
–500
100
500
nA
µA
±3
±5
±8
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = floating
ID(FA) Floating
–40°C to +85°C
–40°C to +125°C
LOGIC INPUT/ OUTPUT
IIH High-level input current
25°C
–2.2
–2.2
–1.1
–1.2
± 0.6
± 0.6
2.2
2.2
1.1
1.2
VEN = VAx = VDD
VEN = VAx = 0 V
µA
µA
–40°C to +125°C
25°C
IIL
Low-level input current
–40°C to +125°C
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7.7 ±20 V Dual Supply: Electrical Characteristics (continued)
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
SWITCHING CHARACTERISTICS
25°C
175
300
VS = 10 V,
RL = 4 kΩ, CL= 12 pF
tON (EN)
tOFF (EN)
tTRAN
Enable turn-on time
Enable turn-off time
Transition time
–40°C to +85°C
–40°C to +125°C
25°C
325
350
400
400
420
245
270
285
ns
ns
ns
350
170
VS = 10 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
25°C
VS = 10 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
25°C
tRESPONSE
tRECOVERY
tBBM
Fault response time
Fault recovery time
RL = 4 kΩ, CL= 12 pF
300
1.2
ns
µs
ns
pC
RL = 4 kΩ, CL= 12 pF
25°C
Break-before-make time delay
Charge injection
VS = 10 V, RL = 4 kΩ, CL= 12 pF
VS = 0 V, CL = 1 nF, RS = 0 Ω
–40°C to +125°C
25°C
50
120
–17
QINJ
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
OISO
Off-isolation
25°C
25°C
25°C
–85
–95
dB
Intra-channel crosstalk
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
XTALK
dB
Inter-channel crosstalk
(TMUX7309F)
–103
–3 dB bandwidth (TMUX7308F)
–3 dB bandwidth (TMUX7309F)
25°C
25°C
150
285
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V
BW
MHz
dB
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
ILOSS
Insertion loss
25°C
–9
Total harmonic distortion plus
noise
RS = 40 Ω, RL = 10k Ω, VS = 20 VPP, VBIAS
= 0 V, f = 20 Hz to 20k Hz
THD+N
CS(OFF)
25°C
25°C
25°C
0.0015
3.5
%
Input off-capacitance
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
pF
Output off-capacitance
(TMUX7308F)
28
CD(OFF)
pF
pF
Output off-capacitance
(TMUX7309F)
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
25°C
25°C
25°C
14
30
16
Input/Output on-capacitance
(TMUX7308F)
CS(ON)
CD(ON)
Input/Output on-capacitance
(TMUX7309F)
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7.7 ±20 V Dual Supply: Electrical Characteristics (continued)
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
POWER SUPPLY
25°C
0.25
0.5
VDD = 22 V, VSS = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
0.5
0.5
0.4
0.4
0.4
mA
0.15
VDD = 22 V, VSS = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
mA
mA
mA
VDD = 22 V, VSS = –22 V,VAx = 0 V, 5 V,
or VDD, VEN = 5 V or VDD
IGND
GND current
25°C
0.075
0.25
25°C
1
1
VS = ± 60 V,
VDD = 22 V, VSS = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IDD(FA)
VDD supply current under fault
–40°C to +85°C
–40°C to +125°C
25°C
1
0.15
0.5
0.5
0.5
VS = ± 60 V,
VDD = 22 V, VSS = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
ISS(FA)
VSS supply current under fault
GND current under fault
–40°C to +85°C
–40°C to +125°C
mA
mA
VS = ± 60 V,VDD = 22 V, VSS = –22 V,VAx
= 0 V, 5 V, or VDD, VEN = 5 V or VDD
IGND(FA)
25°C
0.15
0.15
25°C
0.5
0.5
0.5
0.4
0.4
0.4
mA
mA
mA
mA
mA
mA
VDD = 22 V, VSS = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
IDD(DISABLE)
VDD supply current (disable mode)
–40°C to +85°C
–40°C to +125°C
25°C
0.1
VDD = 22 V, VSS = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
ISS(DISABLE)
VSS supply current (disable mode)
–40°C to +85°C
–40°C to +125°C
(1) When VS is positive,VD is negative. And when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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7.8 12 V Single Supply: Electrical Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG SWITCH
RON
RON
RON
On-resistance
On-resistance
On-resistance
VS = 0 V to 7.8 V, IS = –1 mA
VS = 0 V to 7.8 V, IS = –1 mA
VS = 0 V to 7.8 V, IS = –1 mA
25°C
180
250
330
390
8
Ω
Ω
Ω
–40°C to +85°C
–40°C to +125°C
25°C
2.5
7
On-resistance mismatch between
channels
ΔRON
VS = 0 V to 7.8 V, IS = –1 mA
VS = 0 V to 7.8 V, IS = –1 mA
–40°C to +85°C
–40°C to +125°C
25°C
12
13
30
45
75
7
Ω
Ω
RFLAT
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
1.5
RFLAT
On-resistance flatness
On-resistance drift
VS = 1 V to 7.8 V, IS = –1 mA
VS = 6 V, IS = –1 mA
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
8
Ω
8
RON_DRIFT
1
Ω/°C
nA
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
–1
–1
0.1
1
1
IS(OFF)
Source off leakage current(1)
–40°C to +85°C
–40°C to +125°C
25°C
VD = 1 V / 10 V
–4
4
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
–1
0.1
0.3
1
ID(OFF)
Drain off leakage current(1)
Output on leakage current(2)
–40°C to +85°C
–40°C to +125°C
25°C
–3
3
nA
nA
VD = 1 V / 10 V
–14
–1.5
–5
14
1.5
5
VDD = 13.2 V, VSS = 0 V
Switch state is on
VS = VD = 10 V or 1 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
–22
22
FAULT CONDITION
Input leakage current
durring overvoltage
VS = ± 60 V, GND = 0 V,
VDD = 13.2 V, VSS = 0 V
IS(FA)
–40°C to +125°C
–40°C to +125°C
±145
±135
µA
µA
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = 0 V
IS(FA) Grounded
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = floating
IS(FA) Floating
–40°C to +125°C
±135
±10
µA
nA
25°C
–50
–70
50
70
VS = ± 60 V, GND = 0 V,
VDD = 13.2 V, VSS = 0 V,
1V ≤ VD ≤ 13.2V
Output leakage current
during overvoltage
ID(FA)
–40°C to +85°C
–40°C to +125°C
25°C
–90
90
–50
±1
50
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = 0 V
ID(FA) Grounded
–40°C to +85°C
–40°C to +125°C
25°C
–100
–500
100
500
nA
µA
±3
±5
±8
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = floating
ID(FA) Floating
–40°C to +85°C
–40°C to +125°C
LOGIC INPUT/ OUTPUT
IIH High-level input current
25°C
–2
–2
± 0.6
± 0.6
2
2
µA
µA
VEN = VAx = VDD
VEN = VAx = 0 V
–40°C to +125°C
25°C
–1.1
–1.2
1.1
1.2
IIL
Low-level input current
µA
–40°C to +125°C
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7.8 12 V Single Supply: Electrical Characteristics (continued)
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SWITCHING CHARACTERISTICS
25°C
160
265
VS = 8 V,
RL = 4 kΩ, CL= 12 pF
tON (EN)
tOFF (EN)
tTRAN
Enable turn-on time
Enable turn-off time
Transition time
–40°C to +85°C
–40°C to +125°C
25°C
285
300
485
485
500
215
230
240
ns
ns
ns
420
160
VS = 8 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
25°C
VS = 8 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
25°C
tRESPONSE
tRECOVERY
tBBM
Fault response time
Fault recovery time
RL = 4 kΩ, CL= 12 pF
RL = 4 kΩ, CL= 12 pF
220
0.63
90
ns
µs
ns
pC
25°C
Break-before-make time delay
Charge injection
VS = 10 V, RL = 4 kΩ, CL= 12 pF
VS = 6 V, CL = 1 nF
–40°C to +125°C
25°C
30
QINJ
–11
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
OISO
Off-isolation
25°C
25°C
25°C
–76
–93
dB
dB
dB
XTALK
XTALK
Intra-channel crosstalk
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
Inter-channel crosstalk
(TMUX7309F)
–103
–3 dB bandwidth (TMUX7308F)
–3 dB bandwidth (TMUX7309F)
25°C
25°C
130
250
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V
BW
MHz
dB
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
ILOSS
Insertion loss
25°C
–9
Total harmonic distortion plus
noise
RS = 40 Ω, RL = 10k Ω, VS = 6 VPP, VBIAS
6 V, f = 20 Hz to 20k Hz
=
THD+N
CS(OFF)
25°C
25°C
25°C
0.002
4
%
Input off-capacitance
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
pF
Output off-capacitance
(TMUX7308F)
31
CD(OFF)
pF
pF
Output off-capacitance
(TMUX7309F)
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
25°C
25°C
25°C
16
34
20
Input/Output on-capacitance
(TMUX7308F)
CS(ON)
CD(ON)
Input/Output on-capacitance
(TMUX7309F)
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7.8 12 V Single Supply: Electrical Characteristics (continued)
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLY
25°C
0.25
0.5
VDD = 13.2 V, VSS = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
0.5
0.5
0.4
0.4
0.4
mA
0.15
VDD = 13.2 V, VSS = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
mA
mA
mA
VDD = 13.2 V, VSS = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IGND
GND current
25°C
0.075
0.25
25°C
1
1
VS = ± 60 V,
VDD = 13.2 V, VSS = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IDD(FA)
VDD supply current under fault
–40°C to +85°C
–40°C to +125°C
25°C
1
0.15
0.5
0.5
0.5
VS = ± 60 V,
VDD = 13.2 V, VSS = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
ISS(FA)
VSS supply current under fault
GND current under fault
–40°C to +85°C
–40°C to +125°C
mA
mA
mA
VS = ± 60 V,
VDD = 13.2 V, VSS = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IGND(FA)
25°C
0.17
0.15
25°C
0.5
0.5
0.5
0.4
0.4
0.4
VDD = 13.2 V, VSS = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
IDD(DISABLE)
VDD supply current (disable mode)
–40°C to +85°C
–40°C to +125°C
25°C
0.1
VDD = 13.2 V, VSS = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
ISS(DISABLE)
VSS supply current (disable mode)
–40°C to +85°C
–40°C to +125°C
mA
(1) When VS is 10 V, VD is 1 V. Or when VS is 1 V, VD is 10 V.
(2) When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating.
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7.9 36 V Single Supply: Electrical Characteristics
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
180
250
VS = 0 V to 28 V,
IS = –1 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
330
390
8
Ω
Ω
Ω
2.5
8
On-resistance mismatch between VS = 0 V to 28 V,
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
12
13
65
75
90
3
channels
IS = –1 mA
RFLAT
On-resistance flatness
VS = 0 V to 30 V, IS = –1 mA
–40°C to +85°C
–40°C to +125°C
25°C
1.5
VS = 1 V to 28 V,
IS = –1 mA
RFLAT
On-resistance flatness
On-resistance drift
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
4
Ω
4
RON_DRIFT
VS = 18 V, IS = –1 mA
1
Ω/°C
nA
VDD = 39.6 V, VSS = 0 V
Switch state is off
VS = 30 V / 1 V
–1
–1
0.1
1
1
IS(OFF)
Source off leakage current(1)
–40°C to +85°C
–40°C to +125°C
25°C
VD = 1 V / 30 V
–4
4
VDD = 39.6 V, VSS = 0 V
Switch state is off
VS = 30 V / 1 V
–1
0.1
0.3
1
ID(OFF)
Output on leakage current(2)
Output on leakage current(1)
–40°C to +85°C
–40°C to +125°C
25°C
–3
3
nA
nA
VD = 1 V / 30 V
–14
–1.5
–5
14
1.5
5
VDD = 39.6 V, VSS = 0 V
Switch state is on
VS = VD = 30 V or 1 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
–22
22
FAULT CONDITION
Input leakage current
durring overvoltage
VS = 60 / –40 V,
VDD = 39.6 V, VSS = 0 V, GND = 0 V
IS(FA)
–40°C to +125°C
–40°C to +125°C
±110
±135
µA
µA
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V,
VDD = VSS = 0 V, GND = 0 V
IS(FA) Grounded
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V,
VDD = VSS = floating, GND = 0 V,
IS(FA) Floating
–40°C to +125°C
±135
±10
µA
nA
25°C
–50
–70
50
70
VS = 60 / –40 V,
1V ≤ VD ≤ 39.6V
VDD = 39.6 V, VSS = 0 V, GND = 0V,
Output leakage current
during overvoltage
ID(FA)
–40°C to +85°C
–40°C to +125°C
25°C
–90
90
–50
±1
50
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = 0 V
ID(FA) Grounded
–40°C to +85°C
–40°C to +125°C
25°C
–100
–500
100
500
nA
µA
±3
±5
±8
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = floating
ID(FA) Floating
–40°C to +85°C
–40°C to +125°C
LOGIC INPUT/ OUTPUT
IIH High-level input current
25°C
–3.2
–3.2
–1.1
–1.2
± 0.6
± 0.6
3.2
3.2
1.1
1.2
VEN = VAx = VDD
VEN = VAx = 0 V
µA
µA
–40°C to +125°C
25°C
IIL
Low-level input current
–40°C to +125°C
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7.9 36 V Single Supply: Electrical Characteristics (continued)
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
SWITCHING CHARACTERISTICS
25°C
185
390
VS = 18 V,
RL = 4 kΩ, CL= 12 pF
tON (EN)
tOFF (EN)
tTRAN
Enable turn-on time
Enable turn-off time
Transition time
–40°C to +85°C
–40°C to +125°C
25°C
460
530
450
450
450
230
245
255
ns
ns
ns
380
185
VS = 18 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
25°C
VS = 18 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
25°C
tRESPONSE
tRECOVERY
tBBM
Fault response time
Fault recovery time
RL = 4 kΩ, CL= 12 pF
210
0.63
100
–16
ns
µs
ns
pC
RL = 4 kΩ, CL= 12 pF
25°C
Break-before-make time delay
Charge injection
VS = 18 V, RL = 4 kΩ, CL= 12 pF
VS = 18 V, CL = 1 nF, RS = 0 Ω
–40°C to +125°C
25°C
50
QINJ
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
OISO
Off-isolation
25°C
25°C
25°C
–78
–95
dB
Intra-channel crosstalk
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
XTALK
dB
Inter-channel crosstalk
(TMUX7309F)
–103
–3 dB bandwidth (TMUX7308F)
–3 dB bandwidth (TMUX7309F)
25°C
25°C
130
255
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V
BW
MHz
dB
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
ILOSS
Insertion loss
25°C
–9
Total harmonic distortion plus
noise
RS = 40 Ω, RL = 10k Ω, VS = 18 VPP, VBIAS
= 18 V, f = 20 Hz to 20k Hz
THD+N
CS(OFF)
25°C
25°C
25°C
0.0015
%
Input off-capacitance
f = 1 MHz, VS = 18 V
f = 1 MHz, VS = 18 V
4
pF
Output off-capacitance
(TMUX7308F)
31
CD(OFF)
pF
pF
Output off-capacitance
(TMUX7309F)
f = 1 MHz, VS = 18 V
f = 1 MHz, VS = 18 V
f = 1 MHz, VS = 18 V
25°C
25°C
25°C
16
34
19
Input/Output on-capacitance
(TMUX7308F)
CS(ON)
CD(ON)
Input/Output on-capacitance
(TMUX7309F)
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7.9 36 V Single Supply: Electrical Characteristics (continued)
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
POWER SUPPLY
25°C
0.25
0.5
VDD = 39.6 V, VSS = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
0.5
0.5
0.4
0.4
0.4
mA
0.15
VDD = 39.6 V, VSS = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
mA
mA
mA
VDD = 39.6 V, VSS = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IGND
GND current
25°C
0.075
0.25
25°C
1
1
VS = 60 / –40 V,
VDD = 39.6 V, VSS = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IDD(FA)
VDD supply current under fault
–40°C to +85°C
–40°C to +125°C
25°C
1
0.15
0.5
0.5
0.5
VS = 60 / –40 V,
VDD = 39.6 V, VSS = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
ISS(FA)
VSS supply current under fault
GND current under fault
–40°C to +85°C
–40°C to +125°C
mA
mA
mA
VS = 60 / –40 V,
VDD = 39.6 V, VSS = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IGND(FA)
25°C
0.15
0.15
25°C
0.5
0.5
0.5
0.4
0.4
0.4
VDD = 39.6 V, VSS = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
IDD(DISABLE)
VDD supply current (disable mode)
–40°C to +85°C
–40°C to +125°C
25°C
0.1
VDD = 39.6 V, VSS = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
ISS(DISABLE)
VSS supply current (disable mode)
–40°C to +85°C
–40°C to +125°C
mA
(1) When VS is 30 V, VD is 1 V. Or when VS is 1 V, VD is 30 V.
(2) When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating.
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7.10 Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
1800
420
380
340
300
260
220
180
140
100
VDD = 13.5 V, VSS = -13.5 V
VDD = 13.5 V, VSS = -13.5 V
VDD = 15 V, VSS = -15 V
VDD = 16.5 V, VSS = -16.5 V
VDD = 18 V, VSS = -18 V
VDD = 20 V, VSS = -20 V
VDD = 22 V, VSS = -22 V
1600
1400
1200
1000
800
600
400
200
0
VDD = 15 V, VSS = -15 V
VDD = 16.5 V, VSS = -16.5 V
VDD = 18 V, VSS = -18 V
VDD = 20 V, VSS = -20 V
VDD = 22 V, VSS = -22 V
-22 -18 -14 -10 -6
-2
2
6
10 14 18 22
-22 -18 -14 -10 -6
-2
2
6
10 14 18 22
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
Dual Supply Voltages
Dual Supply Flat RON Region
Figure 7-1. On-Resistance vs Source or Drain Voltage
Figure 7-2. On-Resistance vs Source or Drain Voltage
240
350
VDD = 13.5 V, VSS = -13.5 V
TA = 125C
VDD = 15 V, VSS = -15 V
VDD = 16.5 V, VSS = -16.5 V
VDD = 18 V, VSS = -18 V
VDD = 20 V, VSS = -20 V
VDD = 22 V, VSS = -22 V
230
220
210
200
190
180
170
160
300
TA = 85C
250
TA = 25C
200
150
TA = -40C
100
-10
-6
-2
2
6
10
-18
-14
-10
-6
-2
2
6
10
14
18
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
Flattest RON region for all supply voltages shown
±15 V Supply Flattest RON Region
Figure 7-3. On-Resistance vs Source or Drain Voltage
Figure 7-4. On-Resistance vs Source or Drain Voltage
350
1800
VDD = 7.2V, VSS = 0V
TA = 125C
1600
1400
1200
1000
800
600
400
200
0
VDD = 8V, VSS = 0V
VDD = 8.8V, VSS = 0V
VDD = 10.8V, VSS = 0V
VDD = 12V, VSS = 0V
VDD = 13.2V, VSS = 0V
300
TA = 85C
250
TA = 25C
200
150
TA = -40C
100
-18
0
2
4
6
8
10
12 13.2
-14
-10
-6
-2
2
6
10
14
18
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
Single Supply Voltages
±20 V Supply Flattest RON Region
Figure 7-6. On-Resistance vs Source or Drain Voltage
Figure 7-5. On-Resistance vs Source or Drain Voltage
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7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
480
420
360
300
240
180
350
300
250
200
150
100
TA = 125C
TA = 85C
TA = 25C
VDD = 8V, VSS = 0V
VDD = 8.8V, VSS = 0V
VDD = 10.8V, VSS = 0V
VDD = 12V, VSS = 0V
VDD = 13.2V, VSS = 0V
TA = -40C
120
60
0
2
4
6
8
10
12 13.2
1
2
3
4
5
6
7
8
9
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
Single Supply Flat RON Region
12 V Supply Flattest RON Region
Figure 7-7. On-Resistance vs Source or Drain Voltage
Figure 7-8. On-Resistance vs Source or Drain Voltage
Single Supply Voltages
Single Supply Flat RON Region
Figure 7-9. On-Resistance vs Source or Drain Voltage
Figure 7-10. On-Resistance vs Source or Drain Voltage
350
TA = 125C
300
TA = 85C
250
TA = 25C
200
150
100
TA = -40C
1
5
9
13
17
21
25
29
33
VS or VD - Source or Drain Voltage (V)
44 V Supply Flattest RON Region
36 V Supply Flattest RON Region
Figure 7-12. On-Resistance vs Source or Drain Voltage
Figure 7-11. On-Resistance vs Source or Drain Voltage
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7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
12
11
10
9
IDOFF VS = -10 V, VD = 10 V
IDOFF VS = 10 V, VD = -10 V
IDON VS = -10 V, VD = -10 V
IDON VS = 10 V, VD = 10 V
ISOFF VS = -10 V, VD = 10 V
ISOFF VS = 10 V, VD = -10 V
8
7
6
5
4
3
2
1
0
-1
0
25
50
75
100
125
Temperature (C)
VDD = 12 V, VSS = 0 V
VDD = 15 V, VSS = -15 V
Figure 7-13. Leakage Current vs Temperature
Figure 7-14. Leakage Current vs Temperature
12
12
11
10
9
IDOFF VS = 1 V, VD = 30 V
IDOFF VS = 30 V, VD = 1 V
IDON VS = 1 V, VD = 1 V
IDON VS = 30 V, VD = 30 V
ISOFF VS = 1 V, VD = 30 V
ISOFF VS = 30 V, VD = 1 V
IDOFF VS = -15 V, VD = 15 V
IDOFF VS = 15 V, VD = -15 V
IDON VS = -15 V, VD = -15 V
IDON VS = 15 V, VD = 15 V
ISOFF VS = -15 V, VD = 15 V
ISOFF VS = 15 V, VD = -15 V
11
10
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
-1
-1
0
25
50
75
100
125
0
25
50
75
100
125
Temperature (C)
Temperature (C)
VDD = 36 V, VSS = 0 V
VDD = 20 V, VSS = -20 V
Figure 7-15. Leakage Current vs Temperature
Figure 7-16. Leakage Current vs Temperature
200
100
200
100
IDOFF VS = 1 V, VD = 30 V
IDOFF VS = 30 V, VD = 1 V
IDON VS = 1 V, VD = 1 V
IDON VS = 30 V, VD = 30 V
ISOFF VS = 1 V, VD = 30 V
ISOFF VS = 30 V, VD = 1 V
IDOFF VS = -15 V, VD = 15 V
IDOFF VS = 15 V, VD = -15 V
IDON VS = -15 V, VD = -15 V
IDON VS = 15 V, VD = 15 V
ISOFF VS = -15 V, VD = 15 V
ISOFF VS = 15 V, VD = -15 V
10
1
10
1
0.1
0.1
0.01
0.01
0.0005
0.0005
0
25
50
75
100
125
0
25
50
75
100
125
Temperature (C)
Temperature (C)
VDD = 36 V, VSS = 0 V
VDD = 20 V, VSS = -20 V
Figure 7-17. Leakage Current vs Temperature
Figure 7-18. Leakage Current vs Temperature
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7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
16
16
14
12
10
8
VS = -60 V, VD = 15 V
VS = -60 V, VD = 20 V
VS = -30 V, VD = 20 V
VS = 60 V, VD = -19 V
VS = 30 V, VD = -19 V
14
12
10
8
VS = -30 V, VD = 15 V
VS = 60 V, VD = -14 V
VS = 30 V, VD = -14 V
6
6
4
4
2
2
0
0
-2
-2
0
25
50
75
100
125
0
25
50
75
100
125
Temperature (C)
Temperature (C)
VDD = 15 V, VSS = -15 V
VDD = 20 V, VSS = -20 V
Figure 7-19. ID(FA) Overvoltage Leakage Current vs Temperature Figure 7-20. ID(FA) Overvoltage Leakage Current vs Temperature
16
VS = -40 V, VD = 36 V
14
12
10
8
VS = -30 V, VD = 36 V
VS = 60 V, VD = 1 V
VS = 30 V, VD = 1 V
6
4
2
0
-2
0
25
50
75
100
125
Temperature (C)
VDD = 12 V, VSS = 0 V
VDD = 36 V, VSS = 0 V
Figure 7-21. ID(FA) Overvoltage Leakage Current vs Temperature Figure 7-22. ID(FA) Overvoltage Leakage Current vs Temperature
120
90
0.1
VDD = 15 V, VSS = -15 V
VDD = 20 V, VSS = -20 V
VDD = 36 V, VSS = 0 V
VDD = 44 V, VSS = 0 V
0.05
0.03
0.02
60
30
0.01
0
0.005
-30
-60
-90
-120
-150
-180
0.003
0.002
0.001
0.0005
0.0003
0.0002
VS = -60 V
VS = -30 V
VS = 30 V
VS = 60 V
0.0001
0
4k
8k
12k
16k
20k
0
25
50
75
100
125
Frequency (Hz)
Temperature (C)
VDD = 15 V, VSS = -15 V
Figure 7-23. IS(FA) Overvoltage Leakage Current vs Temperature
Figure 7-24. THD+N vs Frequency
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7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
2
-2
2
-2
-6
-6
-10
-14
-18
-22
-26
-30
-34
-10
-14
-18
-22
VDD = 8 V, VSS = 0 V
VDD = 12 V, VSS = 0 V
VDD = 36 V, VSS = 0 V
VDD = 44 V, VSS = 0 V
-26
VDD = 15 V, VSS = -15 V
VDD = 20 V, VSS = -20 V
-30
-20 -16 -12
0
4
8
12 16 20 24 28 32 36 40 44
VS - Source Voltage (V)
-8
-4
0
4
8
12
16
20
VS - Source Voltage (V)
Figure 7-26. Charge Injection vs Source Voltage – Single Supply
Figure 7-25. Charge Injection vs Source Voltage – Dual Supply
210
VDD: 15 V, VSS: -15 V, Falling Edge
200
190
180
170
160
150
140
130
120
VDD: 15 V, VSS: -15 V, Rising Edge
VDD: 20 V, VSS: -20 V, Falling Edge
VDD: 20 V, VSS: -20 V, Rising Edge
-40
-15
10
35
60
85
110 125
Temperature (C)
Figure 7-27. Transition Times vs Temperature
Figure 7-28. Transition Times vs Temperature
350
330
310
290
270
250
230
210
190
170
150
130
450
420
390
360
330
TOFF 15V
TOFF +8V
TON +8V
TOFF +12V
TON +12V
TOFF +36V
TON +36V
TON 15V
TOFF 20V
TON 20V
300
270
240
210
180
150
120
-40
-15
10
35
60
85
110 125
-40
-15
10
35
60
85
110 125
Temperature (C)
Temperature (C)
Figure 7-29. Turn-On and Turn-Off Times vs Temperature
Figure 7-30. Turn-On and Turn-Off Times vs Temperature
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7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
0
-5
-10
-15
-20
-25
-30
Off-Isolation
CrossTalk: Adjacent Channel
CrossTalk: Nonadjacent Channel
-20
-40
-60
-80
-100
TMUX7308F
TMUX7309F
-120
10k
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
Frequency(Hz)
Frequency (Hz)
Figure 7-31. Off Isolation and Crosstalk vs Frequency
Figure 7-32. On Response vs Frequency
CDOFF TMUX7308F
120
120
100
80
60
40
20
0
CDOFF TMUX7308F
CON TMUX7308F
CSOFF
CDOFF TMUX7309F
CON TMUX7309F
CON TMUX7308F
CSOFF
CDOFF TMUX7309F
CON TMUX7309F
100
80
60
40
20
0
-15 -12
-9
-6
-3
0
3
6
9
12
15
0
3
6
9
12
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
VDD = 15 V, VSS = -15 V
VDD = 12 V, VSS = 0 V
Figure 7-33. Capacitance vs Source or Drain Voltage
Figure 7-34. Capacitance vs Source or Drain Voltage
0.9
0.4
VT Falling
VT Rising
VDD = +10V
VSS = -10V
VS = 10V
0.36
0.32
0.28
0.24
0.2
0.8
0.7
0.6
0.5
0.4
0.16
0.12
0.08
0.04
100k
1M
Frequency(Hz)
10M
50M
-40
-15
10
35
60
85
110 125
Temperature (C)
Figure 7-36. Large Signal Voltage Off Isolation vs Frequency
Figure 7-35. Threshold Voltage vs Temperature
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7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
25
5
2.5
SOURCE
VDD
22.5
20
DRAIN
50V/s fault ramp
0
-2.5
-5
17.5
15
-7.5
-10
12.5
10
-12.5
-15
7.5
5
VSS
DRAIN
-17.5
-20
2.5
0
SOURCE
50V/s fault ramp
-22.5
-25
-2.5
-5
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
3
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
3
Time(s)
Time(s)
Figure 7-38. Drain Output Response – Negative Overvoltage
Figure 7-37. Drain Output Response – Positive Overvoltage
60
55
50
45
0
-6
DRAIN
-12
-18
40
35
30
25
20
15
10
5
SOURCE
VSS
-24
SOURCE
-30
50V/s fault ramp
-36
VDD
50V/s fault ramp
-42
-48
-54
-60
DRAIN
0
-5
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
3
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
3
Time(s)
Time(s)
Figure 7-40. Drain Output Recovery – Negative Overvoltage
Figure 7-39. Drain Output Recovery – Positive Overvoltage
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8 Parameter Measurement Information
8.1 On-Resistance
The on-resistance of the TMUX7308F and TMUX7309F is the ohmic resistance across the source (Sx) and drain
(Dx) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol RON is used
to denote on-resistance. Figure 8-1 shows the measurement setup used to measure RON. ΔRON represents the
difference between the RON of any two channels, while RON_FLAT denotes the flatness that is defined as the
difference between the maximum and minimum value of the on-resistance measured over the specified analog
signal range.
Figure 8-1. On-Resistance Measurement Setup
8.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state, which follows:
1. Source off-leakage current IS(OFF): the leakage current flowing into or out of the source pin when the switch
is off.
2. Drain off-leakage current ID(OFF): the leakage current flowing into or out of the drain pin when the switch is
off.
Figure 8-2 shows the setup used to measure both off-leakage currents.
VDD
VSS
VDD
VSS
Is (OFF)
A
SW
SW
SW
SW
S1
S2
S1
S2
ID (OFF)
VS
D
D
A
GND
VD
SW
SW
S8
S8
VD
GND
VS
GND
GND
GND
GND
IS(OFF)
ID(OFF)
Figure 8-2. Off-Leakage Measurement Setup
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8.3 On-Leakage Current
Source on-leakage current (IS(ON)) and drain on-leakage current (ID(ON)) denote the channel leakage currents
when the switch is in the on state. IS(ON) is measured with the drain floating, while ID(ON) is measured with the
source floating. Figure 8-3 shows the circuit used for measuring the on-leakage currents.
VDD
VSS
VDD
VSS
IS(ON)
A
SW
SW
SW
SW
S1
S2
S1
S2
N.C.
ID(ON)
A
D
D
VS
GND
N.C.
SW
SW
VD
S8
S8
GND
VS
VS
GND
GND
GND
GND
IS(ON)
ID(ON)
Figure 8-3. On-Leakage Measurement Setup
8.4 Input and Output Leakage Current Under Overvoltage Fault
If the voltage on any source pin goes above the supplies (VDD or VSS) by one threshold voltage (VT), the
overvoltage protection feature of the TMUX7308F and TMUX7309F is triggered to turn off the switch under
fault, keeping the fault channel in a high-impedance state. IS(FA) and ID(FA) denotes the input and output
leakage current under overvoltage fault conditions, respectively. For ID(FA) the device is disabled to measure
leakage current on the drain pin without being impacted by the 40 kΩ impedance to the fault supply.When the
overvoltage fault occurs, the supply (or supplies) can either be in normal operating condition (Figure 8-4) or
abnormal operating condition (Figure 8-5). During abnormal operating condition, the supply (or supplies) can
either be unpowered (VDD= VSS = 0 V) or floating (VDD= VSS = no connection), and remains within the leakage
performance specifications.
VDD
VSS
IS (FA)
A
N.C.
SW
SW
S1
S2
ID (FA)
A
VS
D
GND
SW
S8
N.C.
VD
GND
GND
IS(FA) / ID(FA)
( |VS| > |VDD + VT| or |VSS - VT| )
Figure 8-4. Measurement Setup for Input and Output Leakage Current under Overvoltage Fault with
Normal Supplies
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N.C.
GND
VDD
VSS
VDD
VSS
IS (FA)
A
N.C.
IS (FA)
A
N.C.
SW
SW
SW
SW
S1
S2
S1
S2
ID (FA)
A
ID (FA)
VS
VS
D
D
A
GND
GND
SW
SW
S8
S8
GND
GND
N.C.
N.C.
GND
GND
Unpowered
(VDD = VSS = GND = 0 V)
Floating
(VDD = VSS = N.C.)
Figure 8-5. Measurement Setup for Input and Output Leakage Current under Overvoltage Fault with
Unpowered or Floating Supplies
8.5 Break-Before-Make Delay
The break-before-make delay is a safety feature of the TMUX7308F and TMUX7309F. The ON switches first
break the connection before the OFF switches make connection. The time delay between the break and the
make is known as break-before-make delay. Figure 8-6 shows the setup used to measure break-before-make
delay, denoted by the symbol tBBM
.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
SW
SW
S1
S2
3 V
D
tr < 20 ns
VA
tf < 20 ns
0 V
CL
RL
GND
GND
SW
SW
S7
S8
GND
VS
0.8 VS
Output
A0
A1
tBBM
1
tBBM 2
VS
EN
0 V
Decoder
tBBM = min ( tBBM 1, tBBM 2)
A2
GND
VEN
VA
GND
GND
GND
Figure 8-6. Break-Before-Make Delay Measurement Setup
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8.6 Enable Delay Time
tON(EN) time is defined as the time taken by the output of the TMUX7308F and TMUX7309F to rise to a 90% final
value after the EN signal has risen to a 50% final value. tOFF(EN) is defined as the time taken by the output of the
TMUX7308F and TMUX7309F to fall to a 10% initial value after the EN signal has fallen to a 50% initial value.
Figure 8-7 shows the setup used to measure the enable delay time.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
SW
SW
S1
S2
3 V
VS
D
tr < 20 ns
tf < 20 ns
50%
50%
VEN
GND
0 V
VS
RL
GND
CL
SW
S8
0.9 VS
tON(EN)
GND
tOFF(EN)
0.1 VS
GND
Output
A0
A1
EN
Decoder
A2
VEN
GND
GND
GND
Figure 8-7. Enable Delay Measurement Setup
8.7 Transition Time
Transition time is defined as the time taken by the output of the device to rise (to 90% of the transition) or fall (to
10% of the transition) after the address signal (Ax) has fallen or risen to 50% of the transition. Figure 8-8 shows
the setup used to measure transition time, denoted by the symbol tTRAN
.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
SW
SW
S1
S2
3 V
0 V
tr < 20 ns
tf < 20 ns
50%
50%
VA
VS
D
GND
RL
GND
0.9 VS
tTRAN
CL
SW
S8
Output
VS
tTRAN
1
2
GND
0.1 VS
GND
tTRAN = max ( tTRAN 1, tTRAN 2)
A0
A1
EN
Decoder
A2
VEN
VA
GND
GND
GND
Figure 8-8. Transition Time Measurement Setup
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8.8 Fault Response Time
Fault response time (tREPONSE) measures the delay between the source voltage exceeding the supply voltage
(VDD or VSS) by 0.5 V and the drain voltage failing to 50% of the maximum output voltage. Figure 8-9 shows the
setup used to measure tRESPONSE
.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
Max positive fault
0 V
VDD
VSS
VDD + 0.5 V
60V/µs
60V/µs
ramp
SW
SW
VS
VS
Sx
ramp
VSS - 0.5 V
0 V
Max negative fault
VS
tRESPONSE (VDD)
VDD
tRESPONSE (VSS)
Output
CL
D/ DX
0 V
All other
source
pins
Output
0 V
Output
Output × 50%
Output × 50%
GND
RL
GND
SW
VSS
GND
tRESPONSE = max ( tRESPONSE(VDD), tRESPONSE(VSS)
)
GND
Figure 8-9. Fault Response Time Measurement Setup
8.9 Fault Recovery Time
Fault recovery time (tRECOVERY) measures the delay between the source voltage falling from overvoltage
condition to below supply voltage (VDD or VSS) plus 0.5 V and the drain voltage rising from 0 V to 50% of
the final output voltage. Figure 8-10 shows the setup used to measure tRECOVERY
.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
0 V
VDD
VSS
VDD + 0.5 V
VSS - 0.5 V
SW
SW
Sx
VS
VS
tRECOVERY (VSS)
0 V
0 V
tRECOVERY (VDD)
VS
Output
CL
D/ DX
All other
source
pins
GND
Output
0 V
Output x 50%
Output × 50%
Output
RL
GND
SW
GND
tRECOVERY = max ( tRECOVERY(VDD), tRECOVERY(VSS)
)
GND
Figure 8-10. Fault Recovery Time Measurement Setup
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8.10 Charge Injection
Charge injection is a measure of the glitch impulse transferred from the logic input to the signal path during logic
pin switching, and is denoted by the symbol QINJ. Figure 8-11 shows the setup used to measure charge injection
from the source to drain.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
SW
SW
S1
S2
Output
VS
D
3 V
VEN
0 V
GND
CL
SW
S8
tr < 20 ns
tf < 20 ns
GND
GND
A0
A1
Output
VS
EN
VOUT
QINJ = CL ×
VOUT
Decoder
A2
VEN
GND
GND
GND
Figure 8-11. Charge-Injection Measurement Setup
8.11 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to
the source pin (Sx) of an off-channel. Figure 8-12 shows the setup used to measure, and the equation used to
calculate off isolation.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Network Analyzer
VS
S1
D
50Ω
VOUT
VSIG
50Ω
Sx
50Ω
GND
8176
1BB +OKH=PEKJ = 20 × .KC
8
5
Figure 8-12. Off Isolation Measurement Setup
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8.12 Crosstalk
The following are two types of crosstalk that can be defined for the devices:
1. Intra-channel crosstalk (XTALK(INTRA)): the voltage at the source pin (Sx) of an off-switch input, when a
1-VRMS signal is applied at the source pin of an on-switch input in the same channel, as shown in Figure
8-13.
2. Inter-channel crosstalk (XTALK(INTER)): the voltage at the source pin (Sx) of an on-switch input, when a
1-VRMS signal is applied at the source pin of an on-switch input in a different channel, as shown in Figure
8-14. Inter-channel crosstalk applies only to the TMUX7309F device.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
Network Analyzer
SW
SW
S1/S1X
D/ DX
VOUT
S2/S2X
RS
RL
Other
Sx/ Dx
Pins
50Ω
SW
VS
N.C.
Ax, EN
GND
VAX
VEN
8176
+JPN= F ?D=JJAH %NKOOP=HG = 20 × .KC
8
5
Figure 8-13. Intra-channel Crosstalk Measurement Setup
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
Network Analyzer
SW
SxA
DA
Other
SxA Pins
SW
SW
N.C.
N.C.
RS
RL
VOUT
SxB
DB
Other
SxB Pins
SW
50Ω
RL
VS
Ax, EN
GND
VAX
VEN
8176
+JPAN F ?D=JJAH %NKOOP=HG = 20 × .KC
8
5
Figure 8-14. Inter-channel Crosstalk Measurement Setup
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8.13 Bandwidth
Bandwidth (BW) is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to
the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D or Dx) of the TMUX730xF.
Figure 8-15 shows the setup used to measure bandwidth of the switch.
VDD
VSS
0.1 µF
GND
0.1 µF
VDD
VSS
Network Analyzer
GND
SW
SW
SX
N.C.
N.C.
Other
Sx/ Dx
Pins
RS
SW
VOUT
D/ DX
VS
50Ω
Ax, EN
VAX
VEN
GND
8176
$=J@SE@PD = 20 × .KC
8
5
Figure 8-15. Bandwidth Measurement Setup
8.14 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined
as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency
at the multiplexer output. The on-resistance of the TMUX7308F and TMUX7309F varies with the amplitude
of the input signal and results in distortion when the drain pin is connected to a low-impedance load. Total
harmonic distortion plus noise is denoted as THD+N. Figure 8-16 shows the setup used to measure THD+N of
the devices.
VDD
VSS
0.1 µF
GND
0.1 µF
VDD
VSS
Audio Precision
GND
SW
SW
SX
N.C.
N.C.
Other
Sx/ Dx
Pins
RS
SW
VOUT
D/ DX
VS
RL
Ax, EN
GND
VAX
VEN
Figure 8-16. THD+N Measurement Setup
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9 Detailed Description
9.1 Overview
The TMUX7308F and TMUX7309F are a modern complementary metal-oxide semiconductor (CMOS) analog
multiplexers in 8:1 (single ended) and 4:1 (differential) configurations. The devices work well with dual supplies
(±5 V to ±22 V), a single supply (8 V to 44 V), or asymmetric supplies (such as VDD = 15 V, VSS = –5 V). The
devices have an overvoltage protection feature on the source pins under powered and powered-off conditions,
allowing them to be used in harsh industrial environments.
9.2 Functional Block Diagram
VDD
VSS
VDD
VSS
SW
SW
SW
S1
S2
S1A
DA
DB
SW
SW
S4A
S1B
D
SW
SW
S4B
S8
A1
A2
A3
EN
A1
A2
EN
Fault Detection/
Switch Driver/
Logic Decoder
Fault Detection/
Switch Driver/
Logic Decoder
TMUX7308F
TMUX7309F
9.3 Feature Description
9.3.1 Flat On – Resistance
The TMUX7308F and TMUX7309F are designed with a special switch architecture to produce ultra-flat on-
resistance (RON) across most of the switch input operation region. The flat RON response allows the device to
be used in precision sensor applications since the RON is controlled regardless of the signals sampled. The
architecture is implemented without a charge pump so no unwanted noise is produced from the device to affect
sampling accuracy.
9.3.2 Protection Features
The TMUX7308F and TMUX7309F offer a number of protection features to enable robust system
implementations.
9.3.2.1 Input Voltage Tolerance
The maximum voltage that can be applied to any source input pin is +60 V or -60 V, regardless of supply voltage.
This allows the device to handle typical voltage fault conditions in industrial applications. It shall be cautioned
that the device is rated to handle maximum stress of 85 V across different pins, such as the following:
1. Between the source pins and supply rails:
For example, if the device is powered by VDD supply of 20 V, then the maximum negative signal level on any
source pin is –60 V to maintain the 60 V maximum rating on any source pin. If the device is powered by VDD
supply of 40 V, then the maximum negative signal level on any source pin is reduced to –45 V to maintain
the 85 V maximum rating across the source pin and the supply.
2. Between the source pins and one or more drain pins:
For example, if channel S1(A) is ON and the voltage on S1(A) pin is 40 V. In this case, the drain voltage
is also 40 V. The maximum negative voltage on any of the other source pins is –45 V to maintain the 85 V
maximum rating across the source pin and the drain pin.
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9.3.2.2 Powered-Off Protection
When the supplies of TMUX7308F and TMUX7309F are removed (VDD / VSS = 0 V or floating), the source (Sx)
pins of the device remain in the high impedance (Hi-Z) state, and the source (Sx) and drain (Dx) pins of the
device remain within the leakage performance mentioned in the Electrical Specifications. Powered-off protection
minimizes system complexity by removing the need to control power supply sequencing of the system. The
feature prevents errant voltages on the input source pins from reaching the rest of the system and maintains
isolation when the system is powering up. Without powered-off protection, signal on the input source pins can
back-power the supply rails through internal ESD diodes and cause potential damage to the system.For more
information on powered-off protection refer to Eliminate Power Sequencing With Powered-Off Protection Signal
Switches.
The switch remains OFF regardless of whether the VDD and VSS supplies are 0 V or floating. A GND reference
must always be present to ensure proper operation. Source and drain voltage levels of up to ±60 V are blocked
in the powered-off condition.
9.3.2.3 Fail-Safe Logic
Fail-safe logic circuitry allows voltages on the logic control pins to be applied before the supply pins, protecting
the device from potential damage. The switch is specified to be in the OFF state, regardless of the state of the
logic signals. The logic inputs are protected against positive faults of up to +44 V in the powered-off condition,
but do not offer protection against the negative overvoltage condition.
Fail-safe logic also allows the TMUX7308F and TMUX7309F devices to interface with a voltage greater than VDD
during normal operation to add maximum flexibility in system design. For example, with a VDD of = 15 V, the logic
control pins could be connected to +24 V for a logic high signal which allows different types of signals, such as
analog feedback voltages, to be used when controlling the logic inputs. Regardless of the supply voltage, the
logic inputs can be interfaced as high as 44 V.
9.3.2.4 Overvoltage Protection and Detection
The TMUX7308F and TMUX7309F detect overvoltage inputs by comparing the voltage on a source pin (Sx) with
the supplies (VDD and VSS). A signal is considered overvoltage if it exceeds the supply voltages by the threshold
voltage (VT).
When an overvoltage is detected, the switch with the overvoltage automatically turns OFF, and stays OFF
regardless of the logic controls. The source pin becomes high impedance and ensures only small leakage
current flows through the switch and the overvoltage does not appear on the drain. When the overvoltage
channel is selected by the logic control, the drain pin (D or Dx) is pulled to the supply that was exceeded. For
example, if the source voltage exceeds VDD, the drain output is pulled to VDD. If the source voltage exceeds
VSS, the drain output is pulled to VSS. The pull-up impedance is approximately 40 kΩ, and as a result, the drain
current is limited to roughly 1 mA during a shorted load (to GND) condition.
Figure 9-1 shows a detailed view of the how the pullup/down controls the output state of the drain pin under a
fault scenario.
VDD
Ax
Sx
Logic &
Fault
Detection
40 k
40 k
Dx
ESD
Protection
VSS
GND
Figure 9-1. Detailed Functional Diagram
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9.3.2.5 Adjacent Channel Operation During Fault
When the logic pins are set to a channel under a fault, the overvoltage detection will trigger, the switch will open,
and the drain pin will be pulled up/down as described in Section 9.3.2.4. During such an event, all other channels
not under a fault can continue to operate as normal. For example, if S1 voltage exceeds VDD, and the logic pins
are set to S1, the drain output is pulled to VDD. If then the logic pins are changed to set S4, which is not in
overvoltage or undervoltage, the drain will disconnect from the pullup to VDD and the S4 switch will be enabled
and connected to the drain, operating as normal. If the logic pins are switched back to S1, the S4 switch will be
disabled, the drain pin will be pulled up to VDD again, and the switch from S1 to drain will not be enabled until the
overvoltage fault is removed.
9.3.2.6 ESD Protection
All pins on the TMUX7308F and TMUX7309F support HBM ESD protection level up to ±3.5 kV, which helps the
device from getting ESD damages during manufacturing process.
The drain pins (D or Dx) have internal ESD protection diodes to the supplies VDD and VSS, therefore the voltage
at the drain pins must not exceed the supply voltages to prevent excessive diode current. The source pins have
specialized ESD protection that allows the signal voltage to reach ±60 V regardless of supply voltage level.
Exceeding ±60 V on any source input may damage the ESD protection circuitry on the device and cause the
device to malfunction if the damage is excessive.
9.3.2.7 Latch-Up Immunity
Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition
is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains
even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic
damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the
low impedance path.
The TMUX7308F and TMUX7309F devices are constructed on silicon on insulator (SOI) based process where
an oxide layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic
structures from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch
up events due to overvoltage or current injections. The latch-up immunity feature allows the TMUX7308F and
TMUX7309F to be used in harsh environments. For more information on latch-up immunity refer to Using Latch
Up Immune Multiplexers to Help Improve System Reliability.
9.3.2.8 EMC Protection
The TMUX7308F and TMUX7309F are not intended for standalone electromagnetic compatibility (EMC)
protection in industrial applications. There are three common high voltage transient specifications that govern
industrial high voltage transient specification: IEC61000-4-2 (ESD), IEC61000-4-4 (EFT), and IEC61000-4-5
(surge immunity). A transient voltage suppressor (TVS), along with some low-value series current limiting
resistor, are required to prevent source input voltages from going above the rated ±60 V limits.
When selecting a TVS protection device, it is critical to ensure that the maximum working voltage is greater than
both the normal operating range of the input source pins to be protected and any known system common-mode
overvoltage that may be present due to incorrect wiring, loss of power, or short circuit. Figure 9-2 shows one
example of the proper design window when selecting a TVS device.
Region 1 denotes the normal operation region of TMUX7308F and TMUX7309F where the input source voltages
stay below the fault supplies VDD and VSS. Region 2 represents the range of possible persistent DC (or long
duration AC overvoltage fault) presented on the source input pins. Region 3 represents the margin between
any known DC overvoltage level and the absolute maximum rating of the TMUX7308F and TMUX7309F. The
selected TVS breakdown voltage must be less than the absolute maximum rating of the TMUX730xF but
greater than any known possible persistent DC or long duration AC overvoltage fault to avoid triggering the
TVS inadvertently. Region 4 represents the margin that system designers must impose when selecting the TVS
protection device to prevent accidental triggering of the ESD cells of the TMUX7308F and TMUX7309F devices.
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Internal ESD
Trigger Voltage
4
3
2
Device Absolute
Max Rating
TVS
Breakdown
Voltage
System
Overvoltage
Overvoltage
Protection Window
Positive Supply
VDD
0 V
1
Normal Operation
Negative Supply
VSS
2
3
4
System
Overvoltage
Overvoltage
Protection Window
TVS
Breakdown
Voltage
Device Absolute
Max Rating
Internal ESD
Trigger Voltage
Figure 9-2. System Operation Regions and Proper Region of Selecting a TVS Protection Device
9.3.3 Bidirectional Operation
The TMUX7308F and TMUX7309F conducts equally well from source (Sx) to drain (D or Dx) or from drain (D or
Dx) to source (Sx). Each signal path has very similar characteristics in both directions. However, take note that
the overvoltage protection is implemented only on the source (Sx) side. The voltage on the drain is only allowed
to swing between VDD and VSS and no overvoltage protection is available on the drain side.
The flatest on-resistance region extends from VSS to roughly 3 V below VDD. Once the signal is within 3 V of VDD
the on-resistance will expoentially increase and may impact desired signal transmission.
9.3.4 1.8 V Logic Compatible Inputs
The TMUX7308F and TMUX7309F devices have 1.8 V logic compatible control for all logic control inputs. 1.8
V logic level inputs allows the TMUX7308F and TMUX7309F to interface with processors that have lower logic
I/O rails and eliminates the need for an external translator, which saves both space and BOM cost. For more
information on 1.8 V logic implementations refer to Simplifying Design with 1.8 V logic Muxes and Switches.
9.3.5 Integrated Pull-Down Resistor on Logic Pins
The TMUX7308F and TMUX7309F have internal weak pull-down resistors to GND to ensure the logic pins are
not left floating. The value of this pull-down resistor is approximately 4 MΩ, but is clamped to about 1 µA at
higher voltages. This feature integrates up to four external components and reduces system size and cost.
9.4 Device Functional Modes
The TMUX7308F and TMUX7309F offers two modes of operation (Normal mode and Fault mode) depending on
whether any of the input pins experience an overvoltage condition.
9.4.1 Normal Mode
In Normal mode operation, signals of up to VDD and VSS can be passed through the switch from source (Sx) to
drain (D or Dx) or from drain (D or Dx) to source (Sx). The address (Ax) pins and the enable (EN) pin determines
which switch path to turn on, according to Table 9-1 and Table 9-2. The following conditions must be satisfied for
the switch to stay in the ON condition:
•
The difference between the primary supplies (VDD – VSS) must be greater than or equal to 8 V. With a
minimum VDD of 5 V.
•
•
The input signals on the source (Sx) or the drain (D or Dx) must be be between VDD+ VT and VSS – VT.
The logic control (Ax and EN) must have selected the switch.
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9.4.2 Fault Mode
The TMUX7308F and TMUX7309F enter into the Fault mode when any of the input signals on the source
(Sx) pins exceed VDD or VSS by a threshold voltage VT. Under the overvoltage condition, the switch input
experiencing the fault automatically turns OFF regardless of the logic status, and the source pin becomes high
impedance with a negligible amount of leakage current flowing through the switch. When the fault channel is
selected by the logic control, the drain pin (D or Dx) is pulled to the supply that was exceeded through a 40 kΩ
internal resistor.
The overvoltage protection is provided only for the source (Sx) input pins. The drain (D or Dx) pin, if used as a
signal input, must stay in between VDD and VSS at all times since no overvoltage protection is implemented on
the drain pin.
9.4.3 Truth Tables
Table 9-1 shows the truth tables for the TMUX7308F.
Table 9-1. TMUX7308F Truth Table
Selected Source Connected to Drain Pin
EN
A2
A1
A0
(D)
0
X(1)
X(1)
X(1)
All sources are off (HI-Z)
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
S1
S2
S3
S4
S5
S6
S7
S8
(1) "X" means "do not care."
Table 9-2 shows the truth tables for the TMUX7309F.
Table 9-2. TMUX7309F Truth Table
EN
A1
A0
Selected Source Connected to Drain Pins (DA, DB)
0
X(1)
X(1)
All sources are off (HI-Z)
1
1
1
1
0
0
1
1
0
1
0
1
S1A and S1B
S2A and S2B
S3A and S3B
S4A and S4B
(1) "X" means "do not care."
If unused, Ax pins must be tied to GND in order to ensure the device does not consume additional current as
highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (Sx or Dx) should be
connected to GND.
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The TMUX7308F and TMUX7309F are part of the fault protected switches and multiplexers family of devices.
The abilty to protect downstream components from overvoltage events up to ±60 V makes these switches and
multiplexers suitable for harsh environments.
10.2 Typical Application
In analog input programmable logic controllers (PLC) a multiplexer is often used to switch multiple sensors
to a single ADC. By using a multiplexer, the number of components in the system can be reduced to save
system cost and size. In a PLC module a ±10 V input signal range is common for interfacing with external field
transmitters and sensors; however, there are a number of fault cases that may occur that can be damaging
to many of the integrated circuits. Such fault conditions may include, but are not limited to, human error from
wiring connections incorrectly, component failure or wire shorts, electromagnetic interference (EMI) or transient
disturbances, and so forth.
Supply
Power Module
GND
VDD
VSS
PLC Analog
Input Module
Bridge Sensor
TMUX7308F
S1
S2
S3
S4
S5
S6
S7
S8
5V
REF5025
Thermocouple
Current Sensing
D
Gain / Filter
Network
Fault
Protected
Mux Inputs
Signal
Processing
ISO77xx
ADS125H01
Photo
LED
A2
A1
V
Detector
A0
GND
1.8V Logic
Signals
Optical Sensor
Sensors
Figure 10-1. Typical Application
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10.2.1 Design Requirements
Table 10-1. Design Parameters
PARAMETER
VALUE
+15 V
-15 V
Positive supply (VDD) mux and ADC
Negative supply (VSS) mux and ADC
Power board supply voltage
Input / output signal range non-faulted
Overvoltage protection levels
24 V
-15 V to 15 V
-60 V to 60 V
Control logic thresholds
Temperature range
1.8 V compatible, up to 44 V
-40°C to +125°C
10.2.2 Detailed Design Procedure
The image shows the case where an incorrect wiring condition occurred and one of the input connectors has
been shorted to the power board supply voltage. If the board supply voltage is higher than the power supply of
the multiplexer, then the TMUX7308F or TMUX7309F will disconnect the source input from passing the signal to
protect the downstream ADC. The drain pin of the mux will be pulled up to the supply voltage VDD through a 40
kΩ resistor to allow the ADC to determine a fault condition has occurred.
10.2.3 Application Curves
The example application utilizes the fault protection of the TMUX7308F or TMUX7309F to protect downstream
components from potential miswiring conditions from the Power Module board. Figure 10-2 shows an example
of positive overvoltage fault response with a fast fault ramp rate of 50 V/µs. Figure 10-3 shows the extremely
flat on-resistance across source voltage while operating within a common signal range of ±10 V. These features
make the TMUX7308F or TMUX7309F an ideal solution for factory automation applications that may face
various fault conditions but also require excellent linearity and low distortion.
25
22.5
20
240
230
220
210
200
190
180
170
160
VDD = 13.5 V, VSS = -13.5 V
VDD = 15 V, VSS = -15 V
VDD = 16.5 V, VSS = -16.5 V
VDD = 18 V, VSS = -18 V
VDD = 20 V, VSS = -20 V
VDD = 22 V, VSS = -22 V
SOURCE
VDD
50V/s fault ramp
17.5
15
12.5
10
7.5
5
DRAIN
2.5
0
-2.5
-5
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
3
-10
-6
-2
2
6
10
Time(s)
VS or VD - Source or Drain Voltage (V)
Figure 10-2. Positive Overvoltage Response
Figure 10-3. RON Flatness in Non-Fault Region
11 Power Supply Recommendations
The TMUX7308F and TMUX7309F operate across a wide supply range of ±5 V to ±22 V (8 V to 44 V in
single-supply mode). They also perform well with asymmetrical supplies such as VDD = 15 V and VSS= –5 V. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 1 µF to 10 µF at both the VDD
and VSS pins to ground. Always ensure the ground (GND) connection is established before supplies are ramped.
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12 Layout
12.1 Layout Guidelines
The image below illustrates an example of a PCB layout with the TMUX7308F and TMUX7309F. Some key
considerations are:
•
For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and VSS to
GND. We recommend a 0.1 µF and 1 µF capacitor, placing the lowest value capacitor as close to the pin as
possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.
Keep the input lines as short as possible.
Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
•
•
•
12.2 Layout Example
Via to
ground plane
Via to
ground plane
A0
EN
VSS
A1
A2
Wide (low inductance)
trace for power
C
Wide (low inductance)
trace for power
C
GND
VDD
S5
Via to
ground plane
S1
S2
S3
S4
D
TMUX7308F
S6
S7
S8
Figure 12-1. TMUX7308FPW Layout Example
Via to
Via to
ground plane
ground plane
A0
EN
VSS
A1
Wide (low inductance)
trace for power
Wide (low inductance)
trace for power
C
C
GND
VDD
Via to
ground plane
S1B
S1A
S2A
S3A
S4A
DA
S2B
S3B
S4B
DB
TMUX7309F
Figure 12-2. TMUX7309FPW Layout Example
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Wide (low inductance)
trace for power
Wide (low inductance)
trace for power
GND
VDD
S5
VSS
S1
S2
S6
S3
Via to ground plane
Figure 12-3. TMUX7308FQFN Layout Example
Wide (low inductance)
trace for power
Wide (low inductance)
trace for power
VDD
S1B
S2B
S3B
VSS
S1A
S2A
S3A
Via to ground plane
Figure 12-4. TMUX7309FQFN Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
•
•
Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
Texas Instruments, Improving Analog Input Modules Reliability Using Fault Protected Multiplexers application
report
•
•
Texas Instruments, Multiplexers and Signal Switches Glossary application report
Texas Instruments, Protection Against Overvoltage Events, Miswiring, and Common Mode Voltages
application report
•
Texas Instruments, Using Latch-Up Immune Multiplexers to Help Improve System Reliability application
report
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTMUX7308FPWR
PTMUX7308FRRPR
TMUX7308FRRPR
ACTIVE
ACTIVE
ACTIVE
TSSOP
WQFN
WQFN
PW
RRP
RRP
16
16
16
2000
3000
TBD
TBD
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
Call TI
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
TMUX
7308F
TMUX7309FRRPR
ACTIVE
WQFN
RRP
16
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TMUX
7309F
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Dec-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX7308FRRPR
TMUX7309FRRPR
WQFN
WQFN
RRP
RRP
16
16
3000
3000
330.0
330.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMUX7308FRRPR
TMUX7309FRRPR
WQFN
WQFN
RRP
RRP
16
16
3000
3000
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
RRP0016A
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
4.1
3.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.95
SYMM
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
4
9
2X 1.95
SYMM
17
2.6 0.1
12X 0.65
1
12
0.35
16X
PIN 1 ID
0.25
13
16
0.1
C A B
0.45
0.35
0.05
16X
4224816/A 02/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RRP0016A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.6)
SYMM
SEE SOLDER MASK
DETAIL
13
16
16X (0.6)
1
12
16X (0.3)
17
SYMM
12X (0.65)
(3.8)
(1.05)
4
9
(R0.05) TYP
(
0.2) TYP
VIA
5
8
(1.05)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224816/A 02/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RRP0016A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.675) TYP
13
16
16X (0.6)
1
12
16X (0.3)
(0.675) TYP
(3.8)
17
SYMM
12X (0.65)
4X ( 1.15)
9
4
(R0.05) TYP
8
5
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 17
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224816/A 02/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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