TPA2010D1YEFR [TI]
2.5-W MONO FILTER-FREE CLASS-D AUDIO POWER AMPLIFIER; 2.5W单声道无滤波器D类音频功率放大器
| 型号： | TPA2010D1YEFR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.5-W MONO FILTER-FREE CLASS-D AUDIO POWER AMPLIFIER |
| 文件： | 总23页 (文件大小：592K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPA2010D1
www.ti.com
SLOS417B–OCTOBER 2003–REVISED JULY 2006
2.5-W MONO FILTER-FREE CLASS-D AUDIO POWER AMPLIFIER
FEATURES
APPLICATIONS
•
Ideal for Wireless or Cellular Handsets and
PDAs
•
Maximum Battery Life and Minimum Heat
– Efficiency With an 8-Ω Speaker:
• 88% at 400 mW
DESCRIPTION
• 80% at 100 mW
The TPA2010D1 (sometimes referred to as
– 2.8-mA Quiescent Current
– 0.5-µA Shutdown Current
Only Three External Components
TPA2010) is
a 2.5-W high efficiency filter-free
class-D audio power amplifier (class-D amp) in a
1,45 mm × 1,45 mm wafer chip scale package
(WCSP) that requires only three external
components.
•
– Optimized PWM Output Stage Eliminates
LC Output Filter
Features like 88% efficiency, –75-dB PSRR,
improved RF-rectification immunity, and 8 mm2 total
PCB area make the TPA2010D1 (TPA2010) class-D
amp ideal for cellular handsets. A fast start-up time
of 1 ms with minimal pop makes the TPA2010D1
(TPA2010) ideal for PDA applications.
– Internally Generated 250-kHz Switching
Frequency Eliminates Capacitor and
Resistor
– Improved PSRR (–75 dB) and Wide Supply
Voltage (2.5 V to 5.5 V) Eliminates Need for
a Voltage Regulator
In cellular handsets, the earpiece, speaker phone,
and melody ringer can each be driven by the
TPA2010D1. The TPA2010D1 allows independent
gain while summing signals from seperate sources,
and has a low 36 µV noise floor, A-weighted.
– Fully Differential Design Reduces RF
Rectification and Eliminates Bypass
Capacitor
– Improved CMRR Eliminates Two Input
Coupling Capacitors
•
Wafer Chip Scale Packaging (WCSP)
– NanoFree™ Lead-Free (YZF)
– NanoStar™ SnPb (YEF)
APPLICATION CIRCUIT
9-BALL
WAFER CHIP SCALE
YZF, YEF PACKAGES
To Battery
TPA2010D1 DIMENSIONS
(TOP VIEW OF PCB)
Internal
V
DD
Oscillator
C
S
R
R
I
+
-
IN-
IN+
A1
GND
A2
V
O-
V
O+
PWM
H-
_
+
A3
Differential
Input
Bridge
V
O-
V
DD
PV
DD
GND
B3
I
1,55 mm
1,40 mm
IN+
B1
B2
GND
Bias
IN-
C1
SHUTDOWN
C2
V
O+
SHUTDOWN
Circuitry
C3
TPA2010D1
1,55 mm
1,40 mm
Note: Pin A1 is marked with a “0” for
Pb-free (YZF) and a “1” for SnPb (YEF).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree, NanoStar are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPA2010D1
www.ti.com
SLOS417B–OCTOBER 2003–REVISED JULY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
PACKAGE
PART NUMBER
SYMBOL
AJZ
(1)
Wafer chip scale package (YEF)
TPA2010D1YEF
TPA2010D1YZF
–40°C to 85°C
(1)
Wafer chip scale packaging – Lead free (YZF)
AKO
(1) The YEF and YZF packages are only available taped and reeled. To order add the suffix R to the end of the part number for a reel of
3000, or add the suffix T to the end of the part number for a reel of 250 (e.g. TPA2010D1YEFR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
TPA2010D1
In active mode
–0.3 V to 6 V
–0.3 V to 7 V
VDD
VI
Supply voltage
In SHUTDOWN mode
Input voltage
–0.3 V to VDD + 0.3 V
See Dissipation Rating Table
–40°C to 85°C
Continuous total power dissipation
Operating free-air temperature
Operating junction temperature
Storage temperature
TA
TJ
–40°C to 125°C
–65°C to 150°C
260°C
Tstg
YZF
YEF
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
235°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
VDD Supply voltage
2.5
1.3
0
5.5
VDD
0.35
V
V
VIH
VIL
RI
High-level input voltage
SHUTDOWN
Low-level input voltage
Input resistor
SHUTDOWN
V
Gain ≤ 20 V/V (26 dB)
15
kΩ
VDD–0.
8
VIC
TA
Common mode input voltage range VDD = 2.5 V, 5.5 V, CMRR ≤ –49 dB
0.5
V
Operating free-air temperature
–40
85
°C
PACKAGE DISSIPATION RATINGS
T
A ≤ 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
(1)
PACKAGE
DERATING FACTOR
POWER RATING
YEF
YZF
7.8 mW/°C
7.8 mW/°C
780 mW
429 mW
429 mW
312 mW
780 mW
312 mW
(1) Derating factor measure with High K board.
2
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SLOS417B–OCTOBER 2003–REVISED JULY 2006
ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VI = 0 V, AV = 2 V/V, VDD = 2.5 V to 5.5 V
VDD = 2.5 V to 5.5 V
MIN
TYP
1
MAX UNIT
Output offset voltage
(measured differentially)
|VOS
|
25
–55
–49
mV
dB
dB
PSRR
Power supply rejection ratio
–75
–68
VDD = 2.5 V to 5.5 V, VIC = VDD/2 to 0.5 V,
VIC = VDD/2 to VDD –0.8 V
CMRR Common mode rejection ratio
|IIH
|
High-level input current
Low-level input current
VDD = 5.5 V, VI = 5.8 V
VDD = 5.5 V, VI = –0.3 V
VDD = 5.5 V, no load
VDD = 3.6 V, no load
VDD = 2.5 V, no load
V(SHUTDOWN)= 0.35 V, VDD = 2.5 V to 5.5 V
VDD = 2.5 V
100
5
µA
µA
|IIL|
3.4
2.8
2.2
0.5
700
500
400
>1
4.9
I(Q)
Quiescent current
Shutdown current
mA
µA
3.2
2
I(SD)
Static drain-source on-state
resistance
rDS(on)
VDD = 3.6 V
mΩ
VDD = 5.5 V
Output impedance in SHUTDOWN
Switching frequency
V(SHUTDOWN) = 0.4 V
VDD = 2.5 V to 5.5 V
kΩ
f(sw)
200
250
300
kHz
285 kW 300 kW
RI
RI
315 kW
RI
V
V
Gain
VDD = 2.5 V to 5.5 V
Resistance from shutdown to GND
300
kΩ
OPERATING CHARACTERISTICS
TA = 25°C, Gain = 2 V/V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
2.5
UNIT
VDD = 5 V
THD + N = 10%, f = 1 kHz, RL = 4 Ω
THD + N = 1%, f = 1 kHz, RL = 4 Ω
THD + N = 10%, f = 1 kHz, RL = 8 Ω
VDD = 3.6 V
VDD = 2.5 V
VDD = 5 V
1.3
W
0.52
2.08
1.06
0.42
1.45
0.73
0.33
1.19
0.59
0.26
VDD = 3.6 V
VDD = 2.5 V
VDD = 5 V
W
W
W
PO
Output power
VDD = 3.6 V
VDD = 2.5 V
VDD = 5 V
THD + N = 1%, f = 1 kHz, RL = 8 Ω
VDD = 3.6 V
VDD = 2.5 V
VDD = 5 V, PO = 1 W, RL = 8 Ω, f = 1 kHz
0.18%
0.19%
0.20%
Total harmonic distortion plus
noise
THD+N
kSVR
VDD = 3.6 V, PO = 0.5 W, RL = 8 Ω, f = 1 kHz
VDD = 2.5 V, PO = 200 mW, RL = 8 Ω, f = 1 kHz
f = 217 Hz,
V(RIPPLE) = 200
mVpp
VDD = 3.6 V, Inputs ac-grounded
with Ci = 2 µF
Supply ripple rejection ratio
–67
dB
SNR
Vn
Signal-to-noise ratio
Output voltage noise
VDD = 5 V, PO = 1 W, RL = 8 Ω
97
48
dB
No weighting
A weighting
f = 217 Hz
VDD = 3.6 V, f = 20 Hz to 20 kHz,
Inputs ac-grounded with Ci = 2 µF
µVRMS
36
CMRR Common mode rejection ratio VDD = 3.6 V, VIC = 1 Vpp
–63
dB
kΩ
ms
ZI
Input impedance
142
150 158
Start-up time from shutdown
VDD = 3.6 V
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1
3
TPA2010D1
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SLOS417B–OCTOBER 2003–REVISED JULY 2006
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
YEF, YZF
C1
IN–
I
I
Negative differential input
IN+
VDD
VO+
GND
VO-
A1
Positive differential input
Power supply
B1
I
C3
O
I
Positive BTL output
High-current ground
Negative BTL output
Shutdown terminal (active low logic)
Power supply
A2, B3
A3
O
I
SHUTDOWN
PVDD
C2
B2
I
FUNCTIONAL BLOCK DIAGRAM
150 kΩ
*Gain =
*Gain = 2 V/V
V
DD
R
I
B1, B2
V
DD
+
_
Gate
Drive
Deglitch
Logic
150 kΩ
A3
V
C1
A1
C2
IN-
O-
_
_
+
+
_
+
_
+
IN+
C3
V
150 kΩ
+
_
O+
Gate
Drive
Deglitch
Logic
TTL
SD Input
Startup
Protection
Logic
OC
Detect
SHUTDOWN
Buffer
A2, B3
GND
Biases
and
References
Ramp
Generator
300 kΩ
Notes:
150 kΩ
2 x
* Total gain =
R
I
4
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SLOS417B–OCTOBER 2003–REVISED JULY 2006
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
Efficiency
vs Output power
vs Output power
vs Output power
vs Supply voltage
vs Shutdown voltage
vs Supply voltage
vs Load resistance
vs Output power
1, 2
PD
Power dissipation
Supply current
3, 4
5, 6
I(Q)
Quiescent current
Shutdown current
7
I(SD)
8
9
PO
Output power
10, 11
12, 13
THD+N Total harmonic distortion plus noise vs Frequency
vs Common-mode input voltage
vs Frequency
14, 15, 16, 17
18
KSVR
Supply voltage rejection ratio
GSM power supply rejection
Supply voltage rejection ratio
19, 20, 21
vs Time
22
23
24
25
26
vs Frequency
KSVR
vs Common-mode input voltage
vs Frequency
CMRR Common-mode rejection ratio
vs Common-mode input voltage
TEST SET-UP FOR GRAPHS
C
C
TPA2010D1
I
R
R
I
+
IN+
OUT+
+
30 kHz
Measurement
Measurement
Low Pass
Load
I
Output
-
Input
Filter
I
IN-
OUT-
GND
-
V
DD
1 µF
+
-
V
DD
Notes:
(1) C was Shorted for any Common-Mode input voltage measurement
I
(2) A 33-µH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements.
(3) The 30-kHz low-pass filter is required even if the analyzer has an internal low-pass filter. An RC low pass filter (100 Ω, 47 nF) is
used on each output for the data sheet graphs.
5
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SLOS417B–OCTOBER 2003–REVISED JULY 2006
EFFICIENCY
vs
OUTPUT POWER
EFFICIENCY
vs
OUTPUT POWER
POWER DISSIPATION
vs
OUTPUT POWER
1.4
1.2
100
90
90
80
70
60
50
Class-AB 5 V, 4 Ω
V
= 5 V,
DD
L
V
R
= 5 V,
= 8 Ω, 33 µH
DD
R
= 4 Ω,
80
70
60
50
40
30
20
10
V
= 3.6 V,
33 µH
DD
L
L
V
R
= 2.5 V,
= 8 Ω, 33 µH
R
= 4 Ω, 33 µH
1
0.8
0.6
0.4
0.2
0
DD
L
V
R
= 2.5 V,
DD
= 4 Ω, 33 µH
Class-AB 5 V, 8 Ω
L
40
30
20
10
Class AB.
= 5 V,
Class AB.
= 5 V,
V
R
DD
= 4 Ω
V
= 5 V, R = 4 Ω,
L
DD
L
V
R
DD
= 8 Ω
L
V
=
5 V, R = 8 Ω
DD
L
0
0
0.2 0.4 0.6 0.8
1.2 1.4 1.6 1.8
0
1
2
1
0
0.4
0.6
0.8
1.2
1.2
5.5
0.2
0
0
4
0.5
1
1.5
2
2.5
P
− Output Power − W
P
− Output Power − W
O
P
− Output Power − W
O
O
Figure 1.
Figure 2.
Figure 3.
POWER DISSIPATION
vs
OUTPUT POWER
SUPPLY CURRENT
vs
OUTPUT POWER
SUPPLY CURRENT
vs
OUTPUT POWER
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
600
300
R
= 8 Ω, 33 µH
R
= 4 Ω, 33 µH
L
L
250
200
150
100
50
V
= 3.6 V
500
400
DD
Class-AB 3.6 V, 4 Ω
V
=
3.6 V
DD
V
=
2.5 V
DD
Class-AB 3.6 V, 8 Ω
300
200
V
=
3.6 V, R = 4 Ω
DD
L
V
= 2.5 V
0.8
DD
100
0
V
= 5 V,
DD
V
= 3.6 V,
V
= 5 V
DD
DD
R
L
= 8 Ω, 33 µH
0
0.2 0.4
0.6
1.2
1.4
1
0
0.2
0.4
0.6
0.8
1
0
0.5
1
1.5
2
2.5
P
− Output Power − W
O
P
− Output Power − W
P
− Output Power − W
O
O
Figure 4.
Figure 5.
Figure 6.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
SHUTDOWN VOLTAGE
OUTPUT POWER
vs
LOAD RESISTANCE
3
2
5
4.5
4
P
at 10% THD
Gain = 2 V/V
f = 1 kHz
O
2.5
1.5
1
V
DD = 5 V
R
= 8 Ω, (resistive)
L
2
V
= 5 V
DD
R
L
= 8 Ω,
33 µH
V
DD = 3.6 V
1.5
3.5
3
V
= 3.6 V
DD
V
1
DD = 2.5 V
V
= 2.5 V
DD
0.5
0
2.5
0.5
No Load
2
0
8
12
16
20
24
28
32
0
0.1
0.2
0.3
0.4
0.5
2.5
3
3.5
4
4.5
5
Shutdown Voltage − V
R
L
− Load Resistance − Ω
V
− Supply Voltage − V
DD
Figure 7.
Figure 8.
Figure 9.
6
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SLOS417B–OCTOBER 2003–REVISED JULY 2006
TOTAL HARMONIC DISTORTION +
OUTPUT POWER
vs
LOAD RESISTANCE
OUTPUT POWER
vs
SUPPLY VOLTAGE
NOISE
vs
OUTPUT POWER
3
2.5
2
2.5
20
Gain = 2 V/V
f = 1 kHz
P
at 1% THD
O
R
= 4 Ω,
L
Gain = 2 V/V
f = 1 kHz
f = 1 kHz,
Gain = 2 V/V
10
5
2
1.5
1
V
R
L
= 4 Ω, 10% THD
DD = 5 V
2.5 V
R
L
= 4 Ω, 1% THD
3 V
2
1
V
DD = 3.6 V
1.5
1
3.6 V
5 V
V
DD = 2.5 V
0.5
0.5
0
0.5
0
R
= 8 Ω,10% THD
L
0.2
0.1
R
L
= 8 Ω,1% THD
2.5
3
3.5
4
4.5
5
4
8
12
16
20
24
28
32
20m 50m 100m 200m 500m
1
2
3
V
− Supply Voltage − V
R
L
− Load Resistance − Ω
CC
P
− Output Power − W
O
Figure 10.
Figure 11.
Figure 12.
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
NOISE
vs
NOISE
vs
NOISE
vs
OUTPUT POWER
FREQUENCY
FREQUENCY
20
10
5
10
5
R
= 8 Ω,
L
V
= 3.6 V
10
5
DD
C = 2 µF
L
2.5 V
V
= 5 V
P = 25 mW
O
f = 1 kHz,
Gain = 2 V/V
DD
C = 2 µF
L
I
R
= 8 Ω
I
P
= 50 mW
O
R
= 8 Ω
2
1
Gain = 2 V/V
Gain = 2 V/V
3 V
P
= 125 mW
2
1
O
3.6 V
5 V
P = 250 mW
O
0.5
2
1
P
= 500 mW
O
0.5
0.2
0.1
P
= 1W
O
0.2
0.1
0.5
0.05
0.05
0.02
0.01
0.2
0.1
0.02
0.01
0.005
5m 10m 20m 50m 100m 200m 500m 1
2
20
50 100 200 500 1k 2k
5k 10k 20k
20
50 100 200 500 1k 2k
5k 10k 20k
P
− Output Power − W
O
f − Frequency − Hz
f − Frequency − Hz
Figure 13.
Figure 14.
Figure 15.
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
NOISE
vs
NOISE
vs
NOISE
vs
FREQUENCY
FREQUENCY
COMMON MODE INPUT VOLTAGE
10
5
10
5
10
PO = 250 mW
V
= 2.5 V
DD
C = 2 µF
L
f = 1 kHz
= 200 mW
P
= 15 mW
O
C = 2 µF
I
L
I
P
O
R
= 4 Ω
R
= 8 Ω
Gain = 2 V/V
Gain = 2 V/V
2
1
2
V
= 3.6 V
DD
P
= 75 mW
O
1
V
= 3 V
DD
V
= 2.5 V
DD
0.5
0.5
P
= 200 mW
O
1
0.2
0.2
0.1
V
= 2.5 V
DD
V
= 5 V
DD
0.1
0.05
0.05
0.02
0.01
0.02
0.01
V
= 5 V
DD
V
= 4 V
V
= 3.6 V
DD
DD
0.1
20
50 100 200 500 1k 2k
5k 10k 20k
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
20
50 100 200 500
10k 20k
5k
1k 2k
f − Frequency − Hz
f − Frequency − Hz
V
− Common Mode Input Voltage − V
IC
Figure 16.
Figure 17.
Figure 18.
7
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SLOS417B–OCTOBER 2003–REVISED JULY 2006
SUPPLY RIPPLE REJECTION RATIO
SUPPLY RIPPLE REJECTION RATIO
SUPPLY RIPPLE REJECTION RATIO
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
−30
−30
−30
Inputs ac-grounded
C = 2 µF
Inputs ac-grounded
Inputs floating
= 8 Ω
I
R
C = 2 µF
I
L
R
L
= 4 Ω
L
R
= 8 Ω
−40
−40
−50
−60
−70
−80
−90
−40
−50
−60
−70
−80
−90
Gain = 2 V/V
Gain = 2 V/V
V
= 2.5 V
−50
−60
−70
DD
V
= 2. 5 V
DD
V
= 3.6 V
DD
V
= 5 V
DD
V
= 3.6 V
DD
V
= 3.6 V
1 k
DD
−80
−90
V
= 5 V
DD
V
= 5 V
DD
V
= 2.5 V
DD
20
100
10 k20 k
20
100
1 k
10 k20 k
20
100
1 k
10 k 20 k
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 19.
Figure 20.
GSM POWER SUPPLY REJECTION
GSM POWER SUPPLY REJECTION
vs
vs
TIME
FREQUENCY
0
C1 − High
3.6 V
−50
V
DD
200 mV/div
C1 − Amp
512 mV
−100
0
V
Shown in Figure 22
−150
DD
C1 − Duty
12%
C = 2 µF,
Inputs ac-grounded
Gain = 2V/V
I
−50
V
OUT
20 mV/div
−100
−150
0
400
800
1200
1600
2000
t − Time − 2 ms/div
f − Frequency − Hz
Figure 22.
Figure 23.
SUPPLY RIPPLE REJECTION RATIO
vs
DC COMMON MODE VOLTAGE
COMMON-MODE REJECTION RATIO
COMMON-MODE REJECTION RATIO
vs
COMMON-MODE INPUT VOLTAGE
vs
FREQUENCY
0
0
−50
−55
−60
−65
−70
−75
V
= 200 mV
−10
IC
L
PP
R
= 8 Ω
−10
Gain = 2 V/V
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
−30
−40
−50
−60
V
= 3.6 V
DD
V
= 2.5 V
DD
V
= 3.6 V
DD
V
= 3.6 V
DD
V
= 2. 5 V
DD
V
= 5 V
DD
V
= 5 V,
DD
Gain = 2
−70
−80
0
1
2
3
4
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
20
100
1 k
10 k 20 k
V
− Common Mode Input Voltage − V
IC
f − Frequency − Hz
DC Common Mode Voltage − V
Figure 24.
Figure 25.
Figure 26.
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APPLICATION INFORMATION
FULLY DIFFERENTIAL AMPLIFIER
The TPA2010D1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier
consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that the
amplifier outputs a differential voltage on the output that is equal to the differential input times the gain. The
common-mode feedback ensures that the common-mode voltage at the output is biased around VDD/2
regardless of the common-mode voltage at the input. The fully differential TPA2010D1 can still be used with a
single-ended input; however, the TPA2010D1 should be used with differential inputs when in a noisy
environment, like a wireless handset, to ensure maximum noise rejection.
Advantages of Fully DIfferential Amplifiers
•
Input-coupling capacitors not required:
– The fully differential amplifier allows the inputs to be biased at voltage other than mid-supply. For example,
if a codec has a midsupply lower than the midsupply of the TPA2010D1, the common-mode feedback
circuit will adjust, and the TPA2010D1 outputs will still be biased at midsupply of the TPA2010D1. The
inputs of the TPA2010D1 can be biased from 0.5 V to VDD– 0.8 V. If the inputs are biased outside of that
range, input-coupling capacitors are required.
•
•
Midsupply bypass capacitor, C(BYPASS), not required:
– The fully differential amplifier does not require a bypass capacitor. This is because any shift in the
midsupply affects both positive and negative channels equally and cancels at the differential output.
Better RF-immunity:
– GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. The
transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signal
much better than the typical audio amplifier.
COMPONENT SELECTION
Figure 27 shows the TPA2010D1 typical schematic with differential inputs and Figure 28 shows the TPA2010D1
with differential inputs and input capacitors, and Figure 29 shows the TPA2010D1 with single-ended inputs.
Differential inputs should be used whenever possible because the single-ended inputs are much more
susceptible to noise.
Table 1. Typical Component Values
REF DES
RI
VALUE
EIA SIZE
0402
MANUFACTURER
Panasonic
Murata
PART NUMBER
ERJ2RHD154V
150 kΩ (±0.5%)
1 µF (+22%, -80%)
3.3 nF (±10%)
CS
CI(1)
0402
GRP155F50J105Z
GRP033B10J332K
0201
Murata
(1) CI is only needed for single-ended input or if VICM is not between 0.5 V and VDD– 0.8 V. CI = 3.3 nF
(with RI = 150 kΩ) gives a high-pass corner frequency of 321 Hz.
Input Resistors (RI)
The input resistors (RI) set the gain of the amplifier according to Equation 1.
2 x 150 kW
V
V
ǒ Ǔ
Gain +
R
I
(1)
Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic
distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or
better to keep the performance optimized. Matching is more important than overall tolerance. Resistor arrays
with 1% matching can be used with a tolerance greater than 1%.
Place the input resistors very close to the TPA2010D1 to limit noise injection on the high-impedance nodes.
For optimal performance the gain should be set to 2 V/V or lower. Lower gain allows the TPA2010D1 to operate
at its best, and keeps a high voltage at the input making the inputs less susceptible to noise.
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Decoupling Capacitor (CS)
The TPA2010D1 is a high-performance class-D audio amplifier that requires adequate power supply decoupling
to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients,
spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1
µF, placed as close as possible to the device VDD lead works best. Placing this decoupling capacitor close to the
TPA2010D1 is very important for the efficiency of the class-D amplifier, because any resistance or inductance in
the trace between the device and the capacitor can cause a loss in efficiency. For filtering lower-frequency noise
signals, a 10 µF or greater capacitor placed near the audio power amplifier would also help, but it is not required
in most applications because of the high PSRR of this device.
Input Capacitors (CI)
The TPA2010D1 does not require input coupling capacitors if the design uses a differential source that is biased
from 0.5 V to VDD– 0.8 V (shown in Figure 27). If the input signal is not biased within the recommended
common-mode input range, if needing to use the input as a high pass filter (shown in Figure 28), or if using a
single-ended source (shown in Figure 29), input coupling capacitors are required.
The input capacitors and input resistors form a high-pass filter with the corner frequency, fc, determined in
Equation 2.
1
f +
c
ǒ
Ǔ
2p R C
I I
(2)
The value of the input capacitor is important to consider as it directly affects the bass (low frequency)
performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the
corner frequency can be set to block low frequencies in this application.
Equation 3 is reconfigured to solve for the input coupling capacitance.
1
C +
I
ǒ
cǓ
2p R f
I
(3)
If the corner frequency is within the audio band, the capacitors should have a tolerance of ±10% or better,
because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below.
For a flat low-frequency response, use large input coupling capacitors (1 µF). However, in a GSM phone the
ground signal is fluctuating at 217 Hz, but the signal from the codec does not have the same 217 Hz fluctuation.
The difference between the two signals is amplified, sent to the speaker, and heard as a 217 Hz hum.
To Battery
Internal
V
DD
Oscillator
C
S
R
I
I
+
-
IN-
V
O+
PWM
H-
_
+
Bridge
Differential
Input
V
O-
R
IN+
GND
Bias
Circuitry
SHUTDOWN
TPA2010D1
Filter-Free Class D
Figure 27. Typical TPA2010D1 Application Schematic With Differential Input for a Wireless Phone
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To Battery
Internal
V
DD
Oscillator
C
S
C
C
I
R
R
I
IN-
V
O+
PWM
H-
Bridge
_
+
Differential
Input
V
O-
I
I
IN+
GND
Bias
Circuitry
SHUTDOWN
TPA2010D1
Filter-Free Class D
Figure 28. TPA2010D1 Application Schematic With Differential Input and Input Capacitors
To Battery
Internal
V
DD
Oscillator
C
S
C
I
R
R
I
IN-
Single-ended
Input
V
O+
PWM
H-
Bridge
_
+
V
O-
I
IN+
C
I
GND
Bias
Circuitry
SHUTDOWN
TPA2010D1
Filter-Free Class D
Figure 29. TPA2010D1 Application Schematic With Single-Ended Input
SUMMING INPUT SIGNALS WITH THE TPA2010D1
Most wireless phones or PDAs need to sum signals at the audio power amplifier or just have two signal sources
that need separate gain. The TPA2010D1 makes it easy to sum signals or use separate signal sources with
different gains. Many phones now use the same speaker for the earpiece and ringer, where the wireless phone
would require a much lower gain for the phone earpiece than for the ringer. PDAs and phones that have stereo
headphones require summing of the right and left channels to output the stereo signal to the mono speaker.
Summing Two Differential Input Signals
Two extra resistors are needed for summing differential signals (a total of 5 components). The gain for each
input source can be set independently (see Equation 4 and Equation 5, and Figure 30).
V
O
I1
2 x 150 kW
V
V
ǒ Ǔ
Gain 1 +
+
V
R
I1
(4)
(5)
V
V
O
I2
2 x 150 kW
V
V
ǒ Ǔ
Gain 2 +
+
R
I2
If summing left and right inputs with a gain of 1 V/V, use RI1 = RI2 = 300 kΩ.
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If summing a ring tone and a phone signal, set the ring-tone gain to Gain 2 = 2 V/V, and the phone gain to gain
1 = 0.1 V/V. The resistor values would be. . .
RI1 = 3 MΩ, and = RI2 = 150 kΩ.
R
I1
+
-
Differential
Input 1
R
I1
To Battery
Internal
V
DD
Oscillator
C
S
R
R
I2
+
IN-
V
O+
PWM
H-
Bridge
_
+
Differential
Input 2
V
O-
I2
-
IN+
GND
Bias
Circuitry
SHUTDOWN
Filter-Free Class D
Figure 30. Application Schematic With TPA2010D1 Summing Two Differential Inputs
Summing a Differential Input Signal and a Single-Ended Input Signal
Figure 31 shows how to sum a differential input signal and a single-ended input signal. Ground noise can couple
in through IN+ with this method. It is better to use differential inputs. The corner frequency of the single-ended
input is set by CI2, shown in Equation 8. To assure that each input is balanced, the single-ended input must be
driven by a low-impedance source even if the input is not in use
V
O
I1
2 x 150 kW
V
V
ǒ Ǔ
Gain 1 +
+
V
R
I1
(6)
(7)
(8)
V
V
O
I2
1
2 x 150 kW
V
V
ǒ Ǔ
Gain 2 +
+
R
I2
+ ǒ2p R c2Ǔ
C
I2
f
I2
If summing a ring tone and a phone signal, the phone signal should use a differential input signal while the ring
tone might be limited to a single-ended signal. Phone gain is set at gain 1 = 0.1 V/V, and the ring-tone gain is
set to gain 2 = 2 V/V, the resistor values would be…
RI1 = 3 MΩ, and = RI2 = 150 kΩ.
The high pass corner frequency of the single-ended input is set by CI2. If the desired corner frequency is less
than 20 Hz...
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1
C
u
I2
ǒ
Ǔ
2p 150kW 20Hz
(9)
C
u 53 pF
I2
(10)
R
R
I1
Differential
Input 1
To Battery
I1
Internal
V
DD
Oscillator
C
S
C
I2
R
I2
Single-Ended
Input 2
IN-
V
O+
PWM
H-
Bridge
_
+
V
O-
R
I2
IN+
C
I2
GND
Bias
SHUTDOWN
Circuitry
Filter-Free Class D
Figure 31. Application Schematic With TPA2010D1 Summing Differential Input and Single-Ended Input
Signals
Summing Two Single-Ended Input Signals
Four resistors and three capacitors are needed for summing single-ended input signals. The gain and corner
frequencies (fc1 and fc2) for each input source can be set independently (see Equation 11 through Equation 14,
and Figure 32). Resistor, RP, and capacitor, CP, are needed on the IN+ terminal to match the impedance on the
IN- terminal. The single-ended inputs must be driven by low impedance sources even if one of the inputs is not
outputting an ac signal.
V
O
I1
2 x 150 kW
V
V
ǒ Ǔ
Gain 1 +
+
V
R
I1
(11)
(12)
(13)
V
O
I2
1
2 x 150 kW
V
V
ǒ Ǔ
Gain 2 +
+
V
R
I2
+ ǒ2p R c1Ǔ
C
I1
f
I1
1
C
+ ǒ2p R c2Ǔ
I2
f
I2
(14)
(15)
C
+ C ) C
P
I1
I2
R
+ ǒR
R
I1
I1
I2
I2
R
P
Ǔ
) R
(16)
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C
I1
R
I1
Single-Ended
Input 1
To Battery
Internal
V
DD
Oscillator
C
S
C
I2
R
I2
Single-Ended
Input 2
IN-
V
O+
PWM
H-
Bridge
_
+
V
O-
R
P
IN+
C
P
GND
Bias
Circuitry
SHUTDOWN
Filter-Free Class D
Figure 32. Application Schematic With TPA2010D1 Summing Two Single-Ended Inputs
BOARD LAYOUT
In making the pad size for the WCSP balls, it is recommended that the layout use nonsolder mask defined
(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the
opening size is defined by the copper pad width. Figure 33 and Table 2 show the appropriate diameters for a
WCSP layout. The TPA2010D1 evaluation module (EVM) layout is shown in the next section as a layout
example.
Copper
Trace Width
Solder
Pad Width
Solder Mask
Opening
Copper Trace
Thickness
Solder Mask
Thickness
Figure 33. Land Pattern Dimensions
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Table 2. Land Pattern Dimensions
SOLDER PAD
DEFINITIONS
SOLDER MASK
OPENING
COPPER
THICKNESS
STENCIL
OPENING
STENCIL
THICKNESS
COPPER PAD
Nonsolder mask
defined (NSMD)
275 µm
(+0.0, –25 µm)
375 µm
(+0.0, –25 µm)
1 oz max (32 µm) 275 µm x 275 µm Sq.
(rounded corners)
125 µm thick
NOTES:
1. Circuit traces from NSMD defined PWB lands should be 75 µm to 100 µm wide in the exposed area inside
the solder mask opening. Wider trace widths reduce device stand off and impact reliability.
2. Recommend solder paste is Type 3 or Type 4.
3. Best reilability results are achieved when the PWB laminate glass transition temperature is above the
operating the range of the intended application.
4. For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 µm to avoid a reduction in
thermal fatigue performance.
5. Solder mask thickness should be less than 20 µm on top of the copper circuit pattern.
6. Best solder stencil preformance is achieved using laser cut stencils with electro polishing. Use of chemically
etched stencils results in inferior solder paste volume control.
7. Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional
component movement due to solder wetting forces.
Component Location
Place all the external components very close to the TPA2010D1. The input resistors need to be very close to the
TPA2010D1 input pins so noise does not couple on the high impedance nodes between the input resistors and
the input amplifier of the TPA2010D1. Placing the decoupling capacitor, CS, close to the TPA2010D1 is
important for the efficiency of the class-D amplifier. Any resistance or inductance in the trace between the device
and the capacitor can cause a loss in efficiency.
Trace Width
Recommended trace width at the solder balls is 75 µm to 100 µm to prevent solder wicking onto wider PCB
traces. Figure 34 shows the layout of the TPA2010D1 evaluation module (EVM).
For high current pins (VDD, GND VO+, and VO-) of the TPA2010D1, use 100-µm trace widths at the solder balls
and at least 500-µm PCB traces to ensure proper performance and output power for the device.
For input pins (IN-, IN+, and SHUTDOWN) of the TPA2010D1, use 75-µm to 100-µm trace widths at the solder
balls. IN- and IN+ pins need to run side-by-side to maximize common-mode noise cancellation. Placing input
resistors, RIN, as close to the TPA2010D1 as possible is recommended.
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75 mm
100 mm
100 mm
100 mm
375 mm
275 mm
(+0, -25 mm)
(+0, -25 mm)
100 mm
Circular Solder Mask Opening
Paste Mask (Stencil)
= Copper Pad Size
75 mm
100 mm
75 mm
Figure 34. Close Up of TPA2010D1 Land Pattern From TPA2010D1 EVM
EFFICIENCY AND THERMAL INFORMATION
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor
for the YEF and YEZ packages are shown in the dissipation rating table. Converting this to ΘJA:
1
1
q
+
+
+ 128.2°CńW
JA
0.0078
Derating Factor
(17)
Given ΘJA of 128.2°C/W, the maximum allowable junction temperature of 125°C, and the maximum internal
dissipation of 0.4 W (2.25 W, 4-Ω load, 5-V supply, from Figure 3), the maximum ambient temperature can be
calculated with the following equation.
T Max + T Max * q
P
+ 125 * 128.2 (0.4) + 73.7°C
A
J
JA Dmax
(18)
Equation 18 shows that the calculated maximum ambient temperature is 73.7°C at maximum power dissipation
with a 5-V supply and 4-Ω a load, see Figure 3. The TPA2010D1 is designed with thermal protection that turns
the device off when the junction temperature surpasses 150°C to prevent damage to the IC. Also, using
speakers more resistive than 4-Ω dramatically increases the thermal performance by reducing the output current
and increasing the efficiency of the amplifier.
ELIMINATING THE OUTPUT FILTER WITH THE TPA2010D1
This section focuses on why the user can eliminate the output filter with the TPA2010D1.
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Effect on Audio
The class-D amplifier outputs a pulse-width modulated (PWM) square wave, which is the sum of the switching
waveform and the amplified input audio signal. The human ear acts as a band-pass filter such that only the
frequencies between approximately 20 Hz and 20 kHz are passed. The switching frequency components are
much greater than 20 kHz, so the only signal heard is the amplified input audio signal.
Traditional Class-D Modulation Scheme
The traditional class-D modulation scheme, which is used in the TPA005Dxx family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VDD. Therefore,
the differential pre-filtered output varies between positive and negative VDD, where filtered 50% duty cycle yields
0 volts across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown
in Figure 35. Note that even at an average of 0 volts across the load (50% duty cycle), the current to the load is
high causing a high loss and thus causing a high supply current.
OUT+
OUT-
+5 V
Differential Voltage
0 V
Across Load
-5 V
Current
Figure 35. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms Into an
Inductive Load With no Input
TPA2010D1 Modulation Scheme
The TPA2010D1 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUT+ and OUT- are now in phase with each other with no input. The duty cycle of OUT+ is greater
than 50% and OUT- is less than 50% for positive voltages. The duty cycle of OUT+ is less than 50% and OUT-
is greater than 50% for negative voltages. The voltage across the load sits at 0 volts throughout most of the
switching period greatly reducing the switching current, which reduces any I2R losses in the load.
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OUT+
OUT-
Output = 0 V
Differential
+5 V
Voltage
0 V
Across
-5 V
Load
Current
OUT+
OUT-
Output > 0 V
Differential
Voltage
Across
Load
+5 V
0 V
-5 V
Current
Figure 36. The TPA2010D1 Output Voltage and Current Waveforms Into an Inductive Load
Efficiency: Why You Must Use a Filter With the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform
results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple
current is large for the traditional modulation scheme because the ripple current is proportional to voltage
multiplied by the time at that voltage. The differential voltage swing is 2 × VDD and the time at each voltage is
half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from
each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both
resistive and reactive, whereas an LC filter is almost purely reactive.
The TPA2010D1 modulation scheme has very little loss in the load without a filter because the pulses are very
short and the change in voltage is VDD instead of 2 × VDD. As the output power increases, the pulses widen
making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for
most applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance than the speaker that results in less power
dissipated, which increases efficiency.
Effects of Applying a Square Wave Into a Speaker
If the amplitude of a square wave is high enough and the frequency of the square wave is within the bandwidth
of the speaker, a square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A
250-kHz switching frequency, however, is not significant because the speaker cone movement is proportional to
1/f2 for frequencies beyond the audio band. Therefore, the amount of cone movement at the switching frequency
is very small. However, damage could occur to the speaker if the voice coil is not designed to handle the
additional power. To size the speaker for added power, the ripple current dissipated in the load needs to be
calculated by subtracting the theoretical supplied power, PSUP THEORETICAL, from the actual supply power, PSUP, at
maximum output power, POUT. The switching power dissipated in the speaker is the inverse of the measured
efficiency, ηMEASURED, minus the theoretical efficiency, ηTHEORETICAL
.
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P
+ P
–P
(at max output power)
(at max output power)
1
SPKR
SUP SUP THEORETICAL
(19)
P
P
SUP
OUT
SUP THEORETICAL
P
+
–
SPKR
P
P
OUT
(20)
1
ǒ
Ǔ(at max output power)
P
+ P
*
h
h
SPKR
OUT
MEASURED
THEORETICAL
(21)
R
L
hTHEORETICAL +
(at max output power)
R
) 2r
L
DS(on)
(22)
The maximum efficiency of the TPA2010D1 with a 3.6 V supply and an 8-Ω load is 86% from Equation 22. Using
equation Equation 21 with the efficiency at maximum power (84%), we see that there is an additional 17 mW
dissipated in the speaker. The added power dissipated in the speaker is not an issue as long as it is taken into
account when choosing the speaker.
When to Use an Output Filter
Design the TPA2010D1 without an output filter if the traces from amplifier to speaker are short. The TPA2010D1
passed FCC and CE radiated emissions with no shielding with speaker trace wires 100 mm long or less.
Wireless handsets and PDAs are great applications for class-D without a filter.
A ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter, and the
frequency sensitive circuit is greater than 1 MHz. This is good for circuits that just have to pass FCC and CE
because FCC and CE only test radiated emissions greater than 30 MHz. If choosing a ferrite bead, choose one
with high impedance at high frequencies, but very low impedance at low frequencies.
Use an LC output filter if there are low frequency (< 1 MHz) EMI sensitive circuits and/or there are long leads
from amplifier to speaker.
Figure 37 and Figure 38 show typical ferrite bead and LC output filters.
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 37. Typical Ferrite Chip Bead Filter (Chip bead example: NEC/Tokin: N2012ZPS121)
33 µH
OUTP
1 µF
33 µH
OUTN
1 µF
Figure 38. Typical LC Output Filter, Cutoff Frequency of 27 kHz
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TPA2010D1YEFR
TPA2010D1YEFT
TPA2010D1YZFR
ACTIVE
ACTIVE
ACTIVE
XCEPT
XCEPT
DSBGA
YEF
9
9
9
3000
250
TBD
TBD
Call TI
SNPB
Level-1-240C-UNLIM
Level-1-240C-UNLIM
Level-1-260C-UNLIM
YEF
YZF
3000 Green (RoHS &
no Sb/Br)
SNAGCU
TPA2010D1YZFT
ACTIVE
DSBGA
YZF
9
250 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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www.ti.com/audio
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dsp.ti.com
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www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
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power.ti.com
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Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Low Power Wireless www.ti.com/lpw
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
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