TPA3001D1PWP [TI]
20 W MONO CLASS D AUDIO POWER AMPLIFIER; 20瓦单声道D类音频功率放大器
| 型号： | TPA3001D1PWP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 20 W MONO CLASS D AUDIO POWER AMPLIFIER |
| 文件： | 总26页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLOS398A − DECEMBER 2002 − REVISED APRIL 2003
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FEATURES
DESCRIPTION
D
D
D
20 W Into 8-Ω Load From 18-V Supply
The TPA3001D1 is a 20-W mono bridge-tied load (BTL)
class-D audio power amplifier with high efficiency,
eliminating the need for heat sinks. The TPA3001D1
can drive 4-Ω or 8-Ω speakers with only a ferrite bead
filter required to reduce EMI.
(10% THD+N)
Short Circuit Protection (Short to V , Short
CC
to GND, Short Between Outputs)
Third-Generation Modulation Technique:
− Replaces Large LC Filter With Small,
Low-Cost Ferrite Bead Filter in Most
Applications
The gain of the amplifier is controlled by two input
terminals, GAIN1 and GAIN0. This allows the amplifier
to be configured for a gain of 12, 18, 23.6, and 36 dB.
The differential input stage provides high common
mode rejection and improved power supply rejection.
− Improved Efficiency
− Improved SNR
D
D
D
Low Supply Current . . . 8 mA Typ at 12 V
Shutdown Control . . . <1 µA Typ
Space-Saving, Thermally-Enhanced
PowerPAD Packaging
The amplifier also includes depop circuitry to reduce the
amount of pop at power-up and when cycling
SHUTDOWN.
The TPA3001D1 is available in the 24-pin thermally
enhanced TSSOP package (PWP) which eliminates the
need for an external heat sink.
APPLICATIONS
D
D
D
LCD Monitors/TVs
Hands-Free Car Kits
Powered Speakers
EFFICIENCY
MAXIMUM OUTPUT POWER
vs
vs
LOAD IMPEDANCE
21
OUTPUT POWER
90
80
70
60
50
40
30
20
10
0
8 Ω
19
V
= 18 V
CC
4 Ω
17
15
13
11
V
= 15 V
CC
V
= 12 V
CC
9
V
CC
= 18 V
16
T
A
= 25°C,
7
5
10% THD Maximum
0
4
8
12
20
3.6 4
5
6
7
8
9
10
P
O
− Output Power − W
R
− Load Impedance − Ω
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
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Copyright 2002−2003, Texas Instruments Incorporated
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ꢜ ꢠ ꢝ ꢜꢕ ꢖꢪ ꢘꢗ ꢛ ꢣꢣ ꢡꢛ ꢙ ꢛ ꢚ ꢠ ꢜ ꢠ ꢙ ꢝ ꢥ
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SLOS398A − DECEMBER 2002 − REVISED APRIL 2003
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
†
TSSOP (PWP)
TPA3001D1PWP
−40°C to 85°C
†
The PWP package is available taped and reeled. To order a taped and
reeled part, add the suffix R to the part number (e.g., TPA3001D1PWPR).
PWP PACKAGE
(TOP VIEW)
1
24
23
22
21
20
19
18
17
16
15
14
13
INN
INP
GAIN0
V
CC
2
VREF
BYPASS
COSC
ROSC
AGND
AGND
BSP
3
4
GAIN1
5
SHUTDOWN
PGND
6
7
VCLAMP
BSN
8
9
PV
PV
CC
CC
10
11
12
OUTN
OUTN
PGND
OUTP
OUTP
PGND
Terminal Functions
TERMINAL
NAME
AGND
I/O
DESCRIPTION
NO.
18, 19
8
Analog ground terminal
Bootstrap terminal for high-side gate drive of negative BTL output (connect a 0.22-µF capacitor with a
51-Ω resistor in series from OUTN to BSN)
BSN
BSP
I
I
Bootstrap terminal for high-side gate drive of positive BTL output (connect a 0.22-µF capacitor with a
51-Ω resistor in series from OUTP to BSP)
17
BYPASS
COSC
GAIN0
GAIN1
INN
22
I
I
Connect 1-µF capacitor to ground for BYPASS voltage filtering
Connect a 220-pF capacitor to ground to set oscillation frequency
Bit 0 of gain control (see Table 1 for gain settings)
21
3
I
4
I
Bit 1 of gain control (see Table 1 for gain settings)
1
2
I
Negative differential input
INP
I
Positive differential input
OUTN
OUTP
PGND
10, 11
14, 15
6, 12, 13
9, 16
20
O
O
Negative BTL output, connect Schottky diode from PGND to OUTN for short-circuit protection
Positive BTL output, connect Schottky diode from PGND to OUTP for short-circuit protection
Power ground
PV
CC
I
I
High-voltage power supply (for output stages)
ROSC
Connect 120 kΩ resistor to ground to set oscillation frequency
Shutdown terminal (negative logic), TTL compatible, 21-V compliant
Analog high-voltage power supply
SHUTDOWN
5
I
V
CC
24
I
VCLAMP
VREF
7
O
O
Connect 1-µF capacitor to ground to provide reference voltage for H-bridge gates
5-V internal regulator for control circuitry (connect a 0.1-µF to 1-µF capacitor to ground)
23
2
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SLOS398A − DECEMBER 2002 − REVISED APRIL 2003
functional block diagram
VREF
VREF
AGND
V
V
VCLAMP
CC
CC
Clamp
Reference
BSN
PV
CC
+
_
Deglitch
Logic
Gate
Drive
OUTN
Gain
Adjust
_
+
INN
INP
PGND
BSP
_
+
_
+
PV
CC
+
_
_
+
Gain
Adjust
Deglitch
Logic
Gate
Drive
OUTP
PGND
SD
Short-Circuit
Detect
SHUTDOWN
Start-Up
Protection
Logic
GAIN1
Biases
and
References
Ramp
Generator
2
GAIN0
Gain
COSC
ROSC
Thermal
V
OK
CC
BYPASS
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage: V
PV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 21 V
CC,
CC
Load impedance, R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≥3.6 Ω
L
Input voltage: SHUTDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
+ 0.3 V
CC
GAIN0, GAIN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 5.5 V
INN, INP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see Dissipation Rating Table)
Operating free-air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
A
Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
{
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
T
A
≤ 25°C
DERATING FACTOR
T
A
= 70°C
T = 85°C
A
‡
PWP
4.16 W
33.33 mW/°C
2.67 W
2.16 W
‡
The PowerPAD must be soldered to a thermal land on the printed circuit board. Please refer to the PowerPAD
Thermally Enhanced Package application note (SLMA002).
3
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SLOS398A − DECEMBER 2002 − REVISED APRIL 2003
recommended operating conditions
MIN
8
MAX
UNIT
V
†
Supply voltage, V
CC,
PV
CC
R
≥ 3.6 Ω
18
L
Load impedance, R
3.6
2
Ω
L
High-level input voltage, V
IH
GAIN0, GAIN1, SHUTDOWN
GAIN0, GAIN1, SHUTDOWN
V
Low-level input voltage, V
IL
0.8
85
V
Operating free-air temperature, T
−40
°C
A
†
The TPA3001D1 must not be used with any speaker or load (including speaker with output filter) that could vary below 3.6 Ω over the audio
frequency band.
electrical characteristics at T = 25°C, PV
= V
= 12 V (unless otherwise noted)
A
CC
CC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
50
UNIT
V = 0 V,
A
= 12 dB, 18, 23.6 dB
= 36 dB
V
I
V
|V
|
Output offset voltage (measured differentially)
mV
OS
V = 0 V,
I
A
100
PSRR
Power supply rejection ratio
High-level input current
Low-level input current
PV
PV
PV
= 11.5 V to 12.5 V
−73
dB
µA
µA
mA
CC
CC
CC
|I
|I
|
= 12 V, V = PV
CC
1
1
IH
I
|
= 12 V, V = 0 V
I
IL
SHUTDOWN = 2.0 V, No load
SHUTDOWN = V , V = 18 V,
8
15
I
Supply current
CC
CC CC
= 20 W, R = 8 Ω
1.3
A
P
O
L
I
f
Supply current, shutdown mode
Switching frequency
SHUTDOWN = 0.8 V
= 120 kΩ,
1
250
0.3
12
2
µA
kHz
Ω
CC(SD)
R
C
= 220 pF
OSC
s
OSC
= 1 A, T = 25°C
r
Output transistor on resistance (total)
I
O
0.2
10.9
17.1
23
0.7
12.8
18.5
24.3
36.5
ds(on)
J
GAIN1 = 0.8 V, GAIN0 = 0.8 V
GAIN1 = 0.8 V, GAIN0 = 2 V
GAIN1 = 2 V, GAIN0 = 0.8 V
GAIN1 = 2 V, GAIN0 = 2 V
dB
dB
dB
dB
18
G
Gain
23.6
36
33.9
operating characteristics, PV
= V
= 12 V, T = 25°C (unless otherwise noted)
CC
CC A
PARAMETER
TEST CONDITIONS
MIN
TYP
12.8
9
MAX
UNIT
f = 1 kHz,
f = 1 kHz,
f = 1 kHz,
f = 1 kHz,
R
R
R
R
= 4 Ω
= 8 Ω
= 4 Ω
= 8 Ω
Continuous output power at 10%
THD+N
L
L
L
L
P
O
W
10.3
7.2
Continuous output power at 1%
THD+N
THD + N Total harmonic distortion plus noise
P
= 10 W, R = 4 Ω,
f = 20 Hz to 20 kHz
0.2%
20
O
L
B
OM
Maximum output power bandwidth
Supply ripple rejection ratio
Signal-to-noise ratio
THD = 1%
f = 1 kHz,
kHz
dB
k
C
= 1 µF
(BYPASS)
−70
95
SVR
SNR
P
O
= 10 W, R = 4 Ω
dB
L
86
µV(rms)
dBV
C
= 1 µF,
f = 20 Hz to 22 kHz,
(BYPASS)
No weighting filter used, Gain = 12 dB
−81
66
V
Noise output voltage
Input impedance
n
µV(rms)
dBV
C
= 1 µF,
f = 20 Hz to 22 kHz,
Gain = 12 dB
(BYPASS)
A-weighted filter,
−84
Z
i
See Table 1, page 21
>23
kΩ
4
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SLOS398A − DECEMBER 2002 − REVISED APRIL 2003
operating characteristics, PV
= V
= 18 V, T = 25°C (unless otherwise noted)
CC
CC
A
PARAMETER
TEST CONDITIONS
MIN
TYP
12.8
20
MAX
UNIT
f = 1 kHz,
f = 1 kHz,
f = 1 kHz,
f = 1 kHz,
R
R
R
R
= 4 Ω
= 8 Ω
= 4 Ω
= 8 Ω
L
L
L
L
Output power at 10% THD+N
P
O
W
10.3
16
Output power at 1% THD+N
P
= 15 W, R = 8 Ω
f = 20 Hz to 20 kHz
f = 20 Hz to 20 kHz
1%
0.3%
20
O
O
L
THD + N Total harmonic distortion plus noise
P
= 2 W, R = 8 Ω
L
B
Maximum output power bandwidth
Supply ripple rejection ratio
Signal-to-noise ratio
THD = 1%
f = 1 kHz,
kHz
dB
OM
k
C
= 1 µF
BYPASS
−70
102
86
SVR
SNR
P
O
= 15 W, R = 8 Ω
dB
L
µV(rms)
dBV
C
= 1 µF,
f = 20 Hz to 20 kHz,
(BYPASS)
No weighting filter used, Gain = 12 dB
−81
66
V
Noise output voltage
Input impedance
n
µV(rms)
dBV
C
= 1 µF,
f = 20 Hz to 22 kHz,
Gain = 12 dB
(BYPASS)
A-weighted filter,
−84
Z
i
See Table 1, page 21
>23
kΩ
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Efficiency
vs Output power
1
P
Output power
Supply current
Shutdown current
vs Load Impedance
2, 3, 4
O
I
I
5
6
CC
vs Supply voltage
vs Output power
CC(SD)
7, 8, 9, 10, 11,
12, 13, 14, 15,
16, 17, 18
THD+N
Total harmonic distortion + noise
19, 20, 21, 22,
23, 24, 25
vs Frequency
k
Supply voltage rejection ratio
Gain and phase
26
27
28
29
SVR
vs Frequency
CMRR
Common-mode rejection ratio
Input offset voltage
V
vs Common-mode input voltage
IO
5
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SLOS398A − DECEMBER 2002 − REVISED APRIL 2003
TYPICAL CHARACTERISTICS
EFFICIENCY
vs
MAXIMUM OUTPUT POWER
vs
OUTPUT POWER
LOAD IMPEDANCE
21
19
17
15
13
11
90
8 Ω
V
= 18 V
80
CC
4 Ω
70
60
50
40
30
20
V
= 15 V
CC
V
T
= 12 V
CC
9
V
CC
= 12 V
7
5
= 25°C,
10% THD Maximum
10
0
A
0
2
4
6
8
10
12
14
3.6
4
5
6
7
8
9
10
P
O
− Output Power − W
Load Impedance − Ω
Figure 1
Figure 2
MAXIMUM OUTPUT POWER
vs
MAXIMUM OUTPUT POWER
vs
LOAD IMPEDANCE
LOAD IMPEDANCE
21
21
19
17
15
13
11
T = 60°C
A
T
A
= 45°C
19
17
15
13
11
V
= 18 V
CC
V
CC
= 18 V
V
CC
= 15 V
V
CC
= 15 V
9
V
CC
= 12 V
9
V
CC
= 12 V
7
5
7
5
3.6
4
5
6
7
8
9
10
3.6
4
5
6
7
8
9
10
Z
L
− Load Impedance − Ω
Z
L
− Load Impedance − Ω
Figure 3
Figure 4
6
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
SHUTDOWN CURRENT
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
11
10
9
5
4
3
2
1
0
SHUTDOWN = 0.8 V
8
7
6
8
10
12
14
16
18
8
10
12
14
16
18
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
Figure 5
Figure 6
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
vs
OUTPUT POWER
OUTPUT POWER
10
10
V
R
= 18 V,
CC
= 8 Ω,
V
R
= 18 V,
CC
= 8 Ω,
L
L
Gain = 12 dB
Gain = 36 dB
1
1
1 kHz
1 kHz
20 kHz
0.1
20 kHz
0.1
0.01
20 Hz
20 Hz
0.001
0.01
0
5
10
15
20
0
5
10
15
20
P
O
− Output Power − W
P
O
− Output Power − W
Figure 7
Figure 8
7
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TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
vs
OUTPUT POWER
OUTPUT POWER
10
10
V
R
= 15 V,
V
R
= 15 V,
CC
= 8 Ω,
CC
= 8 Ω,
L
L
Gain = 36 dB
Gain = 12 dB
1
1 kHz
1
20 kHz
20 Hz
20 kHz
0.1
1 kHz
20 Hz
0.1
0.01
0.01
0.001
0
5
10
− Output Power − W
15
20
0
5
10
15
20
P
− Output Power − W
P
O
O
Figure 9
Figure 10
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
vs
OUTPUT POWER
OUTPUT POWER
10
10
V
R
= 15 V,
CC
= 4 Ω,
V
R
= 15 V,
CC
= 4 Ω,
L
L
Gain = 12 dB
Gain = 36 dB
1
1
1 kHz
20 Hz
1 kHz
20 Hz
0.1
0.1
20 kHz
20 kHz
10
0.01
0.01
0
5
0
5
10
P
O
− Output Power − W
P
O
− Output Power − W
Figure 11
Figure 12
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SLOS398A − DECEMBER 2002 − REVISED APRIL 2003
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
vs
OUTPUT POWER
OUTPUT POWER
10
10
V
R
= 12 V,
CC
= 8 Ω,
V
R
= 12 V,
CC
= 8 Ω,
L
L
Gain = 12 dB
Gain = 36 dB
1
0.1
1 kHz
1
1 kHz
20 kHz
20 kHz
20 Hz
20 Hz
0.1
0.01
0.01
0.001
0
5
10
15
0
5
10
15
P
O
− Output Power − W
P
O
− Output Power − W
Figure 13
Figure 14
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
vs
OUTPUT POWER
OUTPUT POWER
10
10
V
R
= 12 V,
CC
= 4 Ω,
V
R
= 12 V,
CC
= 4 Ω,
L
L
Gain = 36 dB
Gain = 12 dB
1
1
1 kHz
0.1
1 kHz
20 Hz
0.1
20 kHz
0.01
20 kHz
20 Hz
0.01
0.001
0
5
10
0
5
10
P
O
− Output Power − W
P
O
− Output Power − W
Figure 15
Figure 16
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TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
vs
OUTPUT POWER
OUTPUT POWER
10
10
V
R
= 8 V,
CC
= 4 Ω,
V
R
= 8 V,
CC
= 4 Ω,
L
L
Gain = 36 dB
Gain = 12 dB
1
1
1 kHz
1 kHz
20 Hz
0.1
0.1
20 kHz
20 kHz
20 Hz
0.01
0.01
0
2
4
6
0
2
4
6
P
O
− Output Power − W
P
O
− Output Power − W
Figure 17
Figure 18
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
vs
FREQUENCY
FREQUENCY
1
1
V
R
= 18 V
= 8 Ω
CC
L
V
= 15 V
P
O
= 10 W
P
O
= 10 W
CC
R = 8 Ω
L
P
O
= 500 mW
0.1
0.1
P
O
= 500 mW
P
O
= 2 W
0.01
0.01
P
O
= 2 W
0.001
0.001
20
100
1 k
10 k 20 k
20
100
1 k
10 k 20 k
f − Frequency − Hz
f − Frequency − Hz
Figure 19
Figure 20
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TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
vs
FREQUENCY
FREQUENCY
1
1
V
R
= 15 V
CC
= 4 Ω
V
= 12 V
CC
R = 8 Ω
L
L
P
O
= 5 W
P
O
= 10 W
0.1
0.1
P
O
= 250 mW
P
O
= 500 mW
P
O
= 2 W
0.01
0.01
P
O
= 1 W
0.001
0.001
20
100
1 k
10 k 20 k
20
100
1 k
10 k 20 k
f − Frequency − Hz
f − Frequency − Hz
Figure 21
Figure 22
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
vs
FREQUENCY
FREQUENCY
10
1
V
R
= 12 V
V
R
= 8 V
CC
= 4 Ω
CC
= 8 Ω
L
L
1
P
O
= 3 W
0.1
0.01
P
O
= 2 W
P
O
= 250 mW
P
O
= 500 mW
0.1
P
O
= 1 W
P
O
= 7.5 W
0.01
0.001
0.001
20
100
1 k
10 k 20 k
20
100
1 k
10 k 20 k
f − Frequency − Hz
f − Frequency − Hz
Figure 23
Figure 24
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TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION PLUS NOISE
SUPPLY VOLTAGE REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
10
1
−50
−60
−70
−80
−90
V
R
= 8 V
= 4 Ω
CC
L
C
R
= 1 µF
(Bypass)
L
= 8 Ω
P
= 5 W
O
P
O
= 1 W
V
CC
= 8 V
0.1
P
O
= 250 mW
V
= 15 V
DD
0.01
0.001
20
100
1 k
10 k 20 k
20
100
1k
10k
f − Frequency − Hz
f − Frequency − Hz
Figure 25
Figure 26
COMMON-MODE REJECTION RATIO
GAIN and PHASE
vs
vs
FREQUENCY
FREQUENCY
−40
−41
−42
−43
14
30
20
10
V
R
= 8 V to 18 V
CC
= 8 Ω
Gain
L
12
10
8
0
−10
−20
−30
−40
−50
−60
−70
Phase
6
−44
−45
−46
4
2
0
V
R
= 8 V
= 8 Ω
CC
L
Gain = 12 dB
−80
100k
20
100
1 k
10 k
20
100
1k
10k
f − Frequency − Hz
f − Frequency − Hz
Figure 27
Figure 28
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TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
6
5
V
CC
= 8 V to 18 V
4
3
2
1
0
−1
−2
−3
−4
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V
IC
− Common-Mode Input Voltage − V
Figure 29
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APPLICATION INFORMATION
application circuit
U1
TPA3001D1
V
CC
1
2
3
4
24
23
22
21
20
19
18
0.47 µF
C1
C4
INN
INP
IN−
V
CC
1 µF
C3
1 µF
VREF
IN+
C2 0.47 µF
C11
1 µF
GAIN SELECT
GAIN0
BYPASS
COSC
C12
220 pF
GAIN1
GAIN SELECT
R1
5
6
SHUTDOWN
CONTROL
SHUTDOWN
PGND
ROSC
AGND
AGND
BSP
120 kΩ
7
8
VCLAMP
BSN
R2
R3
C10
17
16
15
14
13
1 µF
C8
0.22 µF
C9
0.22 µF
51 Ω
51 Ω
9
V
PV
CC
PV
CC
V
CC
CC
10
11
12
C6
1 µF
OUTN
OUTN
PGND
OUTP
OUTP
C7
10 µF
C5
1 µF
PGND
D1
D2
PowerPAD
L2
L1
(Ferrite (Ferrite
Bead)
Bead)
C15
1 nF
C14
1 nF
L1, L2: Fair-Rite, Part Number 2512067007Y3
D1, D2: Diodes, Inc., Part Number B130
Figure 30. Typical Application Circuit
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APPLICATION INFORMATION
class-D operation
This section focuses on the class-D operation of the TPA3001D1.
traditional class-D modulation scheme
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, V . Therefore,
CC
the differential prefiltered output varies between positive and negative V , where filtered 50% duty cycle yields
CC
0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown
in Figure 31. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is
high, causing high loss, thus causing a high supply current.
OUTP
OUTN
+12 V
Differential Voltage
0 V
Across Load
−12 V
Current
Figure 31. Traditional Class-D Modulation Scheme’s Output Voltage and
Current Waveforms Into an Inductive Load With No Input
TPA3001D1 modulation scheme
The TPA3001D1 uses a modulation scheme that still has each output switching from ground to V . However,
CC
OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater than 50%
and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN
is greater than 50% for negative output voltages. The voltage across the load is 0 V throughout most of the
2
switching period, greatly reducing the switching current, which reduces any I R losses in the load. (See
Figure 32 on the following page.)
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APPLICATION INFORMATION
TPA3001D1 modulation scheme (continued)
OUTP
OUTN
Output = 0 V
Differential
+12 V
Voltage
0 V
Across
−12 V
Load
Current
OUTP
OUTN
Output > 0 V
Differential
Voltage
Across
Load
+12 V
0 V
−12 V
Current
Figure 32. The TPA3001D1 Output Voltage and Current Waveforms Into an Inductive Load
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APPLICATION INFORMATION
maximum allowable output power (safe operating area)
The TPA3001D1 can drive load impedances as low as 3.6 Ω from power supply voltages ranging from 8 V to
18 V. To prevent device failure, however, the output power of the TPA3001D1 must be limited. Figure 33 shows
the maximum allowable output power versus load impedance for three power supply voltages at an ambient
temperature of 25°C. (For ambient temperatures of 45°C and 60°C, see Figures 3 and 4 on page 6.)
MAXIMUM OUTPUT POWER
vs
LOAD IMPEDANCE
21
19
V
CC
= 18 V
17
15
13
11
V
= 15 V
CC
V
CC
= 12 V
9
T
= 25°C,
7
5
A
10% THD Maximum
3.6 4
5
6
7
8
9
10
Load Impedance − Ω
Figure 33. Output Power
driving a low-impedance load from a high power supply voltage
When driving low-impedance loads (e.g., a 4-Ω speaker), the output power can be limited by reducing the
maximum audio input signal level or by reducing the gain of the TPA3001D1. The maximum input voltage may
be calculated with equation 1.
8P
Ǹ
R
O(avg),max
L
V
+
in(pp),max
A
v
(1)
where
P
= maximum continuous output power (W)
O(avg), max
R = load impedance (Ω)
L
G(dB)
ǒ Ǔ
20
A = voltage gain (V/V) = 10
v
For example, consider an application in which the TPA3001D1 drives a 4-Ω speaker from an 18-V power supply.
The gain is selected to be 18 dB. The maximum allowable output power for a 4-Ω load impedance is 12.8 W.
From equation 1, the input voltage must not exceed 2.54 V
.
pp
In this same example, however, if the maximum output voltage of audio signal source is 5 V , then the gain
pp
of the TPA3001D1 should be reduced to 12 dB to eliminate the need for limiting the input signal.
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APPLICATION INFORMATION
The input voltage may be limited using a variety of methods, depending on what is known about the audio signal
source. If the maximum output voltage of the source is known, a resistive voltage divider in conjunction with
proper TPA3001D1 gain selection may be used to prevent distortion. If the maximum audio source voltage is
unknown, diodes may be used to clamp the input voltage, at the cost of distortion when the input signal level
exceeds the required clamping voltage.
driving the output into clipping
The output of the TPA3001D1 may be driven into clipping to attain a higher output power than is possible with
no distortion. Clipping is typically quantified by a THD measurement of 10%. The amount of additional power
into the load may be calculated with equation 2.
P
+ P
1.25
O(10% THD)
O(1% THD)
(2)
For example, consider an application in which the TPA3001D1 drives an 8-Ω speaker from an 18-V power
supply. The maximum output power with no distortion (less than 1% THD) is 16 W, which corresponds to a
maximum peak output voltage of 16 V. For the same output voltage level driven into clipping (10% THD), the
output power is increased to 20 W.
output filter considerations
A ferrite bead filter (shown in Figure 34) should be used in order to pass FCC and/or CE radiated emissions
specifications and if a frequency sensitive circuit operating higher than 1 MHz is nearby. The ferrite filter reduces
EMI around 1 MHz and higher (FCC and CE only test radiated emissions greater than 30 MHz). When selecting
a ferrite bead, choose one with high impedance at high frequencies, but very low impedance at low frequencies.
Use an additional LC output filter if there are low frequency (<1 MHz) EMI sensitive circuits and/or there are long
wires (greater than 11 inches) from the amplifier to the speaker, as shown in Figure 35 and Figure 36.
Ferrite
Chip Bead
OUTP
1 nF
4 Ω or Greater
Ferrite
Chip Bead
OUTN
1 nF
Figure 34. Typical Ferrite Chip Bead Filter (Chip bead example: Fair-Rite 2512067007Y3)
Ferrite
Chip Bead
15 µH
OUTP
1 µF
1 µF
1 nF
15 µH
4 Ω
Ferrite
Chip Bead
OUTN
1 nF
Figure 35. Typical LC Output Filter for 4-Ω Speaker, Cutoff Frequency of 41 kHz
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APPLICATION INFORMATION
Ferrite
Chip Bead
33 µH
OUTP
0.47 µF
8 Ω
1 nF
33 µH
Ferrite
Chip Bead
OUTN
0.47 µF
1 nF
Figure 36. Typical LC Output Filter for 8-Ω Speaker, Cutoff Frequency of 41 kHz
short-circuit protection
The TPA3001D1 has short circuit protection circuitry on the outputs that prevents damage to the device during
output-to-output shorts, output-to-GND shorts, and output-to-V shorts. When a short-circuit is detected on
CC
the outputs, the part immediately disables the output drive and enters into shutdown mode. This is a latched
fault and must be reset by cycling the voltage on the SHUTDOWN pin to a logic low and back to the logic high
state for normal operation. This will clear the short-circuit flag and allow for normal operation if the short was
removed. If the short was not removed, the protection circuitry will again activate.
Two Schottky diodes are required to provide short-circuit protection. The diodes should be placed as close to
the TPA3001D1 as possible, with the anodes connected to PGND and the cathodes connected to OUTP and
OUTN as shown in the application circuit schematic. The diodes should have a forward voltage rating of 0.5V
at a minimum of 1A output current and a DC blocking voltage rating of at least 30 V. The diodes must also be
rated to operate at a junction temperature of 150°C.
If short-circuit protection is not required, the Schottky diodes may be omitted.
thermal protection
Thermal protection on the TPA3001D1 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a 15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is
not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The device
begins normal operation at this point with no external system interaction.
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APPLICATION INFORMATION
thermal considerations: output power and maximum ambient temperature
To calculate the maximum ambient temperature, the following equation may be used:
T
= T
– Θ
P
Amax
Jmax
JA Dissipated
(3)
where: T
= 150°C
Jmax
Θ
= 1 / derating factor = 1 / 0.03333 = 30°C/W
JA
(The derating factor for the 24-pin PWP package is given in the dissipation rating table on page 3.)
To estimate the power dissipation, the following equation may be used:
P
= P
x ((1 / Efficiency) – 1)
(4)
Dissipated
O(average)
Efficiency = ~85% for an 8-Ω load
= ~75% for a 4-Ω load
Example. What is the maximum ambient temperature for an application that requires the TPA3001D1 to drive
10 W into an 8-Ω speaker?
P
= 10 W x ((1 / 0.85) – 1) = 1.76 W
Dissipated
T
= 150°C – (30°C/W x 1.76 W) = 97.2°C
Amax
This calculation shows that the TPA3001D1 can drive 10 W into an 8-Ω speaker up to the absolute maximum
ambient temperature rating of 85°C, which must never be exceeded. Also, refer to Figures 2, 3, and 4 to
determine the minimum load impedance for the desired output power.
gain setting via GAIN0 and GAIN1 inputs
The gain of the TPA3001D1 is set by two input terminals, GAIN0 and GAIN1.
The gains listed in Table 1 are realized by changing the taps on the input resistors inside the amplifier. This
causes the input impedance (Z ) to be dependent on the gain setting. The actual gain settings are controlled
i
by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance may shift
by 30% due to shifts in the actual resistance of the input resistors.
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 23 kΩ, which is the absolute minimum input impedance of the TPA3001D1. At the lower gain
settings, the input impedance could increase as high as 313 kΩ.
Table 1. Gain Settings
AMPLIFIER GAIN
(dB)
INPUT IMPEDANCE
(kΩ)
GAIN1
GAIN0
TYP
12
TYP
241
168
104
33
0
0
1
1
0
1
0
1
18
23.6
36
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APPLICATION INFORMATION
input resistance
Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest
value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the −3 dB
or cutoff frequency also changes by over six times.
Z
f
C
i
Z
i
IN
Input
Signal
The −3-dB frequency can be calculated using equation 5. Use Table 1 for Z values.
i
1
f +
2p Z C
(5)
i i
input capacitor, C
i
In the typical application an input capacitor (C ) is required to allow the amplifier to bias the input signal to the
i
proper dc level for optimum operation. In this case, C and the input impedance of the amplifier (Z ) form a
i
i
high-pass filter with the corner frequency determined in equation 6.
−3 dB
(6)
1
f
+
c
2pZ C
i
i
f
c
The value of C is important, as it directly affects the bass (low frequency) performance of the circuit. Consider
i
the example where Z is 241 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 6
i
is reconfigured as equation 7.
1
C +
i
2pZ f
(7)
c
i
In this example, C is 33 nF, so one would likely choose a value of 0.1 µF as this value is commonly used. If the
i
gain is known and will be constant, use Z from Table 1 to calculate C . A further consideration for this capacitor
i
i
is the leakage path from the input source through the input network (C ) and the feedback network to the load.
i
This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom,
especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best
choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input
in most applications as the dc level there is held at 2.5 V, which is likely higher than the source dc level. Note
that it is important to confirm the capacitor polarity in the application.
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APPLICATION INFORMATION
power supply decoupling
The TPA3001D1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance
(ESR) ceramic capacitor, typically 1 µF placed as close as possible to the device V
lead works best. For
CC
filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near
the audio power amplifier is recommended.
BSN and BSP capacitors
The full H-bridge output stage uses only NMOS transistors. It therefore requires bootstrap capacitors for the
high side of each output to turn on correctly. A 0.22-µF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 0.22-µF capacitor must be
connected from OUTP to BSP, and one 0.22-µF capacitor must be connected from OUTN to BSN. (See
Figure 30.)
BSN and BSP resistors
To limit the current when charging the bootstrap capacitors, a resistor with a value of approximately 50 Ω
(+/−10% maximum) must be placed in series with each bootstrap capacitor. The current will be limited to less
than 500 µA.
VCLAMP capacitor
To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, an internal
regulator clamps the gate voltage. A 1-µF capacitor must be connected from VCLAMP (pin 7) to ground and
must be rated for at least 25 V. The voltage at VCLAMP (pin 7) varies with V
any other circuitry.
and may not be used for powering
CC
midrail bypass capacitor
The midrail bypass capacitor (C11 of Figure 30) is the most critical capacitor and serves several important
functions. During start-up or recovery from shutdown mode, C determines the rate at which the amplifier
BYPASS
starts up. The second function is to reduce noise produced by the power supply caused by coupling into the
output drive signal. This noise is from the midrail generation circuit internal to the amplifier, which appears as
degraded PSRR and THD+N.
Bypass capacitor (C11) values of 0.47-µF to 1-µF ceramic or tantalum low-ESR capacitors are recommended
for the best THD noise, and depop performance. The bypass capacitor must be a value greater than the input
capacitors for optimum depop performance.
VREF decoupling capacitor
The VREF terminal (pin 23) is the output of an internally-generated 5-V supply, used for the oscillator and gain
setting logic. It requires a 0.1-µF to 1-µF capacitor to ground to keep the regulator stable. The regulator may
not be used to power any additional circuitry.
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APPLICATION INFORMATION
differential input
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel.
To use the TPA3001D1 EVM with a differential source, connect the positive lead of the audio source to the INP
input and the negative lead from the audio source to the INN input. To use the TPA3001D1 with a single-ended
source, ac ground the INN input through a capacitor and apply the audio signal to the INP input. In a
single-ended input application, the INN input should be ac-grounded at the audio source instead of at the device
input for best noise performance.
switching frequency
The switching frequency is determined using the values of the components connected to R
(pin 20) and
(8)
OSC
C
(pin 21) and may be calculated with the following equation:
OSC
6.6
f
+
s
R
C
OSC OSC
The frequency may be varied from 225 kHz to 275 kHz by adjusting the values chosen for R
and C
.
OSC
OSC
SHUTDOWN operation
The TPA3001D1 employs a shutdown mode of operation designed to reduce supply current (I ) to the absolute
CC
minimum level during periods of nonuse for battery-power conservation. The SHUTDOWN input terminal
should be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the
outputs to mute and the amplifier to enter a low-current state, I
unconnected, because amplifier operation would be unpredictable.
= 1 µA. SHUTDOWN should never be left
CC(SD)
Ideally, the device should be held in shutdown when the system powers up and brought out of shutdown once
any digital circuitry has settled. However, if SHUTDOWN is to be left unused, the terminal may be connected
directly to V
.
CC
using low-ESR capacitors
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance the more the real capacitor behaves like an ideal capacitor.
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SLOS398A − DECEMBER 2002 − REVISED APRIL 2003
APPLICATION INFORMATION
printed circuit board (PCB) layout
Because the TPA3001D1 is a class-D amplifier that switches at a high frequency, the layout of the printed circuit
board (PCB) should be optimized according to the following guidelines for the best possible performance.
D
Decoupling capacitors — As described on page 22, the high-frequency 0.1-uF decoupling capacitors
should be placed as close to the PVCC (pin 9 and pin 16) and VCC (pin 24) terminals as possible. The
BYPASS (pin 22) capacitor, VREF (pin 23) capacitor, and VCLAMP (pin 7) capacitor should also be placed
as close to the device as possible. The large (10 uF or greater) bulk power supply decoupling capacitor
should be placed near the TPA3001D1.
D
Grounding — The VCC (pin 24) decoupling capacitor, VREF (pin 23) capacitor, BYPASS (pin 22) capacitor,
COSC (pin 21) capacitor, and ROSC (pin 20) resistor should each be grounded to analog ground (AGND,
pin 18 and pin 19). The PVCC (pin 9 and pin 16) decoupling capacitors should each be grounded to power
ground (PGND, pin 12 and pin 13). Analog ground and power ground may be connected at the PowerPAD,
which should be used as a central ground connection or star ground for the TPA3001D1.
D
D
Output filter — The ferrite filter (Figure 34, page 18) should be placed as close to the output terminals (pins
10, 11, 14, and 15) as possible for the best EMI performance. The LC filter (Figure 35, page 18 and Figure
36, page 19) should be placed close to the ferrite filter. The capacitors used in both the ferrite and LC filters
should be grounded to power ground.
PowerPAD — The PowerPAD must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the PowerPAD thermal land should be 1.6 mm by 6.0 mm (63 mils by 236.2
mils). Two rows of solid vias (four vias per row, 0.3302 mm or 13 mils diameter) should be equally spaced
underneath the thermal land. The vias should connect to a solid copper plane, either on an internal layer
or on the bottom layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. For
additional information, please refer to the PowerPAD Thermally Enhanced Package application note, TI
literature number SLMA002.
For an example layout, please refer to the TPA3001D1 Evaluation Module (TPA3001D1EVM) User Manual, TI
literature number SLOU156. Both the EVM user manual and the PowerPAD application note are available on
the TI web site at http://www.ti.com.
24
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ꢀ ꢁꢂ ꢃꢄꢄ ꢅꢆ ꢅ
SLOS398A − DECEMBER 2002 − REVISED APRIL 2003
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE
20 PINS SHOWN
0,30
0,19
0,65
20
M
0,10
11
Thermal Pad
(See Note D)
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
1
10
0,25
A
0°−ā8°
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
28
DIM
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4073225/F 10/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusions.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
25
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