TPA3112D1PWP [TI]
25-W FILTER-FREE MONO CLASS-D AUDIO POWER AMPLIFIER with SPEAKER GUARD?; 25 -W无滤波器单声道D类音频功率放大器和音箱网罩™
| 型号： | TPA3112D1PWP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 25-W FILTER-FREE MONO CLASS-D AUDIO POWER AMPLIFIER with SPEAKER GUARD? |
| 文件： | 总27页 (文件大小：842K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPA3112D1
www.ti.com
SLOS654A –SEPTEMBER 2009–REVISED JULY 2010
25-W FILTER-FREE MONO CLASS-D AUDIO POWER AMPLIFIER with SPEAKER GUARD™
Check for Samples: TPA3112D1
1
FEATURES
DESCRIPTION
2
•
25-W into an 8-Ω Load at < 0.1% THD+N From
a 24V Supply
The TPA3112D1 is a 25-W efficient, Class-D audio
power amplifier for driving a bridge tied speaker.
Advanced EMI Suppression Technology enables the
use of inexpensive ferrite bead filters at the outputs
while meeting EMC requirements. SpeakerGuard™
speaker protection system includes an adjustable
•
•
•
20-W into an 4-Ω Load at 10% THD+N From a
12-V Supply
94% Efficient Class-D Operation into 8-Ω Load
Eliminates Need for Heat Sinks
Wide Supply Voltage Range Allows Operation
from 8 to 26 V
power limiter and
a DC detection circuit. The
adjustable power limiter allows the user to set a
"virtual" voltage rail lower than the chip supply to limit
the amount of current through the speaker. The DC
detect circuit measures the frequency and amplitude
of the PWM signal and shuts off the output stage if
the input capacitors are damaged or shorts exist on
the inputs.
•
•
Filter-Free Operation
SpeakerGuard™ Speaker Protection Includes
Adjustable Power Limiter plus DC Protection
•
•
Flow Through Pin Out Facilitates Easy Board
Layout
Robust Pin-to-Pin Short Circuit Protection and
Thermal Protection with Auto-Recovery Option
The TPA3112D1 can drive a mono speaker as low as
4Ω. The high efficiency of the TPA3112D1, > 90%,
eliminates the need for an external heat sink when
playing music.
•
•
•
Excellent THD+N/ Pop Free Performance
Four Selectable, Fixed Gain Settings
Differential Inputs
The outputs are fully protected against shorts to
GND, VCC, and output-to-output. The short-circuit
protection and thermal protection includes an
auto-recovery feature.
APPLICATIONS
•
Televisions
•
Consumer Audio Equipment
1uF
OUT+
INP
INN
TPA3112D1
Audio
Source
-
OUT
OUTP
OUTN
25W
8Ω
GAIN0
GAIN1
PLIMIT
Fault
SD
PVCC
8 to 26V
Figure 1. Simplified Application Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
SpeakerGuard is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
TPA3112D1
SLOS654A –SEPTEMBER 2009–REVISED JULY 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
VCC
Supply voltage
AVCC, PVCC
SD, FAULT,GAIN0, GAIN1
PLIMIT
–0.3 V to 30 V
–0.3 V to VCC + 0.3 V
–0.3 V toGVDD + 0.3 V
–0.3 V to 6.3 V
See Dissipation Rating Table
–40°C to 85°C
–40°C to 150°C
–65°C to 150°C
3.2
VI
Interface pin voltage
INN, INP
Continuous total power dissipation
Operating free-air temperature range
Operating junction temperature range(2)
Storage temperature range
TA
TJ
Tstg
RL
Minimum Load Resistance
BTL
Human body model (3) (all pins)
Charged-device model (4) (all pins)
±2 kV
Electrostatic discharge
±500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The TPA3112D1 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical
Briefs SLMA002 for more information about using the HTQFP thermal pad.
(3) In accordance with JEDEC Standard 22, Test Method A114-B.
(4) In accordance with JEDEC Standard 22, Test Method C101-A
TYPICAL DISSIPATION RATINGS
PACKAGE(1)
TA ≤ 25°C
DERATING FACTOR
TA = 85°C
qJP
yJT
28 pin TSSOP
(PWP)
0.72
°C/W
4.98 W
25.1 °C/W
2.59 W
0.45 °C/W
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Supply voltage
TEST CONDITIONS
MIN
8
MAX
UNIT
V
VCC
VIH
VIL
VOL
IIH
PVCC, AVCC
26
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level input current
Low-level input current
Operating free-air temperature
SD, GAIN0, GAIN1
2
V
SD, GAIN0, GAIN1
0.8
0.8
50
5
V
FAULT, RPULLUP=100kΩ, VCC=26V
SD, GAIN0, GAIN1, VI = 2, VCC = 18 V
SD, GAIN0, GAIN1, VI = 0.8V, VCC = 18 V
V
µA
µA
°C
IIL
TA
–40
85
2
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SLOS654A –SEPTEMBER 2009–REVISED JULY 2010
DC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VI = 0 V, Gain = 36 dB
SD = 2 V, no load, PVcc=21V
MIN
TYP MAX UNIT
Class-D output offset voltage (measured
differentially)
| VOS
|
1.5
15
mV
ICC
ICC(SD)
Quiescent supply current
40
400
240
240
20
mA
µA
Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVcc=21V
High Side
IO = 500 mA,
Drain-source on-state resistance
TJ = 25°C
rDS(on)
mΩ
dB
Low side
GAIN0 = 0.8 V
GAIN0 = 2 V
GAIN0 = 0.8 V
GAIN0 = 2 V
19
25
31
35
21
27
33
37
GAIN1 = 0.8 V
26
G
Gain
32
GAIN1 = 2 V
dB
36
tON
Turn-on time
SD = 2 V
10
ms
ms
V
tOFF
Turn-off time
SD = 0.8 V
IGVDD = 2mA
2
GVDD
Gate Drive Supply
6.5
6.9
7.3
DC CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VI = 0 V, Gain = 36 dB
SD = 2 V, no load, PVcc=12V
MIN
TYP MAX UNIT
Class-D output offset voltage (measured
differentially)
| VOS
|
1.5
15
mV
ICC
ICC(SD)
Quiescent supply current
20
200
240
240
20
mA
µA
Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVcc=12V
High Side
IO = 500 mA,
Drain-source on-state resistance
TJ = 25°C
rDS(on)
mΩ
dB
Low side
GAIN0 = 0.8 V
GAIN0 = 2 V
GAIN0 = 0.8 V
GAIN0 = 2 V
19
25
31
35
21
27
33
37
GAIN1 = 0.8 V
26
G
Gain
32
GAIN1 = 2 V
dB
36
tON
Turn-on time
SD = 2 V
10
ms
ms
V
tOFF
Turn-off time
SD = 0.8 V
2
GVDD
PLIMIT
Gate Drive Supply
IGVDD = 2mA
6.5
6.9
7.3
Output Voltage maximum under PLIMIT
control
VPLIMIT=2.0 V; VI=6.0V differential
6.75
7.90 8.75
V
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AC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
200 mVPP ripple from 20 Hz–1 kHz,
Gain = 20 dB, Inputs ac-coupled to AGND
KSVR
PO
Power Supply ripple rejection
Continuous output power
–70
dB
THD+N ≤ 0.1%, f = 1 kHz, VCC = 24 V
25
<0.05
65
W
%
THD+N Total harmonic distortion + noise
VCC = 24 V, f = 1 kHz, PO = 12 W (half-power)
µV
dBV
dB
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
VO = 1 Vrms, Gain = 20 dB, f = 1 kHz
–80
Crosstalk
–70
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
SNR
fOSC
Signal-to-noise ratio
102
dB
Oscillator frequency
Thermal trip point
Thermal hysteresis
250
310 350
kHz
°C
150
15
°C
AC CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
200 mVPP ripple from 20 Hz–1 kHz,
Gain = 20 dB, Inputs ac-coupled to AGND
KSVR
Supply ripple rejection
–70
dB
PO
PO
Continuous output power
Continuous output power
THD+N ≤ 10%, f = 1 kHz , RL = 8Ω
THD+N ≤ 10%, f = 1 kHz , RL = 4Ω
RL = 8 Ω, f = 1 kHz, PO = 5 W (half-power)
10
20
W
W
THD+N Total harmonic distortion + noise
<0.06
65
%
µV
dBV
dB
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
–80
–70
Crosstalk
Po = 1 W, Gain = 20 dB, f = 1 kHz
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
SNR
fOSC
Signal-to-noise ratio
102
dB
Oscillator frequency
Thermal trip point
Thermal hysteresis
250
310 350
kHz
°C
150
15
°C
PWP (TSSOP) Package
(Top View)
1
2
28
27
SD
PVCC
PVCC
BSN
FAULT
3
4
5
6
26
25
24
23
GND
GND
OUTN
PGND
OUTN
GAIN0
GAIN1
7
22
21
20
19
18
17
16
15
AVCC
AGND
GVDD
PLIMIT
BSN
8
BSP
9
OUTP
PGND
OUTP
BSP
10
11
12
13
14
INN
INP
PVCC
PVCC
NC
AVCC
4
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SLOS654A –SEPTEMBER 2009–REVISED JULY 2010
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
Pin #
Shutdown logic input for audio amp(LOW = outputs Hi-Z, HIGH = outputs enabled).
TTL logic levels with compliance to AVCC.
SD
1
I
Open drain output used to display short circuit or dc detect fault status. Voltage
compliant to AVCC. Short circuit faults can be set to auto-recovery by connecting
FAULT pin to SD pin. Otherwise both the short circuit faults and dc detect faults
must be reset by cycling PVCC.
FAULT
2
O
GND
3
4
5
6
7
8
Connect to local ground
GND
Connect to local ground
GAIN0
GAIN1
AVCC
AGND
I
I
Gain select least significant bit. TTL logic levels with compliance to AVCC.
Gain select most significant bit. TTL logic levels with compliance to AVCC.
Analog supply.
P
Analog supply ground. Connect to the thermal pad.
High-side FET gate drive supply. Nominal voltage is 7V. May also be used as
supply for PLILMIT divider. Add a 1mF cap to ground at this pin.
GVDD
9
O
I
Power limit level adjust. Connect directly to GVDD pin for no power limiting. Add a
1mF cap to ground at this pin.
PLIMIT
10
INN
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I
I
Negative audio input. Biased at 3V.
INP
Positive audio input. Biased at 3V.
NC
Not connected
AVCC
PVCC
PVCC
BSP
P
P
P
I
Connect AVCC supply to this pin
Power supply for H-bridge. PVCC pins are also connected internally.
Power supply for H-bridge. PVCC pins are also connected internally.
Bootstrap I/O for positive high-side FET.
Class-D H-bridge positive output.
OUTP
PGND
OUTP
BSP
O
Power ground for the H-bridges.
O
I
Class-D H-bridge positive output.
Bootstrap I/O for positive high-side FET.
Bootstrap I/O for negative high-side FET.
Class-D H-bridge negative output.
BSN
I
OUTN
PGND
OUTN
BSN
O
Power ground for the H-bridges.
O
I
Class-D H-bridge negative output.
Bootstrap I/O for negative high-side FET.
Power supply for H-bridge. PVCC pins are also connected internally.
Power supply for H-bridge. PVCC pins are also connected internally.
PVCC
PVCC
P
P
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FUNCTIONAL BLOCK DIAGRAM
GVDD
PVCC
BSP
PVCC
OUTP FB
OUTP FB
INP
PWM
Gain
Gate
Drive
PLIMIT
Logic
OUTP
PGND
Control
INN
OUTN FB
FAULT
SD
TTL
Buffer
GAIN0
Gain
Control
GAIN1
PLIMIT
PLIMIT
Reference
GVDD
PVCC
BSN
AVDD
PVCC
LDO
AVCC
Regulator
SC Detect
DC Detect
GVDD
Gate
Drive
OUTN
PGND
Biases and
References
GVDD
Ramp
Startup Protection
Logic
Generator
Thermal
Detect
OUTN FB
UVLO/OVLO
AGND
6
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SLOS654A –SEPTEMBER 2009–REVISED JULY 2010
TYPICAL CHARACTERISTICS
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3112D2 EVM which is
available at ti.com.)
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
10
1
10
1
Gain = 20 dB
= 12 V
Z = 8 Ω + 66 µH
L
Gain = 20 dB
V = 24 V
CC
Z = 8 Ω + 66 µH
L
V
CC
P
O
= 1 W
0.1
0.1
P
O
= 1 W
0.01
0.001
0.01
0.001
P
= 10 W
O
P
= 5 W
1k
O
P
O
= 5 W
P
= 2.5 W
O
20
100
10k 20k
20
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
G001
G002
Figure 2.
Figure 3.
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
FREQUENCY
OUTPUT POWER
10
1
10
1
Gain = 20 dB
= 12 V
Z = 4 Ω + 33 µH
L
Gain = 20 dB
V
V
CC
= 12 V
CC
Z = 8 Ω + 66 µH
L
P
O
= 5 W
f = 1 kHz
f = 20 Hz
P
O
= 10 W
0.1
0.1
0.01
0.001
0.01
0.001
P
O
= 1 W
f = 10 kHz
20
100
1k
10k 20k
0.01
0.1
1
10
30
f − Frequency − Hz
P
O
− Output Power − W
G003
G004
Figure 4.
Figure 5.
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TYPICAL CHARACTERISTICS (continued)
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3112D2 EVM which is
available at ti.com.)
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
OUTPUT POWER
OUTPUT POWER
10
1
10
1
Gain = 20 dB
Gain = 20 dB
V
CC
= 24 V
V
CC
= 12 V
Z = 8 Ω + 66 µH
L
Z = 4 Ω + 33 µH
L
f = 1 kHz
f = 20 Hz
f = 1 kHz
f = 20 Hz
0.1
0.1
0.01
0.001
0.01
0.001
f = 10 kHz
0.1
f = 10 kHz
0.01
0.1
1
10
30
0.01
1
10
30
P
O
− Output Power − W
P
O
− Output Power − W
G005
G006
Note: Dashed lines represent thermally limited region.
Figure 6.
Figure 7.
MAXIMUM OUTPUT POWER
OUTPUT POWER
vs
vs
PLIMIT VOLTAGE
PLIMIT VOLTAGE
30
25
20
15
10
5
30
Gain = 20 dB
= 12 V
Z = 4 Ω + 33 µH
L
Gain = 20 dB
V
V
CC
= 24 V
CC
Z = 8 Ω + 66 µH
L
25
20
15
10
5
0
0.0
0
0.5
1.0
V
1.5
2.0
2.5
3.0
3.5
4.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
− PLIMIT Voltage − V
V
PLIMIT
− PLIMIT Voltage − V
PLIMIT
G008
G007
Note: Dashed line represents thermally limited region.
Figure 8.
Figure 9.
8
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TYPICAL CHARACTERISTICS (continued)
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3112D2 EVM which is
available at ti.com.)
GAIN/PHASE
vs
EFFICIENCY
vs
FREQUENCY
OUTPUT POWER
100
100
90
80
70
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
50
V
CC
= 24 V
Phase
0
V
CC
= 12 V
−50
−100
−150
−200
−250
−300
Gain
C = 1 µF
Gain = 20 dB
I
Filter = Audio Precision AUX-0025
= 12 V
V
CC
V = 0.1 Vrms
I
Z
L
= 8 Ω + 66 µH
Gain = 20 dB
Z = 8 Ω + 66 µH
0
10
L
100
1k
10k
100k
f − Frequency − Hz
G009
0
5
10
15
20
25
30
P
O
− Output Power − W
G012
Note: Dashed line represents thermally limited region.
Figure 10.
Figure 11.
EFFICIENCY
vs
SUPPLY CURRENT
vs
OUTPUT POWER
TOTAL OUTPUT POWER
1.2
100
90
80
70
60
50
40
30
20
10
0
Gain = 20 dB
Z = 8 Ω + 66 µH
L
1.0
0.8
0.6
0.4
0.2
0.0
V
CC
= 24 V
V
CC
= 12 V
V
CC
= 12 V
V
CC
= 24 V
Gain = 20 dB
Z = 4 Ω + 33 µH
L
0
5
10
15
20
25
30
0
5
10
15
20
25
30
P
O
− Output Power − W
P
O(Tot)
− Total Output Power − W
G013
G014
Note: Dashed line represents thermally limited region.
Note: Dashed line represents thermally limited region.
Figure 12.
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3112D2 EVM which is
available at ti.com.)
SUPPLY CURRENT
vs
SUPPLY RIPPLE REJECTION RATIO
vs
TOTAL OUTPUT POWER
FREQUENCY
0
−20
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Gain = 20 dB
= 12 V
Z = 8 Ω + 66 µH
L
Gain = 20 dB
= 12 V
Z = 4 Ω + 33 µH
L
V
CC
V
CC
−40
−60
−80
−100
−120
20
100
1k
10k 20k
0
5
10
15
20
25
30
f − Frequency − Hz
P
O(Tot)
− Total Output Power − W
G016
G015
Figure 14.
Figure 15.
DEVICE INFORMATION
Gain setting via GAIN0 and GAIN1 inputs
The gain of the TPA3112D1 is set by two input terminals, GAIN0 and GAIN1. The voltage slew rate of these gain
terminals, along with terminals 1 and 14, must be restricted to no more than 10V/ms. For higher slew rates, use
a 100kΩ resistor in series with the terminals.
The gains listed in Table 1 are realized by changing the taps on the input resistors inside the amplifier. This
causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings are controlled by
ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part
at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 7.2 kΩ, which is the absolute minimum input impedance of the TPA3112D1. At the lower gain
settings, the input impedance could increase as high as 72 kΩ
Table 1. Gain Setting
INPUT IMPEDANCE
AMPLIFIER GAIN (dB)
(kΩ)
TYP
60
GAIN1
GAIN0
TYP
20
0
0
1
1
0
1
0
1
26
30
32
15
36
9
10
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SD OPERATION
The TPA3112D1 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of nonuse for power conservation. The SD input terminal should be held high (see
specification table for trip point) during normal operation when the amplifier is in use. Pulling SD low causes the
outputs to mute and the amplifier to enter a low-current state. Never leave SD unconnected, because amplifier
operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power
supply voltage.
PLIMIT
The voltage at pin 10 can used to limit the power to levels below that which is possible based on the supply rail.
Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also
be used if tighter tolerance is required. Also add a 1mF capacitor from pin 10 to ground.
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. This limit can be thought of as a "virtual"
voltage rail which is lower than the supply connected to PVCC. This "virtual" rail is 4 times the voltage at the
PLIMIT pin. This output voltage can be used to calculate the maximum output power for a given maximum input
voltage and speaker impedance.
TPA3112D1 PLimit Operation
Figure 16. PLIMIT Circuit Operation
The PLIMIT circuits sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle
to fixed maximum value. This limit can be thought of as a “virtual” voltage rail which is lower than the supply
connected to PVCC. This “virtual” rail is 4 times the voltage at the PLIMIT pin. This output voltage can be used to
calculate the maximum output power for a given maximum input voltage and speaker impedance.
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æ
ö2
æ
ç
è
ö
÷
ø
RL
´ V
ç
÷
P
ç
÷
RL + 2´RS
è
ø
POUT
=
for unclipped power
2´RL
(1)
Where:
RS is the total series resistance including RDS(on), and any resistance in the output filter.
RL is the load resistance.
VP is the peak amplitude of the output possible within the supply rail.
VP = 4 × PLIMIT voltage if PLIMIT < 4 × VP
POUT(10%THD) = 1.25 × POUT(unclipped)
Table 2. PLIMIT Typical Operation
Output Voltage
Test Conditions ()
PLIMIT Voltage
Output Power (W)
Amplitude (VP-P
)
PVCC=24V, Vin=1Vrms,
RL=4Ω, Gain=20dB
6.97
1.92
1.24
6.95
1.75
1.20
22.1
10
5
26.9
PVCC=24V, Vin=1Vrms,
RL=4Ω, Gain=20dB
15.0
10.0
20.9
15.3
10.3
PVCC=24V, Vin=1Vrms,
RL=4Ω, Gain=20dB
PVCC=12V, Vin=1Vrms,
RL=4Ω, Gain=20dB
17.2
10
5
PVCC=12V, Vin=1Vrms,
RL=4Ω, Gain=20dB
PVCC=12V, Vin=1Vrms,
RL=4Ω, Gain=20dB
GVDD Supply
The GVDD Supply is used to power the gates of the output full bridge transistors. It can also used to supply the
PLIMIT voltage divider circuit. Add a 1mF capacitor to ground at this pin.
DC Detect
TPA3112D1 has circuitry which will protect the speakers from DC current which might occur due to defective
capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault will be reported on
the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by changing the
state of the outputs to Hi-Z. To clear the DC Detect it is necessary to cycle the PVCC supply. Cycling SD will
NOT clear a DC detect fault.
A DC Detect Fault is issued when the output differential duty-cycle exceeds 14% (eg. +57%, -43%) for more than
420 ms at the same polarity. This feature protects the speaker from large DC currents or AC currents less than 2
Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at power-up until the signals at the
inputs are stable. Also, take care to match the impedance seen at the positive and negative input to avoid
nuisance DC detect faults.
The minimum differential input voltages required to trigger the DC detect are shown in Table Table 3. The inputs
must remain at or above the voltage listed in the table for more than 420 ms to trigger the DC detect.
Table 3. DC Detect Threshold
AV(dB)
20
Vin (mV, differential)
112
56
26
32
28
36
17
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SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATURE
TPA3112D2 has protection from over-current conditions caused by a short circuit on the output stage. The short
circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are switched to a Hi-Z
state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SD pin through
the low state.
If automatic recovery from the short circuit protection latch is desired, connect the FAULT pin directly to the SD
pin. This will allow the FAULT pin function to automatically drive the SD pin low which will clear the short circuit
protection latch.
THERMAL PROTECTION
Thermal protection on the TPA3112D1 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not
a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The device
begins normal operation at this point with no external system interaction.
Thermal protection faults are NOT reported on the FAULT terminal.
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APPLICATION INFORMATION
PVCC
100 μF
0.1 μF
1000pF
100k Ω
Control
System
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
SD
PVCC
PVCC
BSN
1 kΩ
FAULT
GND
GND
GAIN0
GAIN1
AVCC
AGND
GVDD
PLIMIT
INN
3
0.47 μF
4
OUTN
PGND
OUTN
BSN
5
FB
6
AVCC
1000 pF
7
PVCC
10 Ω
TPA3112D1
1 uF
1 uF
8
BSP
1000 pF
9
OUTP
PGND
OUTP
BSP
FB
10
11
12
13
0.47 μF
1 uF
Audio
Source
INP
1 uF
NC
PVCC
0.1 μF
100 μF
14
15
1000pF
AVCC
PVCC
AVCC
GND
29
PowerPAD
PVCC
Figure 17. Mono Class-D Amplifier with BTL Output
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CLASS-D OPERATION
This section focuses on the class-D operation of the TPA3112D1.
TPA3112D1 Modulation Scheme
The TPA3112D1 uses a modulation scheme that allows operation without the classic LC reconstruction filter
when the amp is driving an inductive load. Each output is switching from 0 volts to the supply voltage. The OUTP
and OUTN are in phase with each other with no input so that there is little or no current in the speaker. The duty
cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of
OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load
sits at 0 V throughout most of the switching period, greatly reducing the switching current, which reduces any I2R
losses in the load.
OUTP
OUTN
Output = 0 V
Differential
+12 V
Voltage
0 V
Across
-12 V
Load
Current
OUTP
OUTN
Output > 0 V
Differential
Voltage
Across
Load
+12 V
0 V
-12 V
Current
Figure 18. The TPA3112D1 Output Voltage and Current Waveforms Into an Inductive Load
Ferrite Bead Filter Considerations
Using the Advanced Emissions Suppression Technology in the TPA3112D1 amplifier it is possible to design a
high efficiency Class-D audio amplifier while minimizing interference to surrounding circuits. it is also possible to
accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite
bead used in the filter.
One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite
material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to
the operation of the Class D amplifier. Many of the specifications regulating consumer electronics have
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emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30 MHz
and above range from appearing on the speaker wires and the power supply lines which are good antennas for
these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the
range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance,
the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz.
Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected
for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In
this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak
current the amplifier will see. If these specifications are not available, it is also possible to estimate the bead
current handling capability by measuring the resonant frequency of the filter output at very low power and at
maximum power. A change of resonant frequency of less than fifty percent under this condition is desirable.
Examples of ferrite beads which have been tested and work well with the TPA3112D2 include 28L0138-80R-10
and HI1812V101R-10 from Steward and the 742792510 from Wurth Electronics.
A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good
temperature and voltage characteristics will work best.
Additional EMC improvements may be obtained by adding snubber networks from each of the class D outputs to
ground. Suggested values for a simple RC series snubber network would be 10 ohms in series with a 330 pF
capacitor although design of the snubber network is specific to every application and must be designed taking
into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate
the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make
sure the layout of the snubber network is tight and returns directly to the PGND or the PowerPad beneath the
chip.
Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 x VCC, and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA3112D1 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 x VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
When to Use an Output Filter for EMI Suppression
The TPA3112D1 has been tested with a simple ferrite bead filter for a variety of applications including long
speaker wires up to 125 cm and high power. The TPA3112D1 EVM passes FCC Class B specifications under
these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet
application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency.
There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These
circumstances might occur if there are circuits near which are sensitive to noise. Therefore, a classic second
order Butterworth filter similar to those shown in Figure 19 through Figure 21 can be used.
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33 mH
OUTP
OUTN
C2
L1
1 mF
33 mH
C3
L2
1 mF
Figure 19. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω
15 mH
OUTP
C2
L1
2.2 mF
15 mH
OUTN
C3
2.2 mF
L2
Figure 20. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 4 Ω
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 21. Typical Ferrite Chip Bead Filter (Chip Bead Example: Steward HI0805R800R-10)
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INPUT RESISTANCE
Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 9 kΩ ±20%, to the
largest value, 60 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or
cutoff frequency may change when changing gain steps.
Z
f
C
i
Z
i
IN
Input
Signal
The -3-dB frequency can be calculated using Equation 2. Use the ZI values given in Table 1.
1
f =
2p Zi Ci
(2)
INPUT CAPACITOR, CI
In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a
high-pass filter with the corner frequency determined in Equation 3.
-3 dB
1
2p Zi Ci
fc
=
f
c
(3)
The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where ZI is 60 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 3 is
reconfigured as Equation 4.
1
Ci =
2p Zi fc
(4)
In this example, CI is 0.13 µF; so, one would likely choose a value of 0.15 mF as this value is commonly used. If
the gain is known and is constant, use ZI from Table 1 to calculate CI. A further consideration for this capacitor is
the leakage path from the input source through the input network ©I) and the feedback network to the load. This
leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially
in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. If a
ceramic capacitor is used, use a high quality capacitor with good temperature and voltage coefficient. An X7R
type works well and if possible use a higher voltage rating than required. This will give a better C vs voltage
characteristic. When polarized capacitors are used, the positive side of the capacitor should face the amplifier
input in most applications as the dc level there is held at 3 V, which is likely higher than the source dc level. Note
that it is important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc
offset voltages and it is important to ensure that boards are cleaned properly.
POWER SUPPLY DECOUPLING, CS
The TPA3112D1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker.
Optimum decoupling is achieved by using a network of capacitors of different types that target specific types of
noise on the power supply leads. For higher frequency transients due to parasitic circuit elements such as bond
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wire and copper trace inductances as well as lead frame capacitance,
a
good quality low
equivalent-series-resistance (ESR) ceramic capacitor of value between 220 pF and 1000 pF works well. This
capacitor should be placed as close to the device PVCC pins and system ground (either PGND pins or
PowerPad) as possible. For mid-frequency noise due to filter resonances or PWM switching transients as well as
digital hash on the line, another good quality capacitor typically 0.1 mF to 1 mF placed as close as possible to the
device PVCC leads works best For filtering lower frequency noise signals, a larger aluminum electrolytic
capacitor of 220 mF or greater placed near the audio power amplifier is recommended. The 220 mF capacitor
also serves as a local storage capacitor for supplying current during large signal transients on the amplifier
outputs. The PVCC terminals provide the power to the output transistors, so a 220 mF or larger capacitor should
be placed on each PVCC terminal. A 10 mF capacitor on the AVCC terminal is adequate. Also, a small
decoupling resistor between AVCC and PVCC can be used to keep high frequency class D noise from entering
the linear input amplifiers.
BSN and BSP CAPACITORS
The full H-bridge output stage uses only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 220-nF capacitor must be
connected from OUTP to BSP, and one 220-nF capacitor must be connected from OUTN to BSN. (See the
application circuit diagram in Figure 1.)
The bootstrap capacitors connected between the BSx pins and corresponding output function as a floating power
supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle,
the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on.
DIFFERENTIAL INPUTS
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3112D1 with a differential source, connect the positive lead of the audio source to the INP input and
the negative lead from the audio source to the INN input. To use the TPA3112D1 with a single-ended source, ac
ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply
the audio source to either input. In a single-ended input application, the unused input should be ac grounded at
the audio source instead of at the device input for best noise performance. For good transient performance, the
impedance seen at each of the two differential inputs should be the same.
The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to
allow the input dc blocking capacitors to become completely charged during the 14 msec power-up time. If the
input capacitors are not allowed to completely charge, there will be some additional sensitivity to component
matching which can result in pop if the input components are not well matched.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.
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PRINTED-CIRCUIT BOARD (PCB) LAYOUT
The TPA3112D1 can be used with a small, inexpensive ferrite bead output filter for most applications. However,
since the Class-D switching edges are very fast, it is necessary to take care when planning the layout of the
printed circuit board. The following suggestions will help to meet EMC requirements.
•
Decoupling capacitors—The high-frequency decoupling capacitors should be placed as close to the PVCC
and AVCC terminals as possible. Large (220 mF or greater) bulk power supply decoupling capacitors should
be placed near the TPA3112D1 on the PVCC supplies. Local, high-frequency bypass capacitors should be
placed as close to the PVCC pins as possible. These caps can be connected to the thermal pad directly for
an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between
220 pF and 1000 pF and a larger mid-freqency cap of value between 0.1mF and 1mF also of good quality to
the PVCC connections at each end of the chip.
•
•
•
Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to
PGND as small and tight as possible. The size of this current loop determines its effectiveness as an
antenna.
Output filter—The ferrite EMI filter should be placed as close to the output terminals as possible for the best
EMI performance. The LC filter should be placed close to the outputs. The capacitors used in both the ferrite
and LC filters should be grounded to power ground.
Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the thermal pad and thermal land should be 6.46 mm by 2.35 mm. Seven rows
of solid vias (three vias per row, 0.33 mm or 13 mils diameter) should be equally spaced underneath the
thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom
layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See TI Application Report
SLMA002 for more information about using the TSSOP thermal pad.
For an example layout, see the TPA3112D1 Evaluation Module (TPA3112D1EVM) User Manual. Both the EVM
user manual and the thermal pad application note are available on the TI Web site at http://www.ti.com.
SPACER
REVISION HISTORY
Changes from Original (September 2009) to Revision A
Page
•
•
Added slew rate adjustment information ............................................................................................................................. 10
Added updates for figure 17, pin 7 ..................................................................................................................................... 14
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PACKAGE OPTION ADDENDUM
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19-Jun-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPA3112D1PWP
TPA3112D1PWPR
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
28
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jun-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA3112D1PWPR
HTSSOP PWP
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jun-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 28
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
TPA3112D1PWPR
2000
Pack Materials-Page 2
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
www.ti.com/audio
Data Converters
DLP® Products
Automotive
www.ti.com/automotive
www.ti.com/communications
Communications and
Telecom
DSP
dsp.ti.com
Computers and
Peripherals
www.ti.com/computers
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
Consumer Electronics
Energy
www.ti.com/consumer-apps
www.ti.com/energy
Logic
Industrial
www.ti.com/industrial
Power Mgmt
Microcontrollers
RFID
power.ti.com
Medical
www.ti.com/medical
microcontroller.ti.com
www.ti-rfid.com
Security
www.ti.com/security
Space, Avionics &
Defense
www.ti.com/space-avionics-defense
RF/IF and ZigBee® Solutions www.ti.com/lprf
Video and Imaging
Wireless
www.ti.com/video
www.ti.com/wireless-apps
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