TPA3116D2QDADRQ1 [TI]
汽车类 50W、2 通道、4.5V 至 26V 电源模拟输入 D 类音频放大器 | DAD | 32 | -40 to 125;
| 型号： | TPA3116D2QDADRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 50W、2 通道、4.5V 至 26V 电源模拟输入 D 类音频放大器 | DAD | 32 | -40 to 125 放大器 光电二极管 商用集成电路 音频放大器 |
| 文件： | 总40页 (文件大小：2734K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPA3116D2-Q1, TPA3118D2-Q1
ZHCSE21A –JULY 2015–REVISED AUGUST 2015
TPA311xD2-Q1 100W 和 50W D 类立体声汽车用放大器
1 特性
2 应用范围
1
•
支持多路输出配置
•
•
•
车载音频
紧急呼叫
驾驶员通知
–
21V 电压、4Ω 桥接负载 (BTL) 负载条件下的功
率为 2 × 50W (TPA3116D2-Q1)
–
24V 电压、8Ω BTL 负载条件下的功率为 2 ×
3 说明
30W (TPA3118D2-Q1)
•
•
宽电压范围：4.5V 至 26V
高效 D 类运行
TPA311xD2-Q1 器件是用于驱动扬声器的汽车类高效
立体声数字放大器功率级，单声道模式下的驱动功率高
达 100W/2Ω。 TPA3118D2-Q1 甚至可以在不使用外
部散热器的情况下在双层 PCB 上提供 2 × 30W/8Ω 的
功率。 如果需要更高的功率，可以选用 TPA3116D2-
Q1，这款器件在其顶层散热焊盘上连接一个小型散热
器后可提供 2 × 50W/4Ω 的功率。
–
兼具 > 90% 的功率效率与低空闲损耗特性，大
幅减小了散热器尺寸
–
高级调制系统配置
•
多重开关频率
–
–
–
AM 抑制
主从模式同步
TPA311xD2-Q1 高级振荡器和 PLL 电路采用多开关频
率选项来抑制 AM 干扰；搭配使用主从模式选项时，
还可使多个器件实现同步。
高达 1.2MHz 的切换频率
•
采用具有高 PSRR 的反馈功率级架构，降低了
PSU 需求
•
•
•
•
•
可编程功率限制
TPA311xD2-Q1 器件针对短路、过热、过压、欠压和
直流等故障提供了全面保护。 在过载情况下，器件会
将故障情况报告给处理器，从而避免自身遭到损坏。
差分和单端输入
立体声 BTL 和单声道并行桥接负载 (PBTL) 模式
由单电源供电运行，减少了元件数量
器件信息(1)
封装
集成了具有错误报告功能的自保护电路，其中包括
过压、欠压、过热、直流检测和短路等保护
器件
散热焊盘
顶层
TPA3116D2-Q1
TPA3118D2-Q1
•
•
旨在满足汽车电磁兼容性 (EMC) 要求
HTSSOP (32)
底层
耐热增强型封装
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
–
DAD（32 引脚散热薄型小外形尺寸 (HTSSOP)
封装，焊盘朝上）
简化应用电路
–
–
DAP（32 引脚 HTSSOP 封装，焊盘朝下）
-40°C 至 125°C 环境温度范围
4.5-V to
26-V PSU
Audio Processor
TPA3116D2-Q1
and Control
AM/FM Tuner
Right
•
•
符合汽车应用要求
PBTL
Detect
Left
Right
Left
LC Filter
LC Filter
CD or MP3
Aux In
具有符合 AEC-Q100 的下列结果：
SD
–
–
–
器件温度 1 级：-40°C 至 125°C 的环境运行温
度范围
MUTE
FAULT
AM/FM Avoidance
Control
AM2,1,0
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 H2
GAIN Control and Master or Slave Setting
Power Limit
GAIN/SLV
PLIMIT
SYNC
Capable of Synchronizing
to Other Devices
器件组件充电模式 (CDM) ESD 分类等级 C4B
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLOS862
TPA3116D2-Q1, TPA3118D2-Q1
ZHCSE21A –JULY 2015–REVISED AUGUST 2015
www.ti.com.cn
目录
7.3 Feature Description................................................. 10
7.4 Device Functional Mode ......................................... 18
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application .................................................. 19
Power Supply Recommendations...................... 22
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 DC Electrical Characteristics .................................... 6
6.6 AC Electrical Characteristics..................................... 7
6.7 Timing Requirements................................................ 7
6.8 Typical Characteristics.............................................. 8
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
8
9
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 23
10.3 Heat Sink Used on the EVM................................. 25
11 器件和文档支持 ..................................................... 26
11.1 器件支持................................................................ 26
11.2 相关链接................................................................ 26
11.3 商标....................................................................... 26
11.4 静电放电警告......................................................... 26
11.5 Glossary................................................................ 26
12 机械、封装和可订购信息....................................... 26
7
4 修订历史记录
Changes from Original (July 2015) to Revision A
Page
•
Added all information following the pin description diagrams................................................................................................. 4
2
Copyright © 2015, Texas Instruments Incorporated
TPA3116D2-Q1, TPA3118D2-Q1
www.ti.com.cn
ZHCSE21A –JULY 2015–REVISED AUGUST 2015
5 Pin Configuration and Functions
DAD PowerPAD™ Package
32-Pin HTSSOP With Exposed Thermal Pad Up
TPA3116D2-Q1 Top View
MODSEL
SD
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PVCC
PVCC
BSPR
OUTPR
GND
2
FAULT
RINP
3
4
RINN
PLIMIT
GVDD
GAIN/SLV
GND
5
6
OUTNR
BSNR
GND
7
8
Thermal
Pad
9
BSPL
OUTPL
GND
LINP
10
11
12
13
14
15
16
LINN
MUTE
AM2
OUTNL
BSNL
PVCC
PVCC
AVCC
AM1
AM0
SYNC
DAP PowerPAD Package
32-Pin HTSSOP With Exposed Thermal Pad Down
TPA3118D2-Q1 Top View
MODSEL
SD
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PVCC
PVCC
BSPR
OUTPR
GND
2
FAULT
RINP
3
4
RINN
5
PLIMIT
GVDD
GAIN/SLV
GND
6
OUTNR
BSNR
GND
7
8
Thermal
Pad
9
BSPL
OUTPL
GND
LINP
10
11
12
13
14
15
16
LINN
MUTE
AM2
OUTNL
BSNL
PVCC
PVCC
AVCC
AM1
AM0
SYNC
Copyright © 2015, Texas Instruments Incorporated
3
TPA3116D2-Q1, TPA3118D2-Q1
ZHCSE21A –JULY 2015–REVISED AUGUST 2015
www.ti.com.cn
Table 1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
AM[2:0]
NO.
13–15
17
I
AM avoidance frequency selection
Analog supply
AVCC
BSNL
BSNR
BSPL
BSPR
FAULT
P
20
BST
BST
BST
BST
DO
Bootstrap for negative left channel output, connect to 220-nF X5R, or better ceramic cap to OUTPL
Bootstrap for negative right channel output, connect to 220-nF X5R, or better ceramic cap to OUTNR
Bootstrap for positive left channel output, connect to 220-nF X5R, or better ceramic cap to OUTNL
Bootstrap for positive right channel output, connect to 220-nF X5R or better ceramic cap to OUTPR
26
24
30
3
General fault reporting including overtemperature, dc detect, open drain.
FAULT = High, normal operation
FAULT = Low, fault condition
GAIN/SLV
GND
8
I
Selects gain and selects between master and slave modes depending on pin voltage divider.
Ground
9, 22,
G
25, 28
GVDD
7
PO
Internally generated gate voltage supply. Not to be used as a supply or connected to any component
other than a 1-µF X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers.
LINN
11
10
1
I
I
I
Negative audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode.
Positive audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode.
LINP
MODSEL
Mode selection logic input (LOW = BD mode, HIGH = 1 SPW mode). TTL logic levels with compliance
to AVCC.
MUTE
12
I
Mute signal for fast disable or enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL
logic levels with compliance to AVCC.
OUTNL
OUTNR
OUTPL
OUTPR
PLIMIT
21
27
23
29
6
PO
PO
PO
PO
I
Negative left-channel output
Negative right-channel output
Positive left-channel output
Positive right-channel output
Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect
directly to GVDD for no power limit.
PVCC
18, 19,
31, 32
P
Power supply
RINN
RINP
SD
5
4
2
I
I
I
Negative audio input for right channel. Biased at 3 V.
Positive audio input for right channel. Biased at 3 V.
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels
with compliance to AVCC.
SYNC
16
—
DIO
G
Clock input/output for synchronizing multiple class-D devices. Direction determined by GAIN/SLV pin.
Connect to GND for best system performance. If not connected to GND, leave floating.
Thermal pad
(1) TYPE: DO = Digital output, I = Analog input, G = General ground, PO = Power output, BST = Bootstrap.
4
Copyright © 2015, Texas Instruments Incorporated
TPA3116D2-Q1, TPA3118D2-Q1
www.ti.com.cn
ZHCSE21A –JULY 2015–REVISED AUGUST 2015
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
VALUE
–0.3 to 30
UNIT
V
Supply voltage, VCC
Input voltage, VI
PVCC, AVCC
INPL, INNL, INPR, INNR
–0.3 to 6.3
V
PLIMIT, GAIN/SLV, SYNC
AM0, AM1, AM2, MUTE, SD, MODSEL
AM0, AM1, AM2, MUTE, SD, MODSEL
–0.3 to GVDD + 0.3
–0.3 to PVCC + 0.3
10
V
V
Slew rate, maximum(2)
V/ms
°C
°C
°C
Operating ambient temperature, TA
–40 to 125
Operating junction temperature range, TJ
Storage temperature range, Tstg
–40 to 150
–40 to 125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) 100-kΩ series resistor is needed if maximum slew rate is exceeded.
6.2 ESD Ratings
VALUE
±2000
±450
UNIT
Human-body model (HBM), per AEC Q100-002(1)
All pins
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC
Q100-011
Corner pins (1, 16, 17,
and 32)
±450
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN NOM
MAX UNIT
VCC
VIH
Supply voltage
PVCC, AVCC
4.5
26
V
High-level input
voltage
AM0, AM1, AM2, MUTE, SD, SYNC, MODSEL
2
V
Low-level input
voltage
VIL
VOL
IIH
AM0, AM1, AM2, MUTE, SD, SYNC, MODSEL
FAULT, RPULLUP = 100 kΩ, V(PVCC) = 26 V
0.8
0.8
50
V
V
Low-level output
voltage
High-level input
current
AM0, AM1, AM2, MUTE, SD, MODSEL (VI = 2 V, VCC = 18 V)
µA
Output filter: L = 10 µH, C = 680 nF, BTL
Output filter: L = 10 µH, C = 1 µF, PBTL
3.2
1.6
4
Minimum load
impedance
RL
Lo
Ω
Output-filter
inductance
Minimum output filter inductance under short-circuit condition
1
µH
Copyright © 2015, Texas Instruments Incorporated
5
TPA3116D2-Q1, TPA3118D2-Q1
ZHCSE21A –JULY 2015–REVISED AUGUST 2015
www.ti.com.cn
6.4 Thermal Information
TPA3116D2-Q1 TPA3118D2-Q1
THERMAL METRIC(1)
DAD
32 PINS
44.7(2)
1.2
DAP
32 PINS
32.4
17.2
17.3
0.4
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
21.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.2
ψJB
21
17.2
1
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Modeled with a 15-mm × 15-mm × 2-mm copper heat slug heat sink. A better heat sink or airflow would yield a much better RθJA
.
Perfect heat sink results could be as low as RθJC(top) = 1.2 ºC/W.
6.5 DC Electrical Characteristics
TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Class-D output offset voltage (measured
differentially)
| VOS
ICC
|
VI = 0 V, gain = 36 dB
1.5
15
mV
mA
SD = 2 V, no load or filter, V(PVCC) = 12 V
SD = 2 V, no load or filter, V(PVCC) = 24 V
SD = 0.8 V, no load or filter, V(PVCC) = 12 V
SD = 0.8 V, no load or filter, V(PVCC) = 24 V
20
32
35
50
Quiescent supply current
<50
50
Quiescent supply current in shutdown
mode
ICC(SD)
rDS(on)
µA
mΩ
dB
400
Drain-source on-state resistance,
measured pin-to-pin
V(PVCC) = 21 V, IO = 500 mA, TJ = 25°C
120
R1 = open, R2 = 20 kΩ
R1 = 100 kΩ, R2 = 20 kΩ
R1 = 100 kΩ, R2 = 39 kΩ
R1 = 75 kΩ, R2 = 47 kΩ
R1 = 51 kΩ, R2 = 51 kΩ
R1 = 47 kΩ, R2 = 75 kΩ
R1 = 39 kΩ, R2 = 100 kΩ
R1 = 16 kΩ, R2 = 100 kΩ
V(SD) = 2 V
19
25
31
35
19
25
31
35
20
26
32
36
20
26
32
36
10
2
21
27
33
37
21
27
33
37
G
G
Gain (BTL)
Gain (SLV)
dB
dB
dB
ton
Turn-on time
ms
µs
V
toff
Turn-off time
V(SD) = 0.8 V
GVDD
Gate drive supply
I(GVDD) < 200 µA
6.4
6.9
7.4
Output voltage maximum under PLIMIT
control
VO
V(PLIMIT) = 2 V; VI = 1 Vrms
6.75
7.9
8.75
V
6
Copyright © 2015, Texas Instruments Incorporated
TPA3116D2-Q1, TPA3118D2-Q1
www.ti.com.cn
ZHCSE21A –JULY 2015–REVISED AUGUST 2015
6.6 AC Electrical Characteristics
TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
200 mVPP ripple at 1 kHz, gain = 20 dB, inputs ac-coupled
to GND
KSVR
PO
Power supply ripple rejection
–70
dB
THD+N = 10%, f = 1 kHz, V(PVCC) = 14.4 V
THD+N = 10%, f = 1 kHz, V(PVCC) = 21 V
VCC = 21 V, f = 1 kHz, PO = 25 W (half-power)
25
50
Continuous output power
W
THD+N Total harmonic distortion + noise
0.1%
65
µV
dBV
dB
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, gain = 20 dB
VO = 1 Vrms, gain = 20 dB, f = 1 kHz
–80
–100
Crosstalk
Maximum output at THD+N < 1%, f = 1 kHz, gain = 20 dB,
A-weighted
SNR
Signal-to-noise ratio
102
dB
AM[2:0] = 000
AM[2:0] = 001
AM[2:0] = 010
AM[2:0] = 011
AM[2:0] = 100
AM[2:0] = 101
AM[2:0] = 110
AM[2:0] = 111
376 400
470 500
564 600
940 1000
1128 1200
424
530
636
1060
kHz
fOSC
Oscillator frequency
1278
Reserved
Thermal trip point
Thermal hysteresis
Overcurrent trip point
150
15
°C
°C
A
7.5
6.7 Timing Requirements
MIN
NOM
MAX
UNIT
td
Delay from MUTE rising to SD falling
1.4
s
td
SD
MUTE
FAULT
mP
TPA3116D2-Q1
SD
MUTE
FAULT
Figure 1. Timing Requirement for SD
Copyright © 2015, Texas Instruments Incorporated
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TPA3116D2-Q1, TPA3118D2-Q1
ZHCSE21A –JULY 2015–REVISED AUGUST 2015
www.ti.com.cn
6.8 Typical Characteristics
fs = 400 kHz, BD mode (unless otherwise noted)
10
10
1
PO = 0.5 W
PO = 1 W
PO = 2.5 W
PO = 1 W
PO = 2.5 W
PO = 5 W
1
0.1
0.1
0.01
0.01
0.001
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
D001
D003
Gain = 26 dB
PVCC = 6 V
TA = 25°C
Gain = 26 dB
PVCC = 14.4 V
TA = 25°C
RL = 4 Ω
10-µH + 0.68-µF filter
RL = 4 Ω
10-µH + 0.68-µF filter
Figure 2. Total Harmonic Distortion + Noise (BTL) vs
Frequency
Figure 3. Total Harmonic Distortion + Noise (BTL) vs
Frequency
10
10
20 Hz
1 kHz
6 kHz
20 Hz
1 kHz
6 kHz
1
0.1
1
0.1
0.01
0.01
0.001
0.001
10m
100m
Output Power (W)
1
10
10m
100m
1
10
40
Output Power (W)
D004
D006
Gain = 26 dB
PVCC = 6 V
TA = 25°C
Gain = 26 dB
PVCC = 14.4 V
TA = 25°C
10-µH + 0.68-µF filter
RL = 4 Ω
10-µH + 0.68-µF filter
RL = 4 Ω
Figure 4. Total Harmonic Distortion + Noise (BTL) vs Output
Power
Figure 5. Total Harmonic Distortion + Noise (BTL) vs Output
Power
30
25
20
15
10
5
100
THD+N = 1%
THD+N = 10%
90
80
70
60
50
40
30
20
10
0
0
1
2
3
4
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage (V)
PLIMIT Voltage (V)
D007
D009
Gain = 26 dB
PVCC = 14.4 V
TA = 25°C
Gain = 26 dB
TA = 25°C
RL = 4 Ω
RL = 4 Ω
10-µH + 0.68-µF filter
10-µH + 0.68-µF filter
Figure 6. Output Power (BTL) vs PLIMIT Voltage
Figure 7. Maximum Output Power (BTL) vs Supply Voltage
8
Copyright © 2015, Texas Instruments Incorporated
TPA3116D2-Q1, TPA3118D2-Q1
www.ti.com.cn
ZHCSE21A –JULY 2015–REVISED AUGUST 2015
Typical Characteristics (continued)
fs = 400 kHz, BD mode (unless otherwise noted)
100
0
-20
Right to Left
Left to Right
90
80
70
60
50
40
30
20
-40
-60
-80
-100
-120
-140
PVCC = 6V
PVCC = 12 V
PVCC = 14.4 V
10
0
0
5
10
15
20
25
30
35
40
45
50
20
100
1k
10k 20k
Output Power (W)
Frequency (Hz)
D010
D011
Gain = 26 dB
TA = 25°C
RL = 4 Ω
10-µH + 0.68-µF filter
Gain = 26 dB
PVCC = 12 V
TA = 25°C
RL = 4 Ω
10-µH + 0.68-µF filter
Figure 8. Power Efficiency (BTL) vs Output Power
Figure 9. Crosstalk vs Frequency
30
20
300
200
100
0
0.5
0.1
PO = 1 W
PO = 2.5 W
PO = 5 W
10
0
-10
-20
-30
-40
-50
-100
-200
-300
-400
-500
0.01
Gain
Phase
0.002
20
100
1k
10k 20k
20
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
D012
D014
Gain = 26 dB
PVCC = 14.4 V
TA = 25°C
PVCC = 14.4 V
TA = 25°C
RL = 4 Ω
RL = 4 Ω
22-µH + 1-µF filter
22-µH + 3.3-µF filter
Figure 10. Total Harmonic Distortion + Noise (BTL) vs
Frequency
Figure 11. Gain and Phase (BTL) vs Frequency
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7 Detailed Description
7.1 Overview
The TPA311xD2-Q1 devices are highly efficient class-D audio amplifiers with integrated 120-mΩ MOSFETs that
allow output currents up to 7.5 A. The high efficiency allows the amplifier to provide an excellent audio
performance without the need for a bulky heat sink.
The device can be configured for either master or slave operation by using the SYNC pin. Doing so helps to
prevent audible beat noise.
7.2 Functional Block Diagram
GVDD
PVCC
BSPR
SD
PVCC
TTL
Buffer
Modulation and
PBTL Select
MUTE
Gain
Control
OUTPR_FB
Gate
Drive
OUTPR
GAIN
+
OUTPR_FB
–
–
–
–
GND
RINP
RINN
+
+
PWM
Logic
Gain
Control
PLIMIT
GVDD
–
PVCC
–
+
BSNR
+
PVCC
OUTPNR_FB
OUTNR_
FB
+
FAULT
Gate
Drive
OUTNR
GND
SC Detect
DC Detect
SYNC
GAIN/SLV
Ramp
Generator
Startup Protection
Logic
Biases and
References
Thermal
Detect
AM<2:0>
PLIMIT
Reference
PLIMIT
PVCC
UVLO/OVLO
PVCC
GVDD
PVCC
BSNL
AVDD
GVDD
PVCC
LDO
Regulator
AVCC
GVDD
Gate
Drive
OUTNL
–
OUTNL_FB
OUTNL_
FB
–
+
+
–
LINP
LINN
GND
+
+
Gain
Control
PWM
Logic
PLIMIT
–
GVDD
–
PVCC
+
+
BSPL
PVCC
OUTPL_FB
–
Gate
Drive
OUTPL
GND
Input
Sense
PBTL
Select
Modulation and
PBTL Select
OUTPL_FB
GND
Thermal
Pad
7.3 Feature Description
7.3.1 Gain Setting and Master and Slave
The gain of the TPA311xD2-Q1 family is set by the voltage divider connected to the GAIN/SLV control pin.
Master or slave mode is also controlled by the same pin. An internal ADC is used to detect the eight input states.
The first four stages set the GAIN in master mode to gains of 20, 26, 32, and 36 dB, respectively, whereas the
next four stages set the GAIN in slave mode to gains of 20, 26, 32, and 36 dB, respectively. The gain setting is
latched during power up and cannot be changed while device is powered. Table 2 lists the recommended resistor
values and the state and gain.
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Table 2. Gain and Master or Slave
MASTER / SLAVE
MODE
GAIN
R1 (to GND)(1)
R2 (to GVDD)(1)
INPUT IMPEDANCE
Master
Master
Master
Master
Slave
20 dB
26 dB
32 dB
36 dB
20 dB
26 dB
32 dB
36 dB
5.6 kΩ
20 kΩ
39 kΩ
47 kΩ
51 kΩ
75 kΩ
100 kΩ
100 kΩ
OPEN
100 kΩ
100 kΩ
75 kΩ
51 kΩ
47 kΩ
39 kΩ
16 kΩ
60 kΩ
30 kΩ
15 kΩ
9 kΩ
60 kΩ
30 kΩ
15 kΩ
9 kΩ
Slave
Slave
Slave
(1) Resistor tolerance should be 5% or better.
5
6
INNR
2
1
PLIMIT
GVDD
1
C5 1 µF
2
7
2
1
R2
8
51 k
GAIN/SLV
GND
9
R1 51 k
10
Figure 12. Gain, Master or Slave
In master mode, the SYNC terminal is an output, in slave mode, SYNC terminal is an input for a clock input.
7.3.2 Input Impedance
The input stage of the TPA311xD2-Q1 family is a fully differential input stage, and the input impedance changes
with the gain setting from 9 kΩ at 36-dB gain to 60 kΩ at 20-dB gain. Table 2 lists the values from mininimum to
maximum gain. The tolerance of the input resistor value is ±20%, so the minimum value is higher than 7.2 kΩ.
The inputs must be ac-coupled to minimize the output dc offset and ensure correct ramping of the output
voltages during power ON and power OFF. The input ac-coupling capacitor together with the input impedance
forms a high-pass filter with the following cutoff frequency:
1
ƒ
=
2pZiCi
(1)
If a flat bass response is required down to 20 Hz, the recommended cutoff frequency is a tenth of that, 2 Hz.
Table 3 lists the recommended ac-coupling capacitors for each gain step. If –3 dB is accepted at 20 Hz, 10 times
lower capacitors can used – for example, a 1 µF can be used.
Table 3. Recommended Input AC-Coupling Capacitors
GAIN
20 dB
26 dB
32 dB
36 dB
INPUT IMPEDANCE
INPUT CAPACITANCE
HIGH-PASS FILTER
1.8 Hz
60 kΩ
30 kΩ
15 kΩ
9 kΩ
1.5 µF
3.3 µF
5.6 µF
10 µF
1.6 Hz
2.3 Hz
1.8 Hz
Z
f
C
i
Z
i
IN
Input
Signal
Figure 13. Input Impedance
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The input capacitors used should be a type with low leakage, like quality electrolytic, tantalum, or ceramic. If a
polarized type is used, the positive connection should face the input pins, which are biased to 3 Vdc.
7.3.3 Start-Up and Shutdown Operation
The TPA311xD2-Q1 family employs a shutdown mode of operation designed to reduce supply current (ICC) to the
absolute minimum level for power conservation during periods of nonuse. The SD input pin should be held high
(see Recommended Operating Conditions for SD VIH and VIL levels) during normal operation when the amplifier
is in use. Pulling SD low sets the outputs to mute, and the amplifier enters a low-current state. It is not
recommended to leave SD unconnected, because amplifier operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power
supply. The gain setting is selected at the end of the start-up cycle. At the end of the start-up cycle, the gain is
selected and cannot be changed until the next power up.
7.3.4 PLIMIT Operation
The TPA311xD2-Q1 family has a built-in voltage limiter that can be used to limit the output voltage level below
the supply rail, the amplifier simply operates as if it was powered by a lower supply voltage, and thereby limits
the output power. Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external
reference may also be used if tighter tolerance is required. Add a 1-µF capacitor from the PLIMIT pin to ground
to ensure stability. It is recommended to connect PLIMIT to GVDD when using 1SPW-modulation mode.
Figure 14. Power Limit Example
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle
to a fixed maximum value. This limit can be thought of as a virtual voltage rail which is lower than the supply
connected to PVCC. This virtual rail is approximately 4 times the voltage at the PLIMIT pin. This output voltage
can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance.
æ
ö2
æ
ç
è
ö
÷
ø
RL
´ V
ç
÷
P
ç
÷
RL + 2 ´ RS
è
ø
POUT
=
for unclipped power
2 ´ RL
where
•
•
•
•
•
POUT (10%THD) = 1.25 × POUT (unclipped)
RL is the load resistance.
RS is the total series resistance including RDS(on) and output filter resistance.
VP is the peak amplitude
VP = 4 × PLIMIT voltage if PLIMIT < 4 × VP
(2)
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Table 4. Power Limit Example
PVCC (V)
24 V
PLIMIT VOLTAGE (V)(1)
R to GND
Short
R to GVDD
OUTPUT VOLTAGE (Vrms)
GVDD
3.3
Open
51 kΩ
51 kΩ
Open
51 kΩ
68 kΩ
17.9
12.67
9
24 V
45 kΩ
24 kΩ
Short
24 V
2.25
GVDD
2.25
1.5
12 V
10.33
9
12 V
24 kΩ
18 kΩ
12 V
6.3
(1) PLIMIT measurements taken with EVM gain set to 26 dB and input voltage set to 1 Vrms
.
7.3.5 GVDD Supply
The GVDD supply is used to power the gates of the output full-bridge transistors. The GVDD supply can also be
used to supply the PLIMIT and GAIN/SLV voltage dividers. Decouple GVDD with an X5R ceramic 1-µF capacitor
to GND. The GVDD supply is not intended to be used for external supply. It is recommended to limit the current
consumption by using resistor voltage dividers of 100 kΩ or more for GAIN/SLV and PLIMIT.
7.3.6 BSPx and BSNx Capacitors
The full H-bridge output stages use only NMOS transistors. Therefore, to turn on correctly they require bootstrap
capacitors for the high side of each output. A 220-nF ceramic capacitor of quality X5R or better, rated for at least
16 V, must be connected from each output to its corresponding bootstrap input. (See the application circuit
diagram in Figure 19.) The bootstrap capacitors connected between the BSxx pins and their corresponding
outputs function as a floating power supply for the high-side N-channel power MOSFET gate-drive circuitry.
During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to
keep the high-side MOSFETs turned on.
7.3.7 Differential Inputs
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA311xD2-Q1 family with a differential source, connect the positive lead of the audio source to the
RINP or LINP input and the negative lead from the audio source to the RINN or LINN input. To use the
TPA311xD2-Q1 family with a single-ended source, ac-ground the negative input through a capacitor equal in
value to the input capacitor on the positive input and apply the audio source to either input. In a single-ended
input application, the unused input should be ac-grounded at the audio source instead of at the device input for
best noise performance. For good transient performance, the impedance seen at each of the two differential
inputs should be the same.
The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to
allow the input dc-blocking capacitors to become completely charged during the 10-ms power-up time. If the
input capacitors are not allowed to completely charge, there is some additional sensitivity to component matching
which can result in a pop if the input components are not well matched.
7.3.8 Device Protection System
The TPA311xD2-Q1 family contains a complete set of protection circuits to make system design efficient as well
as to protect the device against any kind of permanent failures due to short circuits, overload, overtemperature,
and undervoltage. The FAULT pin signals if an error is detected according to Table 5:
Table 5. Fault Reporting
TRIGGERING CONDITION
(typical value)
LATCHED OR SELF-
CLEARING
FAULT
FAULT
ACTION
Overcurrent
Output short or short to PVCC or GND
Tj > 150°C
Low
Low
Low
Output high impedance
Output high impedance
Output high impedance
Latched
Latched
Latched
Overtemperature
Too-high dc offset
DC output voltage
Undervoltage on
PVCC
V(PVCC) < 4.5 V
V(PVCC) > 27 V
–
–
Output high impedance
Output high impedance
Self-clearing
Self-clearing
Overvoltage on PVCC
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7.3.9 DC-Detect Protection
The TPA311xD2-Q1 family has circuitry which protects the speakers from dc current, which might occur due to
defective capacitors on the input or shorts on the printed circuit board at the inputs. A dc-detect fault is reported
on the FAULT pin as a low state. The dc-detect fault also causes the amplifier to shut down by changing the
state of the outputs to Hi-Z.
If automatic recovery from the short-circuit protection latch is desired, connect the FAULT pin directly to the SD
pin. This allows the FAULT pin function to automatically drive the SD pin low which clears the dc-detect
protection latch.
A dc-detect fault is issued when the output differential duty-cycle of either channel exceeds 60% for more than
420 ms at the same polarity. For several values of the supply voltage, Table 6 shows some examples of the
typical output offset voltages that trigger dc-detect protection. This feature protects the speaker from large dc
currents or ac currents less than 2 Hz. To avoid nuisance faults due to the dc-detect circuit, hold the SD pin low
at power up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive
and negative inputs to avoid nuisance dc-detect faults.
Table 6 lists the minimum output offset voltages required to trigger the dc detect. The outputs must remain at or
above the voltage listed in the table for more than 420 ms to trigger the dc detect.
Table 6. DC Detect Threshold
V(PVCC) (V)
VOS - OUTPUT OFFSET VOLTAGE (V)
4.5
6
0.96
1.3
12
18
2.6
3.9
7.3.10 Short-Circuit Protection and Automatic Recovery Feature
The TPA311xD2-Q1 family has protection from overcurrent conditions caused by a short circuit on the output
stage. The short-circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are
switched to a high-impedance state when the short-circuit protection latch is engaged. The latch can be cleared
by cycling the SD pin through the low state.
If automatic recovery from the short-circuit protection latch is desired, connect the FAULT pin directly to the SD
pin. This allows the FAULT pin function to automatically drive the SD pin low, which clears the short-circuit
protection latch.
In systems where a possibility of a permanent short from the output to PVDD or to a high-voltage battery like a
car battery can occur, pull the MUTE pin low with the FAULT signal and an inverting transistor to ensure a high-Z
restart, as shown in Figure 15.
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GVDD
32
1
2
3
4
100K
100K
MODSEL
PVCC
31
PVCC
30
SD
SD
FAULT
BSPR
FAULT
29
INPR
INNR
OUTPR
28
GND
27
5
6
GVDD
GVDD
PLIMIT
GVDD
OUTNR
26
BSNR
25
GND
7
8
100K
100K
GAIN/SLV
GND
1uF
24
9
BSPL
10
11
12
23
INPL
INNL
OUTPL
22
GND
21
MUTE
MUTE
AM2
OUTNL
13
14
15
16
20
BSNL
19
AM1
AM0
PVCC
18
PVCC
17
SYNC
AVCC
TPA3116D2-Q1
Figure 15. MUTE Driven by Inverted FAULT
7.3.11 Thermal Protection
Thermal protection on the TPA311xD2-Q1 family prevents damage to the device when the internal die
temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die
temperature exceeds the thermal trip point, the device enters the shutdown state and the outputs are disabled.
This is a latched fault.
Thermal protection faults are reported on the FAULT pin as a low state.
If automatic recovery from the thermal protection latch is desired, connect the FAULT pin directly to the SD pin.
This allows the FAULT pin function to automatically drive the SD pin low, which clears the thermal protection
latch.
7.3.12 TPA311xD2-Q1 Modulation Scheme
The TPA311xD2-Q1 family has the option of running in either BD modulation or 1SPW modulation; this is set by
the MODSEL pin.
7.3.12.1 MODSEL = GND: BD Modulation
Each output is switching from 0 volts to the supply voltage. The OUTPx and OUTNx are in phase with each other
with no input so that there is little or no current in the speaker. The duty cycle of OUTPx is greater than 50% and
OUTNx is less than 50% for positive output voltages. The duty cycle of OUTPx is less than 50% and OUTNx is
greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most of the
switching period, reducing the switching current, which reduces any I2R losses in the load.
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OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
PVCC
Positive Output
-
OUTP OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
OUTP-OUTN
-
PVCC
0A
Speaker
Current
Figure 16. BD Mode Modulation
7.3.12.2 MODSEL = HIGH: 1SPW Modulation
The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty
in THD degradation, and more attention required in the output filter selection. In 1SPW mode, the outputs
operate at approximately 15% modulation during idle conditions. When an audio signal is applied, one output
decreases and one increases. The decreasing output signal quickly rails to GND at which point all the audio
modulation takes place through the rising output. The result is that only one output is switching during a majority
of the audio cycle. Efficiency is improved in this mode due to the reduction of switching losses. The THD penalty
in 1SPW mode is minimized by the high-performance feedback loop. The resulting audio signal at each half-
output has a discontinuity each time the output rails to GND. This can cause ringing in the audio reconstruction
filter unless care is taken in the selection of the filter components and type of filter used.
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OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
-PVCC
OUTP
-OUTN
0
A
Speaker
Current
Figure 17. 1SPW Mode Modulation
7.3.13 AM Avoidance EMI Reduction
To reduce interference in the AM radio band, the TPA3116D2-Q1 has the ability to change the switching
frequency via the AM[2:0] pins. The recommended frequencies are listed in Table 7. The fundamental frequency
and its second harmonic straddle the AM radio band listed. This eliminates the tones that can be present due to
the switching frequency being demodulated by the AM radio.
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Table 7. AM Frequencies
US
EUROPEAN
AM FREQUENCY (kHz)
AM FREQUENCY (kHz)
522–540
SWITCHING FREQUENCY (kHz)
AM2
AM1
AM0
540–917
917–1125
1125–1375
1375–1547
540–914
500
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
0
0
1
914–1122
1122–1373
1373–1548
600 (or 400)
500
600 (or 400)
1547–1700
1548–1701
600 (or 500)
7.4 Device Functional Mode
7.4.1 Mono Mode (PBTL)
The TPA311xD2-Q1 family can be connected in MONO mode enabling up to 100-W output power. This is done
by:
•
•
•
Connecting INPL and INNL directly to ground (without capacitors) to set the device in mono mode during
power up
Connecting OUTPR and OUTNR together for the positive speaker terminal and OUTNL and OUTPL together
for the negative terminal
Applying the analog input signal to INPR and INNR
TPA3116D2-Q1
4.5 V–26 V
PSU
OUTPR
Right
OUTNR
LC Filter
OUTPL
OUTNL
PBTL
Detect
Left
Figure 18. Mono Mode (PBTL)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
This section describes a 2.1 master-and-slave application. The master is configured as stereo outputs and the
slave is configured as a mono PBTL output.
8.2 Typical Application
A 2.1 solution, U1 TPA3116D2-Q1 in master mode 400 kHz, BTL, gain if 20 dB, power limit not implemented. U2
in Slave, PBTL mode gain of 20dB. Inputs are connected for differential inputs.
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Typical Application (continued)
OUTPUT LC FILTER
10uH
EMI C-RC SNUBBER
PVCC DECOUPLING
PVCC
10nF
3.3R
10nF
220uF
1nF
100nF
3.3R
100nF
1nF
1nF
1nF
1nF
680nF
100K
32
31
30
1
MODSEL
PVCC
2
SD_LR
SD
PVCC
BSPR
220nF
3
4
1nF
1nF
FAULT
IN_P_RIGHT
IN_N_RIGHT
29
28
27
26
25
24
10nF
3.3R
INPR
INNR
OUTPR
GND
5
6
680nF
PLIMIT
GVDD
OUTNR
BSNR
7
100K
10uH
10uH
8
220nF
220nF
GAIN/SLV
GND
GND
1uF
9
BSPL
20K
10
11
12
23
22
21
INPL
INNL
OUTPL
GND
3.3R
10nF
1nF
1nF
680nF
IN_P_LEFT
IN_N_LEFT
MUTE
AM2
OUTNL
BSNL
13
14
15
16
20
19
18
17
220nF
MUTE_LR
AM1
AM0
PVCC
PVCC
PVCC
100K
SYNC
AVCC
10nF
3.3R
680nF
220uF
1nF
100nF
TPA3116D2-Q1
10uH
PVCC DECOUPLING
10K
OUTPUT LC FILTER
10uH
EMI C-RC SNUBBER
PVCC DECOUPLING
PVCC
PVCC
3.3R
220uF
1nF
100nF
1nF
1uF
100K
10nF
32
31
30
1
2
3
4
MODSEL
PVCC
SD_SUB
SD
PVCC
BSPR
220nF
1nF
1nF
FAULT
IN_P_SUB
IN_N_SUB
29
28
27
26
25
24
10nF
INPR
INNR
OUTPR
GND
5
6
1nF
1uF
1uF
1uF
PLIMIT
GVDD
OUTNR
BSNR
3.3R
7
47K
75K
10uH
10uH
8
220nF
220nF
GAIN/SLV
GND
GND
1uF
9
BSPL
10
11
12
23
22
21
INPL
INNL
OUTPL
GND
3.3R
1nF
MUTE_SUB
MUTE
AM2
OUTNL
BSNL
13
14
15
16
20
19
18
17
10nF
220nF
100K
AM1
AM0
PVCC
PVCC
PVCC
SYNC
AVCC
10nF
1nF
220uF
1nF
100nF
TPA3116D2-Q1
3.3R
1nF
10uH
PVCC DECOUPLING
Figure 19. Typical Application Schematic
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Typical Application (continued)
8.2.1 Design Requirements
DESIGN PARAMETERS
Input voltage range, V(PVCC)
PWM output frequencies
Maximum output power
EXAMPLE VALUE
4.5 V to 26 V
400 kHz, 500 kHz, 600 kHz, 1 MHz or 1.2 MHz
50 W
8.2.2 Detailed Design Procedure
The TPA311xD2-Q1 family is a very flexible and easy-to-use class-D amplifier; therefore, the design process is
straightforward. Before beginning the design, gather the following information regarding the audio system.
•
•
•
•
PVCC rail planned for the design
Speaker or load impedance
Maximum output-power requirement
Desired PWM frequency
8.2.2.1 Select the PWM Frequency
Set the PWM frequency by using AM0, AM1 and AM2 pins.
8.2.2.2 Select the Amplifier Gain and Master or Slave Mode
In order to select the amplifier gain setting, the designer must determine the maximum power target and the
speaker impedance. Once these parameters have been determined, calculate the required output-voltage swing
which delivers the maximum output power.
Choose the lowest analog gain setting that produces an output-voltage swing greater than the required output
swing for maximum power. The analog gain and master or slave mode can be set by selecting the voltage
divider resistors (R1 and R2) on the GAIN/SLV pin.
8.2.2.3 Select Input Capacitance
Select the bulk capacitors at the PVCC inputs for proper voltage margin and adequate capacitance to support the
power requirements. In practice, with a well-designed power supply, two 100-μF, 50-V capacitors should be
sufficient. One capacitor should be placed near the PVCC inputs at each side of the device. PVCC capacitors
should be a low-ESR type because they are being used in a high-speed switching application.
8.2.2.4 Select Decoupling Capacitors
Good-quality decoupling capacitors must be added at each of the PVCC inputs to provide good reliability, good
audio performance, and to meet regulatory requirements. X5R or better ratings should be used in this
application. Consider temperature, ripple current, and voltage overshoots when selecting decoupling capacitors.
Also, these decoupling capacitors should be located near the PVCC and GND connections to the device in order
to minimize series inductances.
8.2.2.5 Select Bootstrap Capacitors
Each of the outputs requires bootstrap capacitors to provide gate drive for the high-side output FETs. For this
design, use 0.22-μF, 25-V capacitors of X5R quality or better.
Copyright © 2015, Texas Instruments Incorporated
21
TPA3116D2-Q1, TPA3118D2-Q1
ZHCSE21A –JULY 2015–REVISED AUGUST 2015
www.ti.com.cn
8.2.3 Application Curves
10
10
1
20 Hz
1 kHz
6 kHz
20 Hz
1 kHz
6 kHz
1
0.1
0.1
0.01
0.01
0.001
0.001
10m
100m
1
10
40
10m
100m
1
10
40
Output Power (W)
Output Power (W)
D005
D006
Gain = 26 dB
PVCC = 12 V
TA = 25°C
10-µH + 0.68-µF filter
Gain = 26 dB
PVCC = 14.4 V
TA = 25°C
RL = 4 Ω
RL = 4 Ω
10-µH + 0.68-µF filte
Figure 20. Total Harmonic Distortion + Noise (BTL) vs
Output Power
Figure 21. Total Harmonic Distortion + Noise (BTL) vs
Output Power
9 Power Supply Recommendations
The power supply requirements for the TPA3116D2-Q1 consist of one higher-voltage supply to power the output
stage of the speaker amplifier. Several on-chip regulators are included on the TPA3116D2-Q1 to generate the
voltages necessary for the internal circuitry of the audio path. It is important to note that the voltage regulators
which have been integrated are sized only to provide the current necessary to power the internal circuitry. The
external pins are provided only as a connection point for off-chip bypass capacitors to filter the supply.
Connecting external circuitry to these regulator outputs may result in reduced performance and damage to the
device. The high-voltage supply, between 4.5 V and 26 V, supplies the analog circuitry (AVCC) and the power
stage (PVCC). The AVCC supply feeds the internal LDOs, including GVDD. The LDO outputs are connected to
external pins for filtering purposes, but should not be connected to external circuits. The GVDD LDO output has
been sized to provide current necessary for internal functions but not for external loading.
10 Layout
10.1 Layout Guidelines
Because the class-D switching edges are fast, it is necessary to take care when planning the layout of the
printed circuit board. The following suggestions help to meet EMC requirements.
•
Decoupling capacitors — The high-frequency decoupling capacitors should be placed as close to the PVCC
and AVCC terminals as possible. Large (100 μF or greater) bulk power supply decoupling capacitors should
be placed near the TPA3116D2-Q1 on the PVCC supplies. Local, high-frequency bypass capacitors should
be placed as close to the PVCC pins as possible. These capacitors can be connected to the IC GND pad
directly for an excellent ground connection. Consider adding a small, good-quality, low-ESR ceramic capacitor
between 220 pF and 1 nF and a larger mid-frequency capacitor of value between 100 nF and 1 µF, also of
good quality, to the PVCC connections at each end of the chip.
•
•
•
Keep the current loop from each of the outputs through the filter and back to GND as small and tight as
possible. The size of this current loop determines its effectiveness as an antenna.
Grounding — The PVCC decoupling capacitors should connect to GND. All ground should be connected at
the IC GND, which should be used as a central ground connection or star ground for the TPA3116D2-Q1.
Output filter — The LC filter should be placed close to the outputs. The capacitor used in the LC filter should
be grounded.
22
Copyright © 2015, Texas Instruments Incorporated
TPA3116D2-Q1, TPA3118D2-Q1
www.ti.com.cn
ZHCSE21A –JULY 2015–REVISED AUGUST 2015
Layout Guidelines (continued)
For an example layout, see the TPA3116D2 Evaluation Module (TPA3116D2EVM) User Guide (SLOU336). Both
the EVM user manual and the thermal pad application reports, SLMA002 and SLMA004, are available on the TI
Web site at http://www.ti.com.
10.2 Layout Example
Figure 22. Layout Example Top
Copyright © 2015, Texas Instruments Incorporated
23
TPA3116D2-Q1, TPA3118D2-Q1
ZHCSE21A –JULY 2015–REVISED AUGUST 2015
www.ti.com.cn
Layout Example (continued)
Figure 23. Layout Example Bottom
24
Copyright © 2015, Texas Instruments Incorporated
TPA3116D2-Q1, TPA3118D2-Q1
www.ti.com.cn
ZHCSE21A –JULY 2015–REVISED AUGUST 2015
10.3 Heat Sink Used on the EVM
The heat sink (part number ATS-TI 10 OP-521-C1-R1 or equivalent) used on the EVM is a 14-mm × 25-mm ×
50-mm extruded aluminum heat sink with three fins (see Figure 24). For additional information on the heat sink,
go to www.qats.com.
50.00 0.38
[1.969 .015]
SINK LENGTH
MACHINE THESE
3 EDGES AFTER
0.00
ANODIZATION
25.00
–0.60
3.00
[.118]
+.000
–.024
SINK HEIGHT
.984
1.00
[.118]
6.35
[.250]
3.00
[.118]
13.90 0.38
[.547 .015]
BASE WIDTH
6.95
[.274]
5.00
[.197]
40.00
[1.575]
2X 4-40 x 6.5
Figure 24. EVM Heatsink
This size heat sink has shown to be sufficient for continuous output power. The crest factor of music and having
airflow lowers the requirement for heat sinking, and smaller types of heat sinks can be used.
版权 © 2015, Texas Instruments Incorporated
25
TPA3116D2-Q1, TPA3118D2-Q1
ZHCSE21A –JULY 2015–REVISED AUGUST 2015
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 8. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
TPA3116D2-Q1
TPA3118D2-Q1
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 本数据随时可能发生变更
并且不对本文档进行修订，恕不另行通知。 要获得这份数据表的浏览器版本，请查阅左侧的导航窗格。
26
版权 © 2015, Texas Instruments Incorporated
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都遵循在订单确认时所提供的TI 销售条款与条件。
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用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险，
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Copyright © 2015, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
TPA3116D2QDADRQ1
TPA3118D2QDAPRQ1
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ACTIVE
HTSSOP
HTSSOP
DAD
32
32
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
TPA
3116Q
D2
ACTIVE
DAP
NIPDAU
-40 to 125
TPA3118Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA3116D2QDADRQ1 HTSSOP DAD
TPA3118D2QDAPRQ1 HTSSOP DAP
32
32
2000
2000
330.0
330.0
24.4
24.4
8.6
8.6
11.5
11.5
1.6
1.6
12.0
12.0
24.0
24.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPA3116D2QDADRQ1
TPA3118D2QDAPRQ1
HTSSOP
HTSSOP
DAD
DAP
32
32
2000
2000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
TM
DAD0032C
PowerPAD TSSOP - 1.15 mm max height
S
C
A
L
E
1
.
6
0
0
PLASTIC SMALL OUTLINE
C
8.3
7.9
SEATING PLANE
TYP
A
0.1 C
PIN 1 ID AREA
30X 0.65
32
1
EXPOSED
THERMAL PAD
11.1
10.9
NOTE 3
3.74
3.16
2X
9.75
16
17
0.30
32X
0.19
3.04
2.46
0.1
C A B
6.2
6.0
B
(0.15) TYP
0.25
SEE DETAIL A
1.15
1.00
GAGE PLANE
0.75
0.50
0.15
0.05
0 - 8
DETAIL A
TYPICAL
4223628/B 02/2020
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DAD0032C
PowerPAD TMTSSOP - 1.15 mm max height
PLASTIC SMALL OUTLINE
32X (1.5)
SEE DETAILS
SYMM
1
32
32X (0.45)
30X (0.65)
SYMM
(R0.05) TYP
17
16
(7.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL UNDER
SOLDER MASK
SOLDER MASK
SOLDER MASK
OPENING
METAL
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4223628/B 02/2020
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DAD0032C
PowerPAD TSSOP - 1.15 mm max height
PLASTIC SMALL OUTLINE
32X (1.5)
SYMM
1
32
32X (0.45)
30X (0.65)
SYMM
(R0.05) TYP
16
17
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:8X
4223628/B 02/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DAP 32
8.1 x 11, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225303/A
www.ti.com
PACKAGE OUTLINE
TM
DAP0032C
PowerPAD TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC SMALL OUTLINE
8.3
7.9
TYP
A
PIN 1 ID AREA
30X 0.65
32
1
11.1
10.9
NOTE 3
2X
9.75
16
B
17
0.30
32X
0.19
6.2
6.0
0.1 C
0.1
C A B
SEATING PLANE
(0.15) TYP
C
SEE DETAIL A
3.04
2.46
EXPOSED
THERMAL PAD
0.25
GAGE PLANE
3.74
3.16
1.2 MAX
0.75
0.50
0.15
0.05
2X (0.6)
NOTE 5
0 - 8
2X (0.15)
NOTE 5
DETAIL A
TYPICAL
4223691/A 05/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ and may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DAP0032C
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(5.2)
NOTE 9
SOLDER MASK
DEFINED PAD
(3.04)
32X (1.5)
SYMM
SEE DETAILS
1
32
32X (0.45)
30X (0.65)
(11)
NOTE 9
SYMM
(3.74)
(1.2 TYP)
(
0.2) TYP
VIA
(R0.05) TYP
16
17
METAL COVERED
BY SOLDER MASK
(0.65) TYP
(1.3) TYP
(7.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL UNDER
SOLDER MASK
SOLDER MASK
METAL
SOLDER MASK
OPENING
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4223691/A 05/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DAP0032C
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.04)
BASED ON
0.125 THICK
STENCIL
32X (1.5)
1
32
32X (0.45)
30X (0.65)
(3.74)
BASED ON
SYMM
0.125 THICK
STENCIL
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
17
16
METAL COVERED
BY SOLDER MASK
SYMM
(7.5)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.40 X 4.18
3.04 X 3.74 (SHOWN)
2.78 X 3.41
0.125
0.15
0.175
2.57 X 3.16
4223691/A 05/2017
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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