TPA3136AD2PWP [TI]
10W 立体声、20W 单声道、8V 至 14.4V、模拟输入 D 类音频放大器,无电感器和低 EMI | PWP | 28 | -40 to 125;型号: | TPA3136AD2PWP |
厂家: | TEXAS INSTRUMENTS |
描述: | 10W 立体声、20W 单声道、8V 至 14.4V、模拟输入 D 类音频放大器,无电感器和低 EMI | PWP | 28 | -40 to 125 放大器 光电二极管 商用集成电路 音频放大器 电感器 |
文件: | 总38页 (文件大小:2157K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TPA3136D2, TPA3136AD2
ZHCSF30F –MAY 2016–REVISED JANUARY 2020
具有超低 EMI 的 TPA3136D2,TPA3136AD2 10W 无电感器立体声 (BTL)
D 类音频放大器
1 特性
3 说明
1
•
•
•
电源电压为 12V、总谐波失真 + 噪声 (THD+N) 为
10%、负载为 6Ω 时的功率为 2 × 10W/通道
TPA3136D2,TPA3136AD2 器件一款高效 D 类音频
功率放大器,适用于以高达 10W 的功率驱动阻抗为
6Ω 或 8Ω(每通道)的桥接式立体声扬声器。
电源电压为 13V、THD+N 为 10%、负载为 8Ω 时
的功率为 2 × 10W/通道
借助采用扩展频谱控制方案的高级 EMI 抑制技术,既
能实现在输出端使用成本较低的铁氧体磁珠滤波器,同
时能够满足 EMC 要求,降低了系统成本。
D 类运行(负载为 8Ω)时效率高达 90%,无需散
热器
•
•
在 1W/4Ω/1kHz 条件下,THD+N <0.05%
TPA3136D2,TPA3136AD2 器件不仅针对短路和过载
提供全面的保护,而且 SpeakerGuard™扬声器保护电
路包括一个功率限制器和一个直流检测电路,可以保护
所连接的扬声器。直流检测及引脚至引脚、引脚接地和
引脚至电源短路保护电路可以防止扬声器在生产过程中
发生输出直流和引脚短路。同时充分保护输出,防止
GND、PVCC、输出至输出短路。短路保护和热保护具
有自动恢复功能。
宽电源电压范围允许在 4.5V(TPA3136AD2 为
8V)至 14.4V 范围内运行
•
•
•
无电感器运行
通过扩展频谱技术增强了 EMI 性能
SpeakerGuard™扬声器保护包括功率限制器和直
流保护
•
可靠的引脚对引脚、引脚对地、引脚对电源短路保
护和热保护
•
•
•
26dB 固定增益
TPA3136D2,TPA3136AD2 器件可驱动阻抗低至 4Ω
的立体声扬声器。TPA3136D2,TPA3136AD2 的效率
在负载为 8Ω 时高达 90%,无需外部散热器,而且
TPA3136D2,TPA3136AD2 将在双层印刷电路板
(PCB) 上实现全功率输出。
单端或差动模拟输入
启动时无喀哒声
2 应用
•
•
•
•
•
电视
器件信息(1)
蓝牙、无线扬声器
迷你扬声器
USB 扬声器
消费类音频设备
器件型号
TPA3136D2
TPA3136AD2
封装
HTSSOP (28)
HTSSOP (28)
封装尺寸(标称值)
9.70mm × 4.40mm
9.70mm × 4.40mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
简化原理图
TPA3136D2
Ferrite
Bead
Filter
RIGHT
LEFT
Audio
Source
And Control
Ferrite
Bead
Filter
SD
FAULT
PBTL
SELECT
Power Supply
4.5V-14.4V
PBTL Mode Select
PLIMIT
Power Limiter Threshold Select
110VAC->240VAC
Copyright © 2017, Texas Instruments Incorporated
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLOS938
TPA3136D2, TPA3136AD2
ZHCSF30F –MAY 2016–REVISED JANUARY 2020
www.ti.com.cn
目录
9.4 Device Functional Modes........................................ 16
10 Application and Implementation........................ 17
10.1 Application Information.......................................... 17
10.2 Typical Applications ............................................. 17
11 Power Supply Recommendations ..................... 24
11.1 Power Supply Decoupling, CS ............................. 24
12 Layout................................................................... 25
12.1 Layout Guidelines ................................................. 25
12.2 Layout Example .................................................... 26
13 器件和文档支持 ..................................................... 27
13.1 器件支持 ............................................................... 27
13.2 文档支持 ............................................................... 27
13.3 相关链接................................................................ 27
13.4 接收文档更新通知 ................................................. 27
13.5 支持资源................................................................ 27
13.6 商标....................................................................... 27
13.7 静电放电警告......................................................... 27
13.8 Glossary................................................................ 27
14 机械、封装和可订购信息....................................... 28
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 4
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings ............................................................ 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 7
7.5 Electrical Characteristics........................................... 7
7.6 Switching Characteristics.......................................... 7
7.7 Typical Characteristics.............................................. 8
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
9.1 Overview ................................................................. 11
9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 13
8
9
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision E (December 2017) to Revision F
Page
•
Changed the Functional Block Diagram, missing and unconnected lines .......................................................................... 12
Changes from Revision D (March 2017) to Revision E
Page
•
Changed the Supply Voltage (AVCC to GND, PVCC to GND) MAX value From: 16 V To: 20 V in the Absolute
Maximum Ratings................................................................................................................................................................... 6
Changed Figure 18 .............................................................................................................................................................. 17
Changed Figure 19 .............................................................................................................................................................. 18
•
•
Changes from Revision C (March 2017) to Revision D
Page
•
•
Changed text From: "channel exceeds 14% (for example, +57%, –43%)." To: "channel exceeds 24% (±10%)." in the
DC Detect section................................................................................................................................................................. 14
Deleted text "The inputs must remain at or above the voltage..." from the DC Detect section............................................ 14
Changes from Revision B (June 2016) to Revision C
Page
•
已添加 在数据表中添加了 TPA3136AD2 器件。 .................................................................................................................... 1
Changes from Revision A (June 2016) to Revision B
Page
•
•
•
Updated Thermal Characteristics .......................................................................................................................................... 7
Fixed Output Power characteristic to match initial description .............................................................................................. 7
Fixed duplicate graph issue ................................................................................................................................................... 8
2
版权 © 2016–2020, Texas Instruments Incorporated
TPA3136D2, TPA3136AD2
www.ti.com.cn
ZHCSF30F –MAY 2016–REVISED JANUARY 2020
Changes from Original (May 2016) to Revision A
Page
•
Changed data sheet from Product Preview to Production Data ............................................................................................ 4
Copyright © 2016–2020, Texas Instruments Incorporated
3
TPA3136D2, TPA3136AD2
ZHCSF30F –MAY 2016–REVISED JANUARY 2020
www.ti.com.cn
5 Device Comparison Table
DEVICE NAME
DESCRIPTION
15-W Filter-Free Class-D Stereo Amplifier with
SpeakerGuard™
TPA3110D2
TPA3140D2
10-W Inductor-Free Class-D Stereo Amplifier with
Ultra Low EMI and AGL
6 Pin Configuration and Functions
PWP Package
28-Pin HTSSOP
(Top View)
SD
FAULT
LINP
LINN
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PVCC
PVCC
BSPL
2
3
4
OUTPL
GND
5
NC
6
OUTNL
BSNL
BSNR
OUTNR
GND
AVCC
GND
GVDD
PLIMIT
RINN
RINP
NC
7
Thermal
Pad
8
9
10
11
12
13
14
OUTPR
BSPR
PVCC
PVCC
PBTL
Not to scale
Pin Functions
PIN
NUMBER
I/O/P(1)
DESCRIPTION
NAME
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels
with compliance to AVCC.
SD
1
I
Open drain output used to display short circuit or dc detect fault status. Voltage compliant to AVCC.
Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise, both
short circuit faults and dc detect faults must be reset by cycling PVCC.
FAULT
2
O
LINP
LINN
NC
3
I
I
Positive audio input for left channel. Biased at 3 V.
Negative audio input for left channel. Biased at 3 V.
No Connect Pin. Can be shorted to PVCC or shorted to GND or left open.
Analog supply
4
5, 6, 13
I
AVCC
GND
7
8
P
P
Analog signal ground.
(1) I = Input, O = Output, P = Power
4
Copyright © 2016–2020, Texas Instruments Incorporated
TPA3136D2, TPA3136AD2
www.ti.com.cn
PIN
ZHCSF30F –MAY 2016–REVISED JANUARY 2020
Pin Functions (continued)
I/O/P(1)
DESCRIPTION
NAME
GVDD
PLIMIT
RINN
NUMBER
9
O
I
High-side FET gate drive supply. Nominal voltage is 7 V.
Power Limiter Control pin
10
11
12
14
I
Negative audio input for right channel. Biased at 3 V.
Positive audio input for right channel. Biased at 3 V.
RINP
I
PBTL
I
Parallel BTL mode select pin. L=Stereo BTL mode, H=Mono PBTL mode
Power supply for right channel H-bridge. Right channel and left channel power supply inputs are
connected internally.
PVCC
15, 16
P
BSPR
OUTPR
GND
17
18
19
20
21
22
23
24
25
26
I
Bootstrap I/O for right channel, positive high-side FET.
Class-D H-bridge positive output for right channel.
Power ground for the H-bridges.
O
P
O
I
OUTNR
BSNR
BSNL
Class-D H-bridge negative output for right channel.
Bootstrap I/O for right channel, negative high-side FET.
Bootstrap I/O for left channel, negative high-side FET.
Class-D H-bridge negative output for left channel.
Power ground for the H-bridges.
I
OUTNL
GND
O
P
O
I
OUTPL
BSPL
Class-D H-bridge positive output for left channel.
Bootstrap I/O for left channel, positive high-side FET.
Power supply for left channel H-bridge. Right channel and left channel power supply inputs are
connected internally.
PVCC
27, 28
P
P
Thermal Pad
Connect to GND for best thermal and electrical performance.
Copyright © 2016–2020, Texas Instruments Incorporated
5
TPA3136D2, TPA3136AD2
ZHCSF30F –MAY 2016–REVISED JANUARY 2020
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Supply voltage
Input current
AVCC to GND, PVCC to GND
To any pin except supply pins
–0.3
20
10
AVCC + 0.3
10
mA
V
–0.3
Voltage
Voltage
SD, FAULT to GND(2)
V/ms
V
RINN, RINP, LINN, LINP
BTL, PVCC > 12 V
BTL, PVCC ≤ 12 V
PBTL, PVCC > 12 V
PBTL, PVCC ≤ 12 V
–0.3
4.8
3.2
2.5
1.8
6.3
Minimum load resistance, RL
Ω
Continuous total power dissipation
Operating free-air temperature range, TA
Temperature range
See the Thermal Information Table
(3)
–40
–65
–65
85
°C
°C
°C
150
150
Storage temperature range, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100 kΩ resister in series
with the pins.
(3) The TPA3136D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.
7.2 ESD Ratings
VALUE
±1000
±250
UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
Charged device model (CDM), per JEDEC specification JESD22-C101
V(ESD) Electrostatic discharge
V
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC Supply voltage
VCC Supply voltage
TEST CONDITIONS
MIN MAX UNIT
PVCC, AVCC
PVCC, AVCC
SD, PBTL
TPA3136
4.5 14.4
V
V
TPA3136A
8
14.4
AVC
C
VIH
VIL
High-level input voltage
Low-level input voltage
2
V
SD, PBTL
0.8
0.8
50
5
V
V
VOL Low-level output voltage
FAULT, RPULL-UP=100 k, PVCC=14.4 V
SD, PBTL, VI = 2 V, AVCC = 12 V
SD, PBTL, VI = 0.8 V, AVCC = 12 V
IIH
IIL
High-level input current
Low-level input current
µA
µA
°C
TA
Operating free-air
temperature(1)
–40
85
TJ
Operating junction
temperature(1)
-40 150
°C
(1) The TPA3136D2, TPA3136AD2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must
be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal
protection shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.
6
Copyright © 2016–2020, Texas Instruments Incorporated
TPA3136D2, TPA3136AD2
www.ti.com.cn
ZHCSF30F –MAY 2016–REVISED JANUARY 2020
7.4 Thermal Information
TPA3136D2,
TPA3136AD2
THERMAL METRIC(1)
UNIT
PWP (HTSSOP)
28 PINS
RθJA
Junction-to-ambient thermal resistance
30.3
33.5
17.5
0.9
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
7.2
RθJC(bot)
0.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
TA = 25°C, AVCC = PVCC = 12 V, RL = 6 Ω (unless otherwise noted).(1) Over operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
DC CHARACTERISTICS
Class-D output offset voltage (measured
differentially)
| VOS
ICC
ICC(SD)
rDS(on)
|
VI = 0 V, Gain = 26 dB
1.5
35
15
40
mV
mA
Quiescent supply current
SD = 2 V, no load, 300 ohm Ferrite Bead + 1nF Output
Filter
Quiescent supply current in shutdown mode
Drain-source on-state resistance
SD = 0.8 V, no load
40
240
240
60
µA
IO = 500 mA, TJ = 25°C High Side
Excluding Metal and
Bond Wire Resistance
mΩ
Low side
G
Gain
25
26
14
27
dB
ms
µs
V
ton
Turn-on time
Turn-off time
Gate drive supply
SD = 2 V
tOFF
GVDD
SD = 0.8 V
IGVDD = 2 mA
2.5
6.9
6.4
7.4
VRINN = 3.1 V and VRINN = 2.9 V, or VRINN = 2.9 V and
VRINN = 3.1 V
tDCDET
DC detect time
950
ms
AC CHARACTERISTICS
200-mVPP ripple at 1 kHz,
Gain = 26 dB, Inputs ac-coupled to GND
PSRR
Power supply ripple rejection
–65
dB
PO
Continuous output power
THD+N = 10%, f = 1 kHz
10
10
W
W
W
PO
Continuous output power
THD+N = 10%, f = 1 kHz, PVCC = 13 V, RL = 8 Ω
THD+N = 10%, f = 1 kHz, PVCC = 13 V, RL = 4 Ω
f = 1 kHz, PO = 5 W (half-power)
PO
Continuous output power, PBTL (mono)
Total harmonic distortion + noise
20
THD+N
0.06%
91
µV
dBV
dB
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 26 dB
–81
–75
Crosstalk
VO = 1 Vrms, Gain = 26 dB, f = 1 kHz
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 26 dB, A-weighted
SNR
OTE
Signal-to-noise ratio
102
dB
Thermal trip point
Thermal hysteresis
150
15
°C
°C
(1) Using the TPA3136D2 EVM (SLOU444), unless otherwise noted.
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
315
MAX
355
UNIT
fOSC, SS
Oscillator frequency, Spread Spectrum ON
255
kHz
Copyright © 2016–2020, Texas Instruments Incorporated
7
TPA3136D2, TPA3136AD2
ZHCSF30F –MAY 2016–REVISED JANUARY 2020
www.ti.com.cn
7.7 Typical Characteristics
All Measurements taken at 26dB closed loop gain, 1-kHz audio, T A= 25°C unless otherwise noted. Measurements were
made with AES17 filter using the TPA3136D2 EVM, which is available at ti.com.
10
10
1W
2.5W
5W
1W
2.5W
5W
1
1
0.1
0.1
0.01
0.01
0.001
0.001
20
50 100 200
500 1k
Frequency (Hz)
2k
5k 10k 20k
20
50 100 200
500 1k
Frequency (Hz)
2k
5k 10k 20k
D001
D002
AVCC=PVCC = 12 V, Load = 6 Ω + 47 µH, 1 W, 2.5 W, 5 W
AVCC=PVCC = 13 V, Load = 8 Ω + 66 µH, 1 W, 2.5 W, 5 W
Figure 1. Total Harmonic Distortion vs Frequency (BTL)
Figure 2. Total Harmonic Distortion vs Frequency (BTL)
10
10
20 Hz
1 kHz
20 Hz
1 kHz
1
1
0.1
0.1
0.01
10m 20m 50m 100m200m 500m
Output Power (W)
0.01
10m 20m 50m 100m200m 500m
Output Power (W)
1
2
5
10 20
1
2
5
10 20
D003
D004
AVCC=PVCC = 12 V, Load = 6 Ω + 47 µH, 20 Hz, 1 kHz
AVCC=PVCC = 13 V, Load = 8 Ω + 66 µH, 20 Hz, 1 kHz
Figure 3. Total Harmonic Distortion + Noise vs Output
Power (BTL)
Figure 4. Total Harmonic Distortion + Noise vs Output
Power (BTL)
20
16
18
16
14
12
10
8
14
12
10
8
6
6
4
4
2
2
0
0
4
5
6
7
8
9
Supply Voltage (V)
10 11 12 13 14 15
4
5
6
7
8
9
Supply Voltage (V)
10 11 12 13 14 15
D005
D006
AVCC=PVCC = 4.5 V to 14.4 V, Load = 6 Ω + 47 µH
Figure 5. Output Power vs Supply Voltage (BTL)
AVCC=PVCC = 4.5 V to 14.4 V, Load = 8 Ω + 66 µH
Figure 6. Output Power vs Supply Voltage (BTL)
8
Copyright © 2016–2020, Texas Instruments Incorporated
TPA3136D2, TPA3136AD2
www.ti.com.cn
ZHCSF30F –MAY 2016–REVISED JANUARY 2020
Typical Characteristics (continued)
All Measurements taken at 26dB closed loop gain, 1-kHz audio, T A= 25°C unless otherwise noted. Measurements were
made with AES17 filter using the TPA3136D2 EVM, which is available at ti.com.
36
32
28
24
20
16
12
8
300
240
180
120
60
100
90
80
70
60
50
40
30
20
10
0
0
-60
-120
-180
-240
PVcc = 6V
PVcc = 12V
PVcc = 14.4V
Gain
Phase
4
0
20
50 100 200
500 1k
Frequency
2k
5k 10k 20k
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Total Output Power (W)
D007
D008
AVCC=PVCC = 12 V, Load = 6 Ω + 47 µH (device pins)
AVCC=PVCC = 6 V, 12 V, 14.4 V, Load = 6 Ω + 47 µH
Figure 7. Gain/Phase vs Frequency (BTL)
Figure 8. Efficiency vs Output Power (BTL)
100
0
Ch 2 to Ch1
Ch 1 to Ch2
-10
-20
90
80
70
60
50
40
30
-30
-40
-50
-60
-70
-80
-90
20
PVcc = 6V
PVcc = 13V
PVcc = 14.4V
-100
-110
-120
10
0
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Power (W)
20
50 100 200
500 1k
Frequency (Hz)
2k
5k 10k 20k
D009
D010
AVCC=PVCC= 6 V, 13 V, 14.4 V, Load = 8 Ω + 66 µH
AVCC=PVCC = 12 V, 1 W, Load = 6 Ω + 47 µH
Figure 9. Efficiency vs Output Power (BTL)
Figure 10. Crosstalk vs Frequency (BTL)
0
10
1 W
2.5 W
5 W
5
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
20
50 100 200
500 1k
Frequency (Hz)
2k
5k 10k 20k
20
50 100 200
500 1k
Frequency (Hz)
2k
5k 10k 20k
D011
D012
AVCC=PVCC = 12 V, Load = 4 Ω + 33 µH
AVCC=PVCC = 13 V, Load = 4 Ω + 33 µH, 1 W, 2.5 W, 5 W
Figure 11. Supply Ripple Rejection Ratio vs Frequency
(BTL)
Figure 12. Total Harmonic Distortion + Noise vs Frequency
(PBTL)
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Typical Characteristics (continued)
All Measurements taken at 26dB closed loop gain, 1-kHz audio, T A= 25°C unless otherwise noted. Measurements were
made with AES17 filter using the TPA3136D2 EVM, which is available at ti.com.
10
32
28
24
20
16
12
8
20 Hz
1 kHz
1
0.1
0.01
4
0
10m 20m 50m100m200m 500m 1
Output Power (W)
2
5
10 20
4
5
6
7
8
9
Supply Voltage (V)
10 11 12 13 14 15
D013
D014
AVCC=PVCC = 13 V, Load = 4 Ω + 33 µH, 20 Hz, 1 kHz
AVCC=PVCC = 4.5 V to 14.4 V, Load = 4 Ω + 33 µH
Figure 13. Total Harmonic Distortion + Noise vs Output
Power (PBTL)
Figure 14. Output Power vs Supply Voltage (PBTL)
100
90
80
70
60
50
40
30
20
10
0
PVcc = 6V
PVcc = 13V
PVcc = 14.4V
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Total Output Power (W)
D015
AVCC=PVCC = 6 V, 13 V, 14.4 V, Load = 4 Ω + 33 µH
Figure 15. Efficiency vs Output Power (PBTL)
8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications section.
Most audio analyzers will not give correct readings of Class-D amplifiers’ performance due to their sensitivity to
out of band noise present at the amplifier output. An AES-17 pre analyzer filter is recommended to use for Class-
D amplifier measurements. In absence of such filter, a 30-kHz low-pass filter (10 Ω + 47 nF) can be used to
reduce the out of band noise remaining on the amplifier outputs.
10
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9 Detailed Description
9.1 Overview
To facilitate system design, the TPA3136D2, TPA3136AD2 needs only a single power supply between 4.5 V (8V
for TPA3136AD2) and 14.4 V for operation. An internal voltage regulator provides suitable voltage levels for the
gate driver, digital, and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply,
as in the high-side gate drive, is accommodated by built-in bootstrap circuitry with integrated boot strap diodes
requiring only an external capacitor for each half-bridge.
The audio signal path, including the gate drive and output stage, is designed as identical, independent full-
bridges. All decoupling capacitors should be placed as close to their associated pins as possible. In general, the
physical loop with the power supply pins, decoupling capacitors and GND return path to the device pins must be
kept as short as possible and with as little area as possible to minimize induction (see reference board
documentation for additional information).
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BSXX) to the power-stage output pin (OUTXX). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD) and the bootstrap
pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential
and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching
frequencies in the range of 315 kHz, use ceramic capacitors with at least 220-nF capacitance, size 0603 or 0805,
for the bootstrap supply. These capacitors ensure sufficient energy storage, even during clipped low frequency
audio signals, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of its
ON cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. For optimal electrical performance, EMI compliance, and system reliability, each PVCC
pin should be decoupled with ceramic capacitors that are placed as close as possible to each supply pin. It is
recommended to follow the PCB layout of the TPA3136D2, TPA3136AD2 reference design. For additional
information on recommended power supply and required components, see the application diagrams in this data
sheet.
The PVCC power supply should have low output impedance and low noise. The power-supply ramp and SD
release sequence is not critical for device reliability as facilitated by the internal power-on-reset circuit, but it is
recommended to release SD after the power supply is settled for minimum turn on audible artifacts.
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9.2 Functional Block Diagram
GVDD
BSPL
PVCC
PVCC
OUTPL
FB
Gate
Drive
OUTPL
PBTL Select
OUTPL FB
GND
LINP
LINN
PWM
Logic
BSNL
PLIMIT
GVDD
PVCC
PVCC
OUTNL FB
FAULT
OUTNL
FB
Gate
Drive
OUTNL
GND
TTL
Buffer
SD
SD Detect
DC Detect
Startup
Protection
Logic
Biases and
References
Spread Spectrum
Control
Ramp
Generator
Thermal
Detect
UVLO/
OVLO
LIMITER
Reference
BSNR
PLIMIT
GVDD
PVCC
AVDD
PVCC
LDO
AVCC
Regulator
GVDD
Gate
Drive
OUTNR
GVDD
+
OUTNR FB
OUTNR
FB
œ
œ
œ
RINN
RINP
GND
+
PWM
Logic
PLIMIT
BSPR
œ
GVDD
+
+
+
PVCC
PVCC
OUTNR FB
œ
Gate
Drive
PBTL Select
OUTPR
OUTPR
FB
PBTL
Control
PBTL
GND
12
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9.3 Feature Description
9.3.1 Fixed Analog Gain
The analog gain of the TPA3136D2, TPA3136AD2 is fixed to 26 dB.
9.3.2 SD Operation
The TPA3136D2, TPA3136AD2 device employs a shutdown mode of operation designed to reduce supply
current (ICC) to the absolute minimum level during periods of nonuse for power conservation. The SD input pin
should be held high (see specification table for trip point) during normal operation when the amplifier is in use.
Pulling SD low causes the outputs to mute and the amplifier to enter a low-current state. Never leave SD
unconnected, because amplifier operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power
supply voltage.
9.3.3 PLIMIT
The PLIMIT operation will, if selected, limit the output voltage level to a voltage level below the supply rail. In this
case, the amplifier operates as if it was powered by a lower supply voltage, and thereby limiting the output power
by voltage clipping. PLIMIT threshold is set by the PLIMIT pin voltage.
Figure 16. PLIMIT Circuit Operation
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle
to a fixed maximum value. The limit can be thought of as a "virtual" voltage rail which is lower than the supply
connected to PVCC. The "virtual" rail is approximately four times the voltage at the PLIMIT pin. The output
voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker
impedance.
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Feature Description (continued)
æ
ö2
æ
ç
è
ö
÷
ø
RL
´ V
ç
÷
P
ç
÷
RL + 2 ´ RS
è
ø
POUT
=
for unclipped power
2 ´ RL
where
•
•
•
•
POUT (10%THD) = 1.25 × POUT (unclipped)
RL is the load resistance.
RS is the total series resistance including RDS(on), and output filter resistance.
VP is the peak amplitude, which is limited by "virtual" voltage rail.
(1)
9.3.4 Spread Spectrum and De-Phase Control
The TPA3136D2, TPA3136AD2 device has built-in spread spectrum control of the oscillator frequency and de-
phase of the PWM outputs to improve EMI performance. The spread spectrum schemes is internally fixed is
always turned on.
De-phase inverts the phase of the output PWM such that the idle output PWM waveforms of the two audio
channels are inverted. De-phase does not affect the audio signal, or its polarity.
9.3.5 GVDD Supply
The GVDD Supply is used to power the gates of the output full bridge transistors. Add a 1-μF capacitor to ground
at this pin.
9.3.6 DC Detect
The TPA3136D2, TPA3136AD2 device has circuitry which will protect the speakers from DC current which might
occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect
fault will be reported on the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to
shutdown by changing the state of the outputs to Hi-Z.
A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 24% (±10%) for
more than 950 msec at the same polarity. This feature protects the speaker from large DC currents or AC
currents less than 2 Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at power-up
until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and
negative inputs to avoid nuisance DC detect faults.
The minimum differential input voltage required to trigger the DC detect is 130 mV.
9.3.7 PBTL Select
The TPA3136D2, TPA3136AD2 device offers the feature of parallel BTL operation with two outputs of each
channel connected directly. If the PBTL (pin 14) is tied high, the positive and negative outputs of each channel
(left and right) are synchronized and in phase. To operate in this PBTL (mono) mode, tie PBTL pin to VCC and
apply the input signal to the RINP and RINN inputs and place the speaker between the LEFT and RIGHT outputs
with OUTPL connected to OUTNL and OUTPR connected to OUTNR to parallel the output half bridges for
highest power efficiency. For an example of the PBTL connection, see the schematic in the Typical Applications
section.
9.3.8 Short-Circuit Protection and Automatic Recovery Feature
The TPA3136D2, TPA3136AD2 device has protection from overcurrent conditions caused by a short circuit on
the output stage. The short circuit protection fault is reported on the FAULT pin as a low state. The amplifier
outputs are switched to a Hi-Z state when the short circuit protection latch is engaged. The latch can be cleared
by cycling the SD pin through the low state.
If automatic recovery from the short circuit protection latch is desired, connect the FAULT pin directly to the SD
pin. This allows the FAULT pin function to automatically drive the SD pin low which clears the short-circuit
protection latch.
14
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Feature Description (continued)
9.3.9 Thermal Protection
Thermal protection on the TPA3136D2, TPA3136AD2 device prevents damage to the device when the internal
die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die
temperature exceeds the thermal trip point, the device enters into the shutdown state and the outputs are
disabled. This is a latched fault.
Thermal protection faults are reported on the FAULT pin.
If automatic recovery from the thermal protection latch is desired, connect the FAULT pin directly to the SD pin.
This allows the FAULT pin function to automatically drive the SD pin low which clears the thermal protection
latch.
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9.4 Device Functional Modes
The TPA3136D2, TPA3136AD2 device is running in BD-modulation.
This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is
driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.
The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the
speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.
The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The
voltage across the load sits at 0 V throughout most of the switching period, reducing the switching current, which
reduces any I2R losses in the load.
OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
-
OUTP OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
OUTP-OUTN
-
PVCC
0A
Speaker
Current
Figure 17. BD Mode Modulation
16
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPA3136D2, TPA3136AD2 device is designed for use in inductor free applications with limited distance wire
length) between amplifier and speakers like in TV sets, sound docks and Bluetooth speakers. The TPA3136D2,
TPA3136AD2 device can either be configured in stereo or mono mode, depending on output power conditions.
Depending on output power requirements and necessity for (speaker) load protection, the built in PLIMIT circuit
can be used to control system power, see functional description of these features.
10.2 Typical Applications
PVCC
FB1
PVCCL
OUTPL
3.1A
C7
1000pF
C2
100 µF
C3
0.1µF
C4
1000pF
C6
1000pF
R2
68
PVCC
GND
GND
GND
6R
GND
PVCCR
GND
C8
100 µF
C9
0.1µF
C10
1000pF
FB2
OUTNL
C11
3.1A
LINP
LINN
GND
GND
GND
IN_LEFT
C13
1000pF
C14
1000pF
1µF
C15
PVCC
U1
AVCC
7
9
25
23
OUTPL
OUTNL
OUTPL
OUTNL
R4
68
R5
R6
1µF
GND
GVDD
C1
1µF
20
18
OUTNR
OUTPR
39k
56k
OUTNR
OUTPR
28
27
PVCCL
PVCCL
C16
1µF
GND
GND
26
22
21
17
C17
0.22µF
C18
0.22µF
C19
0.22µF
C20
0.22µF
BSPL
BSNL
BSNR
BSPR
16
15
GND
PVCCR
PVCCR
GND
FB3
GND
OUTNR
LINP
LINN
3
4
LINP
LINN
3.1A
C22
1000pF
C23
1000pF
RINN
RINP
11
12
C24
RINN
RINP
RINP
RINN
IN_RIGHT
1µF
C25
R8
68
PVCC
R9
SD
1
10
14
2
FAULT
GND
SD
FAULT
6R
PLIMIT
PBTL
PLIMIT
PBTL
1µF
24
19
PGND
PGND
100k
GND
GND
5
6
8
NC
NC
NC
GND
PAD
FB4
13
29
OUTPR
/SHUTDOWN
3.1A
C28
1000pF
TPA3136D2
C27
1000pF
GND
GND
GND
R11
68
GND
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 18. Stereo Class-D Amplifier with BTL Output and Single-Ended Inputs with Spread Spectrum
Modulation
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Typical Applications (continued)
PVCC
L1
10µH
C2
100 µF
C3
0.1µF
C4
1000pF
C6
0.68uF
PVCC
GND
GND
GND
GND
C8
100 µF
C9
0.1µF
C10
1000pF
GND
GND
GND
PVCC
U1
AVCC
7
9
25
23
OUTPL
OUTNL
R5
R6
GVDD
4R
C1
1µF
20
18
39k
56k
OUTNR
OUTPR
28
27
PVCCL
PVCCL
C16
1µF
GND
26
22
21
17
C17
0.47µF
BSPL
BSNL
BSNR
BSPR
16
15
PVCCR
PVCCR
GND
GND
C19
0.47µF
3
4
LINP
LINN
11
12
C24
RINN
RINP
RINP
RINN
IN
1µF
C25
PVCC
R9
SD
1
10
14
2
FAULT
SD
FAULT
PLIMIT
PLIMIT
PBTL
1µF
24
19
PGND
PGND
PVCC
100k
GND
5
6
8
NC
NC
NC
GND
PAD
L2
R10
100k
13
29
/SHUTDOWN
10µH
TPA3136D2
C27
0.68uF
GND
GND
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 19. Stereo Class-D Amplifier with PBTL Output and Single-Ended Input with Spread Spectrum
Modulation
10.2.1 Design Requirements
10.2.1.1 PCB Material Recommendation
FR-4 Glass Epoxy material with 1 oz. (35 µm) is recommended for use with the TPA3136D2, TPA3136AD2. The
use of this material can provide for higher power output, improved thermal performance, and better EMI margin
(due to lower PCB trace inductance). It is recommended to use several GND underneath the device thermal pad
for thermal coupling to a bottom side copper GND plane for best thermal performance.
10.2.1.2 PVCC Capacitor Recommendation
The large capacitors used in conjunction with each full-bridge, are referred to as the PVCC Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 100 μF, 16 V will support most applications
with 12-V power supply. 25-V capacitor rating is recommended for power supply voltage higher than 12 V. For
The PVCC capacitors should be low ESR type because they are used in a circuit associated with high-speed
switching.
10.2.1.3 Decoupling Capacitor Recommendations
In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the ceramic capacitors that are placed on the power supply to each full-bridge. They must withstand
the voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and
the ripple current created by high power output. A minimum voltage rating of 16 V is required for use with a 12-V
power supply.
18
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Typical Applications (continued)
10.2.2 Detailed Design Procedure
A rising-edge transition on SD input allows the device to start switching. It is recommended to ramp the PVCC
voltage to its desired value before releasing SD for minimum audible artifacts.
The device is non-inverting the audio signal from input to output.
The GVDD pin is not recommended to be used as a voltage source for external circuitry.
10.2.2.1 Ferrite Bead Filter Considerations
Using the Advanced Emissions Suppression Technology in the TPA3136D2, TPA3136AD2 amplifier it is possible
to design a high efficiency Class-D audio amplifier while minimizing interference to surrounding circuits. It is also
possible to accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select
the ferrite bead used in the filter.
One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite
material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to
the operation of the Class-D amplifier. Many of the specifications regulating consumer electronics have
emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30-MHz
and above range from appearing on the speaker wires and the power supply lines which are good antennas for
these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the
range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance,
the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz.
Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected
for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In
this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak
current the amplifier will see. If these specifications are not available, it is also possible to estimate the bead's
current handling capability by measuring the resonant frequency of the filter output at low power and at maximum
power. A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of
ferrite beads which have been tested and work well with the TPA3136D2, TPA3136AD2 device include
NFZ2MSM series from Murata.
A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good
temperature and voltage characteristics will work best.
Additional EMC improvements may be obtained by adding snubber networks from each of the class-D outputs to
ground. Suggested values for a simple RC series snubber network would be 68 Ω in series with a 100-pF
capacitor although design of the snubber network is specific to every application and must be designed taking
into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate
the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make
sure the layout of the snubber network is tight and returns directly to the GND or the thermal pad beneath the
chip.
10.2.2.2 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA3136D2, TPA3136AD2 modulation scheme has little loss in the load without a filter because the pulses
are short and the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen,
making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for
most applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
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Typical Applications (continued)
10.2.2.3 When to Use an Output Filter for EMI Suppression
The TPA3136D2 device has been tested with a simple ferrite bead filter for a variety of applications including
long speaker wires up to 100 cm and high power. The TPA3136D2 EVM passes FCC Class B specifications
under these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet
application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency.
There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These
circumstances might occur if there are nearby circuits which are sensitive to noise. In these cases, a classic
second order Butterworth filter similar to those shown in the following figures can be used.
Some systems have little power supply decoupling from the AC line, but are also subject to line conducted
interference (LCI) regulations. These include systems powered by "wall warts" and "power bricks." In these
cases, LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using
low frequency ferrite material can also be effective at preventing line conducted interference.
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 20. Typical Ferrite Chip Bead Filter (Chip Bead Example: NFZ2MSM series from Murata)
33 mH
OUTP
C2
L1
1 mF
33 mH
OUTN
C3
L2
1 mF
Figure 21. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω
15 mH
OUTP
C2
L1
2.2 mF
15 mH
OUTN
C3
2.2 mF
L2
Figure 22. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 6 Ω
10.2.2.4 Input Resistance
The typical input resistance of the amplifier is fixed to 30 kΩ ±20%.
20
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Typical Applications (continued)
Z
f
C
i
Z
i
IN
Input
Signal
10.2.2.5 Input Capacitor, Ci
In the typical application, an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, Ci and the input impedance of the amplifier (Zi) form a high-
pass filter with the corner frequency determined in Equation 2.
-3 dB
1
2p Zi Ci
fc
=
f
c
(2)
The value of Ci is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where Zi is 30 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 2 is
reconfigured as Equation 3.
1
Ci =
2p Zi fc
(3)
In this example, Ci is 0.27 µF; so, one would likely choose a value of 0.33 μF as this value is commonly used. A
further consideration for this capacitor is the leakage path from the input source through the input network (Ci)
and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the
amplifier that reduces useful headroom. For this reason, a low-leakage tantalum or ceramic capacitor is the best
choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in
most applications as the dc level there is held at 3 V, which is likely higher than the source dc level. Note that it
is important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset
voltages and it is important to ensure that boards are cleaned properly.
10.2.2.6 BSN and BSP Capacitors
The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 0.22-μF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 0.22-μF capacitor must be
connected from OUTPx to BSPx, and one 0.22-μF capacitor must be connected from OUTNx to BSNx. (See the
application circuit diagram in Figure 18.)
The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating
power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching
cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs
turned on.
Copyright © 2016–2020, Texas Instruments Incorporated
21
TPA3136D2, TPA3136AD2
ZHCSF30F –MAY 2016–REVISED JANUARY 2020
www.ti.com.cn
Typical Applications (continued)
10.2.2.7 Differential Inputs
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3136D2, TPA3136AD2 device with a differential source, connect the positive lead of the audio
source to the INP input and the negative lead from the audio source to the INN input. To use the TPA3136D2,
TPA3136AD2 with a single-ended source, ac ground the INP or INN input through a capacitor equal in value to
the input capacitor on INN or INP and apply the audio source to either input. In a single-ended input application,
the unused input should be ac grounded at the audio source instead of at the device input for best noise
performance. For good transient performance, the impedance seen at each of the two differential inputs should
be the same.
The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to
allow the input dc blocking capacitors to become completely charged during the 14-ms power-up time. If the input
capacitors are not allowed to completely charge, there is some additional sensitivity to component matching
which can result in pop if the input components are not well matched.
10.2.2.8 Using Low-ESR Capacitors
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.
22
Copyright © 2016–2020, Texas Instruments Incorporated
TPA3136D2, TPA3136AD2
www.ti.com.cn
ZHCSF30F –MAY 2016–REVISED JANUARY 2020
Typical Applications (continued)
10.2.3 Application Performance Curves
10.2.3.1 EN55013 Radiated Emissions Results
TPA3136D2 EVM, PVCC = 12 V, 8-Ω speakers, PO = 4 W
Figure 23. Radiated Emission - Horizontal
Figure 24. Radiated Emission - Vertical
10.2.3.2 EN55022 Conducted Emissions Results
TPA3136D2 EVM, PVCC = 12 V, 8-Ω speakers, PO = 4 W
EN55022 Class B
EN55022 Class B
80
80
70
60
50
40
30
20
QP readings
QP limit
QP readings
QP limit
70
60
50
40
30
20
0.15
0.3 0.5
1
2
Frequency (MHz)
3
5
10
20 30
0.15
0.3 0.5
1
2
Frequency (MHz)
3
5
10
20 30
Figure 25. Conducted Emission - Line
Figure 26. Conducted Emission - Neutral
Copyright © 2016–2020, Texas Instruments Incorporated
23
TPA3136D2, TPA3136AD2
ZHCSF30F –MAY 2016–REVISED JANUARY 2020
www.ti.com.cn
11 Power Supply Recommendations
11.1 Power Supply Decoupling, CS
The TPA3136D2, TPA3136AD2 device is a high-performance CMOS audio amplifier that requires adequate
power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power
supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker.
Optimum decoupling is achieved by using a network of capacitors of different types that target specific types of
noise on the power supply leads. For higher frequency transients due to parasitic circuit elements such as bond
wire and copper trace inductances as well as lead frame capacitance, a good quality low equivalent-series-
resistance (ESR) ceramic capacitor of value between 220 pF and 1000 pF works well. This capacitor should be
placed as close to the device PVCC pins and system ground (either GND pins or thermal pad) as possible. For
mid-frequency noise due to filter resonances or PWM switching transients as well as digital hash on the line,
another good quality capacitor typically 0.1 μF to 1 µF placed as close as possible to the device PVCC leads
works best. For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 100 μF or
greater placed near the audio power amplifier is recommended. The 100-μF capacitor also serves as a local
storage capacitor for supplying current during large signal transients on the amplifier outputs. The PVCC pins
provide the power to the output transistors, so a 100-µF or larger capacitor should be placed on each PVCC pin.
A 1-µF capacitor on the AVCC pin is adequate. Also, a small decoupling resistor between AVCC and PVCC can
be used to keep high frequency class-D noise from entering the linear input amplifiers.
24
Copyright © 2016–2020, Texas Instruments Incorporated
TPA3136D2, TPA3136AD2
www.ti.com.cn
ZHCSF30F –MAY 2016–REVISED JANUARY 2020
12 Layout
12.1 Layout Guidelines
The TPA3136D2, TPA3136AD2 device can be used with a small, inexpensive ferrite bead output filter for most
applications. However, since the Class-D switching edges are fast, it is necessary to take care when planning the
layout of the printed circuit board. The following suggestions will help to meet EMC requirements.
•
Decoupling capacitors—The high-frequency decoupling capacitors should be placed as close to the PVCC
and AVCC pins as possible. Large (100-µF or greater) bulk power supply decoupling capacitors should be
placed near the TPA3136D2, TPA3136AD2 device on the PVCC supplies. Local, high-frequency bypass
capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the
thermal pad directly for an excellent ground connection. Consider adding a small, good quality low ESR
ceramic capacitor between 220 pF and 1000 pF and a larger mid-frequency cap of value between 0.1 μF and
1 μF also of good quality to the PVCC connections at each end of the chip.
•
•
Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to
GND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna.
Grounding—The AVCC (pin 14) decoupling capacitor should be connected to ground (GND). The PVCC
decoupling capacitors should connect to GND. Analog ground and power ground should be connected at the
thermal pad, which should be used as a central ground connection or star ground for the TPA3136D2,
TPA3136AD2.
•
•
Output filter—The ferrite EMI filter (Figure 20) should be placed as close to the output pins as possible for the
best EMI performance. The capacitors used in the ferrite should be grounded to power ground.
Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the thermal pad and thermal land should be 6.46 mm × 2.35 mm. Six rows of
solid vias (three vias per row, 0.3302 mm or 13 mils diameter) should be equally spaced underneath the
thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom
layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See the TI Application
Report SLMA002 for more information about using the TSSOP thermal pad. For recommended PCB
footprints, see figures at the end of this data sheet.
For an example layout, see the TPA3136D2 Evaluation Module (TPA3136D2EVM) User Manual. Both the EVM
user manual and the thermal pad application report are available on the TI Web site at http://www.ti.com.
Copyright © 2016–2020, Texas Instruments Incorporated
25
TPA3136D2, TPA3136AD2
ZHCSF30F –MAY 2016–REVISED JANUARY 2020
www.ti.com.cn
12.2 Layout Example
100mF
100nF
FB
1
2
3
4
5
6
7
28
27
26
25
24
23
22
1nF
1nF
1nF
0.22mF
FB
FB
0.22mF
0.22mF
1mF
8
21
9
20
19
18
17
1mF
10
1nF
1nF
11
12
0.22mF
13
14
16
15
1nF
FB
100nF
100mF
Top Layer Ground and Thermal Pad
Via to Bottom Ground Plane
Top Layer Signal Traces
Pad to Top Layer Ground Pour
Figure 27. BTL Layout Example
26
版权 © 2016–2020, Texas Instruments Incorporated
TPA3136D2, TPA3136AD2
www.ti.com.cn
ZHCSF30F –MAY 2016–REVISED JANUARY 2020
13 器件和文档支持
13.1 器件支持
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
13.2 文档支持
13.2.1 相关文档
《PowerPAD™ 耐热增强型封装应用报告》(文献编号:SLMA002)
13.3 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件,以及立即订购快速访问。
表 1. 相关链接
器件
产品文件夹
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
TPA3136D2
TPA3136AD2
13.4 接收文档更新通知
要接收文档更新通知,请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册,即可每周接收产品
信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
13.5 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.6 商标
SpeakerGuard, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.7 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
13.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2016–2020, Texas Instruments Incorporated
27
TPA3136D2, TPA3136AD2
ZHCSF30F –MAY 2016–REVISED JANUARY 2020
www.ti.com.cn
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
28
版权 © 2016–2020, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPA3136AD2PWP
TPA3136AD2PWPR
TPA3136D2PWP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
HTSSOP
HTSSOP
PWP
PWP
PWP
PWP
28
28
28
28
50
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 85
-40 to 85
TPA3136AD2
2000 RoHS & Green
50 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
TPA3136AD2
TPA3136D2
TPA3136D2
TPA3136D2PWPR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA3136AD2PWPR
TPA3136D2PWPR
HTSSOP PWP
HTSSOP PWP
28
28
2000
2000
330.0
330.0
16.4
16.4
6.9
6.9
10.2
10.2
1.8
1.8
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPA3136AD2PWPR
TPA3136D2PWPR
HTSSOP
HTSSOP
PWP
PWP
28
28
2000
2000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TPA3136AD2PWP
TPA3136D2PWP
PWP
PWP
HTSSOP
HTSSOP
28
28
50
50
530
530
10.2
10.2
3600
3600
3.5
3.5
Pack Materials-Page 3
GENERIC PACKAGE VIEW
PWP 28
4.4 x 9.7, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224765/B
www.ti.com
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