TPA3138D2PWPR [TI]

无电感器型、10W 立体声、18.5W 单声道、3.5V 至 14.4V、模拟输入 D 类音频放大器 | PWP | 28 | -40 to 85;


型号：	TPA3138D2PWPR
厂家：	TEXAS INSTRUMENTS
描述：	无电感器型、10W 立体声、18.5W 单声道、3.5V 至 14.4V、模拟输入 D 类音频放大器 \| PWP \| 28 \| -40 to 85 放大器光电二极管商用集成电路音频放大器电感器
文件：	总38页 (文件大小：1757K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPA3138D2

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

TPA3138D2 10W、3.5V 至 14.4V、无电感器、立体声 D 类扬声器放大器

1 特性

2 应用

•

宽电源电压范围 3.5V 至 14.4V

•

电视和监控器

Bluetooth^®扬声器和无线扬声器

智能设备中的音频放大器

物联网中的音频扬声器

消费类音频设备

–

6Ω、1% THD+N、12V 电源条件下，功率为 2

× 10W

4Ω、10% THD+N、12V 电源条件下，功率为 1

x 18.5W

1W、1kHz 输入、6Ω 条件下，THD+N 为

0.04%

3 说明

•

电池寿命更长，适用于便携式应用：

TPA3138D2 是一款每通道功率为 10W 的高效率、低

空闲电流 D 类立体声音频放大器。它可驱动负载低至

3.2Ω 的立体声扬声器。在 1SPW 模式下，它仅消耗

21mA (12V) 的低空闲电流，且可在低至 3.5V 条件下

运行，从而可实现更长的音频播放时间并改善蓝牙扬声

器、电池供电设备和其他功率敏感性应用中的热性能

范围内实现精确性能。

–

1SPW 模式下，空闲电流为 20mA (12V)

>90% D 类效率

降低了解决方案尺寸和成本：

–

无电感器运行

不使用电感器时，符合 EN55013 和 EN55022

EMC 标准

–

无需外部散热器

利用扩频控制实现先进的 EMI 抑制功能，允许在满足

EMC 降低系统成本要求的同时，使用价格低廉的铁氧

体磁珠滤波器。

•

灵活的音频解决方案：

–

单端或差动模拟输入

可选增益：20dB 和 26dB

启动时无喀哒声

为了进一步简化设计，TPA3138D2 集成了重要的保护

特性，包括欠压、过压、功率限制、短路、过热以及

直流扬声器保护。所有这些保护都可以自动恢复。

综合保护和自动恢复：

–

引脚对引脚、引脚对地、引脚对电源短路保护

热保护、欠压保护和过压保护

客户可以利用现有设计中的每个 TPA3138D2 特性，

因为它与 TI 的 TPA3110D2、TPA3136D2 和

TPA3136AD2 完全引脚对引脚兼容。

功率限制器和直流扬声器保护

与 TPA3110D2、TPA3136D2 和 TPA3136AD2 引

脚对引脚兼容

器件信息⁽¹⁾

器件型号

TPA3138D2

封装

封装尺寸（标称值）

HTSSOP (28)

9.70mm × 4.40mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

简化原理图

采用铁氧体磁珠的 TPA3138 布局

TPA3138D2

RIGHT

Audio

Source

And Control

PBTL

DETECT

LEFT

SD/FAULT

Power Supply

3.5V t 14.4V

PVCC/AVCC

GAIN_SEL

MOD_SEL

PLIMIT

20dB/26dB GAIN Select

Modulation Schemes/UV Level Select

Power Limit

20.50 mm

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLOS993

TPA3138D2

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

www.ti.com.cn

9.3 Feature Description................................................. 13

9.4 Device Functional Modes........................................ 16

10 Application and Implementation........................ 18

10.1 Application Information.......................................... 18

10.2 Typical Applications ............................................. 18

11 Power Supply Recommendations ..................... 25

11.1 Power Supply Decoupling, C_S............................. 25

12 Layout................................................................... 26

12.1 Layout Guidelines ................................................. 26

12.2 Layout Example .................................................... 27

13 器件和文档支持 ..................................................... 28

13.1 器件支持 ............................................................... 28

13.2 文档支持 ............................................................... 28

13.3 接收文档更新通知 ................................................. 28

13.4 社区资源................................................................ 28

13.5 商标....................................................................... 28

13.6 静电放电警告......................................................... 28

13.7 术语表 ................................................................... 28

14 机械、封装和可订购信息....................................... 28

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings ............................................................ 5

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 7

7.6 Switching Characteristics.......................................... 7

7.7 Typical Characteristics.............................................. 8

Parameter Measurement Information ................ 10

Detailed Description ............................................ 11

9.1 Overview ................................................................. 11

9.2 Functional Block Diagram ....................................... 12

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (March 2018) to Revision A

Page

•

更改了器件状态：将“预告信息”更改成了“生产数据” ............................................................................................................... 1

TPA3138D2

www.ti.com.cn

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

5 Device Comparison Table

Product

Supply Voltage Modulation Scheme

Package

Rdson

180-mΩ

240-mΩ

Gain

20-dB, 26-dB

20-dB, 26-dB, 32-dB, 36-dB

26-dB

Inductor Free

TPA3138D2

TPA3110D2

TPA3136D2

TPA3136AD2

3.5-V to 14.4-V

8-V to 26-V

BD, 1SPW

HTSSOP-28

YES

4.5-V to 14.4-V

8-V to 14.4-V

YES

26-dB

6 Pin Configuration and Functions

PWP Package

28-Pin HTSSOP

(Top View)

SD/FAULT

LINP

PVCCL

BSPL

LINN

OUTPL

GND

GAIN_SEL

MODE_SEL

AVCC

OUTNL

BSNL

Thermal

Pad

GND

BSNR

OUTNR

GND

GVDD

PLIMIT

RINN

OUTPR

BSPR

RINP

PVCCR

AGND

Not to scale

Pin Functions

I/O/P⁽¹⁾

DESCRIPTION

NAME

NO.

–

No Connect Pin. Can be shorted to PVCC or shorted to GND or left open.

TTL logic levels with compliance to AVCC. Shutdown logic input for audio amp (LOW , outputs Hi-Z;

HIGH , outputs enabled). General fault reporting including Over-Temp, Over-Current, DC Detect.

SD/FAULT= High, normal operation, SD/FAULT= Low, fault condition Device will auto-recover once

the OT/OC/DC Fault has been removed.

SD/FAULT

LINP

LINN

Positive audio input for left channel. Biased at 2.5 V. Connect to GND for PBTL mode.

Negative audio input for left channel. Biased at 2.5 V. Connect to GND for PBTL mode.

Gain select least significant bit. TTL logic levels with compliance to AVDD. Low = 20 dB Gain, High =

26 dB Gain, Floating = 26 dB Gain.

GAIN_SEL

(1) I = Input, O = Output, IO = Input and Output, P = Power

TPA3138D2

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

www.ti.com.cn

Pin Functions (continued)

I/O/P⁽¹⁾

DESCRIPTION

NAME

NO.

Mode select least significant bit. TTL logic levels with compliance to AVDD. Low = BD Mode/UV

Threshold = 7.5 V, High = Low-Idle-Current 1SPW Mode/UV Threshold = 3.4V, Floating = Low-Idle-

Current 1SPW Mode/UV threshold = 3.4V

MODE_SEL

AVCC

GND

–

Analog supply.

Analog signal ground.

GVDD

FET gate drive supply. Nominal voltage is 5 V.

Power limiter level control. Connect a resistor divider from GVDD to GND to set power limit. Connect

directly to GVDD for no power limit.

PLIMIT

RINN

RINP

Negative audio input for right channel. Biased at 2.5 V.

Positive audio input for right channel. Biased at 2.5 V.

No Connect Pin. Can be shorted to PVCC or shorted to GND or left open.

Analog signal ground. Connect to the thermal pad.

–

AGND

Power supply for right channel H-bridge. Right channel and left channel power supply inputs are

connected internally.

PVCCR

15, 16

BSPR

OUTPR

GND

–

Bootstrap supply (BST) for right channel, positive high-side FET.

Class-D H-bridge positive output for right channel.

Power ground for the H-bridges.

OUTNR

BSNR

BSNL

–

Class-D H-bridge negative output for right channel.

Bootstrap supply (BST) for right channel, negative high-side FET.

Bootstrap supply (BST) for left channel, negative high-side FET.

Class-D H-bridge negative output for left channel.

Power ground for the H-bridges.

OUTNL

GND

OUTPL

BSPL

Class-D H-bridge positive output for left channel.

Bootstrap supply (BST) for left channel, positive high-side FET.

Power supply for left channel H-bridge. Right channel and left channel power supply inputs are

connected internally.

PVCCL

27, 28

–

Thermal Pad

Connect to GND for best thermal and electrical performance

TPA3138D2

www.ti.com.cn

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Supply voltage

Input current

AVCC to GND, PVCC to GND

To any pin except supply pins

–0.3

AVCC + 0.3

SD/FAULT to GND⁽²⁾, GAIN_SEL, MODE_SEL

V/ms

Interface pin voltage

PLIMIT

-0.3

–0.3

4.8

GVDD + 0.3

5.5

RINN, RINP, LINN, LINP

BTL, (10 V < PVCC < 14.4 V)

BTL, (3.5 V < PVCC < 10 V)

PBTL, (10 V < PVCC < 14.4 V)

PBTL, (3.5 V < PVCC < 10 V)

3.2

Minimum load resistance, R_L

2.4

1.6

See the Thermal

Information Table

Continuous total power dissipation

Operating Juncation Temperature range

Storage temperature range, T_stg

–25

–40

150

125

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100 kΩ resister in series

with the pins.

7.2 ESD Ratings

VALUE

±1000

±250

UNIT

(1)

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001

Charged device model (CDM), per JEDEC specification JESD22-C101

V_(ESD)Electrostatic discharge

(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

TPA3138D2

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

www.ti.com.cn

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Supply voltage

TEST CONDITIONS

MIN

3.5

MAX

UNIT

V_CC

V_IH

V_IL

PVCC, AVCC

14.4

AVCC

0.8

High-level input voltage

Low-level input voltage

Low-level output voltage

High-level input current

SD/FAULT ⁽¹⁾, GAIN_SEL, MODE_SEL

SD/FAULT, GAIN_SEL, MODE_SEL⁽²⁾

SD/FAULT, R_PULL-UP=100 kΩ, PVCC = 14.4 V

SD/FAULT, GAIN_SEL, MODE_SEL, V_I= 2 V, AVCC = 12 V

V_OL

I_IH

0.8

µA

SD/FAULT, GAIN_SEL, MODE_SEL, V_I= 0.8 V, AVCC = 12

I_IL

Low-level input current

µA

T_A

T_J

Operating free-air temperature⁽³⁾

Operating junction temperature⁽³⁾

–10

-10

°C

150

(1) Set SD/FAULT to high level, make sure the pull-up resistor is larger than 4.7 kΩ and smaller than 500 kΩ

(2) Set GAIN_SEL and MODE_SEL to low level, make sure pull down resistor<10kΩ

(3) The TPA3138D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected

to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection

shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.

7.4 Thermal Information

TPA3138D2

THERMAL METRIC⁽¹⁾

PWP (HTSSOP)

UNIT

28 PINS

30.3

33.5

17.5

0.9

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

7.2

R_θJC(bot)

0.9

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

TPA3138D2

www.ti.com.cn

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

7.5 Electrical Characteristics

T_A= 25°C, AVCC = PVCC = 12 V, RL = 6 Ω. Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

AC CHARACTERISTICS

200-mV_PPripple at 1 kHz,

PSRR

Power supply ripple rejection

–70

Gain = 26 dB, Inputs ac-coupled to GND

THD+N = 1%, f = 1 kHz, PV_CC= 12 V, R_L= 6 Ω

THD+N = 10%, f = 1 kHz, PV_CC= 12 V, R_L= 6 Ω

THD+N = 1%, f = 1 kHz, PV_CC= 12 V, R_L= 8 Ω

THD+N = 10%, f = 1 kHz, PV_CC= 12 V, R_L= 8 Ω

THD+N = 10%, f = 1 kHz, PV_CC= 12 V, R_L= 4 Ω

f = 1 kHz, R_L= 3 Ω

P_O

Continuous output power, BTL

Continuous output power, PBTL (mono)

Maximum output current

P_O

9.9

18.5

3.5

0.04

P_O

I_O

THD+N

Total harmonic distortion + noise

f = 1 kHz, P_O= 5 W (half-power)

µV

dBV

µV

dBV

20 Hz to 22 kHz, A-weighted filter, Gain = 26 dB

–81

V_n

Output integrated noise

20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB

V_O= 1 Vrms, Gain = 26 dB, f = 1 kHz

-82.6

-95

Crosstalk

Maximum output at THD+N < 1%,

f = 1 kHz, Gain = 26 dB, A-weighted

SNR

OTE

Signal-to-noise ratio

102

Thermal trip point

Thermal hysteresis

150

°C

DC CHARACTERISTICS

Output offset voltage

(measured differentially)

| V_OS

I_CC

V_I= 0 V, Gain = 26 dB

1.5

SD/FAULT = 2 V, 10 µF + 680 nF output filter,

1SPW Mode, PV_CC= 12 V

Quiescent supply current

SD/FAULT = 2 V, 10 µF + 680 nF output filter,

BD Mode, PV_CC= 12 V

I_CC

Quiescent supply current

µA

I_CC(SD)

r_DS(on)

Quiescent supply current in shutdown mode

SD/FAULT = 0.8 V, no load

I_O= 500 mA, T_J= 25°C High Side

excluding metal and

bond wire resistance

180

Drain-source on-state resistance

mΩ

Low side

180

Gain

GAIN_SEL= 0.8 V

GAIN_SEL= 2 V

SD/FAULT = 2 V

SD/FAULT = 0.8 V

I_GVDD= 2 mA

2.9

µs

Gain

t_ON

Turn-on time

Turn-off time

Gate drive supply

t_OFF

GVDD

4.8

5.2

V_RINP= 2.6 V and V_RINN= 2.4 V,

or V_RINP= 2.4 V and V_RINN= 2.6 V

t_DCDET

DC detect time

800

OVP

UVP

Over Voltage Protection

Under Voltage Protection

15.8

7.5

MODE_SEL = 0.8 V (BD mode)

MODE_SEL = 2 V, or floating (1SPW mode)

3.4

7.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

NOM

MAX

340

UNIT

f_{OSC, SS}

Oscillator frequency, Spread Spectrum ON

305

kHz

TPA3138D2

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

www.ti.com.cn

7.7 Typical Characteristics

All measurements taken at audio frequency = 1 kHz, closed-loop gain = 26 dB, BD mode, T = 25°C, AES17 filter using the

TPA3138D2EVM, unless otherwise noted.

P _O=1W

P_O=2.5W

P_O=5W

P _O=1W

P_O=2.5W

P_O=5W

0.1

0.01

0.001

100

10k 20k

100

10k 20k

Frequency (Hz)

D001

D00412

AVCC=PVCC = 12 V, Load = 6 Ω + 47 µH, 1 W, 2.5 W, 5 W

AVCC=PVCC = 13 V, Load = 8 Ω + 66 µH, 1 W, 2.5 W, 5 W

图 1. THD+N vs Frequency (BTL)

图 2. THD+N vs Frequency (BTL)

f= 20Hz

f= 1kHz

f= 20Hz

f= 1kHz

0.5

0.3

0.2

0.3

0.2

0.1

0.05

0.03

0.02

0.03

0.02

0.01

0.1

0.01

0.1

Output Power (W)

D003

D004

AVCC=PVCC = 12 V, Load = 6 Ω + 47 µH, 20 Hz, 1 kHz

AVCC=PVCC = 13 V, Load = 8 Ω + 66 µH, 20 Hz, 1 kHz

图 3. THD+N vs Output Power (BTL)

图 4. THD+N + Noise vs Output Power (BTL)

THD+N=1%

THD+N=10%

THD+N=1%

THD+N=10%

Supply Voltage (V)

D005

D006

AVCC=PVCC = 7.5 V to 15 V, Load = 6 Ω + 47 µH

图 5. Output Power vs Supply Voltage (BTL)

AVCC=PVCC = 7.5 V to 15 V, Load = 8 Ω + 66 µH

图 6. Output Power vs Supply Voltage (BTL)

TPA3138D2

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ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

Typical Characteristics (接下页)

All measurements taken at audio frequency = 1 kHz, closed-loop gain = 26 dB, BD mode, T = 25°C, AES17 filter using the

TPA3138D2EVM, unless otherwise noted.

THD+N=1%

THD+N=10%

THD+N=1%

THD+N=10%

10 11 12 13 14 15 16

Supply Voltage (V)

D019

D018

AVCC=PVCC = 3.5 V to 15 V, Load = 6 Ω + 47 µH, Low-Idle-

AVCC= PVCC = 3.5 V to 15 V, Load = 8 Ω + 66 µH, Low-Idle-

Current 1SPW Mode

图 7. Output Power vs Supply Voltage (BTL)

图 8. Output Power vs Supply Voltage (BTL)

325

100

Gain

Phase

275

225

175

125

-25

-75

-125

PV_CC= 13V

PV_CC= 14.4 V

100

10k 20k

Frequency (Hz)

Two Channel Total Output Power (W)

D008

D007

D008

AVCC= PVCC = 12 V, Load = 6 Ω + 47 µH

AVCC=PVCC = 12 V, 14.4 V, Load = 6 Ω + 47 µH

图 10. Efficiency vs Output Power (BTL)

图 9. Gain and Phase vs Frequency (BTL)

100

CH2 to CH1

CH1 to CH2

-20

-40

-60

-80

-100

-120

PV_CC= 13V

PV_CC= 14.4 V

100

10k 20k

Two Channel Total Output Power (W)

D009

f - Frequency - Hz

D009

D010

AVCC=PVCC= 13 V, 14.4 V, Load = 8 Ω + 66 µH

图 11. Efficiency vs Output Power (BTL)

AVCC=PVCC = 12 V, 1 W, Load = 6 Ω + 47 µH

图 12. Crosstalk vs Frequency (BTL)

TPA3138D2

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

www.ti.com.cn

Typical Characteristics (接下页)

All measurements taken at audio frequency = 1 kHz, closed-loop gain = 26 dB, BD mode, T = 25°C, AES17 filter using the

TPA3138D2EVM, unless otherwise noted.

2.5W

20 Hz

1 kHz

0.1

0.01

0.001

100

10k 20k

10m

100m

f - Frequency - Hz

Po - Output Power - W

D012

D013

AVCC=PVCC = 13 V, Load = 4 Ω + 33 µH, 1 W, 2.5 W, 5 W

AVCC=PVCC = 13 V, Load = 4 Ω + 33 µH, 20 Hz, 1 kHz

图 13. THD+N vs Frequency (PBTL)

图 14. THD+N vs Output Power (PBTL)

100

THD+N=1%

THD+N=10%

PV_CC= 12V

PV_CC= 14.4 V

Supply Voltage (V)

Total Output Power (W)

D013

D014

AVCC=PVCC = 7.5 V to 14.4 V, Load = 4 Ω + 33 µH

AVCC=PVCC = 13 V, 14.4 V, Load = 4 Ω + 33 µH

图 16. Efficiency vs Output Power (PBTL)

图 15. Output Power vs Supply Voltage (PBTL)

8 Parameter Measurement Information

All parameters are measured according to the conditions described in the Specifications section.

Most audio analyzers does not give correct readings of Class-D amplifiers’ performance due to their sensitivity to

the out-of-band noise present at the amplifier outputs. An AES-17 pre-analyzer filter is recommended to use for

Class-D amplifier measurements. In absence of such filters, a 30-kHz low-pass filter (10 Ω + 47 nF) can be used

to reduce the out-of-band noise remaining on the amplifier outputs.

TPA3138D2

www.ti.com.cn

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

9 Detailed Description

9.1 Overview

The TPA3138D2 is designed as a low-idle-power, cost-effective, general-purpose Class-D audio amplifier. The

built-in spread spectrum control efficiently reduces EMI and enables the use of the ferrite beads instead of the

inductors for ≤2x10W applications.

To facilitate system design, the TPA3138D2 needs only a single power supply between 3.5 V and 14.4 V for

operation. An internal voltage regulator provides suitable voltage levels for the gate driver, digital, and low-

voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, as in the high-side gate drive,

is accommodated by built-in bootstrap circuitry with integrated boot strap diodes requiring only an external

capacitor for each half-bridge.

The audio signal path, including the gate drive and output stage, is designed as identical, independent full-

bridges. All decoupling capacitors should be placed as close as possible to their associated pins. The physical

loop with the power supply pins, decoupling capacitors, and GND return path to the device pins must be kept as

short as possible, and with as little area as possible to minimize induction (see reference board documentation

for additional information).

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin

(BSXX) to the power-stage output pin (OUTXX). When the power-stage output is low, the bootstrap capacitor is

charged through an internal diode connected between the gate-drive power-supply pin (GVDD) and the bootstrap

pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential

and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching

frequencies in the datasheet specified range, use ceramic capacitors with at least 220-nF capacitance, size 0603

or 0805, for the bootstrap supply. These capacitors ensure sufficient energy storage, even during clipped low

frequency audio signals, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining

part of its ON cycle.

Special attention should be paid to the power-stage power supply; this includes component selection, PCB

placement, and routing. For optimal electrical performance, EMI compliance, and system reliability, each PVCC

pin should be decoupled with ceramic capacitors that are placed as close as possible to each supply pin. It is

recommended to follow the PCB layout of the reference design. For additional information on recommended

power supply and required components, see the application diagrams in this data sheet.

The PVCC power supply should have low output impedance and low noise. The power-supply ramp and

SD/FAULT release sequence is not critical for device reliability as facilitated by the internal power-on-reset

circuit, but it is recommended to release SD/FAULT after the power supply is settled for minimum turn on audible

artifacts.

TPA3138D2

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

www.ti.com.cn

9.2 Functional Block Diagram

GVDD

PVCC

BSPL

PVCC

Input

PBTL

Sense

Select

Modulation Scheme

and PBTL Select

OUTPL FB

Gate

Drive

OUTPL

OUTNL FB

LINN

GND

BSNL

Gain

Control

PWM

Logic

PLIMIT

GVDD

PVCC

LINP

PVCC

OUTPL FB

OUTNL FB

OUTNL

Gate

Drive

FAULT

SD/FAULT

Gain

Control

SC Detect

GND

TTL

DC Detect

Buffer

GAIN_SEL

Modulation scheme

/UVLO Select

Biases and

References

Ramp

Generator

Startup Protection

Logic

Spread Spectrum

Control

Thermal

Detect

MOD_SEL

PLIMIT

UVLO/OVLO

LIMITER

Reference

GVDD

PVCC

BSNR

AVDD

GVDD

PVCC

UVLO Select

LDO

Regulator

AVCC

GVDD

Gate

OUTNR

Drive

OUTNR FB

OUTPR FB

RINN

RINP

GND

BSPR

Gain

Control

PWM

Logic

PLIMIT

GVDD

PVCC

OUTNR FB

Gate

Drive

OUTPR

Modulation Scheme

and PBTL Select

GND

OUTPR FB

GND

TPA3138D2

www.ti.com.cn

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

9.3 Feature Description

9.3.1 Analog Gain

The analog gain of the TPA3138D2 can be changed by GAIN_SEL pin. Low Level, Gain = 20 dB; High Level,

Gain = 26 dB.

9.3.2 SD/FAULT Operation

The TPA3138D2 device employs a shutdown mode of operation designed to reduce supply current (I_CC) to the

absolute minimum level during periods of nonuse for power conservation. The SD/FAULT input pin should be

held high (see Specifications table for trip point) during normal operation when the amplifier is in use. Pulling

SD/FAULT low causes the outputs to mute and the amplifier to enter a low-current state. Never leave SD/FAULT

unconnected, because the amplifier operation would be unpredictable.

For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power

supply voltage.

9.3.3 PLIMIT

If selected, the PLIMIT operation limits the output voltage level to a voltage level below the supply rail. If the

amplifier operates like it is powered by a lower supply voltage, then it limits the output power by voltage clipping.

Add a resistor divider from GVDD to ground to set the threshold voltage at the PLIMIT pin.

图 17. PLIMIT Circuit Operation

The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle

to a fixed maximum value. The limit can be thought of as a "virtual" voltage rail which is lower than the supply

connected to PVCC. The "virtual" rail is approximately 5.7 times (with BD mode) and 11.4 times (with 1SPW

mode) the voltage at the PLIMIT pin. The output voltage can be used to calculate the maximum output power for

a given maximum input voltage and speaker impedance.

TPA3138D2

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

www.ti.com.cn

Feature Description (接下页)

ö²

R_L

´ V

R_L+ 2 ´ R_S

P_OUT

for unclipped power

2 ´ R_L

where

•

P_OUT(10%THD) = 1.25 × P_OUT(unclipped)

R_Lis the load resistance.

R_Sis the total series resistance including R_DS(on), and output filter resistance.

V_Pis the peak amplitude, which is limited by "virtual" voltage rail.

(1)

9.3.4 Spread Spectrum and De-Phase Control

The TPA3138D2 device has built-in spread spectrum control of the oscillator frequency and de-phase of the

PWM outputs to improve EMI performance. The spread spectrum scheme is internally fixed and is always turned

on.

De-phase inverts the phase of the output PWM such that the idle output PWM waveforms of the two audio

channels are inverted. De-phase does not affect the audio signal, or its polarity. De-phase only works with BD

mode, it is auto-disabled in 1SPW mode

9.3.5 GVDD Supply

The GVDD Supply is used to power the gates of the output full-bridge transistors. Add a 1-μF capacitor to ground

at this pin.

9.3.6 DC Detect

The TPA3138D2 device integrates a circuitry which protects the speakers from DC current that might occur due

to defective capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault is

reported on the SD/FAULT pin as a low state. The DC Detect fault also causes the amplifier to shutdown by

changing the state of the outputs to Hi-Z.

A DC Detect Fault is issued when the output DC voltage sustain for more than 800 msec at the same polarity.

This feature protects the speaker from large DC currents or AC currents less than 1 Hz. To avoid nuisance faults

due to the DC detect circuit, hold the SD/FAULT pin low at power-up until the signals at the inputs are stable.

Also, take care to match the impedance seen at the positive and negative inputs to avoid nuisance DC detect

faults.

9.3.7 PBTL Select

The TPA3138D2 device offers the feature of Parallel BTL operation with two outputs of each channel connected

directly. Connecting LINP and LINN directly to Ground (without capacitors) sets the device in Mono Mode during

power up. Connect the OUTPR and OUTNR together for the positive speaker terminal and OUTNL and OUTPL

together for the negative speaker terminal. Analog input signal is applied to INPR and INNR. For an example of

the PBTL connection, see the schematic in the Typical Applications section.

9.3.8 Short-Circuit Protection and Automatic Recovery Feature

The TPA3138D2 features over-current conditions against the output stage short-circuit conditions. The short-

circuit protection fault is reported on the SD/FAULT pin as a low state. The amplifier outputs are switched to a Hi-

Z state when the short circuit protection latch is triggered .

The device recovers automatically once the over-current condition has been removed.

9.3.9 Over-Temperature Protection (OTP)

Thermal protection on the TPA3138D2 device prevents damage to the device when the internal die temperature

exceeds 150°C. This triggering point has a ±15°C tolerance from device to device. Once the die temperature

exceeds the thermal triggering point, the device is switched to the shutdown state and the outputs are disabled.

Thermal protection faults are reported on the SD/FAULT pin.

TPA3138D2

www.ti.com.cn

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

Feature Description (接下页)

The device recovers automatically once the over temperature condition has been removed.

9.3.10 Over-Voltage Protection (OVP)

The TPA3138D2 device monitors the voltage on PVCC voltage threshold. When the voltage on PVCCL pin and

PVCCR pin exceeds the over-voltage threshold (15.8 V typ), the OVP circuit puts the device into shutdown

mode.

The device recovers automatically once the over-voltage condition has been removed.

9.3.11 Under-Voltage Protection (UVP)

When the voltage on PVCCL pin and PVCCR pin falls below the under-voltage threshold, the UVP circuit puts

the device into shutdown mode. When MODE_SEL pin is set to LOW (BD mode), the under-voltage threshold is

7.5 V typical. When MODE_SEL pin is set to HIGH or floating, the TPA3138D2 operates in 1SPW mode, and the

under-voltage threshold is 3.4 V typical.

The device recovers automatically once the under-voltage condition has been removed.

TPA3138D2

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

www.ti.com.cn

9.4 Device Functional Modes

9.4.1 MODE_SEL = LOW: BD Modulation

This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is

driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.

The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the

speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.

The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The

voltage across the load sits at 0 V throughout most of the switching period, reducing the switching current, which

reduces any I²R losses in the load.

OUTP

OUTN

No Output

OUTP-OUTN

Speaker

Current

OUTP

OUTN

Positive Output

PVCC

OUTP OUTN

Speaker

Current

OUTP

Negative Output

OUTN

OUTP-_OUTN

PVCC

Speaker

Current

图 18. BD Mode Modulation

TPA3138D2

www.ti.com.cn

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

Device Functional Modes (接下页)

9.4.2 MODE_SEL = HIGH: Low-Idle-Current 1SPW Modulation

The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty

in THD degradation and more attention required in the output filter selection. In 1SPW mode the outputs operate

at ~15% modulation during idle conditions. When an audio signal is applied one output decreases and the other

output increases. The decreasing output signal rails to GND. At which point all the audio modulation takes place

through the rising output. The result is that only one output is switching during a majority of the audio cycle.

Efficiency is improved in this mode due to the reduction of switching losses.

OUTP

OUTN

No Output

OUTP-OUTN

Speaker

Current

OUTP

OUTN

Positive Output

PVCC

OUTP-OUTN

Speaker

Current

OUTP

Negative Output

OUTN

-PVCC

OUTP

-OUTN

Speaker

Current

图 19. Low-Idle-Current 1SPW Modulation

TPA3138D2

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

www.ti.com.cn

10 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The TPA3138D2 device is designed for use in inductor-free applications with limited distance wire length

between amplifier and speakers, suitable for applications such as TV sets, sound docks and Bluetooth speakers.

The TPA3138D2 device can either be configured in stereo or mono mode. Depending on the output power

requirements and necessity for (speaker) load protection, the built-in PLIMIT circuit can be used to control the

system power, see functional description of these features.

10.2 Typical Applications

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图 20. Stereo Class-D Amplifier in BTL Configuration with Single-Ended Inputs, Spread Spectrum

Modulation and BD Mode

TPA3138D2

www.ti.com.cn

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

Typical Applications (接下页)

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图 21. Stereo Class-D Amplifier in PBTL Configuration with Single-Ended Input, Spread Spectrum

Modulation and 1SPW Mode

10.2.1 Design Requirements

10.2.1.1 PCB Material Recommendation

FR-4 Glass Epoxy material with 1 oz. (35 µm) is recommended for use with the TPA3138D2. The use of this

material can provide higher power output, improved thermal performance, and better EMI margin (due to lower

PCB trace inductance). It is recommended to use several GND underneath the device thermal pad for thermal

coupling to a bottom-side copper GND plane for best thermal performance.

10.2.1.2 PVCC Capacitor Recommendation

The large capacitors used in conjunction with each full-bridge, are referred to as the PVCC capacitors. These

capacitors should be selected for proper voltage margin and adequate capacitance to support the power

requirements. In practice, with a well designed system power supply, a capacitor with 100 μF and 16 V supports

most applications with 12-V power supply. 25-V capacitor rating is recommended for power supply voltage higher

than 12 V. For The PVCC capacitors should be low ESR type because they are used in a circuit associated with

high-speed switching.

TPA3138D2

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

www.ti.com.cn

Typical Applications (接下页)

10.2.1.3 Decoupling Capacitor Recommendations

In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good

audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this

application.

The voltage of the decoupling capacitors should be selected in accordance with good design practices.

Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the

selection of the ceramic capacitors that are placed on the power supply to each full-bridge. They must withstand

the voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and

the ripple current created by high power output. A minimum voltage rating of 16 V is required for use with a 12-V

power supply.

10.2.2 Detailed Design Procedure

A rising-edge transition on SD/FAULT input allows the device to start switching. It is recommended to ramp the

PVCC voltage to its desired value before releasing SD/FAULT for minimum audible artifacts.

The device is not inverting the audio signal from input to output.

The GVDD pin is not recommended to be used as a voltage source for external circuitry.

10.2.2.1 Ferrite Bead Filter Considerations

With Advanced Emissions Suppression Technology, the TPA3138D2 amplifier delivers high-efficiency Class-D

performance while minimizing interference to surrounding circuits, even with a low-cost ferrite bead filter. But

couple factors need to be taken into considerations when selecting the ferrite beads.

One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite

material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to

the operation of the Class-D amplifier. Many of the specifications regulating consumer electronics have

emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30-MHz

and above range from appearing on the speaker wires and the power supply lines which are good antennas for

these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the

range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance,

the resonant frequency of the ferrite bead and capacitor filter should be less than 10 MHz.

Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected

for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. If it

is possible, make sure the ferrite bead maintains an adequate amount of impedance at the peak current that the

amplifier detects. If these specifications are not available, it is possible to estimate the bead's current handling

capability by measuring the resonant frequency of the filter output at low power and at maximum power. A

change of resonant frequency of less than fifty percent under this condition is desirable. Examples of ferrite

beads which have been tested and work well with the TPA3138D2 device include NFZ2MSM series from Murata.

A high-quality ceramic capacitor is also required for the ferrite bead filter. A low ESR capacitor with good

temperature and voltage characteristics works best.

Additional EMC improvements may be obtained by adding snubber networks from each of the class-D outputs to

ground. Suggested values for a simple RC series snubber network would be 68 Ω in series with a 100-pF

capacitor although design of the snubber network is specific to every application and must be designed taking

into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate

the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make

sure the layout of the snubber network is tight and returns directly to the GND or the thermal pad beneath the

chip.

TPA3138D2

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ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

Typical Applications (接下页)

10.2.2.2 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme

The main reason that the traditional class-D amplifier requires an output filter is that the switching waveform

results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple

current is large for the traditional modulation scheme, because the ripple current is proportional to voltage

multiplied by the time at that voltage. The differential voltage swing is 2 × V_CC, and the time at each voltage is

half the period for the traditional modulation scheme. An ideal LC filter is required to store the ripple current from

each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both

resistive and reactive, whereas an LC filter is almost purely reactive.

The TPA3138D2 modulation scheme has little loss in the load without a filter because the pulses are short and

the change in voltage is V_CCinstead of 2 × V_CC. As the output power increases, the pulses widen, making the

ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most

applications the filter is not required.

An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow

through the filter instead of the load. The filter has less resistance but higher impedance at the switching

frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.

10.2.2.3 When to Use an Output Filter for EMI Suppression

The TPA3138D2 device has been tested with a simple ferrite bead filter for a variety of applications including

long speaker wires up to 100 cm and high power. The TPA3138D2 EVM passes FCC Class B specifications

under these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet

application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency.

There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These

circumstances might occur if there are nearby circuits which are sensitive to noise. In these cases a classic

second order Butterworth filter similar to those shown in the figures below can be used.

Some systems have little power supply decoupling from the AC line but are also subject to line conducted

interference (LCI) regulations. These include systems powered by "wall warts" and "power bricks." In these

cases, LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using

low frequency ferrite material can also be effective at preventing line conducted interference.

Ferrite

Chip Bead

OUTP

1 nF

Ferrite

Chip Bead

OUTN

1 nF

图 22. Typical Ferrite Chip Bead Filter (Chip Bead Example: NFZ2MSM series from Murata)

33 mH

OUTP

1 mF

33 mH

OUTN

1 mF

图 23. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω

TPA3138D2

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

www.ti.com.cn

Typical Applications (接下页)

15 mH

OUTP

2.2 mF

15 mH

OUTN

2.2 mF

图 24. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 6 Ω

10.2.2.4 Input Resistance

The typical input resistance of the amplifier is fixed to 20 kΩ ±15% for 26dB Gain and 40kΩ ±15% for 20dB

Gain .

Input

Signal

10.2.2.5 Input Capacitor, C_i

In the typical application, an input capacitor (C_i) is required to allow the amplifier to bias the input signal to the

proper dc level for optimum operation. In this case, C_iand the input impedance of the amplifier (Z_i) form a high-

pass filter with the corner frequency determined in 公式 2.

-3 dB

2p Z_iC_i

f_c

(2)

The value of C_iis important, as it directly affects the bass (low-frequency) performance of the circuit. Consider

the example where Z_iis 20 kΩ (26dB Gain) and the specification calls for a flat bass response down to 20 Hz. 公

式 2 is reconfigured as 公式 3.

C_i=

2p Z_if_c

(3)

In this example, C_iis 0.4 µF; so, one would likely choose a value of 0.39 μF as this value is commonly used. A

further consideration for this capacitor is the leakage path from the input source through the input network (C_i)

and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the

amplifier that reduces useful headroom. For this reason, a low-leakage tantalum or ceramic capacitor is the best

choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in

most applications as the dc level there is held at 3 V, which is likely higher than the source dc level. Note that it

is important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset

voltages and it is important to ensure that boards are cleaned properly.

TPA3138D2

www.ti.com.cn

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

Typical Applications (接下页)

10.2.2.6 BSN and BSP Capacitors

The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the

high side of each output to turn on correctly. A 0.22-μF ceramic capacitor, rated for at least 25 V, must be

connected from each output to its corresponding bootstrap input. Specifically, one 0.22-μF capacitor must be

connected from OUTPx to BSPx, and one 0.22-μF capacitor must be connected from OUTNx to BSNx. (See the

application circuit diagram in 图 20.)

The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating

power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching

cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs

turned on.

10.2.2.7 Differential Inputs

The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To

use the TPA3138D2 device with a differential source, connect the positive lead of the audio source to the INP

input and the negative lead from the audio source to the INN input. To use the TPA3138D2 with a single-ended

source, ac ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP

and apply the audio source to either input. In a single-ended input application, the unused input should be ac

grounded at the audio source instead of at the device input for best noise performance. For good transient

performance, the impedance seen at each of the two differential inputs should be the same.

The impedance seen at the inputs should be limited to an RC time constant of 3 ms or less if possible. This is to

allow the input dc blocking capacitors to become completely charged during the 50-ms power-up time. If the input

capacitors are not allowed to completely charge, there is some additional sensitivity to component matching

which can result in pop if the input components are not well matched.

10.2.2.8 Using Low-ESR Capacitors

Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor

can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor

minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,

the more the real capacitor behaves like an ideal capacitor.

TPA3138D2

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

www.ti.com.cn

Typical Applications (接下页)

10.2.3 Application Performance Curves

10.2.3.1 EN55013 Radiated Emissions Results

TPA3138D2 EVM, PVCC = 12 V, 8-Ω speakers, P_O= 4 W

图 25. Radiated Emission - Horizontal

图 26. Radiated Emission - Vertical

10.2.3.2 EN55022 Conducted Emissions Results

TPA3138D2 EVM, PVCC = 12 V, 8-Ω speakers, P_O= 4 W

EN55022 Class B

QP readings

QP limit

QP readings

QP limit

0.15

0.3 0.5

20 30

0.15

0.3 0.5

20 30

Frequency (MHz)

图 27. Conducted Emission - Line

图 28. Conducted Emission - Neutral

TPA3138D2

www.ti.com.cn

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

11 Power Supply Recommendations

11.1 Power Supply Decoupling, C_S

The TPA3138D2 device is a high-performance CMOS audio amplifier that requires adequate power supply

decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply

decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. Optimum

decoupling is achieved by using a network of capacitors of different types that target specific types of noise on

the power supply leads. For higher frequency transients due to parasitic circuit elements such as bond wire and

copper trace inductances as well as lead frame capacitance, a good quality low equivalent-series-resistance

(ESR) ceramic capacitor of value between 220 pF and 1000 pF works well. This capacitor should be placed as

close to the device PVCC pins and system ground (either GND pins or thermal pad) as possible. For mid-

frequency noise due to filter resonances or PWM switching transients as well as digital hash on the line, another

good quality capacitor typically 0.1 μF to 1 µF placed as close as possible to the device PVCC leads works best.

For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 100 μF or greater placed

near the audio power amplifier is recommended. The 100-μF capacitor also serves as a local storage capacitor

for supplying current during large signal transients on the amplifier outputs. The PVCC pins provide the power to

the output transistors, so a 100-µF or larger capacitor should be placed on each PVCC pin. A 1-µF capacitor on

the AVCC pin is adequate. Also, a small decoupling resistor between AVCC and PVCC can be used to keep high

frequency class-D noise from entering the linear input amplifiers.

TPA3138D2

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

www.ti.com.cn

12 Layout

12.1 Layout Guidelines

The TPA3138D2 device can be used with a small, inexpensive ferrite bead output filter for most applications.

However, since the Class-D switching edges are fast, it is necessary to take care when planning the layout of the

printed circuit board. The following suggestions help meet EMC requirements.

•

Decoupling capacitors—The high-frequency decoupling capacitors should be placed as close to the PVCC

and AVCC pins as possible. Large (100-µF or greater) bulk power supply decoupling capacitors should be

placed near the TPA3138D2 device on the PVCC supplies. Local, high-frequency bypass capacitors should

be placed as close to the PVCC pins as possible. These caps can be connected to the thermal pad directly

for an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor

between 220 pF and 1000 pF and a larger mid-frequency cap of value between 0.1 μF and 1 μF also of good

quality to the PVCC connections at each end of the chip.

•

Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to

GND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna.

Grounding—The AVCC (pin 7) decoupling capacitor should be connected to ground (GND). The PVCC

decoupling capacitors should connect to GND. Analog ground and power ground should be connected at the

thermal pad, which should be used as a central ground connection or star ground for the TPA3138D2.

•

Output filter—The ferrite EMI filter (图 22) should be placed as close to the output pins as possible for the

best EMI performance. The capacitors used in the ferrite should be grounded to power ground.

Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal

reliability. The dimensions of the thermal pad and thermal land should be 3.04 mm × 2.34 mm. Seven rows of

solid vias (three vias per row, 0.3302 mm or 13 mils diameter) should be equally spaced underneath the

thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom

layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See the TI Application

Report SLMA002 for more information about using the TSSOP thermal pad. For recommended PCB

footprints, see figures at the end of this data sheet.

For an example layout, see the TPA3138D2 Evaluation Module (TPA3138D2EVM) User Manual. Both the EVM

user manual and the thermal pad application report are available on the TI Web site at http://www.ti.com.

TPA3138D2

www.ti.com.cn

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

12.2 Layout Example

Top Layer 3D view

Top Layer layout view

Bot Layer layout view

图 29. BTL Layout Example

TPA3138D2

ZHCSHR9A –MARCH 2018–REVISED JUNE 2018

www.ti.com.cn

13 器件和文档支持

13.1 器件支持

13.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

13.2 文档支持

13.2.1 相关文档

《PowerPAD™ 耐热增强型封装应用报告》（文献编号：SLMA002）

13.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

13.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

13.5 商标

E2E is a trademark of Texas Instruments.

Bluetooth is a registered trademark of Bluetooth SIG, Inc.

All other trademarks are the property of their respective owners.

13.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

13.7 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

14 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPA3138D2PWP

TPA3138D2PWPR

ACTIVE

HTSSOP

PWP

RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 85

TPA3138D2

2000 RoHS & Green

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

21-Jul-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPA3138D2PWPR

HTSSOP PWP

2000

330.0

16.4

6.9

10.2

1.8

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

21-Jul-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP PWP 28

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

TPA3138D2PWPR

2000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

21-Jul-2023

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

PWP HTSSOP

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

TPA3138D2PWP

530

10.2

3600

3.5

Pack Materials-Page 3

GENERIC PACKAGE VIEW

PWP 28

4.4 x 9.7, 0.65 mm pitch

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224765/B

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPA3138D2PWPR [TI]

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