TPA3139D2RGER [TI]
10W 3.5V 至 14.4V 无电感器型立体声 QFN 模拟输入 D 类音频放大器 | RGE | 24 | -10 to 85;
| 型号： | TPA3139D2RGER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10W 3.5V 至 14.4V 无电感器型立体声 QFN 模拟输入 D 类音频放大器 | RGE | 24 | -10 to 85 放大器 商用集成电路 音频放大器 电感器 |
| 文件： | 总40页 (文件大小：3410K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPA3139D2
ZHCSKD5A –OCTOBER 2019 –REVISED AUGUST 2020
TPA3139D2 10W 立体声、3.5V 至14.4V、低空闲电流、
无电感器、D 类放大器
1 特性
3 说明
• 8Ω、1% THD+N、7.4V 电源条件下，功率为2 ×
TPA3139D2 是一款 10W 立体声 D 类音频放大器，具
有小于 15ms 的快速开通时间和静音功能。它仅消耗
20mA (12V) 的低空闲电流，并且可以在低至 3.5V 的
电压下工作，从而能够实现更长的音频播放时间。
TPA3139D2 采用小型 4 x 4mm2 QFN 封装，并针对空
间受限的 2 节或 3 节电池供电系统进行了优化。此
外，扩频控制支持使用价格低廉的铁氧体磁珠滤波器，
同时满足降低系统成本的EMC 要求。
3W
• 8Ω、1% THD+N、13.5V 电源条件下，功率为2 ×
10W
• 开速开通时间< 15ms
• 宽电源电压范围：3.5V 至14.4V
–
• 具有低空闲电流且小型尺寸，适用于便携式音频应
用
TPA3139D2 集成了重要的保护特性，包括欠压、过
压、功率限制、短路、过热和直流扬声器保护，可进一
步简化设计。所有这些保护都支持自动恢复。
– 4 x 4mm2 QFN-24 封装
– 1SPW 调制时空闲电流为20mA (12V)
– > 90% 的D 类效率
器件信息(1)
• 灵活的音频解决方案：
封装尺寸（标称值）
器件型号
TPA3139D2
封装
VQFN (24)
– 可实现输出快速启用和禁用的MUTE 信号
– 单端或差动模拟输入
4.0mm × 4.0mm
– 可选增益：20dB 和26dB
• 集成保护和自动恢复功能：
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 引脚对引脚、引脚对地、引脚对电源短路保护
– 热保护、欠压保护和过压保护
– 功率限制器和直流扬声器保护
• 扩频调制可降低EMI 发射
TPA3139D2
FB
RIGHT
Audio
Source
And Control
PBTL
DETECT
LEFT
• 降低了解决方案尺寸和成本：
FB
– 采用铁氧体磁珠滤波器，符合EN55022 EMC
标准
– 无需外部散热器
SD/FAULTZ
Power Supply
3.5V t 14.4V
PVCC/AVCC
MUTE
MUTE Control
GAIN_SEL
MOD_SEL
PLIMIT
20dB/26dB GAIN Select
Modulation Schemes/UV Level Select
Power Limit
2 应用
• 便携式移动无线电
• 笔记本电脑
Copyright
©
2019, Texas Instruments Incorporated
• Bluetooth® 扬声器和无线扬声器
• 智能家用电器
• 电视和监视器
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLOS810
TPA3139D2
ZHCSKD5A –OCTOBER 2019 –REVISED AUGUST 2020
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................20
8 Application and Implementation..................................22
8.1 Application Information............................................. 22
8.2 Typical Applications.................................................. 22
9 Power Supply Recommendations................................29
9.1 Power Supply Decoupling, CS ................................. 29
10 Layout...........................................................................30
10.1 Layout Guidelines................................................... 30
10.2 Layout Example...................................................... 31
11 Device and Documentation Support..........................32
11.1 Device Support........................................................32
11.2 Documentation Support.......................................... 32
11.3 接收文档更新通知................................................... 32
11.4 支持资源..................................................................32
11.5 Trademarks............................................................. 32
11.6 静电放电警告...........................................................32
11.7 术语表..................................................................... 32
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................7
6.6 Switching Characteristics............................................8
6.7 Typical Characteristics,...............................................9
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagram.........................................16
7.3 Feature Description...................................................17
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (October 2019) to Revision A (August 2020)
Page
• Added note (4) to TA in the Recommended Operating Condition .......................................................................6
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Device Comparison Table
Product
TPA3139D2
TPA3138D2
TPA3110D2
TPA3136D2
TPA3136AD2
Supply Voltage
3.5-V to 14.4-V
3.5-V to 14.4-V
8-V to 26-V
Modulation Scheme
Package
VQFN-24
R(ds)on
180-mΩ
180-mΩ
240-mΩ
240-mΩ
240-mΩ
Gain
20-dB, 26-dB
20-dB, 26-dB
20-dB, 26-dB, 32-dB, 36-dB
26-dB
Inductor Free
YES
BD, 1SPW
BD, 1SPW
BD
HTSSOP-28
HTSSOP-28
HTSSOP-28
HTSSOP-28
YES
NO
4.5-V to 14.4-V
8-V to 14.4-V
BD
YES
BD
26-dB
YES
5 Pin Configuration and Functions
OUTPL
BSPL
1
2
3
4
5
6
18
17
16
15
14
13
OUTPR
BSPR
PVCCR
MUTE
RINP
PVCCL
SD/FAULT
LINP
Thermal
Pad
LINN
RINN
Not to scale
图5-1. RGE Package, 24-Pin VQFN, (Top View)
Pin Functions
PIN
I/O/P(1)
DESCRIPTION
NAME
OUTPL
BSPL
NO.
1
2
O
P
Class-D H-bridge positive output for left channel.
Bootstrap supply (BST) for positive high-side FET of the left channel.
Power supply for left channel H-bridge. Right channel and left channel power supply inputs are
connected internally.
PVCCL
3
P
TTL logic levels with compliance to AVCC. Shutdown logic input for audio amp (LOW, outputs Hi-Z;
HIGH, outputs enabled). General fault reporting includes Over-Temp, Over-Current, and DC Detect.
SD/ FAULT= High, normal operation, SD/ FAULT= Low, fault condition. Device will auto-recover once
the OT/OC/DC Fault has been removed.
SD/FAULT
4
IO
LINP
LINN
5
6
I
I
Positive audio input for left channel. Biased at 2.5 V. Connect to GND for PBTL mode.
Negative audio input for left channel. Biased at 2.5 V. Connect to GND for PBTL mode.
Gain select least significant bit. TTL logic levels with compliance to AVDD. Low = 20-dB Gain, High =
26-dB Gain, Floating = 26-dB Gain.
GAIN_SEL
7
I
Mode select least significant bit. TTL logic levels with compliance to AVDD. Low = BD Mode with UV
Threshold = 7.5 V, High = 1SPW Mode with UV Threshold = 3.4V, Floating = 1SPW Mode with UV
threshold = 3.4V.
MODE_SEL
AVCC
8
9
I
P
Analog supply.
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PIN
I/O/P(1)
DESCRIPTION
NAME
AGND
GVDD
NO.
10
P
Analog signal ground.
FET gate drive supply. Nominal voltage is 5 V.
11
O
Power limiter level control. Connect a resistor divider from GVDD to GND to set power limit. Connect
directly to GVDD for no power limit.
PLIMIT
12
I
RINN
RINP
13
14
I
I
Negative audio input for right channel. Biased at 2.5 V.
Positive audio input for right channel. Biased at 2.5 V.
Mute signal for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL
logic levels with compliance to AVCC.
MUTE
15
16
I
Power supply for right channel H-bridge. Right channel and left channel power supply inputs are
connected internally.
PVCCR
P
BSPR
17
18
19
20
21
22
23
24
P
O
P
O
P
P
O
P
P
Bootstrap supply (BST) for positive high-side FET of the right channel.
Class-D H-bridge positive output for right channel.
Power ground for the H-bridges.
OUTPR
PGND
OUTNR
BSNR
Class-D H-bridge negative output for right channel.
Bootstrap supply (BST) for negative high-side FET of the right channel.
Bootstrap supply (BST) for negative high-side FET of the left channel.
Class-D H-bridge negative output for left channel.
Power ground for the H-bridges.
BSNL
OUTNL
PGND
Thermal Pad
Connect to GND for best thermal and electrical performance
(1) I = Input, O = Output, IO = Input and Output, P = Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Supply voltage
AVCC to GND, PVCC to GND
To any pin except supply pins
20
10
–0.3
Input current
mA
V/ms
V
Slew rate, maximum(2)
SD/ FAULT to GND, GAIN_SEL, MODE_SEL, MUTE
SD/ FAULT to GND, GAIN_SEL, MODE_SEL, MUTE
PLIMIT
10
AVCC + 0.3
GVDD + 0.3
5.5
–0.3
-0.3
–0.3
4.8
Interface pin voltage
V
RINN, RINP, LINN, LINP
V
BTL, (10 V ≤PVCC ≤14.4 V)
BTL, (3.5 V < PVCC < 10 V)
PBTL, (10 V ≤PVCC < 14.4 V)
PBTL, (3.5 V ≤PVCC < 10 V)
3.2
Minimum load resistance, RL
Ω
2.4
1.6
See the Thermal Information
Table
Continuous total power dissipation
Operating Juncation Temperature range
Storage temperature range, Tstg
150
125
°C
°C
–25
–40
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100 kΩresister in series
with the pins.
6.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
V(ESD) Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
3.5
2
MAX
UNIT
V
VCC
VIH
VIL
VOL
IIH
Supply voltage
PVCC, AVCC
14.4
AVCC
0.8
High-level input voltage
SD/ FAULT (1), MUTE, GAIN_SEL, MODE_SEL
SD/ FAULT, MUTE, GAIN_SEL, MODE_SEL(2)
SD/ FAULT, RPULL-UP =100 kΩ, PVCC = 14.4 V
SD/ FAULT, MUTE, GAIN_SEL, MODE_SEL, VI = 2 V, AVCC = 12 V
SD/ FAULT, MUTE, GAIN_SEL, MODE_SEL, VI = 0.8 V, AVCC = 12 V
V
Low-level input voltage
V
Low-level output voltage
High-level input current
0.8
V
50
µA
µA
°C
°C
IIL
Low-level input current
5
TA
Operating free-air temperature(3) (4)
Operating junction temperature(3)
85
–10
TJ
-10
150
(1) Set SD/ FAULT to high level, make sure the pull-up resistor is larger than 4.7 kΩ and smaller than 500 kΩ
(2) Set GAIN_SEL and MODE_SEL to low level, make sure pull down resistor<10 kΩ
(3) The TPA3138D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.
(4) TPA3139D2 supports -40°C ~85°C ambient temperature range with ≤12 V operating PVDD range.
6.4 Thermal Information
TPA3139D2
THERMAL METRIC(1)
RGE (QFN)
24 PINS
37.4
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
35.1
16.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.9
ψJT
16.7
ψJB
RθJC(bot)
7.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
TA = 25°C, AVCC = PVCC = 12 V, RL = 8 Ω, Gain = 20 dB, ferrite beads used, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
AC CHARACTERISTICS
3.8
14.3
3.0
W
W
W
W
W
PVCC = 7.4 V, RL = 8 Ω, f = 1 kHz, 1SPW mode
PVCC = 12 V, RL = 4 Ω, f = 1 kHz, BD mode
PVCC = 7.4 V, RL = 8 Ω, f = 1 kHz, 1SPW mode
PVCC = 12 V, RL = 4 Ω, f = 1 kHz, BD mode
PVCC = 5 V, RL = 4 Ω, f = 1 kHz, 1SPW mode
PVCC = 12 V, RL = 4 Ω, f = 1 kHz, BD mode
PVCC = 12 V, RL = 8 Ω, f = 1 kHz, BD mode
PVCC = 5 V, RL = 4 Ω, f = 1 kHz, 1SPW mode
PVCC = 12 V, RL = 4 Ω, f = 1 kHz, BD mode
PVCC = 12 V, RL = 8 Ω, f = 1 kHz, BD mode
f = 1 kHz, RL = 3 Ω
Output power (BTL), 10% THD+N
Output power (BTL), 1% THD+N
13.6
3.5
PO
Output power (PBTL), 10% THD+N
Output power (PBTL), 1% THD+N
19.1
10.5
3
W
W
15.7
8.9
W
A
IO
Maximum output current
3.5
THD+N
PSRR
Total harmonic distortion + noise
Power supply ripple rejection
f = 1 kHz, PO = 5 W (half-power)
0.04
-85
%
200-mVPP ripple at 1 kHz, inputs ac-coupled to GND
dB
µV
dBV
µV
dBV
dB
dB
°C
85
20 Hz to 22 kHz, A-weighted filter, Gain = 26 dB
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
-81
Vn
Output integrated noise
72
-82.6
-100
102
150
15
Crosstalk
VO = 1 Vrms, f = 1 kHz
SNR
OTE
Signal-to-noise ratio
Thermal trip point
Thermal hysteresis
Maximum output at THD+N < 1%, f = 1 kHz, A-weighted
°C
DC CHARACTERISTICS
Output offset voltage
(measured differentially)
| VOS
|
VI = 0 V
1.5
20
mV
mA
mA
mA
SD/ FAULT = 2 V, ferrite bead filter, 1SPW Mode, PVCC
12 V
=
SD/ FAULT = 2 V, ferrite bead filter, BD Mode, PVCC = 12
V
37
ICC
Quiescent supply current
SD/ FAULT = 2 V, 10 µH + 680 nF output filter, 1SPW
Mode, PVCC = 7.4 V
17
SD/ FAULT = 2 V, 10 µH + 680 nF output filter, 1SPW
Mode, PVCC = 12 V
22.8
mA
µA
ICC(SD)
rDS(on)
Quiescent supply current in shutdown mode
Drain-source on-state resistance
SD/ FAULT = 0.8 V, no load
10
IO = 500 mA, TJ = 25°C High Side
excluding metal and
bond wire resistance
180
mΩ
Low side
180
GAIN_SEL= 0.8 V
GAIN_SEL= 2 V
SD/ FAULT = 2 V
SD/ FAULT = 0.8 V
IGVDD = 2 mA
19
25
20
26
15
2.9
5
21
27
dB
dB
ms
µs
V
G
Gain
tON
Turn-on time
tOFF
Turn-off time
GVDD
Gate drive supply
4.8
5.2
VRINP = 2.6 V and VRINN = 2.4 V,
or VRINP = 2.4 V and VRINN = 2.6 V
tDCDET
DC detect time
800
ms
OVP
UVP
UVP
Over Voltage Protection
Under Voltage Protection
Under Voltage Protection
15.8
7.5
V
V
V
MODE_SEL = 0.8 V (BD mode)
MODE_SEL = 2 V, or floating (1SPW mode)
3.4
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6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
340
UNIT
fOSC, SS
Oscillator frequency, Spread Spectrum ON
305
kHz
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6.7 Typical Characteristics,
6.7.1 Bridge -Tied Load (BTL)
All measurements taken at audio frequency = 1 kHz, closed-loop gain = 26 dB, BD Modulation, 10 µH + 0.68 µF, TA = 25°C,
AES17 measurement filter, unless otherwise noted.
10
10
f = 100 Hz
f = 1 kHz
f = 10 kHz
f = 100 Hz
f = 1 kHz
f = 10 kHz
1
1
0.1
0.1
0.01
0.01
10m
100m
1
Output Power (W)
10 20
10m
100m
1
Output Power (W)
10 20
D001
D002
AVCC = PVCC = 12 V, Load = 8 Ω, LC Filter
AVCC=PVCC = 8 V, Load = 4 Ω, LC Filter
图6-1. THD+N vs Power (BTL)
图6-2. THD+N vs Power (BTL)
10
10
Po = 2 W
Po = 5 W
Po = 2 W
Po = 5 W
1
0.1
1
0.1
0.01
0.01
0.001
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D004
D005
AVCC = PVCC = 12 V, Load = 8 Ω, LC Filter
AVCC=PVCC = 12 V, Load = 4 Ω
图6-3. THD+N vs Frequency (BTL)
图6-4. THD+N vs Frequency (BTL)
24
20
THD+N = 1 %
THD+N = 10 %
THD+N = 1 %
THD+N = 10 %
22
20
18
16
14
12
10
8
18
16
14
12
10
8
6
6
4
4
2
2
0
0
8
9
10
11 12
Supply Voltage (V)
13
14
15
8
9
10
11 12
Supply Voltage (V)
13
14
15
Load = 4 Ω
Load = 8 Ω
图6-5. Output Power vs Supply Voltage (BTL)
图6-6. Output Power vs Supply Voltage (BTL)
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100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
10
0
PVCC = 8 V
PVCC = 12 V
PVCC = 8 V
PVCC = 12 V
10
0
0
2
4
6
8
Output Power (W)
10
12
14
16
18
20
0
2
4
6
8
Output Power (W)
10
12
14
16
18
20
D011
D012
A.
Load = 4 Ω
Load = 8 Ω
图6-7. Efficiency vs Output Power (BTL)
图6-8. Efficiency vs Output Power (BTL)
60
55
50
45
40
35
30
25
20
36
325
275
225
175
125
75
Gain
Phase
32
28
24
20
16
12
8
25
-25
-75
-125
BD
1SPW
4
15
10
0
20
100
1k
Frequency (Hz)
10k 20k
3
5
7
9
Supply Voltage (V)
11
13
15
D007
Load = 8 Ω, 1SPW and BD
A.
AVCC= PVCC = 12 V
Load = 6 Ω+ 47 µH
图6-9. Idle Power vs Supply Voltage (BTL)
图6-10. Gain and Phase vs Frequency (BTL)
0
100
90
80
70
60
50
40
30
20
CH2 to CH1
CH1 to CH2
-20
-40
-60
-80
-100
-120
PVCC = 8 V
PVCC = 12 V
10
0
20
100
1k
f - Frequency - Hz
10k 20k
0
2
4
6
8
10
12
Output Power (W)
14
16
18
20
D010
D041
AVCC=PVCC = 12 V, 1 W
Load = 6 Ω+ 47 µH
A.
Ferrite Bead Filter
Load = 8 Ω
图6-11. Crosstalk vs Frequency (BTL)
图6-12. Efficiency vs Output Power, 8 Ω
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100
90
80
70
60
50
40
30
20
10
10
f = 100 Hz
f = 1 kHz
f = 10 kHz
1
0.1
0.01
0
8
9
10
11 12
Supply Voltage (V)
13
14
15
10m
100m
1
Output Power (W)
10 20
D018
A.
Ferrite Bead Filter
Load = 8 Ω
A.
AVCC=PVCC = 12 V, 1 W
1SPW
Load = 8 Ω
图6-13. Idle Current vs Supply Voltage, 8 Ω
图6-14. THD+N vs Output Power, 8 Ω
10
10
f = 100 Hz
f = 1 kHz
f = 10 kHz
Po = 2 W
Po = 5 W
1
0.1
1
0.1
0.01
0.01
0.001
10m
100m
1
Output Power (W)
10 20
20
100
1k
Frequency (Hz)
10k 20k
D019
D022
A.
AVCC=PVCC = 7.4 V
1SPW A.
AVCC=PVCC = 12 V
1SPW
Load = 4 Ω
Load = 8 Ω
图6-15. THD+N vs Output Power, 4 Ω
图6-16. THD+N vs Frequency, 8 Ω
10
20
18
16
14
12
10
8
Po = 2 W
Po = 5 W
THD+N = 1 %
THD+N = 10 %
1
0.1
6
0.01
4
2
0.001
0
20
100
1k
Frequency (Hz)
10k 20k
4
5
6
7
8
Supply Voltage (V)
9
10 11 12 13 14 15
D023
D025
A.
AVCC=PVCC = 12 V
1SPW A.
Load = 4 Ω
Load = 8 Ω, 1SPW
图6-17. THD+N vs Frequency, 4 Ω
图6-18. Output Power vs Supply Voltage, 8 Ω
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20
100
90
80
70
60
50
40
30
20
10
0
THD+N = 1 %
THD+N = 10 %
18
16
14
12
10
8
6
4
PVCC = 7.4 V
PVCC = 12 V
2
0
4
5
6
7
8
Supply Voltage (V)
9
10 11 12 13 14 15
0
2
4
6
8
Output Power (W)
10
12
14
16
18
20
D026
D029
A.
A.
Load = 4 Ω, 1SPW
Load = 4 Ω, 1SPW
图6-19. Output Power vs Supply Voltage, 4 Ω
图6-20. Efficiency vs Output Power, 4 Ω
100
90
80
70
60
50
40
30
20
20
THD+N = 1 %
THD+N = 10 %
18
16
14
12
10
8
6
4
PVCC = 7.4 V
PVCC = 12 V
10
0
2
0
0
2
4
6
8
Output Power (W)
10
12
14
16
18
20
4
5
6
7
8
9
Supply Voltage (V)
10 11 12 13 14 15
D030
D038
A.
A.
Ferrite Bead Filte
1SPW
Load = 8 Ω, 1SPW
Load = 8 Ω,
图6-21. Efficiency vs Output Power, 8 Ω
图6-22. Output Power vs Supply Voltage, 8 Ω
60
50
40
30
20
10
0
4
5
6
7
8
Supply Voltage (V)
9
10 11 12 13 14 15
A.
Ferrite Bead Filter
1SPW
Load = 8 Ω
图6-23. Idle Current vs Supply Voltage
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6.7.2 Paralleled Bridge -Tied Load (PBTL)
All measurements taken at audio frequency = 1 kHz, closed-loop gain = 20 dB, BD Modulation, 10 µH + 0.68 µF, TA = 25°C,
AES17 measurement filter, unless otherwise noted.
20
18
16
14
12
10
8
32
28
24
20
16
12
8
THD+N = 1 %
THD+N = 10 %
THD+N = 1 %
THD+N = 10 %
6
4
4
2
0
0
8
9
10
11 12
Supply Voltage (V)
13
14
15
8
9
10
11 12
Supply Voltage (V)
13
14
15
A.
A.
Load = 8 Ω
Load = 4 Ω
图6-24. Output Power vs Supply Voltage, 8 Ω
图6-25. Output Power vs Supply Voltage, 4 Ω
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
PVCC = 8 V
PVCC = 12 V
PVCC = 8 V
PVCC = 12 V
10
0
10
0
0
2
4
6
8
Output Power (W)
10
12
14
16
18
20
0
2
4
6
8
Output Power (W)
10
12
14
16
18
20
D014
D013
A.
A.
Load = 8 Ω
Load = 4 Ω
图6-26. Efficiency vs Output Power, 8 Ω
图6-27. Efficiency vs Output Power, 4 Ω
32
20
THD+N = 1 %
THD+N = 10 %
THD+N = 1 %
THD+N = 10 %
18
16
14
12
10
8
28
24
20
16
12
8
6
4
4
2
0
0
4
5
6
7
8
Supply Voltage (V)
9
10 11 12 13 14 15
4
5
6
7
8
Supply Voltage (V)
9
10 11 12 13 14 15
D027
A.
Load = 4 Ω, 1SPW
A.
Load = 8 Ω, 1SPW
图6-29. Output Power vs Supply Voltage, 4 Ω
图6-28. Output Power vs Supply Voltage, 8 Ω
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100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
10
0
PVCC = 5 V
PVCC = 7.4 V
PVCC = 12 V
PVCC = 7.4 V
PVCC = 12 V
10
0
0
2
4
6
8
10
12
Output Power (W)
14
16
18
20
0
2
4
6
8
10
12
Output Power (W)
14
16
18
20
D032
D031
A.
Load = 8 Ω, 1SPW
A.
Load = 4 Ω, 1SPW
图6-30. Efficiency vs Output Power, 8 Ω
图6-31. Efficiency vs Output Power, 4 Ω
32
THD+N = 1 %
THD+N = 10 %
28
24
20
16
12
8
4
0
4
5
6
7
8
Supply Voltage (V)
9
10 11 12 13 14 15
A.
Load = 4 Ω, Ferrite Bead Filter, 1SPW
图6-32. Output Power vs Supply, 4 Ω
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7 Detailed Description
7.1 Overview
The TPA3139D2 is designed as a low-idle-power, cost-effective, general-purpose Class-D audio amplifier. The
fast turn-on time (15-ms) along with MUTE function allows TPA3139D2 to quickly power up while avoiding pop.
The built-in spread spectrum control scheme efficiently suppresses EMI and enables the use of ferrite beads
instead of inductors for ≤2 x 10 W applications.
To facilitate system design, the TPA3139D2 needs only one power supply between 3.5 V and 14.4 V for
operation. An internal voltage regulator provides suitable voltage levels for the gate driver, digital, and low-
voltage analog circuitry. For a properly functioning bootstrap circuit, a small ceramic capacitor must be
connected from each bootstrap pin (BSxx) to the power-stage output pin (OUTxx). When the power-stage output
is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-
supply pin (GVDD) and the bootstrap pins. When the power-stage output is high, the bootstrap capacitor
potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate
driver. In an application with PWM switching frequencies in the datasheet specified range, use ceramic
capacitors with at least 220-nF capacitance, size 0603 or 0805, for the bootstrap supply. These capacitors
ensure sufficient energy storage, even during clipped low frequency audio signals, to keep the high-side power
stage FET (LDMOS) fully turned on during the remaining part of its ON cycle.
The audio signal path, including the gate drive and output stage, is designed as identical, independent full-
bridges. All decoupling capacitors should be placed as close as possible to their associated pins. The physical
loop with the power supply pins, decoupling capacitors, and GND return path to the device pins must be kept as
short as possible, and with as little area as possible to minimize induction.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. For optimal electrical performance, EMI compliance, and system reliability, each PVCC
pin should be decoupled with ceramic capacitors that are placed as close as possible to each supply pin. It is
recommended to follow the PCB layout of the TPA3139D2 reference design. For additional information on
recommended power supply and required components, see the application diagrams in this data sheet.
The PVCC power supply should have low output impedance and low noise. The power-supply ramp and SD/
FAULT release sequence is not critical for device reliability as facilitated by the internal power-on-reset circuit,
but it is recommended to release SD/ FAULT after the power supply is settled for minimum turn-on audible
artifacts.
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7.2 Functional Block Diagram
GVDD
PVCC
BSPL
PVCC
Input
PBTL
Sense
Select
Modulation Scheme
and PBTL Select
OUTPL FB
Gate
Drive
OUTPL
OUTPL FB
LINP
LINN
GND
BSNL
Gain
Control
PWM
Logic
PLIMIT
GVDD
PVCC
PVCC
OUTNL FB
OUTNL FB
Gate
Drive
FAULT
OUTNL
GND
SD/FAULT
Gain
Control
SC Detect
SD
TTL
DC Detect
Buffer
GAIN_SEL
MOD_SEL
MUTE
Modulation scheme
/UVLO Select
Biases and
References
Ramp
Generator
Startup Protection
Logic
Spread Spectrum
Control
Thermal
Detect
UVLO/OVLO
LIMITER
Reference
PLIMIT
GVDD
PVCC
BSNR
AVDD
GVDD
PVCC
UVLO Select
LDO
Regulator
AVCC
GVDD
Gate
Drive
OUTNR
OUTNR FB
OUTNR FB
RINN
RINP
GND
BSPR
Gain
Control
PWM
Logic
PLIMIT
GVDD
PVCC
PVCC
OUTPR FB
Gate
Drive
OUTPR
GND
Modulation Scheme
and PBTL Select
GND
OUTPR FB
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7.3 Feature Description
7.3.1 Analog Gain
The analog gain of the TPA3139D2 can be changed by GAIN_SEL pin. Low Level, Gain = 20 dB; High Level,
Gain = 26 dB.
7.3.2 SD/ FAULT and MUTE Operation
The TPA3139D2 device employs a shutdown mode of operation designed to reduce supply current (ICC) to the
absolute minimum level during periods of nonuse for power conservation. The SD/ FAULT input pin should be
held high (see 节 6 table for trip point) during normal operation when the amplifier is in use. Pulling SD/ FAULT
low causes the outputs to mute and the amplifier to enter a low-current state. Never leave SD/ FAULT
unconnected, because the amplifier operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown or mute mode prior to removing the
power supply voltage.
For some single ended input application case, suggest to mute the device first then release SD/ FAULT, then
umute the output. This sequence power-up sequence with best pop performance.
7.3.3 PLIMIT
If selected, the PLIMIT operation limits the output voltage to a level below the supply rail. If the amplifier operates
like it is powered by a lower supply voltage, then it limits the output power by voltage clipping. Add a resistor
divider from GVDD to ground to set the threshold voltage at the PLIMIT pin.
图7-1. PLIMIT Circuit Operation
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle
to a fixed maximum value. The limit can be thought of as a "virtual" voltage rail which is lower than the supply
connected to PVCC. The "virtual" rail is approximately 5.7 times (with BD mode) and 11.4 times (with 1SPW
mode) the voltage at the PLIMIT pin. The output voltage can be used to calculate the maximum output power for
a given maximum input voltage and speaker impedance.
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æ
ö2
æ
ç
è
ö
÷
ø
RL
´ V
ç
÷
P
ç
÷
RL + 2 ´ RS
è
ø
POUT
=
for unclipped power
2 ´ RL
(1)
where
• POUT (10%THD) = 1.25 × POUT (unclipped)
• RL is the load resistance.
• RS is the total series resistance including RDS(on), and output filter resistance.
• VP is the peak amplitude, which is limited by "virtual" voltage rail.
7.3.4 Spread Spectrum and De-Phase Control
The TPA3139D2 device has built-in spread spectrum control of the oscillator frequency and de-phase of the
PWM outputs to improve EMI performance. The spread spectrum scheme is internally fixed and is always turned
on.
De-phase inverts the phase of the output PWM such that the idle output PWM waveforms of the two audio
channels are inverted. De-phase does not affect the audio signal, or its polarity. De-phase only works with BD
mode, it is auto-disabled in 1SPW mode.
7.3.5 GVDD Supply
The GVDD Supply is used to power the gates of the output full-bridge transistors. Add a 1-μF capacitor to
ground at this pin.
7.3.6 DC Detect
The TPA3139D2 device integrates a circuitry which protects the speakers from DC current that might occur due
to defective capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault is
reported on the SD/ FAULT pin as a low state. The DC Detect fault also causes the amplifier to shutdown by
changing the state of the outputs to Hi-Z.
A DC Detect Fault is issued when the output DC voltage sustain for more than 800 msec at the same polarity.
This feature protects the speaker from large DC currents or AC currents less than 1 Hz. To avoid nuisance faults
due to the DC detect circuit, hold the SD/ FAULT pin low at power-up until the signals at the inputs are stable.
Also, take care to match the impedance seen at the positive and negative inputs to avoid nuisance DC detect
faults.
7.3.7 PBTL Select
The TPA3139D2 device offers the feature of Parallel BTL operation with two outputs of each channel connected
directly. Connecting LINP and LINN directly to Ground (without capacitors) sets the device in Mono Mode during
power up. Connect the OUTPR and OUTNR together for the positive speaker terminal and OUTNL and OUTPL
together for the negative speaker terminal. Analog input signal is applied to INPR and INNR. For an example of
the PBTL connection, see the schematic in the 节8.2 section.
7.3.8 Short-Circuit Protection and Automatic Recovery Feature
The TPA3139D2 features over-current conditions against the output stage short-circuit conditions. The short-
circuit protection fault is reported on the SD/ FAULT pin as a low state. The amplifier outputs are switched to a
Hi-Z state when the short circuit protection latch is triggered .
The device recovers automatically once the over-current condition has been removed.
7.3.9 Over-Temperature Protection (OTP)
Thermal protection on the TPA3139D2 device prevents damage to the device when the internal die temperature
exceeds 150°C. This triggering point has a ±15°C tolerance from device to device. Once the die temperature
exceeds the thermal triggering point, the device is switched to the shutdown state and the outputs are disabled.
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Thermal protection faults are reported on the SD/ FAULT pin.
The device recovers automatically once the over temperature condition has been removed.
7.3.10 Over-Voltage Protection (OVP)
The TPA3139D2 device monitors the voltage on PVCC voltage threshold. When the voltage on PVCCL pin and
PVCCR pin exceeds the over-voltage threshold (15.8 V typ), the OVP circuit puts the device into shutdown
mode.
The device recovers automatically once the over-voltage condition has been removed.
7.3.11 Under-Voltage Protection (UVP)
When the voltage on PVCCL pin and PVCCR pin falls below the under-voltage threshold, the UVP circuit puts
the device into shutdown mode. When MODE_SEL pin is set to LOW (BD mode), the under-voltage threshold is
7.5 V typical. When MODE_SEL pin is set to HIGH or floating, the TPA3139D2 operates in 1SPW mode, and the
under-voltage threshold is 3.4 V typical.
The device recovers automatically once the under-voltage condition has been removed.
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7.4 Device Functional Modes
7.4.1 MODE_SEL = LOW: BD Modulation
This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is
driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.
The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the
speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.
The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The
voltage across the load sits at 0 V throughout most of the switching period, reducing the switching current, which
reduces any I2R losses in the load.
OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
-
OUTP OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
OUTP-OUTN
-
PVCC
0A
Speaker
Current
图7-2. BD Mode Modulation
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7.4.2 MODE_SEL = HIGH: Low-Idle-Current 1SPW Modulation
The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty
in THD degradation and more attention required in the output filter selection. In 1SPW mode, the outputs
operate at ~15% modulation during idle conditions. When an audio signal is applied, one output decreases and
the other output increases. The decreasing output signal rails to GND. At which point, all the audio modulation
takes place through the rising output. The result is that only one output is switching during a majority of the audio
cycle. Efficiency is improved in this mode due to the reduction of switching losses.
OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
-PVCC
OUTP
-OUTN
0
A
Speaker
Current
图7-3. Low-Idle-Current 1SPW Modulation
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8 Application and Implementation
Note
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TPA3139D2 device is designed for use in inductor-free applications with limited distance wire length
between amplifier and speakers, suitable for applications such as TV sets, sound docks and Bluetooth speakers.
The TPA3139D2 device can either be configured in stereo or mono mode. Depending on the output power
requirements and necessity for (speaker) load protection, the built-in PLIMIT circuit can be used to control the
system power, see functional description of these features.
8.2 Typical Applications
PVCC
L3
PVCCL
L2
OUTPL
OUTL+
C6
C9
0.1uF
25V
C10
1000pF
50V
C8
100uF
50V
C5
C7
330pF
50V
1000pF
100V
1000pF
50V
R1
10.0
R2
68.0
PVCC
GND
GND
GND
GND
GND
GND
GND
L1
PVCCR
C3
0.1uF
25V
C4
1000pF
50V
C2
100uF
50V
LINP
TP3
GND
GND
C11
J4
LINP
LINN
3
4
1
L4
L5
L6
OUTNL
OUTL-
1uF
35V
PVCC
GND
GND
GND
C12
330pF
50V
C13
1000pF
100V
C14
1000pF
50V
LIN
U1
PVCCL
LINN
TP4
C1
1uF
35V
J6
OUTPL
OUTNL
C15
3
1
23
OUTPL
OUTNL
R3
10.0
R4
68.0
16
PVCCR
AVCC
1uF
35V
OUTNR
OUTPR
20
18
OUTNR
OUTPR
LGND
GND
9
GND
C17
2
BSPL
BSNL
BSNR
BSPR
GVDD
LINP
LINN
25V
25V
25V
25V
0.22uF
C18
0.22uF
C19
0.22uF
C20
0.22uF
GND
GND
5
6
LINP
LINN
22
21
17
11
RINP
TP7
RINN
RINP
OUTNR
OUTR-
C24
13
14
RINN
RINP
J9
RINP
3
4
1
C21
330pF
50V
C22
1000pF
100V
C23
1000pF
50V
1uF
35V
SD/FAULT
GAIN_SEL
MODE_SEL
4
7
8
RIN
SDZ/FAULT
GAIN_SEL
MOD_SEL
24
19
10
PGND
PGND
AGND
R7
10.0
R8
68.0
IN = 20dB Gain
OUT = 26dB Gain
MUTE
15
12
RINN
TP8
MUTE
PLIMIT
PVCC
R9
J10
PLIMIT
C25
25
PAD
TP5
RINN
PVCC
GVDD
1uF
35V
TPA3139D2RGE
GND
GND
100k
RGND
GND
R12
100k
J7
TP9
SHUTDOWNz
GND
OUTPR
OUTR+
J13
S1
C26
330pF
50V
C27
1000pF
100V
C28
1000pF
50V
SHUTDOWN
R6
PLIMIT ADJ
R5
GND
GAIN SEL
GND
100k
10.0k
C16
1uF
35V
TP6
R10
10.0
R11
68.0
GND
PLIMIT
GND
PLIMIT
GND
GND
R13
100k
PVCC
J14
R15
200k
MODE SEL
Q1
IN = BD
OUT = Low Idle Current
GND
图8-1. Stereo Class-D Amplifier in BTL Configuration with Single-Ended Inputs, Spread Spectrum
Modulation and BD Mode
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PVCC
PVCC
PVCC
L3
PVCCL
C9
0.1uF
25V
C10
1000pF
50V
C8
100uF
50V
GND
GND
GND
L1
PVCCR
C3
0.1uF
25V
C4
1000pF
50V
C2
100uF
50V
L1
OUTPL
OUTL+
C6
GND
GND
GND
C5
C7
330pF
50V
1000pF
100V
1000pF
50V
U1
PVCCL
C1
1uF
35V
3
1
23
OUTPL
OUTNL
OUTPL
OUTNL
R1
10.0
R2
68.0
16
GND
PVCCR
AVCC
20
18
OUTNR
OUTPR
OUTNR
OUTPR
GND
9
2
C17
BSPL
BSNL
BSNR
BSPR
GVDD
5
6
25V
25V
25V
25V
0.22uF
C18
0.22uF
C19
0.22uF
C20
0.22uF
GND
GND
LINP
LINN
22
21
17
11
RINP
TP7
GND
RINN
RINP
13
14
C24
RINN
RINP
J9
3
4
1
RINP
1uF
35V
SD/FAULT
GAIN_SEL
MODE_SEL
4
7
8
RIN
SDZ/FAULT
GAIN_SEL
MOD_SEL
L2
24
19
10
OUTPR
OUTR+
PGND
PGND
AGND
IN = 20dB Gain
MUTE
15
12
C26
330pF
50V
C27
1000pF
100V
C28
1000pF
50V
RINN
TP8
MUTE
OUT = 26dB Gain
PVCC
R9
J10
PLIMIT
25
C25
PLIMIT
PAD
TP5
RINN
PVCC
GVDD
1uF
35V
R10
10.0
R11
68.0
TPA3139D2RGE
100k
RGND
GND
GND
R12
100k
J7
TP9
SHUTDOWNz
GND
J13
S1
SHUTDOWN
R6
GND
GND
PLIMIT ADJ
R5
GND
GAIN SEL
GND
100k
10.0k
C16
1uF
35V
TP6
GND
PLIMIT
GND
PLIMIT
R13
100k
PVCC
J14
R15
200k
MODE SEL
Q1
IN = BD
OUT = Low Idle Current
GND
图8-2. Stereo Class-D Amplifier in PBTL Configuration with Single-Ended Input, Spread Spectrum
Modulation and 1SPW Mode
8.2.1 Design Requirements
8.2.1.1 PCB Material Recommendation
FR-4 Glass Epoxy material with 1 oz. (35 µm) is recommended for use with the TPA3139D2. The use of this
material can provide higher power output, improved thermal performance, and better EMI margin (due to lower
PCB trace inductance). It is recommended to use several GND underneath the device thermal pad for thermal
coupling to a bottom-side copper GND plane for best thermal performance.
8.2.1.2 PVCC Capacitor Recommendation
The large capacitors used in conjunction with each full-bridge, are referred to as the PVCC capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, a capacitor with 100 μF and 16 V supports
most applications with 12-V power supply. 25-V capacitor rating is recommended for power supply voltage
higher than 12 V. For The PVCC capacitors should be low ESR type because they are used in a circuit
associated with high-speed switching.
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8.2.1.3 Decoupling Capacitor Recommendations
In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the ceramic capacitors that are placed on the power supply to each full-bridge. They must withstand
the voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and
the ripple current created by high power output. A minimum voltage rating of 16 V is required for use with a 12-V
power supply.
8.2.2 Detailed Design Procedure
A rising-edge transition on SD/ FAULT input allows the device to start switching. It is recommended to ramp the
PVCC voltage to its desired value before releasing SD/ FAULT for minimum audible artifacts.
The device is not inverting the audio signal from input to output.
The GVDD pin is not recommended to be used as a voltage source for external circuitry.
8.2.2.1 Ferrite Bead Filter Considerations
With Advanced Emissions Suppression Technology, the TPA3139D2 amplifier delivers high-efficiency Class-D
performance while minimizing interference to surrounding circuits, even with a low-cost ferrite bead filter. But
couple factors need to be taken into considerations when selecting the ferrite beads.
One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite
material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to
the operation of the Class-D amplifier. Many of the specifications regulating consumer electronics have
emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30-MHz
and above range from appearing on the speaker wires and the power supply lines which are good antennas for
these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the
range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance,
the resonant frequency of the ferrite bead and capacitor filter should be less than 10 MHz.
Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected
for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. If it
is possible, make sure the ferrite bead maintains an adequate amount of impedance at the peak current that the
amplifier detects. If these specifications are not available, it is possible to estimate the bead current handling
capability by measuring the resonant frequency of the filter output at low power and at maximum power. A
change of resonant frequency of less than fifty percent under this condition is desirable. Examples of ferrite
beads which have been tested and work well with the TPA3139D2 device include NFZ2MSM series from Murata.
A high-quality ceramic capacitor is also required for the ferrite bead filter. A low ESR capacitor with good
temperature and voltage characteristics works best.
Additional EMC improvements may be obtained by adding snubber networks from each of the class-D outputs to
ground. Suggested values for a simple RC series snubber network would be 68 Ω in series with a 100-pF
capacitor although design of the snubber network is specific to every application and must be designed taking
into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate
the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make
sure the layout of the snubber network is tight and returns directly to the GND or the thermal pad beneath the
chip.
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8.2.2.2 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier requires an output filter is that the switching waveform
results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple
current is large for the traditional modulation scheme, because the ripple current is proportional to voltage
multiplied by the time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is
half the period for the traditional modulation scheme. An ideal LC filter is required to store the ripple current from
each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both
resistive and reactive, whereas an LC filter is almost purely reactive.
The TPA3139D2 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not required.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
8.2.2.3 When to Use an Output Filter for EMI Suppression
The TPA3139D2 device has been tested with a simple ferrite bead filter for a variety of applications including
long speaker wires up to 100 cm and high power. The TPA3139D2 EVM passes FCC Class B specifications
under these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet
application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency.
There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These
circumstances might occur if there are nearby circuits which are sensitive to noise. In these cases a classic
second order Butterworth filter similar to those shown in the figures below can be used.
Some systems have little power supply decoupling from the AC line but are also subject to line conducted
interference (LCI) regulations. These include systems powered by "wall warts" and "power bricks." In these
cases, LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using
low frequency ferrite material can also be effective at preventing line conducted interference.
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
图8-3. Typical Ferrite Chip Bead Filter (Chip Bead Example: NFZ2MSM series from Murata)
33 mH
OUTP
C2
L1
1 mF
33 mH
OUTN
C3
L2
1 mF
图8-4. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω
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15 mH
OUTP
C2
L1
2.2 mF
15 mH
OUTN
C3
2.2 mF
L2
图8-5. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 6 Ω
8.2.2.4 Input Resistance
The typical input resistance of the amplifier is fixed to 20 kΩ ±15% for 26dB Gain and 40kΩ ±15% for 20dB
Gain .
Z
f
C
i
Z
i
IN
Input
Signal
8.2.2.5 Input Capacitor, Ci
In the typical application, an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, Ci and the input impedance of the amplifier (Zi) form a high-
pass filter with the corner frequency determined in 方程式2.
-3 dB
1
2p Zi Ci
fc
=
f
c
(2)
The value of Ci is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where Zi is 20 kΩ (26dB Gain) and the specification calls for a flat bass response down to 20 Hz. 方
程式2 is reconfigured as 方程式3.
1
Ci =
2p Zi fc
(3)
In this example, Ci is 0.4 µF; so, one would likely choose a value of 0.39 μF as this value is commonly used. A
further consideration for this capacitor is the leakage path from the input source through the input network (Ci)
and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the
amplifier that reduces useful headroom. For this reason, a low-leakage tantalum or ceramic capacitor is the best
choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in
most applications as the dc level there is held at 3 V, which is likely higher than the source dc level. Note that it is
important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset
voltages and it is important to ensure that boards are cleaned properly.
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8.2.2.6 BSN and BSP Capacitors
The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 0.22-μF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 0.22-μF capacitor must be
connected from OUTPx to BSPx, and one 0.22-μF capacitor must be connected from OUTNx to BSNx. (See
the application circuit diagram in 图8-1.)
The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating
power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching
cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs
turned on.
8.2.2.7 Differential Inputs
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3139D2 device with a differential source, connect the positive lead of the audio source to the INP
input and the negative lead from the audio source to the INN input. To use the TPA3139D2 with a single-ended
source, ac ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP
and apply the audio source to either input. In a single-ended input application, the unused input should be ac
grounded at the audio source instead of at the device input for best noise performance. For good transient
performance, the impedance seen at each of the two differential inputs should be the same.
The impedance seen at the inputs should be limited to an RC time constant of 3 ms or less if possible. This is to
allow the input dc blocking capacitors to become completely charged during the 50-ms power-up time. If the
input capacitors are not allowed to completely charge, there is some additional sensitivity to component
matching which can result in pop if the input components are not well matched.
8.2.2.8 Using Low-ESR Capacitors
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance, the more the real capacitor behaves like an ideal capacitor.
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8.2.3 Application Performance Curves
8.2.3.1 EN55013 Radiated Emissions Results
TPA3139D2 EVM, PVCC = 12 V, 8-Ωspeakers, PO = 4 W
图8-6. Radiated Emission - Horizontal
图8-7. Radiated Emission - Vertical
8.2.3.2 EN55022 Conducted Emissions Results
TPA3139D2 EVM, PVCC = 12 V, 8-Ωspeakers, PO = 4 W
EN55022 Class B
EN55022 Class B
80
80
70
60
50
40
30
20
QP readings
QP limit
QP readings
QP limit
70
60
50
40
30
20
0.15
0.3 0.5
1
2
Frequency (MHz)
3
5
10
20 30
0.15
0.3 0.5
1
2
Frequency (MHz)
3
5
10
20 30
图8-8. Conducted Emission - Line
图8-9. Conducted Emission - Neutral
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9 Power Supply Recommendations
9.1 Power Supply Decoupling, CS
The TPA3139D2 device is a high-performance CMOS audio amplifier that requires adequate power supply
decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply
decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. Optimum
decoupling is achieved by using a network of capacitors of different types that target specific types of noise on
the power supply leads. For higher frequency transients due to parasitic circuit elements such as bond wire and
copper trace inductances as well as lead frame capacitance, a good quality low equivalent-series-resistance
(ESR) ceramic capacitor of value between 220 pF and 1000 pF works well. This capacitor should be placed as
close to the device PVCC pins and system ground (either GND pins or thermal pad) as possible. For mid-
frequency noise due to filter resonances or PWM switching transients as well as digital hash on the line, another
good quality capacitor typically 0.1 μF to 1 µF placed as close as possible to the device PVCC leads works
best. For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 100 μF or greater
placed near the audio power amplifier is recommended. The 100-μF capacitor also serves as a local storage
capacitor for supplying current during large signal transients on the amplifier outputs. The PVCC pins provide the
power to the output transistors, so a 100-µF or larger capacitor should be placed on each PVCC pin. A 1-µF
capacitor on the AVCC pin is adequate. Also, a small decoupling resistor between AVCC and PVCC can be used
to keep high frequency class-D noise from entering the linear input amplifiers.
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10 Layout
10.1 Layout Guidelines
The TPA3139D2 device can be used with a small, inexpensive ferrite bead output filter for most applications.
However, since the Class-D switching edges are fast, it is necessary to take care when planning the layout of the
printed circuit board. The following suggestions help meet EMC requirements.
• Decoupling capacitors—The high-frequency decoupling capacitors should be placed as close to the PVCC
and AVCC pins as possible. Large (100-µF or greater) bulk power supply decoupling capacitors should be
placed near the TPA3139D2 device on the PVCC supplies. Local, high-frequency bypass capacitors should
be placed as close to the PVCC pins as possible. These caps can be connected to the thermal pad directly
for an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor
between 220 pF and 1000 pF and a larger mid-frequency cap of value between 0.1 μF and 1 μF also of
good quality to the PVCC connections at each end of the chip.
• Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to
GND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna.
• Grounding—The AVCC decoupling capacitor should be connected to ground (GND). The PVCC decoupling
capacitors should connect to GND. Analog ground and power ground should be connected at the thermal
pad, which should be used as a central ground connection or star ground for the TPA3139D2.
• Output filter—The ferrite EMI filter (图8-3) should be placed as close to the output pins as possible for the
best EMI performance. The capacitors used in the ferrite should be grounded to power ground.
• Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the thermal pad and thermal land should be 3.04 mm × 2.34 mm. Seven rows of
solid vias (three vias per row, 0.3302 mm or 13 mils diameter) should be equally spaced underneath the
thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom
layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See the TI Application
Report SCBA017D for more information about using the QFN thermal pad. For recommended PCB footprints,
see figures at the end of this data sheet.
For an example layout, see the TPA3139D2 Evaluation Module (TPA3139D2EVM) User Manual. Both the EVM
user manual and the thermal pad application report are available on the TI Web site at http://www.ti.com.
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10.2 Layout Example
Top Layer 3D view
Top Layer layout view
Bot Layer layout view
图10-1. BTL Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 Documentation Support
11.2.1 Related Documentation
PowerPAD™ Thermally Enhanced Package Application Report (SLMA002)
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索
现有解答或提出自己的问题，获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的使用条款。
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
所有商标均为其各自所有者的财产。
11.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPA3139D2RGER
ACTIVE
VQFN
RGE
24
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-10 to 85
TPA
3139D2
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA3139D2RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RGE 24
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TPA3139D2RGER
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
ꢀꢀꢀꢀꢁꢂꢃꢄꢂꢅ
(0.2) TYP
2X 2.5
12
7
20X 0.5
6
13
25
2X
SYMM
2.5
1
18
0.30
PIN 1 ID
(OPTIONAL)
24X
0.18
24
19
0.1
0.05
C A B
C
SYMM
0.48
0.28
24X
4219016 / A 08/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
2.7)
(
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.825)
2X
(1.1)
ꢆꢄꢂꢁꢇꢀ9,$
TYP
6
13
(R0.05)
7
12
2X(1.1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219016 / A 08/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
4X ( 1.188)
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.825)
(0.694)
TYP
6
13
25
(R0.05) TYP
METAL
TYP
7
12
(0.694)
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219016 / A 08/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
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