TPA3223 [TI]
具有低空闲电流的 200W 立体声、400W 单声道、10 至 45V 电源电压、模拟输入 D 类音频放大器;
| 型号： | TPA3223 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有低空闲电流的 200W 立体声、400W 单声道、10 至 45V 电源电压、模拟输入 D 类音频放大器 放大器 音频放大器 |
| 文件： | 总44页 (文件大小：2040K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPA3223
ZHCSQ35 –NOVEMBER 2022
TPA3223 200W 立体声、400W 单声道HD 模拟输入D 类放大器
1 特性
3 说明
• 10V 至42V 宽电源电压范围
• 立体声(2 x BTL) 和单声道(1 x PBTL) 配置
• THD+N 为10% 时的输出功率
– 200W/4Ω，BTL 立体声配置
– 300W/3Ω，PBTL 单声道配置
– 425W/2Ω，PBTL 单声道配置
• THD+N 为1% 时的输出功率
TPA3223 是一款可在全功率、空闲和待机状态下实现
高效运行的高功率 D 类放大器。该器件具有闭环反
馈，从而在整个音频频带内实现低失真并提供出色的音
质。该器件以 AD 调制运行，最多可为 4Ω负载提供 2
x 200W 的功率，或为 2Ω 负载提供 1 x 400W 的功
率。
TPA3223 具有单端或差分模拟输入接口，最高支持
2VRMS，具有四种可选增益：20dB、23.5dB、32dB 和
36dB。TPA3223 还实现了大于 90% 的效率、低空闲
功率和超低待机功耗 (< 0.1W)。这是通过采用 60mΩ
MOSFET、经优化的栅极驱动方案和低功耗运行模式
实现的。为进一步简化设计，该器件集成了重要的保护
功能，包括欠压、过压、逐周期电流限制、短路、削波
检测、过热警告和关断以及直流扬声器保护。
– 170W/4Ω，BTL 立体声配置
– 325W/2Ω，PBTL 单声道配置
• 闭环反馈设计
– 1W/4Ω时的THD+N 小于0.02%
– 60dB PSRR（BTL，无输入信号）
– 输出噪声（A 加权）< 100µV
– SNR（A 加权）> 110dB
• 低功耗运行模式
器件信息(1)
– 待机模式：静音和关断
– 单通道BTL 运行
封装尺寸（NOM）
器件型号
TPA3223
封装
HTSSOP (44)
6.10mm x 14.00mm
• 多输入选项，可简化前置放大器设计
– 差分或单端模拟输入
– 可选增益：20dB、23.5dB、32dB、36dB
• 集成式保护：欠压、过压、过流、逐周期电流限
制、短路、削波检测、过热警告和关断以及直流扬
声器保护
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
TPA3223
RIGHT
LEFT
LC Filter
LC Filter
PBTL
Detect
• 轻松同步多个器件
• 90% 高效D 类运行(4Ω)
Audio Source
And Control
OTW_CLIP
RESET
FAULT
VDD
AVDD
GVDD
2 应用
CMUTE
5V
• 蓝牙和Wi-Fi™ 扬声器
• 条形音箱
• 低音炮
Power Supply
42V
Switching Frequency Select
Clock Synchronization
FREQ_ADJ
OSCM/P
PVDD
110VAC->240VAC
• 专业和公共广播(PA) 扬声器
简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASEF0
TPA3223
ZHCSQ35 –NOVEMBER 2022
www.ti.com.cn
Table of Contents
9 Detailed Description......................................................17
9.1 Overview...................................................................17
9.2 Functional Block Diagrams....................................... 18
9.3 Feature Description...................................................20
9.4 Device Functional Modes..........................................24
10 Application and Implementation................................30
10.1 Application Information........................................... 30
10.2 Typical Applications................................................ 30
10.3 Power Supply Recommendations...........................34
10.4 Layout..................................................................... 35
11 Device and Documentation Support..........................38
11.1 Documentation Support.......................................... 38
11.2 Receiving Notification of Documentation Updates..38
11.3 支持资源..................................................................38
11.4 Trademarks............................................................. 38
11.5 Electrostatic Discharge Caution..............................38
11.6 术语表..................................................................... 38
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................4
6.1 Pin Functions.............................................................. 5
7 Specifications.................................................................. 6
7.1 绝对最大额定值...........................................................6
7.2 ESD 等级.................................................................... 6
7.3 建议运行条件.............................................................. 7
7.4 热性能信息..................................................................7
7.5 电气特性......................................................................8
7.6 音频特性(BTL)..........................................................10
7.7 音频特性(PBTL)....................................................... 10
7.8 Typical Characteristics, BTL Configuration, AD-
mode............................................................................11
7.9 Typical Characteristics, PBTL Configuration, AD-
mode........................................................................... 14
8 Parameter Measurement Information..........................16
Information.................................................................... 38
4 Revision History
DATE
REVISION
NOTES
November 2022
*
Initial release
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5 Device Comparison
表5-1. Device Comparison Table
SUPPLY
VOLTAGE
THERMAL PAD
LOCATION
DEVICE NAME
DESCRIPTION
TPA3220
TPA3221
TPA3244
TPA3245
TPA3250
TPA3251
TPA3255
60-W Stereo, 110-W Peak HD Analog-Input, Pad-Down Class-D Amplifier
100 W Stereo, 200 W Mono HD, Analog-Input, Class-D Amplifier
32 V
Bottom
Top
32 V
60-W Stereo, 110-W peak PurePath™ Ultra-HD Pad Down Class-D Amplifier
115-W Stereo, 230-W Mono PurePath™ Ultra-HD Analog-Input Class-D Amplifier
70 W Stereo, 130 W Peak Ultra-HD, Analog-Input, Pad-Down Class-D Amplifier
175 W Stereo, 350 W Mono Ultra-HD, Analog-Input Class-D Amplifier
315 W Stereo, 600 W Mono Ultra-HD, Analog-Input Class-D Amplifier
31.5 V
31.5 V
38 V
Bottom
Top
Bottom
Top
38 V
53.5 V
Top
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6 Pin Configuration and Functions
The TPA3223 is available in a thermally enhanced TSSOP package.
The package type contains a thermal pad that is located on the top side of the device for convenient thermal
coupling to the heat sink.
GVDD
AVDD
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
BST2_M
BST2_P
GND
2
NC
3
GND
4
GND
GND
5
OUT2_M
OUT2_M
PVDD
CMUTE
IN2_M
IN2_P
6
7
8
PVDD
FREQ_ADJ
OSCP
9
PVDD
10
11
12
13
14
15
16
17
18
19
20
21
22
OUT2_P
GND
OSCM
GND
PowerPad™
GND
RESET
IN1_M
IN1_P
OUT1_M
PVDD
PVDD
GND
PVDD
NC
OUT1_P
OUT1_P
GND
NC
FAULT
OTW_CLIP
GAIN/CLKSYNC
VDD
GND
BST1_M
BST1_P
Not to scale
图6-1. DDV Package, HTSSOP 44-Pin, Top View
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6.1 Pin Functions
表6-1. Pin Functions Table
NAME
NO.
2
I/O(1)
P
DESCRIPTION
AVDD
AVDD voltage supply. Refer to: 节10.3.1.2
BST1_M
BST1_P
BST2_M
BST2_P
24
P
OUT1_M HS bootstrap supply (BST), 0.033 μF capacitor to OUT1_M required.
Refer to: 节10.2.1.2.3
23
44
43
P
P
P
OUT1_P HS bootstrap supply (BST), 0.033 μF capacitor to OUT1_P required.
Refer to: 节10.2.1.2.3
OUT2_M HS bootstrap supply (BST), 0.033 μF capacitor to OUT2_M required.
Refer to: 节10.2.1.2.3
OUT2_P HS bootstrap supply (BST), 0.033 μF capacitor to OUT2_P required.
Refer to: 节10.2.1.2.3
CMUTE
6
19
9
P
O
O
Mute and Startup Timing Capacitor. Connect a 33 nF capacitor to GND. Refer to: 节9.4.3
Shutdown signal, open drain; active low. Refer to: 节9.3.6
FAULT
FREQ_ADJ
Oscillator frequency programming pin. Refer to: 节9.3.4
Closed loop gain and clock synchronization configuration pin.
Refer to: 节9.3.1
GAIN/CLKSYNC
GND
21
I
4,5,12,16,25,
26,42,33,34,
41
P
Ground
GVDD
IN1_M
IN1_P
IN2_M
IN2_P
NC
1
P
I
Gate drive supply. Refer to: 节10.3.1.2
Negative audio input for channel 1
Positive audio input for channel 1
Negative audio input for channel 2
Positive audio input for channel 2
Not connected or pulled to ground
14
15
I
7
8
I
I
3,17,18
11
OSCM
I/O
I/O
O
Oscillator synchronization interface.
Refer to: 节9.3.1
OSCP
10
20
Oscillator synchronization interface.
Refer to: 节9.3.1
OTW_CLIP
Clipping warning and Over-temperature warning; open drain; active low.
Refer to: 节9.3.6
OUT1_M
OUT1_P
OUT2_M
OUT2_P
PVDD
32
27,28
39,40
35
O
O
O
O
P
Negative output for channel 1
Positive output for channel 1
Negative output for channel 2
Positive output for channel 2
29,30,31,36,
37,38
PVDD supply. Refer to: 节10.2.1.2.2 and 节10.3.1.3
RESET
13
22
I
Device reset input; active low. Refer to: 节9.4.5.7, 节9.4.1, 节9.4.2
Input power supply. Refer to: 节10.3.1.1
VDD
P
P
PowerPad™
Ground, connect to grounded heatsink. Placed on top side of device.
(1) I=Input, O=Output, I/O= Input/Output, P=Power
表6-2. Mode Selection Pins
MODE PINS(2)
OUTPUT
CONFIGURATION
INPUT MODE(1)
DESCRIPTION
IN2_M
IN2_P
X
X
1N/2N + 1
1N/2N + 1
2 × BTL
Stereo, BTL output configuration, AD mode modulation
Mono, Paralleled BTL configuration. Connect OUT1_P to OUT2_P
and OUT1_M to OUT2_M, AD mode modulation
0
1
0
1
1 x PBTL
1 x BTL
Mono, BTL configuration. OUT1_M and OUT1_P active, AD mode
modulation
1N/2N + 1
(1) 2N refers to differential input signal, 1N refers to single ended input signal. +1 refers to number of logic control ( RESET) input pins.
(2) X refers to inputs connected through AC coupling capacitor, 0 refers to logic low (GND), 1 refers to logic high (AVDD).
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7 Specifications
7.1 绝对最大额定值
在自然通风条件下的工作温度范围内测得（除非另有说明）(1)
最小值
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
最大值
单位
50
57
V
PVDD 至GND
PVDD 至GND（瞬态小于8ns）(2)
V
V
50
BST_X 至GVDD
电源电压
50
V
VDD 至GND
GVDD 至GND(2)
AVDD 至GND
5.5
5.5
50
V
V
V
OUT1_M、OUT1_P、OUT2_M、OUT2_P 至GND
输出引脚
OUT1_M、OUT1_P、OUT2_M、OUT2_P 至GND（瞬态小于8ns）(2)
57
V
5.5
5.5
5.5
9
V
IN1_M、IN1_P、IN2_M、IN2_P 至GND
FREQ_ADJ、GAIN/CLKSYNC、CMUTE、RESET、OSCP、OSCM 至GND
FAULT、OTW_CLIP 至GND
V
接口引脚
V
mA
°C
°C
持续灌电流、FAULT、OTW_CLIP 至GND
工作结温范围
TJ
0
150
150
Tstg
-40
贮存温度范围
(1) 应力超出绝对最大额定值下所列的值可能会对器件造成永久损坏。这些列出的值仅仅是应力额定值，这并不表示器件在这些条件下以及
在建议运行条件以外的任何其他条件下能够正常运行。长时间处于绝对最大额定条件下可能会影响器件的可靠性。
(2) 这些电压表示在各种条件下测得的器件端子直流电压+ 峰值交流波形。
7.2 ESD 等级
值
单位
人体放电模型(HBM)，符合ANSI/ESDA/JEDEC JS-001，所有引脚(1)
充电器件模型（CDM），符合JEDEC 规范JESD22-C101，所有引脚(2)
±3000
V
VESD
静电放电
±1500
V
(1) JEDEC 文档JEP155 指出：500V HBM 可实现在标准ESD 控制流程下安全生产。
(2) JEDEC 文件JEP157 指出：250V CDM 可实现在标准ESD 控制流程下安全生产。
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7.3 建议运行条件
在自然通风条件下的工作温度范围内测得（除非另有说明）
最小值
典型值 最大值
单位
PVDD
VDD(1)
AVDD
GVDD
VIN
10
42
5
45
5.5
V
功率级电源
直流电源电压
直流电源电压
直流电源电压
直流电源电压
4.5
4.5
4.5
V
V
V
V
VDD、GVDD 和AVDD 的外部电源
模拟电路的电源电压
5
5.5
5
5.5
栅极驱动电路的电源电压
最大输入电压摆幅（INx_P、INx_M）
±2.8
3.5
4
PVDD = 42V，输出滤波器电感在推荐范围内
PVDD =< 42V，输出滤波器电感在推荐范围内
PVDD = 42V，输出滤波器电感在推荐范围内
PVDD/
RL(BTL)
负载阻抗BTL
Ω
（IOC
，
BTL）
RL(PBTL)
1.6
3
10
负载阻抗PBTL
Ω
LOUT(BTL)
LOUT(PBTL)
5
IOC 处的最小输出电感
μH
μH
输出滤波器电感
5
10
输出滤波器电感，LC 滤波器后的PBTL
每个电感器在一半IOC 处的最小输出电感
460
510
575
2.3
480
533
600
500
555
标称值
AM1
为避免AM 干扰，PWM 帧速率可供选择；1%
电阻容差
FPWM
kHz
AM2
625
fOSC(IO)
3.78
10.1
30.3
50.5
MHz
OSCM/OSCP 上的CLK 输入（外设模式）
PWM 帧速率编程电阻
9.9
10
30
50
1.0
5
标称值；主模式
AM1；主模式
AM2；主模式
R(FREQ_ADJ)
29.7
49.5
kΩ
CPVDD
V(FREQ_ADJ)
TJ
PVDD 闭合去耦电容器
μF
V
用于外设模式运行的FREQ_ADJ 引脚上的电压 外设模式（连接至AVDD）
0
125
°C
结温
(1) VDD 必须连接至5V 电源
7.4 热性能信息
TPA3223
热指标(1)
DDV 44 引脚HTSSOP
单位
JEDEC 标准4 层PCB
RθJA
42.6
0.9
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
结至环境热阻
RθJC(top)
RθJB
结至外壳（顶部）热阻
结至电路板热阻
13.8
0.4
ψJT
结至顶部特征参数
结至电路板特征参数
结至外壳（底部）热阻
13.5
ψJB
RθJC(bot)
不适用
(1) 有关新旧热指标的更多信息，请参阅半导体和IC 封装热指标应用报告。
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7.5 电气特性
PVDD = 42V，VDD = 5V，GVDD = 5V，AVDD = 5V，TC（外壳温度）= 75°C，fS = 480kHz，除非另有说明。
最小
值
参数
测试条件
典型值 最大值
单位
电源电压和电流消耗
IVDD
150
5
µA
µA
运行，无音频信号，VDD = 5V
复位模式，VDD = 5V
VDD 电源电流
IVDD
IGVDD
IGVDD
IPVDD
IPVDD
IPVDD
模拟输入
23
5
mA
µA
50% 占空比，VDD = 5V
栅极电源电流。AD 模式调制
复位模式，VDD = 5V
45
35
1
mA
mA
mA
总PVDD 空闲电流，AD 模式调制，BTL
总PVDD 空闲电流，AD 模式调制，BTL
总PVDD 空闲电流，AD 模式调制，BTL
使用推荐输出滤波器，占空比为50%
使用推荐输出滤波器，占空比为50%，TC = 25ºC
复位模式，无开关
20
23.5
32
R1 = 5.6kΩ，R2 = 断开
R1 = 20kΩ，R2 = 100kΩ
R1 = 39kΩ，R2 = 100kΩ
R1 = 47kΩ，R2 = 75kΩ
R1 = 51kΩ，R2 = 51kΩ
R1 = 75kΩ，R2 = 47kΩ
R1 = 100kΩ，R2 = 39kΩ
R1 = 100kΩ，R2 = 16kΩ
G = 20dB
反相电压增益，VOUT/VIN（主时钟同步器件配
置）
36
G
dB
20
23.5
32
反相电压增益，VOUT/VIN（外设时钟同步器件
配置）
36
48
G = 23.5dB
24
RIN
kΩ
输入电阻
G = 32dB
12
G = 36dB
7.3
振荡器
2.76
3.06
3.45
2.7
2.88
3.198
3.6
3
3.33
3.75
标称值，主模式
AM1，主模式
AM2，主模式
高电平输入电压
低电平输入电压
(1)
fOSC(IO)
FPWM × 6
MHz
VIH
VIL
V
V
0.7
外部振荡器（外设模式）
输出级MOSFET
60
60
漏源电阻，低侧(LS)
mΩ
mΩ
TJ = 25°C，不包括金属化电阻，
GVDD = 5V
RDS(on)
漏源电阻，高侧(HS)
I/O 保护
Vuvp,AVDD
Vuvp,AVDD,hyst
Vuvp,PVDD
Vuvp,PVDD,hyst
Vovp,PVDD
Vovp,PVDD,hyst
OTW
4
0.2
V
V
欠压保护限制，AVDD
欠压保护迟滞，AVDD
欠压保护限制，PVDD_x
欠压保护迟滞，PVDD_x
过压保护限制，PVDD_x
过压保护迟滞，PVDD_x
过热警告，OTW_CLIP
9.1
V
0.6
V
46
V
0.85
125
V
°C
需将温度降至OTW 温度以下，才能在OTW
事件后停用OTW_CLIP。
OTWhyst
20
°C
OTE
155
20
°C
°C
°C
ms
A
过热错误
OTEhyst
需复位才能在OTE 事件后释放FAULT
OTE-OTW 差分
OTE-OTW(differential)
OLPC
25
2.2
10
fPWM = 480kHz（1024 个PWM 周期）
1Ω负载时的标称峰值电流
过载保护计数器
IOC, BTL
过流限制保护，扬声器负载电流
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7.5 电气特性(continued)
PVDD = 42V，VDD = 5V，GVDD = 5V，AVDD = 5V，TC（外壳温度）= 75°C，fS = 480kHz，除非另有说明。
最小
值
参数
测试条件
典型值 最大值
单位
IOC, PBTL
IOCT
20
A
过流限制保护，扬声器输出电流
1Ω负载时的标称峰值电流
150
ns
过流响应时间
由过流引起的从开关转换到翻转状态的时间。
静态数字规格
VIH
VIL
2.3
V
V
高电平输入电压
低电平输入电压
输入漏电流
RESET
0.7
Ilkg
100
OSCM、OSCP、RESET
μA
OTW/关断（故障）
内部上拉电阻，OTW_CLIP 至AVDD，
FAULT 至AVDD
RINT_PU
26
kΩ
VOH
VOL
4.5
5
5.5
V
高电平输出电压
低电平输出电压
内部上拉电阻
IO = 4 mA
200
500
mV
(1) 标称值，AM1 和AM2 使用相同的内部振荡器，其固定比率为4 : 4.5 : 5
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7.6 音频特性(BTL)
PCB 和系统配置符合推荐指南。音频频率= 1kHz，PVDD_X = 42V，VDD = 5V，GVDD = 5V，RL = 4Ω、fS = 480kHz，TC
= 75°C，输出滤波器：LDEM = 10μH，CDEM = 1µF，AD 调制，AES17 + AUX-0025 测量滤波器，除非另有说明。
最大
值
参数
测试条件
最小值
典型值
单位
PO
200
170
W
W
%
RL = 4Ω，10% THD+N
每通道功率输出
每通道功率输出
总谐波失真+ 噪声
PO
RL = 4Ω，1% THD+N
THD+N
1W
0.02
A 加权，AES17 滤波器，输入电容器接地，增益=
20dB
Vn
100
μV
输出积分噪声
|VOS
|
5
108
109
1.5
20
mV
dB
dB
W
输入交流耦合至GND
输出失调电压
信噪比(1)
SNR
DNR
Pidle
A 加权，增益= 20dB
A 加权，增益= 20dB
PO = 0，所有输出开关，AD 调制，TC = 25°C(2)
动态范围
空闲损耗引起的功率耗散(IPVDD_X
)
(1) SNR 根据1% THD+N 输出电平计算得出。
(2) 实际系统空闲损耗也受输出电感器磁芯损耗的影响。
7.7 音频特性(PBTL)
PCB 和系统配置符合推荐指南。音频频率= 1kHz，PVDD_X = 42V，VDD = 5V，GVDD = 5V，RL = 3Ω，fS = 480kHz，TC =
75°C，输出滤波器：LDEM = 10μH，CDEM = 1µF，后置滤波器PBTL，AD 调制，AES17 + AUX-0025 测量滤波器，除非另有
说明。
参数
测试条件
RL = 2Ω，10% THD+N
最小值
典型值 最大值 单位
425
300
W
W
RL = 3Ω，10% THD+N
RL = 4Ω，10% THD+N
RL = 2Ω，1% THD+N
RL = 3Ω，1% THD+N
RL = 4Ω，1% THD+N
1W
250
PO
每通道功率输出
325
245
195
THD+N
Vn
0.017
%
总谐波失真+ 噪声
A 加权，AES17 滤波器，输入电容器接地，增益=
20dB
100
μV
输出积分噪声
|VOS
|
10
109
110
1.5
mV
dB
dB
W
输入交流耦合至GND
输出失调电压
信噪比(1)
SNR
DNR
Pidle
A 加权，增益= 20dB
A 加权，增益= 20dB
PO = 0，所有输出开关，AD 调制，TC = 25°C(2)
动态范围
空闲损耗引起的功率耗散(IPVDD_X)
(1) SNR 根据1% THD+N 输出电平计算得出。
(2) 实际系统空闲损耗受输出电感器磁芯损耗的影响。
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7.8 Typical Characteristics, BTL Configuration, AD-mode
All Measurements taken at audio frequency = 1 kHz, PVDD = 42 V, VDD = 5 V, GVDD = 5 V, RL = 4 Ω, fS = 480 kHz, TC =
75°C, Output Filter: LDEM = 10 μH, CDEM = 1 μFAES17 + AUX-0025 measurement filters, unless otherwise noted.
10
5
10
5
RL=4
TC=75C
PVDD=42V
TC=75C
BTL Mode
1W
10W
50W
100W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
Load=4
Load=6
Load=8
0.005
0.002
0.001
0.002
0.001
20
100
1k
10k 20k
0.01
0.1
1
10
100 200
Frequency (Hz)
Output Power (W)
图7-2. Total Harmonic Distortion+Noise vs Frequency
图7-1. Total Harmonic Distortion + Noise vs Output Power
10
200
3
1W
5
180
3 - CB3C Limited
10W
50W
100W
2
1
4
160
6
8
140
120
100
80
0.5
0.2
0.1
0.05
0.02
0.01
60
AUX-0025 Filter
80kHz analyzer BW
RL=4 TC=75C
40
0.005
THD+N = 10%
TC=75C
BTL Mode
20
0.002
0.001
0
10
20
100
1k
Frequency (Hz)
10k 20k 40k
15
20
25
30
35
40 42
PVDD - Supply Voltage - V
D014
D037
图7-3. Total Harmonic Distortion+Noise vs Frequency
图7-4. Output Power vs Supply Voltage, AD-mode
200
3
180
3 - CB3C Limited
4
160
6
8
140
120
100
80
60
40
THD+N = 1%
TC=75C
BTL Mode
20
0
10
15
20
25
30
35
40
PVDD - Supply Voltage - V
D014
D037
图7-5. Output Power vs Supply Voltage, AD-mode
图7-6. System Efficiency vs Output Power
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7.8 Typical Characteristics, BTL Configuration, AD-mode (continued)
All Measurements taken at audio frequency = 1 kHz, PVDD = 42 V, VDD = 5 V, GVDD = 5 V, RL = 4 Ω, fS = 480 kHz, TC =
75°C, Output Filter: LDEM = 10 μH, CDEM = 1 μFAES17 + AUX-0025 measurement filters, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
4
6
8
4
6
8
TC=75C
TC=75C
PVDD = 24V
PVDD = 12V
BTL Mode
BTL Mode
0
20
40
60
80 100 120 140 160 180 200
0
5
10
15
20
25
30
35
40
45
50
2 Channel Output Power - W
2 Channel Output Power - W
D024
D024
图7-7. System Efficiency vs Output Power
图7-8. System Efficiency vs Output Power
275
250
225
200
175
150
125
100
75
THD+N=10%
BTL Mode
50
4
6
8
25
0
0
25
50
75
100
TC - Case Temperature - C
图7-10. Output Power vs Case Temperature
图7-9. Power Dissipation vs Output Power
图7-11. Noise Amplitude vs Frequency
图7-12. CCIF Intermodulation
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7.8 Typical Characteristics, BTL Configuration, AD-mode (continued)
All Measurements taken at audio frequency = 1 kHz, PVDD = 42 V, VDD = 5 V, GVDD = 5 V, RL = 4 Ω, fS = 480 kHz, TC =
75°C, Output Filter: LDEM = 10 μH, CDEM = 1 μFAES17 + AUX-0025 measurement filters, unless otherwise noted.
0
TC=75C
4
Pout=25W/channel
FFT size=16384
BTL Mode
-20
-40
-60
-80
-100
-120
-140
AUX-0025 filter
80kHz Analyzer BW
0
5k
10k
15k
20k
25k
30k
35k
40k
f - Frequency - Hz
图7-14. Power Supply Rejection Ratio vs Frequency
18 kHz + 19 kHz Ratio 1 : 1
图7-13. CCIF Intermodulation
0
-20
50
CH1 to CH2
CH2 to CH1
RL=4, TC=75C
Aggressor Amplitude = 2Vrms(1W)
BTL Mode
45
40
35
30
25
20
15
10
5
-40
-60
-80
RL=4
TC=25C
BTL Mode
-100
-120
0
20
100
1k
10k 20k
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42
Supply Voltage (V)
Frequency (Hz)
D014
D037
图7-15. Channel to Channel Crosstalk vs Frequency
图7-16. PVDD Idle Current vs Supply Voltage
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7.9 Typical Characteristics, PBTL Configuration, AD-mode
All Measurements taken at audio frequency = 1 kHz, PVDD = 42 V, VDD = 5 V, GVDD = 5 V, RL = 2 Ω, fS = 480 kHz, TA =
75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, Post-Filter PBTL, AES17 + AUX-0025 measurement filters, unless
otherwise noted.
10
10
RL=2
TC=75C
1W
25W
100W
5
PVDD=42V
TC=75C
Post-PBTL Mode
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
Load=2
Load=3
Load=4
0.005
0.002
0.001
0.002
0.001
20
100
1k
10k 20k
0.01
0.1
1
10
100
500
Frequency (Hz)
Output Power (W)
图7-18. Total Harmonic Distortion+Noise vs Frequency
图7-17. Total Harmonic Distortion+Noise vs Output
10
350
2
1W
25W
100W
5
3
300
2
1
4
250
0.5
0.2
0.1
200
150
0.05
0.02
0.01
100
AUX-0025 Filter
80kHz analyzer BW
RL=2 TC=75C
0.005
THD+N = 1%
TC=75C
Post-PBTL Mode
50
0.002
0.001
0
10
20
100
1k
10k 20k 40k
15
20
25
30
35 40 42
Frequency (Hz)
PVDD - Supply Voltage - V
D014
D037
图7-19. Total Harmonic Distortion+Noise vs Frequency
图7-20. Output Power vs Supply Voltage
100
2
3
4
70
50
30
20
10
7
5
3
2
TC=75C
PVDD = 42V
Post-PBTL Mode
1
0.7
0.5
0.01
0.05
0.2 0.5
1
2 3 45 710 20 50 100200 500
2 Channel Output Power - W
D024
图7-21. System Efficiency vs Output Power
图7-22. Power Dissipation vs Output Power
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7.9 Typical Characteristics, PBTL Configuration, AD-mode (continued)
All Measurements taken at audio frequency = 1 kHz, PVDD = 42 V, VDD = 5 V, GVDD = 5 V, RL = 2 Ω, fS = 480 kHz, TA =
75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, Post-Filter PBTL, AES17 + AUX-0025 measurement filters, unless
otherwise noted.
500
400
300
200
100
0
0
-20
TC=75C
2
Pout=1W/channel
FFT size=16384
Post-PBTL Mode
-40
-60
-80
-100
-120
-140
2
3
4
AUX-0025 filter
80kHz Analyzer BW
THD+N=10%
Post-PBTL Mode
0
5k
10k
15k
20k
25k
30k
35k
40k
0
25
50
TC - Case Temperature - C
75
100
f - Frequency - Hz
18 kHz + 19 kHz Ratio 1 : 1
图7-24. CCIF Intermodulation vs Frequency
图7-23. Output Power vs Case Temperature
图7-25. CCIF Intermodulation vs Frequency
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8 Parameter Measurement Information
All parameters are measured according to the conditions described in the 节7.3 .
Most audio analyzers will not give correct readings of Class-D amplifiers’performance due to their sensitivity to
out of band noise present at the amplifier output. AES-17 + AUX-0025 pre-analyzer filters are recommended to
use for Class-D amplifier measurements. In absence of such filters, a 30-kHz low-pass filter (10 Ω + 47 nF) can
be used to reduce the out of band noise remaining on the amplifier outputs.
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9 Detailed Description
9.1 Overview
TPA3223 is designed as a feature-enhanced cost efficient high power Class-D audio amplifier. The device has
built-in advanced protection circuitry to provide for maximum product robustness as well as a flexible feature set
including selectable gain settings, switching frequency, clock synchronization of multiple devices, mute function,
temperature and clipping status signals. TPA3223 has a bandwidth up to 100 kHz and low output noise designed
for high resolution audio applications and accepts both differential and single ended analog audio inputs at levels
from 1 VRMS to 2 VRMS. With the closed loop operation TPA3223 is designed for high audio performance with a
system power supply between 10 V and 42 V.
An external 5 V supply is used for the AVDD and VDD supply pins. Although supplied from the same 5 V source,
separating AVDD and VDD on the printed-circuit board (PCB) by RC filters (see 节 10.2 for details) is
recommended. These RC filters provide the recommended high-frequency isolation. Special attention needs to
be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, the physical
loop with the power supply pins, decoupling capacitors and GND return path to the device pins must be kept as
short as possible and with as little area as possible to minimize induction (see 节 10.4.2 for additional
information).
The floating supplies for the output stage high side gate drives are supplied by built-in bootstrap circuitry
requiring only an external capacitor for each half-bridge.
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap
pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap
capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD) and
the bootstrap pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the
output potential and thus provides an acceptable voltage supply for the high-side gate driver. TI recommends to
use 33 nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33 nF capacitors maintain
sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET
(LDMOS) fully turned on during the remaining part of the PWM cycle.
Special attention needs to be paid to the power stage power supply; this includes component selection, PCB
placement, and routing.
For good electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X node
is decoupled with 1 μF ceramic capacitors placed as close as possible to the PVDD supply pins. TI
recommends to follow the PCB layout of the TPA3223 reference design. For additional information on
recommended power supply and required components, see 节10.2.
The external power supply for the AVDD and VDD supplies must be from a low-noise, low-output-impedance
voltage regulator. Likewise, the 42V power stage supply is assumed to have low output impedance throughout
the entire audio band, and low noise. The power supply sequence is not critical as facilitated by the internal
power-on-reset circuit, but TI recommends to release RESET after the power supply is settled for minimum turn
on audible artifacts. Moreover, the TPA3223 is fully protected against erroneous power-stage turn on due to
parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are noncritical within the specified range (see
the 节7.3 table of this data sheet).
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9.2 Functional Block Diagrams
AVDD
VDD
RESET
AVDD
GVDD
GVDD
ERROR
HANDLING
OTW_CLIP
FAULT
DIFFOC
CB3C
IOUT1_M
IOUT1_P
IOUT2_M
IOUT2_P
OVER-LOAD
PROTECTION
CURRENT
SENSE
GAIN/CLKSYNC
PWM ACTIVITY
DETECTOR
PVDD
PPSC
OUT_X
POWER-UP
RESET
TEMP
I/O LOGIC
SENSE
CMUTE
STARTUP
CONTROL
PVDD
AVDD
UVP
STARTUP & CONTROL
FREQ_ADJ
OSCILLATOR
OSCM
OUTPUT DC
CONTROL
OSCP
PROTECTION
GVDD
BST1_M
PVDD
-
GATE-DRIVE
GATE-DRIVE
OUT1_M
GND
+
IN1_P
ANALOG
PWM
RECEIVER
TIMING
CONTROL
LOOP
CONTROL
FILTER
IN1_M
+
-
OUT_1_P
PVDD
GVDD
BST1_P
CHANNEL 1
GVDD
BST2_M
PVDD
-
GATE-DRIVE
GATE-DRIVE
OUT2_M
GND
+
IN2_P
ANALOG
PWM
RECEIVER
TIMING
CONTROL
LOOP
CONTROL
FILTER
IN2_M
+
-
OUT2_P
PVDD
GVDD
BST2_P
CHANNEL 2
图9-1. Functional Block Diagram
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System
microcontroller or
Analog circuitry
BST1_P
OSCM
OSCP
Oscillator
Synchronization
Bootstrap
Capacitors
BST1_M
2nd Order
L-C Output
Filter for
each
OUT1_P
Output
H-Bridge 1
IN1_M
IN1_P
Input DC
Blocking
Caps
ANALOG_IN1_M
ANALOG_IN1_P
OUT1_M
Input
H-Bridge 1
H-Bridge
Hardwire PWM
Frame Adjust
2-CHANNEL
H-BRIDGE
BTL MODE
FREQ_ADJ
Gain and Clock
Synchronization
GAIN/CLKSYNC
2nd Order
L-C Output
Filter for
each
OUT2_P
OUT2_M
IN2_M
IN2_P
Input DC
Blocking
Caps
ANALOG_IN2_M
ANALOG_IN2_P
Output
H-Bridge 2
Input
H-Bridge 2
H-Bridge
PBTL
Detect
BST2_P
BST2_M
Bootstrap
Capacitors
PVDD
PVDD
Power Supply
Decoupling
VDD, AVDD
& GVDD
Power Supply
Decoupling
42 V
SYSTEM Power
Supplies
GND
VDD, GVDD, AVDD
GND
5 V
VAC
*NOTE1: Logic AND in or outside microcontroller
图9-2. System Block Diagram
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9.3 Feature Description
9.3.1 Input Configuration, Gain Setting And Primary / Peripheral Operation
TPA3223 is designed to accept either a differential or a single-ended audio input signal. To accept a wide range
of system front ends TPA3223 has selectable input gain that allows full scale output with a wide range of input
signal levels.
Best system noise performance is obtained with balanced audio interface. However, in systems with only a
single ended audio input signal available, one input terminal can be connected to AC ground to accept single
ended audio input signals.
IN1_P
IN1_P
IN1_M
+
-
IN1_M
IN2_P
IN2_P
IN2_M
+
-
IN2_M
TPA322x
图9-3. Balanced Audio Input Configuration
In systems with single ended audio inputs, set the device gain higher than for systems with balanced audio input
signals.
IN1_P
IN1
+
-
IN1_M
IN2_P
IN2
+
-
IN2_M
TPA322x
图9-4. Single Ended Audio Input Configuration
9.3.2 Gain Setting And Clock Synchronization
The gain of TPA3223 is set by the voltage divider connected to the GAIN/CLKSYNC control pin. Clock
synchronization configuration is also controlled by the same pin. An internal ADC is used to detect the 8 input
states. The first four stages sets the GAIN in Primary mode in gains of 20, 23.5, 32 and 36 dB respectively, while
the next four stages sets the GAIN in peripheral mode in gains of 20, 23.5, 32 and 36 dB respectively. The gain
setting is latched when RESET goes high and cannot be changed while RESET is high. 表 9-1 shows the
recommended resistor values, the state and gain:
表9-1. Clock Synchronization Configuration
Primary / Peripheral
Mode
Differential Input Signal Level
(each input pin)
Single Ended Input Signal
Level
Gain
R1 (to GND)
R2 (to AVDD)
Primary
Primary
20 dB
23.5 dB
32 dB
36 dB
20 dB
23.5 dB
32 dB
36 dB
OPEN
100 kΩ
100 kΩ
75 kΩ
51 kΩ
47 kΩ
39 kΩ
16 kΩ
2 VRMS
1 VRMS
2 VRMS
2 VRMS
5.6 kΩ
20 kΩ
39 kΩ
47 kΩ
51 kΩ
75 kΩ
100 kΩ
100 kΩ
Primary
0.5 VRMS
0.32 VRMS
2 VRMS
1 VRMS
Primary
0.63 VRMS
2 VRMS
Peripheral
Peripheral
Peripheral
Peripheral
1 VRMS
2 VRMS
0.5 VRMS
0.32 VRMS
1 VRMS
0.63 VRMS
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AVDD
R2
AVDD
GAIN/CLKSYNC
TPA3223
R1
GND
图9-5. Clock Synchronization Setup
For easy multi-channel system design TPA3223 has a Clock Synchronization feature that allows automatic
synchronization of multiple peripheral devices operated at the PWM switching frequency of a Primary device.
Using clock synchronization benefits system noise performance by eliminating spurious crosstalk sum and
difference tones due to unsynchronized channel-to-channel switching frequencies. Furthermore, the Clock
Synchronization scheme is designed to interleave switching of the individual channels in a multi-channel system
such that the power supply current ripple frequency is moved to a higher frequency, which reduces the RMS
ripple current in the power supply bulk capacitors.
The Clock Synchronization scheme and the interleaving of the output stage switching are automatically
configured by connecting the OSCx pins between a Primary and multiple peripheral devices. There are two
different configurations of peripheral devices (secondary or tertiary) depending on how the OSCx pins are
connected. Connect the OSCM of the Primary device to the OSCM of a peripheral device and the OSCP of the
Primary device to the OSCP pin of a peripheral device to configure as a secondary. Connect the OSCM of the
Primary device to the OSCP of a peripheral device and the OSCP of the Primary device to the OSCM pin of a
peripheral device to configure as a tertiary. The Primary, secondary and tertiary PWM switching is 30 degrees
out of phase with each other. All switching channels are automatically synchronized by releasing RESET on all
devices at the same time.
AVDD
47k
47k
OSCM
OSCP
OSCM
OSCP
OSCM
OSCP
OSCM
OSCP
OSCM
OSCP
OSCM
OSCP
OSCM
OSCP
TPA322x
Secondary
RESET
TPA322x
Tertiary
RESET
TPA322x
Secondary
RESET
TPA322x
Primary
RESET
TPA322x
Tertiary
RESET
TPA322x
Secondary
RESET
TPA322x
Tertiary
RESET
图9-6. Gain and Primary PCB Implementation
Placement on the PCB and connection of multiple TPA3223 devices in a multi channel system is illustrated in 图
9-6. Peripheral devices must be placed on either side of the Primary device, with a secondary device on one
side of the Primary device, and a tertiary device on the other. In systems with more than 3 TPA3223 devices, the
Primary must be in the middle, and every second peripheral device must be a secondary or tertiary as illustrated
in 图9-6. A 47 kΩpull up resistor to AVDD must be connected to the Primary device OSCM output and a 47 kΩ
pull down resistor to GND must be connected to the Primary OSCP CLK outputs.
9.3.3 PWM Modulation
The TPA3223 uses the AD-Mode PWM modulation scheme which continuous switches the two half bridge
outputs in each BTL output channel.
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OUTP
OUTN
0V
0V
0A
OUTP Current
OUTN Current
0A
图9-7. AD Mode Output Waveforms, Idle
OUTP
OUTN
0V
0V
>0A
OUTP Current
OUTN Current
<0A
图9-8. AD Mode Output Waveforms, High Level Output
PVDD
PVDD
OUTX_P (PWM)
OUTX_M (PWM)
SpeakerX_P
PVDD/2
PVDD/2
SpeakerX_M
0V
SpeakerX_Diff
图9-9. AD Mode Speaker Output Signals, Low or and High Level Output
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9.3.4 Oscillator
The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin.
To reduce interference problems while using radio receiver tuned within the AM band, change the switching
frequency from nominal to higher values. Choose these values so that the nominal and the higher value
switching frequencies together results in the fewest cases of interference throughout the AM band. Select the
oscillator frequency by changing the FREQ_ADJ resistor value connected to GND in Primary mode, according to
the description in the 节7.3.
For peripheral mode operation, turn off the oscillator by pulling the FREQ_ADJ pin to AVDD. Doing so configures
the OSC_I/O pins as inputs to be controlled from an external differential clock. In a multiple device system, inter-
channel delay is automatically set up between the switching of the audio channels, which can be illustrated by
no idle channels switching at the same time. Doing so will not influence the audio output, but only the switch
timing to minimize noise coupling between audio channels through the power supply to optimize audio
performance and to get better operating conditions for the power supply. The inter-channel delay will be set up
for a peripheral device depending on the polarity of the OSC_I/O connection such that a secondary is selected
by connecting the primary device OSC_I/O to the secondary device OSC_I/O with same polarity (+ to + and - to
-), and tertiary is selected with the inverse polarity (+ to - and - to +).
9.3.5 Input Impedance
The TPA3223 input stage is a fully differential input stage and the input impedance changes with the gain setting
from 7.3 kΩat 36 dB gain to 48 kΩat 20 dB gain. 表9-2 lists the values from min to max gain. The tolerance of
the input resistor value is ±20 % so the minimum value is higher than 5.8 kΩ. The inputs need to be AC-coupled
to minimize the output DC-offset and ensure correct ramping of the output voltages during power-ON and power-
OFF. The input ac-coupling capacitor together with the input impedance forms a high-pass filter with the
following cut-off frequency:
If a flat bass response is required down to 20 Hz, then the recommended cut-off frequency is a tenth of that,
which is 2 Hz. 表 9-2 lists the recommended ac-couplings capacitors for each gain step. If a -3 dB in frequency
response is accepted at 20 Hz, then 10 times lower capacitors can be used –for example, a 1 μF can be used.
表9-2. Recommended Input AC-Coupling Capacitors
Gain
20 dB
23.5 dB
32 dB
36 dB
Input Impedance
Input AC-Coupling Capacitance
Input High Pass Filter
4.7 µF
10 µF
10 µF
10 µF
0.7 Hz
0.7 Hz
1.3 Hz
2.2 Hz
48 kΩ
24 kΩ
12 kΩ
7.3 kΩ
Use an input capacitors with low leakage, like quality electrolytic, tantalum, film or ceramic. If a polarized type of
input capacitor is used, then place the positive connection such that the capacitor has a positive DC bias.
9.3.6 Error Reporting
The FAULT, and OTW_CLIP, pins are active-low, open-drain outputs. The FAULT function is for protection-mode
signaling to a system-control device. Any fault resulting in device shutdown is signaled by the FAULT pin going
low. Also, OTW_CLIP goes low when the device junction temperature exceeds 125°C (see 表9-3).
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表9-3. Error Reporting
FAULT
OTW_CLIP (1)
DESCRIPTION
Overtemperature (OTE), overload (OLP), undervoltage (UVP) or overvoltage (OVP).
Junction temperature higher than 125°C (overtemperature warning).
0
0
Overload (OLP), undervoltage (UVP), overvoltage (OVP). Junction temperature lower
than 125°C
0
1
1
1
0
1
Junction temperature higher than 125°C (overtemperature warning)
Junction temperature lower than 125°C and no OLP or UVP faults (normal operation)
(1) Static value. OTW_CLIP is static low when OTW is asserted, and toggling when output signal is CLIP
备注
Asserting RESET low forces the FAULT signal high, independent of faults being present. TI
recommends monitoring the OTW_CLIP signal using the system microcontroller and responding to an
overtemperature warning signal by turning down the volume to prevent further heating of the device
resulting in device shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT and
OTW_CLIP outputs.
9.4 Device Functional Modes
TPA3223 can be configured in either a stereo BTL (Bridge Tied Load) mode, mono BTL mode (only one output
BTL channel active), or in a mono PBTL (Parallel Bridge Tied Load) mode. In PBTL mode the two output BTL
channels are paralleled with double output current available. The paralleling of the two BTL outputs must be
made after the output LC filter.
See 表6-2 for mode configuration setup.
OUT1_P
OUT1_P
IN1_P
IN1_P
IN1_P
IN1_P
OUT1_M
OUT2_P
OUT1_M
OUT2_P
IN1_M
IN1_M
IN1_M
IN1_M
TPA322x
TPA322x
IN2_P
IN2_P
IN2_P
IN2_M
IN2_M
IN2_M
AVDD
OUT2_M
OUT2_M
图9-10. Stereo BTL
图9-11. Mono BTL
OUT1_P
IN1_P
IN1_P
OUT1_M
OUT2_P
IN1_M
IN1_M
TPA322x
IN2_P
IN2_M
OUT2_M
图9-12. Mono PBTL, Post LC Filter
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9.4.1 Powering Up
The TPA3223 does not require a power-up sequence because of the integrated undervoltage protection (UVP),
but TI recommends to hold RESET low until PVDD supply voltage is stable to avoid audio artifacts. The outputs
of the H-bridges remain in a high-impedance state until the gate-drive supply (GVDD) and AVDD voltages are
above their UVP voltage thresholds (see the 节7.5 table of this data sheet). Doing so allows an internal circuit to
charge the external bootstrap capacitors by enabling a weak pull-down of the half-bridge output as well as
initiating a controlled ramp up sequence of the output voltage.
PVDD
VDD
GVDD
RESET
AVDD
t
Precharge
C 20ms
FAULT
VIN_X
OUT_X
VOUT_X
t
Startup ramp
V_CMUTE
图9-13. Startup Timing
When RESET is released to turn on TPA3223, FAULT signal turns low. FAULT stays low until AVDD reaches the
undervoltage protection (UVP) voltage threshold (see the 节7.5 table of this data sheet). After a pre-charge time
to stabilize the DC voltage across the input AC coupling capacitors, the ramp up sequence starts and completes
once the CMUTE node is charged to the final value.
9.4.1.1 Startup Ramp Time
During the startup ramp the CMUTE capacitor is charged by an internal current generator. With use of the
recommended 33 nF CMUTE capacitor value, the startup ramp time is approximately 20 ms. Higher CMUTE
capacitor value will increase the ramp time, and a lower value will decrease the ramp time. The recommended
CMUTE capacitor value is selected for minimum audible artifacts during startup and shutdown ramp.
9.4.2 Powering Down
The TPA3223 does not require a power-down sequence. The device remains fully operational as long as the
VDD, AVDD and PVDD voltages are above their undervoltage protection (UVP) voltage thresholds (see 节 7.5).
Although not specifically required, TI recommends to hold RESET low during power down, thus preventing
audible artifacts including pops or clicks by initiating a controlled ramp down sequence of the output voltage. The
ramp down sequence will complete once the CMUTE node is discharged.
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9.4.2.1 Power Down Ramp Time
During the power down ramp the CMUTE capacitor is discharged by internal circuitry. With use of the
recommended 33 nF CMUTE capacitor value, the power-down ramp time is approximately 20 ms.
9.4.3 Device Reset
Asserting RESET low initiates the device ramp down. The output FETs go into a Hi-Z state after the ramp down
is complete. Output pull downs are active in both BTL mode and PBTL mode with RESET low.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the RESET input low
enables weak pull-down of the half-bridge outputs.
Asserting RESET low removes any fault information to be signaled on the FAULT output, that is, FAULT is forced
high. A rising-edge transition on RESET allows the device to resume operation after a fault. To make sure of
thermal reliability, the rising edge of RESET must occur no sooner than 4 ms after the falling edge of FAULT.
The TPA3223 will enter a low power state once the ramp down sequence is complete.
9.4.4 Device Soft Mute
Asserting CMUTE low initiates the device soft mute function. The soft mute function initiates a ramp down
sequence of the outputs, and the output FETs go into a Hi-Z state after the ramp down is complete. All internal
circuits are powered while in soft mute state. External control of the soft mute function must provide high
impedance output when not engaged (open drain output) to allow the CMUTE node to charge/discharge during
device ramp up and ramp down when de-asserting and asserting RESET.
9.4.5 Device Protection System
The TPA3223 contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, overvoltage, and undervoltage. The TPA3223 responds to a fault by
immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In
situations other than overload and overtemperature error (OTE), the device automatically recovers when the
fault condition has been removed, that is, the supply voltage has increased. The device will handle errors, as
shown in 表9-4.
表9-4. Device Protection
BTL MODE
LOCAL ERROR IN
PBTL MODE
TURNS OFF
LOCAL ERROR IN
TURNS OFF
A
B
C
D
A
B
C
D
A+B
A+B+C+D
C+D
Bootstrap UVP does not shutdown according to the table, it shuts down the respective half-bridge (non-latching,
does not assert FAULT).
9.4.5.1 Overload and Short Circuit Current Protection
TPA3223 has fast reacting current sensors on all high-side and low-side FETs. To prevent output current from
increasing beyond the overcurrent threshold, TPA3223 uses current limiting of the output current for each
switching cycle (Cycle By Cycle Current Control, CB3C) in case of excess output current. CB3C prevents
premature shutdown due to high output current transients caused by high level music transients and a drop of
the real load impedance of the speaker, and allows the output current to be limited to a maximum programmed
level. If the maximum output current persists, for example the power stage being overloaded with too low load
impedance, then the device will shut down the affected output channel and the affected output is put in a high-
impedance (Hi-Z) state until a RESET cycle is initiated. CB3C works individually for each full-bridge output. If an
over current event is triggered, then the CB3C performs a state flip of the full-bridged output that is cleared upon
beginning of next PWM frame.
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PWM_X
HS PWM
RISING EDGE PWM
SETS CB3C LATCH
LS PWM
OC EVENT RESETS
CB3C LATCH
OC THRESHOLD
OUTPUT CURRENT
OCH
HS GATE-DRIVE
LS GATE-DRIVE
图9-14. CB3C Timing Example
9.4.5.2 Signal Clipping and Pulse Injector
A built-in activity detector monitors the PWM activity of the OUT_X pins. TPA3223 is designed to drive unclipped
output signals all the way to PVDD and GND rails. In case of audio signal clipping when applying excessive input
signal voltage, or in case of CB3C current protection being active, the amplifier feedback loop of the audio
channel will respond to this condition with a saturated state, and the output PWM signals will stop unless special
circuitry is implemented to handle this situation. To prevent the output PWM signals from stopping in a clipping or
CB3C situation, narrow pulses are injected to the gate drive to maintain output activity. The injected narrow
pulses are injected at every 4th PWM frame, and thus the effective switching frequency during this state is
reduced to 1/4 of the normal switching frequency.
Signal clipping is signaled on the OTW_CLIP pin and is self clearing when signal level reduces and the device
reverts to normal operation. The OTW_CLIP pulses start at the onset to output clipping, typically at a THD level
around 0.01%, resulting in narrow OTW_CLIP pulses starting with a pulse width of approximately 500 ns.
图9-15. Signal Clipping PWM and Speaker Output Signals
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9.4.5.3 DC Speaker Protection
The output DC protection scheme protects a speaker from excess DC current in case one terminal of the
speaker is connected to the amplifier while the other is accidentally shorted to the chassis ground. Such a short
circuit results in a DC voltage of PVDD/2 across the speaker, which potentially can result in destructive current
levels. The output DC protection detects any unbalance of the output and input current of a BTL or PBTL output
configuration (current into/out of one half-bridge equals current out of/into the other half-bridge), and in the event
of the imbalance exceeding a programmed threshold, the overload counter increments until the maximum value
and the affected output channel is shut down. DC Speaker Protection is enabled in both BTL and PBTL mode
operation.
9.4.5.4 Pin-to-Pin Short Circuit Protection (PPSC)
The PPSC detection system protects the device from permanent damage in the case that a power output pin
(OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent
after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup after RESET is pulled high. When PPSC detection is activated by a short on the output, all
half-bridges are kept in a Hi-Z state until the short is removed; the device then continues the startup sequence
and starts switching. The detection is controlled globally by a two step sequence. The first step ensures that
there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X to
PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The
typical duration is < 15 ms/μF. While the PPSC detection is in progress, FAULT is kept low. If no shorts are
present, then the PPSC detection passes, and FAULT is released. A device reset will start a new PPSC
detection. PPSC detection is enabled in both BTL and PBTL output configurations. To ensure not to trip the
PPSC detection system, TI recommends not to insert a resistive load to GND_X or PVDD_X.
9.4.5.5 Overtemperature Protection OTW and OTE
TPA3223 has a two-level temperature-protection system that asserts an active-low warning signal ( OTW_CLIP)
when the device junction temperature exceeds 125°C (typical). If the device junction temperature exceeds
155°C (typical), then the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the
high-impedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To clear the OTE latch,
RESET must be asserted. Thereafter, the device resumes normal operation.
9.4.5.6 Undervoltage Protection (UVP), Overvoltage Protection (OVP), and Power-on Reset (POR)
The UVP, OVP and POR circuits of the TPA3223 fully protect the device in any power-up/down and brownout
situation, and also in overvoltage situation with PVDD not exceeding the values stated in 节 7.1. While powering
up, the POR circuit ensures that all circuits are fully operational when the AVDD supply voltage reaches the
value stated in 节 7.5. Although AVDD is independently monitored, a supply voltage drop below the UVP
threshold on AVDD pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state.
The device automatically resumes operation when all supply voltages have increased above their UVP
threshold. In case of an OVP event, all half-bridge outputs are immediately set in the high-impedance (Hi-Z)
state and FAULT is asserted low until PVDD is below the OVP threshold.
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9.4.5.7 Fault Handling
If a fault situation occurs while in operation, then the device acts accordingly to the fault being a global or a
channel fault. A global fault is a chip-wide fault situation and causes all PWM activity of the device to be shut
down, and asserts FAULT low. A global fault is a latching fault and clearing FAULT and restarting operation
requires resetting the device by toggling RESET. De-asserting RESET is never allowed with excessive system
temperature, so TI recommends to monitor RESET with a system microcontroller and only release RESET
( RESET high) if the OTW_CLIP signal is cleared (high). A channel fault results in shutdown of the PWM activity
of the affected channels.
备注
Asserting RESET low forces the FAULT signal high, independent of faults being present.
表9-5. Error Reporting
Fault/Event
Description
Latched/Self
Clearing
Action needed to
Clear
Fault/Event
PVDD_X UVP
PVDD_X OVP
Global or Channel
Reporting Method
Output FETs
Increase affected
supply voltage
Decrease affected
supply voltage
Voltage Fault
Global
FAULT pin
Self Clearing
HI-Z
Increase affected
supply voltage
AVDD UVP
POR (AVDD UVP)
OTW
Power On Reset
Thermal Warning
Global
Global
FAULT pin
Self Clearing
Self Clearing
Allow AVDD to rise
HI-Z
Cool below OTW
threshold
OTW_CLIP pin
Normal operation
OTE
Thermal Shutdown
OC Shutdown
Global
FAULT pin
FAULT pin
Latched
Latched
Toggle RESET
Toggle RESET
HI-Z
HI-Z
OLP (CB3C>2.1 ms)
Channel
Reduce signal level
or remove short
Flip state, cycle by
cycle at fs/3
CB3C
OC Limiting
Channel
Global
None
None
Self Clearing
Self Clearing
No OSC_IO activity
in Peripheral Mode
Resume OSC_IO
activity
Stuck at Fault(1)
HI-Z
(1) Stuck at Fault occurs when input OSC_IO input signal frequency drops below minimum frequency given in the Electrical
Characteristics table of this data sheet.
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
TPA3223 can be configured either in stereo BTL, mono BTL or mono PBTL mode depending on output power
conditions and system design.
10.2 Typical Applications
10.2.1 Stereo BTL Application
220 nF
BST2_M
BST2_P
GND
GVDD
AVDD
NC
10µH
44
43
42
41
+5V
1
2
3
1µF
10nF
1µF
220 nF
1nF
1nF
1µF
GND
GND
3R3
4
5
OUT2_M
OUT2_M
PVDD
GND
33nF
1µF
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
3R3
CMUTE
IN2_M
IN2_P
FREQ_ADJ
OSCP
6
PVDD
1µF
1k
IN2_M
10nF
CMUTE
10µH
7
PVDD
IN2_P
1µF
470uF
1µF
8
1µF
PVDD
9
50k
OUT2_P
GND
10
11
12
13
OSCM
GND
TPA3223
GND
OUT1_M
PVDD
PVDD
RESET
IN1_M
IN1_P
GND
RESET
PVDD
IN1_M
IN1_P
14
15
16
17
18
19
20
21
22
10µH
1µF
1µF
1µF
1000 uF
1000 uF
1µF
10nF
PVDD
OUT1_P
OUT1_P
GND
1nF
1nF
1µF
1µF
NC
3R3
NC
3R3
FAULT
FAULT
OTW_CLIP
GAIN/CLKSYNC
VDD
10nF
GND
OTW_CLIP
220 nF
BST1_M
BST1_P
10µH
5.6k
+5V
220 nF
100nF
470uF
图10-1. Typical Differential (2N) AD-Mode BTL Application
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10.2.1.1 Design Requirements
For this design example, use the parameters in 表10-1.
表10-1. Design Requirements, BTL Application
DESIGN PARAMETER
Low Power Supply
High Power Supply
EXAMPLE
5 V
10 - 42 V
IN1_M = ±2.8V (peak, max)
IN1_P = ±2.8V (peak, max)
Analog Inputs
IN2_M = ±2.8V (peak, max)
IN2_P = ±2.8V (peak, max)
Output Filters
Inductor-Capacitor Low Pass Filter (10 µH + 1 µF)
3.5 - 8 Ω
Speaker Impedance
10.2.1.2 Detailed Design Procedures
A rising-edge transition on RESET input allows the device to execute the startup sequence and start switching.
A toggling OTW_CLIP signal is indicating that the output is approaching clipping. The signal can be used either
to decrease audio volume or to control an intelligent power supply nominally operating at a low rail adjusting to a
higher supply rail.
The device inverts the audio signal from input to output.
10.2.1.2.1 Decoupling Capacitor Recommendations
In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, use X7R in this application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This is particularly true in the selection
of the 1 μF capacitor that is placed on the power supply to each full-bridge. The capacitor must withstand the
voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the
ripple current created by high power output. A minimum voltage rating of 75 V is required for use with a 42 V
power supply.
10.2.1.2.2 PVDD Capacitor Recommendation
The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. Select
these capacitors for proper voltage margin and adequate capacitance to support the power requirements. In
practice, with a well designed system power supply, two 1000 μF capacitors, 75 V supports most applications.
Use PVDD capacitors with low ESR type because they are used in a circuit associated with high-speed
switching.
10.2.1.2.3 BST capacitors
To make sure of a large enough bootstrap energy storage for the high side gate drive to work correctly with all
audio source signals, 33 nF / 50 V X7R BST capacitors are recommended.
10.2.1.2.4 PCB Material Recommendation
FR-4 Glass Epoxy material with 2 oz. (70 μm) copper is recommended for use with the TPA3223. The use of
this material can provide for higher power output, improved thermal performance, and better EMI margin due to
lower PCB trace inductance.
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10.2.2 Application Curves
Relevant performance plots for TPA3223 in BTL configuration are shown in 节7.8
10
5
10
5
PVDD=42V
TC=75C
BTL Mode
1W
10W
50W
100W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
AUX-0025 Filter
80kHz analyzer BW
RL=4 TC=75C
Load=4
Load=6
Load=8
0.005
0.005
0.002
0.001
0.002
0.001
0.01
0.1
1
10
100 200
20
100
1k
Frequency (Hz)
10k 20k 40k
Output Power (W)
图10-2. Total Harmonic Distortion + Noise vs
图10-3. Total Harmonic Distortion+Noise vs
Output Power
Frequency
200
3
180
160
140
120
100
80
3 - CB3C Limited
4
6
8
60
40
THD+N = 10%
TC=75C
BTL Mode
20
0
10
15
20
25
30
35
40 42
PVDD - Supply Voltage - V
D014
D037
图10-4. Output Power vs Supply Voltage, AD-mode
图10-5. System Efficiency vs Output Power
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10.2.3 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled after LC filter)
TPA3223 can be configured in mono PBTL mode by paralleling the outputs before the LC filter (see ) or after the
LC filter. Paralleled outputs after the LC filter can be preferred if a single board design must support both PBTL
and BTL, or in the case multiple, smaller paralleled inductors are preferred due to size or cost. Paralleling after
the LC filter requires four inductors, one for each OUT_x. This section shows an example of paralleled outputs
after the LC filter.
220 nF
BST2_M
BST2_P
GND
GVDD
AVDD
NC
44
43
42
41
+5V
1
2
3
1µF
1µF
220 nF
GND
GND
4
5
10µH
10µH
OUT2_M
OUT2_M
PVDD
GND
33nF
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
CMUTE
IN2_M
IN2_P
FREQ_ADJ
OSCP
PVDD
6
1k
CMUTE
7
PVDD
1µF
470uF
1µF
8
10nF
PVDD
9
50k
1nF
1nF
OUT2_P
GND
1µF
1µF
10
11
12
13
3R3
OSCM
GND
TPA3223
GND
3R3
OUT1_M
PVDD
PVDD
RESET
IN1_M
IN1_P
GND
RESET
10nF
PVDD
10µH
10µH
IN1_M
IN1_P
14
15
16
17
18
19
20
21
22
1µF
1µF
1µF1000uF 1000uF 1µF
PVDD
OUT1_P
OUT1_P
GND
NC
NC
FAULT
FAULT
OTW_CLIP
GAIN/CLKSYNC
VDD
GND
OTW_CLIP
220 nF
BST1_M
BST1_P
5.6k
+5V
220 nF
100nF
470uF
图10-6. Typical Differential (2N) AD-Mode PBTL Application
10.2.3.1 Design Requirements
Refer to 节10.2.1 for the Design Requirements.
表10-2. Design Requirements, PBTL Application
DESIGN PARAMETER
Low Power Supply
High Power Supply
EXAMPLE
5 V
10 - 42 V
IN1_M = ±2.8 V (peak, max)
IN1_P = ±2.8 V (peak, max)
IN2_M = Grounded
Analog Inputs
IN2_P = Grounded
Output Filters
Inductor-Capacitor Low Pass Filter (10 µH + 1 µF)
Speaker Impedance
2 - 4 Ω
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10.3 Power Supply Recommendations
10.3.1 Power Supplies
The TPA3223 device requires an external power supply for PVDD to power the output stage of the speaker
amplifier and the associated circuitry.
An external power supply must be connected to GVDD, AVDD and VDD to power the gate-drive and other
internal digital and analog circuit blocks in the device.
The allowable voltage range for both the PVDD and GVDD/AVDD/VDD supplies are listed in 节7.3. Ensure both
the PVDD and the GVDD/AVDD/VDD supplies can deliver more current than listed in 节7.3.
10.3.1.1 VDD Supply
An external 5 V power supply needs to be connected to VDD, AVDD and GVDD.
Proper connection, routing, and decoupling techniques are highlighted in the TPA3223 EVM User's Guide (as
well as 节 10.1 and 节 10.4.2) and must be followed as closely as possible for proper operation and
performance. Deviation from the guidance offered in the TPA3223 device EVM User's Guide, which followed the
same techniques as those shown in 节 10.1, may result in reduced performance, errant functionality, or even
damage to the TPA3223 device.
10.3.1.2 AVDD and GVDD Supplies
AVDD and GVDD can be supplied through an external 5 V power supply to power internal analog and digital
circuits and the gate-drivers for the output H-bridges. Proper connection, routing, and decoupling techniques are
highlighted in the TPA3223 device EVM User's Guide (as well as 节10.1 and 节10.4.2) and must be followed as
closely as possible for proper operation and performance. Deviation from the guidance offered in the TPA3223
device EVM User's Guide, which followed the same techniques as those shown in 节 10.1 may result in reduced
performance, errant functionality, or even damage to the TPA3223 device.
10.3.1.3 PVDD Supply
The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which
provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques
are highlighted in the TPA3223 device EVM User's Guide (as well as 节 10.1 and 节 10.4.2) and must be
followed as closely as possible for proper operation and performance. Due to the high-voltage switching of the
output stage, it is particularly important to properly decouple the output power stages in the manner described in
the TPA3223 device EVM User's Guide. The lack of proper decoupling, like that shown in the EVM User's Guide,
can result in voltage spikes which can damage the device, or cause poor audio performance and device
shutdown faults.
10.3.1.4 BST Supply
TPA3223 has built-in bootstrap supply for each half bridge gate drive to supply the high side MOSFETs, only
requiring a single capacitor per half bridge. The capacitors are connected to each half bridge output, and are
charged by the GVDD supply via an internal diode while the PWM outputs are in low state. The high side gate
drive is supplied by the voltage across the BST capacitor while the output PWM is high. It is recommended to
place the BST capacitors close to the TPA3223 device, and to keep PCB routing traces at minimum length.
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10.4 Layout
10.4.1 Layout Guidelines
• Use an unbroken ground plane to have good low impedance and inductance return path to the power supply
for power and audio signals.
• Maintain a contiguous ground plane from the ground pins to the PCB area surrounding the device for as
many of the ground pins as possible, since the ground pins are the best conductors of heat in the package.
• PCB layout, audio performance and EMI are linked closely together.
• Routing the audio input should be kept short and together with the accompanied audio source ground.
• The small bypass capacitors on the PVDD lines should be placed as close to the PVDD pins as possible.
• A solid local ground area underneath the device is important to minimize ground bounce.
• Orient the passive component so that the narrow end of the passive component is facing the TPA3223
device, unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads.
• Avoid placing other heat producing components or structures near the TPA3223 device.
• Avoid cutting off the flow of heat from the TPA3223 device to the surrounding ground areas with traces or via
strings, especially on output side of device.
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10.4.2 Layout Examples
10.4.2.1 BTL Application Printed Circuit Board Layout Example
T3
T1
1
44
2
43
T2
3
42
4
41
5
40
6
39
7
38
8
37
T2
9
36
10
35
11
34
12
T2
33
13
32
14
31
15
30
16
29
T2
17
28
18
27
19
26
20
25
T1
21
24
2
23
T3
System Processor
Bo om to top layer connec on via
Bo om Layer Signal Traces
Pad to top layer ground pour
Top Layer Signal Traces
A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer copper traces. All PCB
area not used for traces must be GND copper pour (transparent on example image)
B. Note T1: PVDD decoupling bulk capacitors must be as close as possible to the PVDD and GND_X pins, the heat sink sets the distance.
Wide traces must be routed on the top layer with direct connection to the pins and without going through vias. No vias or traces must be
blocking the current path.
C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and close to the pins.
D. Note T3: Heat sink needs to have a good connection to PCB ground.
图10-7. BTL Application Printed Circuit Board - Composite
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10.4.2.2 PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board Layout Example
T3
T1
1
44
2
43
T2
3
42
4
41
5
40
6
39
7
38
8
37
T2
9
36
10
35
11
34
12
T2
33
13
32
14
31
15
30
16
29
T2
17
28
18
27
19
26
20
25
T1
21
24
22
23
T3
System Processor
Bo om to top layer connec on via
Top Layer Signal Traces
Bo om Layer Signal Traces
Pad to top layer ground pour
A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer copper traces. All PCB
area not used for traces must be GND copper pour (transparent on example image)
B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat sink sets the
distance. Wide traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or
traces must be blocking the current path.
C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and close to the pins.
D. Note T3: Heat sink needs to have a good connection to PCB ground.
图10-8. PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board - Composite
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11 Device and Documentation Support
11.1 Documentation Support
• TPA3223 Evaluation Module User's Guide
• Multi-Device Configuration for TPA32xx Amplifiers
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
Wi-Fi™ is a trademark of Wi-Fi Alliance.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPA3223DDVR
ACTIVE
HTSSOP
DDV
44
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
3223
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DDV0044D
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
2
5
0
PLASTIC SMALL OUTLINE
C
8.3
7.9
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
42X 0.635
44
1
2X (0.3)
NOTE 6
14.1
13.9
NOTE 3
2X
13.335
7.30
6.72
EXPOSED
THERMAL
PAD
(0.15) TYP
NOTE 6
2X (0.6)
NOTE 6
23
22
0.27
0.17
44X
4.43
3.85
0.08
C A B
6.2
6.0
B
(0.15) TYP
0.25
1.2
1.0
GAGE PLANE
SEE DETAIL A
0.75
0.50
0.15
0.05
0 - 8
DETAIL A
TYPICAL
4218830/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. The exposed thermal pad is designed to be attached to an external heatsink.
6. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DDV0044D
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
SEE DETAILS
SYMM
44X (1.45)
44X (0.4)
1
44
42X (0.635)
SYMM
(R0.05) TYP
23
22
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
METAL UNDER
SOLDER MASK
SOLDER MASK
METAL
SOLDER MASK
OPENING
OPENING
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4218830/A 08/2016
NOTES: (continued)
7. Publication IPC-7351 may have alternate designs.
8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDV0044D
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
44X (1.45)
44X (0.4)
SYMM
1
44
42X (0.635)
SYMM
23
22
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE :6X
4218830/A 08/2016
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
10. Board assembly site may have different recommendations for stencil design.
www.ti.com
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