TPA3245DDVR [TI]
115W 立体声、230W 单声道、12V 至 31.5V 电源电压、模拟输入 D 类音频放大器 | DDV | 44 | 0 to 70;
| 型号： | TPA3245DDVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 115W 立体声、230W 单声道、12V 至 31.5V 电源电压、模拟输入 D 类音频放大器 | DDV | 44 | 0 to 70 放大器 音频放大器 |
| 文件： | 总48页 (文件大小：1673K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPA3245
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
TPA3245 115W 立体声、230W 单声道 PurePath™ 超高清模拟输入 D 类
放大器
1 特性
•
采用推荐的系统设计时，符合电磁干扰 (EMI) 标准
1
•
•
差分模拟输入
2 应用
总谐波失真+噪声 (THD+N) 为 10% 时的总输出功
率
•
•
•
•
•
Blu-Ray Disc™/DVD 接收器
高端电视机
–
–
–
115W/4Ω，BTL 立体声配置
145W/3Ω，BTL 立体声配置
230W/2Ω，PBTL 单声道配置
高端条形音箱
微型 Combo 系统
有源扬声器和低音炮
•
•
总谐波失真+噪声 (THD+N) 为 1% 时的总输出功率
–
–
–
95W/4Ω，BTL 立体声配置
115W/3Ω，BTL 立体声配置
185W/2Ω，PBTL 单声道配置
3 说明
TPA3245 是一款高性能 D 类功率放大器，它具有 D
类效率并且能够带来真正的高端音质。该器件 特有 高
级集成反馈设计和专有高速栅极驱动器错误校正功能
（PurePath™ 超高清）。该技术可使器件在整个音频
频带内保持超低失真，同时展现完美音质。该器件在
AD 模式下工作，最多可驱动 2 个 115W/4Ω 负载和 2
个 145W/3Ω 负载，并且 特有 一个 2 VRMS 模拟输入
接口，支持与高性能 DAC（例如 TI 的 PCM5242）无
缝连接。除了出色的音频性能外，TPA3245 还兼具高
功率效率和超低功率级空闲损耗（0.45W 以下）两大
优点。这可以利用 65mΩ MOSFET 以及优化型栅极驱
动器方案来实现，该方案相比传统的分立实现方案可显
著降低空闲损耗。
采用高级集成反馈设计，具有高速栅极驱动器错误
校正功能
（PurePath™超清）
–
–
–
高达 100kHz 的信号宽带，用于高清 (HD) 源的
高频成分
超低 THD+N：1W/4Ω 时为 0.005%；削波时
<0.01%
电源抑制比 (PSRR) 为 65dB（BTL，无输入信
号）
–
–
（A 加权）输出噪声 < 50µV
（A 加权）信噪比 (SNR) > 112dB
•
多种配置可供选择：
立体声、单声道、2.1 和 4xSE
–
器件信息(1)
•
•
•
•
启动和停止时无喀哒声和噼啪声
90% 高效 D 类操作 (4Ω)
器件型号
TPA3245
封装
封装尺寸（标称值）
HTSSOP (44)
6.10mm x 14.00mm
12V 至 30V 宽电源电压工作范围
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
具有错误报告功能的自保护设计（包括欠压、过
压、削波和短路保护）
简化电路原理图
总谐波失真
10
TPA3245
3W
4W
8W
RIGHT
LEFT
LC Filter
LC Filter
1
0.1
Audio Source
And Control
/CLIP_OTW
/RESET
/FAULT
12V
Operation Mode Select
M1:M2
Power Supply
30V
0.01
Switching Frequency Select
FREQ_ADJ
OSC_IOM/P
Master/Slave Synchronization
TC = 75èC
110VAC->240VAC
Copyright © 2016, Texas Instruments Incorporated
0.001
10m
100m
1
10
100 200
Po - Output Power - W
D003
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLASEC7
TPA3245
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
目录
9.2 Functional Block Diagrams ..................................... 15
9.3 Feature Description................................................. 17
9.4 Device Protection System....................................... 17
10 Application and Implementation........................ 22
10.1 Application Information.......................................... 22
10.2 Typical Applications .............................................. 22
11 Power Supply Recommendations ..................... 31
11.1 Power Supplies ..................................................... 31
11.2 Powering Up.......................................................... 31
11.3 Powering Down..................................................... 32
12 Layout................................................................... 32
12.1 Layout Guidelines ................................................. 32
12.2 Layout Examples................................................... 34
13 器件和文档支持 ..................................................... 38
13.1 文档支持................................................................ 38
13.2 接收文档更新通知 ................................................. 38
13.3 社区资源................................................................ 38
13.4 商标....................................................................... 38
13.5 静电放电警告......................................................... 38
13.6 Glossary................................................................ 38
14 机械、封装和可订购信息....................................... 39
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 Audio Characteristics (BTL) ...................................... 8
7.7 Audio Characteristics (SE) ....................................... 9
7.8 Audio Characteristics (PBTL) ................................... 9
7.9 Typical Characteristics, BTL Configuration............. 10
7.10 Typical Characteristics, SE Configuration............. 12
7.11 Typical Characteristics, PBTL Configuration ........ 13
Parameter Measurement Information ................ 14
Detailed Description ............................................ 14
9.1 Overview ................................................................. 14
8
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (April 2016) to Revision A
Page
•
已将器件状态由“产品预览”更改为“量产数据” .......................................................................................................................... 1
2
Copyright © 2016, Texas Instruments Incorporated
TPA3245
www.ti.com.cn
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
5 Device Comparison Table
DEVICE NAME
TPA3244
DESCRIPTION
40-W Stereo, 100-W peak PurePath™ Ultra-HD Pad Down Class-D Amplifier
70-W Stereo, 130-W peak PurePath™ Ultra-HD Pad Down Class-D Amplifier
175-W Stereo, 350-W Mono PurePath™ Ultra-HD Analog-Input Class-D Amplifier
315-W Stereo, 600-W Mono PurePath™ Ultra-HD Analog-Input Class-D Amplifier
TPA3250
TPA3251
TPA3255
6 Pin Configuration and Functions
The TPA3245 is available in a thermally enhanced TSSOP package.
The package type contains a PowerPad™ that is located on the top side of the device for convenient thermal
coupling to the heat sink.
DDV Package
HTSSOP 44-Pin
(Top View)
BST_A
BST_B
GND
GVDD_AB
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VDD
M1
3
GND
M2
4
OUT_A
OUT_A
PVDD_AB
PVDD_AB
PVDD_AB
OUT_B
GND
5
INPUT_A
6
INPUT_B
OC_ADJ
7
FREQ_ADJ
OSC_IOM
OSC_IOP
DVDD
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Thermal
Pad
GND
GND
OUT_C
PVDD_CD
PVDD_CD
PVDD_CD
OUT_D
OUT_D
GND
GND
AVDD
C_START
INPUT_C
INPUT_D
RESET
FAULT
VBG
GND
BST_C
BST_D
CLIP_OTW
GVDD_CD
Copyright © 2016, Texas Instruments Incorporated
3
TPA3245
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
Pin Functions
NAME
NO.
14
44
43
24
23
21
15
11
19
8
I/O
P
DESCRIPTION
AVDD
Internal voltage regulator, analog section
BST_A
BST_B
BST_C
BST_D
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_A required.
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_B required.
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_C required.
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_D required.
Clipping warning and Over-temperature warning; open drain; active low. Do not connect if not used.
Startup ramp, requires a charging capacitor to GND
P
P
P
CLIP_OTW
C_START
DVDD
O
O
P
Internal voltage regulator, digital section
FAULT
O
O
P
Shutdown signal, open drain; active low. Do not connect if not used.
Oscillator frequency programming pin
FREQ_ADJ
12, 13, 25, 26,
33, 34, 41, 42
GND
Ground
GVDD_AB
GVDD_CD
INPUT_A
INPUT_B
INPUT_C
INPUT_D
M1
1
P
P
I
Gate-drive voltage supply; AB-side, requires 0.1 µF capacitor to GND
Gate-drive voltage supply; CD-side, requires 0.1 µF capacitor to GND
Input signal for half bridge A
22
5
6
I
Input signal for half bridge B
16
I
Input signal for half bridge C
17
I
Input signal for half bridge D
3
I
Mode selection 1 (LSB)
M2
4
I
Mode selection 2 (MSB)
OC_ADJ
OSC_IOM
OSC_IOP
OUT_A
7
I/O
I/O
O
O
O
O
O
P
P
I
Over-Current threshold programming pin
Oscillator synchronization interface. Do not connect if not used.
Oscillator synchronization interface. Do not connect if not used.
Output, half bridge A
9
10
39, 40
35
OUT_B
Output, half bridge B
OUT_C
32
Output, half bridge C
OUT_D
27, 28
36, 37, 38
29, 30, 31
18
Output, half bridge D
PVDD_AB
PVDD_CD
RESET
PVDD supply for half-bridge A and B
PVDD supply for half-bridge C and D
Device reset Input; active low
VDD
2
P
P
P
Power supply for internal voltage regulator requires a 10-µF capacitor with a 0.1-µF capacitor to GND for decoupling.
Internal voltage reference requires a 0.1-µF capacitor to GND for decoupling.
Ground, connect to grounded heat sink
VBG
20
PowerPad™
Table 1. Mode Selection Pins
MODE PINS
OUTPUT
CONFIGURATION
INPUT MODE
DESCRIPTION
M2
0
M1
0
2N + 1
2N/1N + 1
2N + 1
2 × BTL
1 x BTL + 2 x SE
1 x PBTL
Stereo BTL output configuration
0
1
2.1 BTL + SE mode. Channel AB: BTL, channel C + D: SE
Parallelled BTL configuration. Connect INPUT_C and INPUT_D to GND.
Single ended output configuration
1
0
1
1
1N +1
4 x SE
4
Copyright © 2016, Texas Instruments Incorporated
TPA3245
www.ti.com.cn
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
-0.3
MAX
43
UNIT
V
BST_X to GVDD_X(2)
VDD to GND
GVDD_X to GND(2)
13.2
13.2
43
V
V
Supply voltage
PVDD_X to GND(2)
V
DVDD to GND
4.2
8.5
4.2
43
V
AVDD to GND
V
VBG to GND
V
OUT_X to GND(2)
BST_X to GND(2)
–0.3
–0.3
–0.3
–0.3
–0.3
V
55.5
4.2
4.2
7
V
OC_ADJ, M1, M2, OSC_IOP, OSC_IOM, FREQ_ADJ, C_START, to GND
RESET, FAULT, CLIP_OTW to GND
V
Interface pins
V
INPUT_X to GND
V
Continuous sink current, RESET, FAULT, CLIP_OTW to GND
Operating junction temperature range
9
mA
°C
°C
TJ
0
150
150
Tstg
Storage temperature range
–40
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins
±1000
V
(1)
VESD
Electrostatic discharge
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
±250
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2016, Texas Instruments Incorporated
5
TPA3245
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
PVDD_x
GVDD_x
Half-bridge supply
DC supply voltage
DC supply voltage
DC supply voltage
12
30
31.5
13.2
13.2
V
Supply for logic regulators and gate-drive
circuitry
10.8
12
V
V
VDD
Digital regulator supply voltage
10.8
2.7
1.5
1.6
5
12
4
RL(BTL)
RL(SE)
Output filter inductance within
recommended value range
Load impedance
3
Ω
RL(PBTL)
LOUT(BTL)
LOUT(SE)
LOUT(PBTL)
2
Output filter inductance
Minimum output inductance at IOC
5
μH
kHz
kΩ
5
Nominal
575
475
430
9.9
19.8
29.7
600
500
450
10
625
525
PWM frame rate selectable for AM
interference avoidance; 1% Resistor
tolerance
FPWM
AM1
AM2
470
Nominal; Master mode
AM1; Master mode
AM2; Master mode
10.1
20.2
30.3
R(FREQ_ADJ)
PWM frame rate programming resistor
20
30
CPVDD
ROC
PVDD close decoupling capacitors
Over-current programming resistor
1.0
μF
kΩ
kΩ
Resistor tolerance = 5%
Resistor tolerance = 5%
22
47
30
64
ROC(LATCHED) Over-current programming resistor
Voltage on FREQ_ADJ pin for slave
mode operation
V(FREQ_ADJ)
Slave mode
3.3
V
TJ
Junction temperature
0
125
°C
7.4 Thermal Information
TPA3251D2
DDV 44-PINS HTSSOP
THERMAL METRIC(1)
UNIT
FIXED 85°C HEATSINK TEMPERATURE(2)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
2.8(2)
RθJC(top)
RθJB
0.5
n/a
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.9
ψJB
n/a
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Thermal data are obtained with 85°C heat sink temperature using thermal compound with 0.7W/mK thermal conductivity and 2mil
thickness. In this model heat sink temperature is considered to be the ambient temperature and only path for dissipation is to the
heatsink.
6
Copyright © 2016, Texas Instruments Incorporated
TPA3245
www.ti.com.cn
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
7.5 Electrical Characteristics
PVDD_X = 30 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 600 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as reference
DVDD
VDD = 12 V
3.3
7.8
V
V
node
Voltage regulator, only used as reference
node
AVDD
VDD = 12 V
Operating, 50% duty cycle
Idle, reset mode
40
10
IVDD
VDD supply current
mA
mA
50% duty cycle
19
IGVDD_X
Gate-supply current per full-bridge
PVDD idle current per full bridge
Reset mode
2.5
15
50% duty cycle with recommended output filter
Reset mode, No switching
mA
mA
IPVDD_X
1.1
ANALOG INPUTS
RIN
Input resistance
24
18
kΩ
V
VIN
Maximum input voltage swing
Maximum input current
Inverting voltage Gain
7
1
IIN
mA
dB
G
VOUT/VIN
OSCILLATOR
Nominal, Master Mode
AM1, Master Mode
3.45
2.85
2.58
1.86
3.6
3
3.75
3.15
2.82
(1)
fOSC(IO+)
FPWM × 6
MHz
AM2, Master Mode
2.7
VIH
VIL
High level input voltage
Low level input voltage
V
V
1.45
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS)
65
65
mΩ
mΩ
TJ = 25°C, Includes metallization resistance,
GVDD = 12 V
RDS(on)
Drain-to-source resistance, high side (HS)
I/O PROTECTION
Undervoltage protection limit, GVDD_x and
VDD
Vuvp,VDD,GVDD
8.6
V
(2)
Vuvp,VDD, GVDD,hyst
Vuvp,PVDD
0.85
9.7
V
V
Undervoltage protection limit, PVDD_x
Overtemperature warning, CLIP_OTW(2)
(2)
Vuvp,PVDD,hyst
1.25
125
V
OTW
115
145
135
165
°C
Temperature drop needed below OTW
temperature for CLIP_OTW to be inactive
after OTW event.
(2)
OTWhyst
20
°C
OTE(2)
Overtemperature error
155
20
°C
°C
A reset needs to occur for FAULT to be
released following an OTE event
(2)
OTEhyst
OTE-OTW(differential)
OTE-OTW differential
30
1.7
°C
ms
A
(2)
OLPC
IOC
Overload protection counter
Overcurrent limit protection
fPWM = 600 kHz (1024 PWM cycles)
Resistor – programmable, nominal peak current in
1Ω load, ROCP = 22 kΩ
13.5
Resistor – programmable, peak current in 1Ω load,
ROCP = 47kΩ
IOC(LATCHED)
IDCspkr
Overcurrent limit protection
13.5
2
A
A
DC Speaker Protection Current Threshold
Overcurrent response time
BTL current imbalance threshold
Time from switching transition to flip-state induced
by overcurrent.
IOCT
150
ns
Connected when RESET is active to provide
bootstrap charge. Not used in SE mode.
IPD
Output pulldown current of each half
3
mA
(1) Nominal, AM1 and AM2 use same internal oscillator with fixed ratio 6 : 5 : 4.5
(2) Specified by design.
Copyright © 2016, Texas Instruments Incorporated
7
TPA3245
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
Electrical Characteristics (continued)
PVDD_X = 30 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 600 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC DIGITAL SPECIFICATIONS
VIH
VIL
Ilkg
High level input voltage
Low level input voltage
Input leakage current
1.9
V
V
M1, M2, OSC_IOP, OSC_IOM, RESET
0.8
100
μA
OTW/SHUTDOWN (FAULT)
Internal pullup resistance, CLIP_OTW to
RINT_PU
20
3
26
32
kΩ
DVDD, FAULT to DVDD
High level output voltage
Low level output voltage
CLIP_OTW, FAULT
VOH
Internal pullup resistor
IO = 4 mA
3.3
200
30
3.6
V
VOL
500
mV
Device fanout
No external pullup
devices
7.6 Audio Characteristics (BTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 30 V,
GVDD_X = 12 V, RL = 4 Ω, fS = 600 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00,
AES17 + AUX-0025 measurement filters,unless otherwise noted.
PARAMETER
TEST CONDITIONS
RL = 3 Ω, 10% THD+N
MIN
TYP MAX UNIT
145
RL = 4 Ω, 10% THD+N
RL = 3 Ω, 1% THD+N
RL = 4 Ω, 1% THD+N
1 W
115
PO
Power output per channel
W
115
95
THD+N Total harmonic distortion + noise
0.005%
A-weighted, AES17 filter, Input Capacitor
Grounded
Vn
Output integrated noise
50
μV
|VOS
|
Output offset voltage
Signal-to-noise ratio(1)
Inputs AC coupled to GND
20
112
113
0.45
60
mV
dB
dB
W
SNR
DNR
Pidle
Dynamic range
Power dissipation due to Idle losses (IPVDD_X
)
PO = 0, 4 channels switching(2)
(1) SNR is calculated relative to 1% THD+N output level.
(2) Actual system idle losses also are affected by core losses of output inductors.
8
Copyright © 2016, Texas Instruments Incorporated
TPA3245
www.ti.com.cn
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
7.7 Audio Characteristics (SE)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 30 V,
GVDD_X = 12 V, RL = 2 Ω, fS = 600 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 15 μH, CDEM = 680 nF, MODE = 11,
AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER
TEST CONDITIONS
RL = 2 Ω, 10% THD+N
MIN
TYP MAX UNIT
55
39
RL = 3 Ω, 10% THD+N
RL = 4 Ω, 10% THD+N
RL = 2 Ω, 1% THD+N
RL = 3 Ω, 1% THD+N
RL = 4 Ω, 1% THD+N
1 W
30
PO
Power output per channel
W
44
32
25
THD+N Total harmonic distortion + noise
0.01%
A-weighted, AES17 filter, Input Capacitor
Grounded
Vn
Output integrated noise
100
μV
SNR
DNR
Pidle
Signal to noise ratio(1)
A-weighted
106
101
dB
dB
W
Dynamic range
A-weighted
PO = 0, 4 channels switching(2)
Power dissipation due to idle losses (IPVDD_X)
0.45
(1) SNR is calculated relative to 1% THD+N output level.
(2) Actual system idle losses are affected by core losses of output inductors.
7.8 Audio Characteristics (PBTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 30 V,
GVDD_X = 12 V, RL = 2 Ω, fS = 600 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, MODE = 10,
outputs paralleled before LC filter, AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER
TEST CONDITIONS
RL = 2 Ω, 10% THD+N
MIN
TYP MAX UNIT
230
160
RL = 3 Ω, 10% THD+N
RL = 4 Ω, 10% THD+N
RL = 2 Ω, 1% THD+N
RL = 3 Ω, 1% THD+N
RL = 4 Ω, 1% THD+N
1 W
125
W
PO
Power output per channel
185
130
100
THD+N Total harmonic distortion + noise
0.005%
A-weighted, AES17 filter, Input Capacitor
Grounded
Vn
Output integrated noise
45
μV
SNR
DNR
Pidle
Signal to noise ratio(1)
A-weighted
113
113
dB
dB
W
Dynamic range
A-weighted
PO = 0, 4 channels switching(2)
Power dissipation due to idle losses (IPVDD_X)
0.45
(1) SNR is calculated relative to 1% THD+N output level.
(2) Actual system idle losses are affected by core losses of output inductors.
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7.9 Typical Characteristics, BTL Configuration
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 30 V, GVDD_X = 12 V, RL = 4 Ω, fS = 600 kHz, ROC = 22 kΩ,
TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00, AES17 + AUX-0025 measurement filters,unless otherwise
noted.
10
1
10
1
TC = 75èC
1W
20W
60W
TC = 75èC
1W
20W
60W
0.1
0.01
0.1
0.01
0.001
0.0003
20
100
1k
10k 20k
0.001
f - Frequency - Hz
D001
20
100
1k
10k
40k
RL = 4 Ω
P = 1W, 20W, 60W
TC = 75°C
f - Frequency - Hz
D002
RL = 4 Ω
P = 1W, 20W, 60W
TC = 75°C
AUX-0025 filter, 80 kHz analyzer BW
图 1. Total Harmonic Distortion+Noise vs Frequency
图 2. Total Harmonic Distortion+Noise vs Frequency
175
10
3W
4W
8W
3W
4W
8W
150
125
100
75
1
0.1
50
0.01
25
THD+N = 10%
TC = 75èC
TC = 75èC
0
0.001
10
15
20
25
30
33
10m
100m
1
10
100 200
PVDD - Supply Voltage - V
Po - Output Power - W
D004
D003
RL = 3 Ω, 4 Ω, 8 Ω
THD+N = 10%
TC = 75°C
RL = 3 Ω, 4 Ω, 8 Ω
TC = 75°C
图 4. Output Power vs Supply Voltage
图 3. Total Harmonic Distortion + Noise vs Output Power
140
100
10
1
3W
3W
4W
8W
4W
120
8W
100
80
60
40
20
THD+N = 1%
TC = 75èC
TC = 75èC
0
10
15
20
25
30
33
10m
100m
1
10
100
400
PVDD - Supply Voltage - V
2 Channel Output Power - W
D005
D006
RL = 3 Ω, 4 Ω, 8 Ω
THD+N = 1%
TC = 75°C
RL = 3 Ω, 4 Ω, 8 Ω
THD+N = 10%
TC = 75°C
图 5. Output Power vs Supply Voltage
图 6. System Efficiency vs Output Power
10
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ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
Typical Characteristics, BTL Configuration (接下页)
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 30 V, GVDD_X = 12 V, RL = 4 Ω, fS = 600 kHz, ROC = 22 kΩ,
TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00, AES17 + AUX-0025 measurement filters,unless otherwise
noted.
45
30
15
0
175
150
125
100
75
3W
4W
8W
50
3W
4W
8W
25
TC = 75èC
THD+N = 10%
75 100
0
0
100
200
300
0
25
50
2 Channel Output Power - W
TC - Case Temperature - èC
D007
D008
RL = 3 Ω, 4 Ω, 8 Ω
THD+N = 10%
TC = 75°C
RL = 3 Ω, 4 Ω, 8 Ω
THD+N = 10%
TC = 75°C
图 7. System Power Loss vs Output Power
图 8. Output Power vs Case Temperature
0
TC = 75èC
4W
Vref = 21.21 V
FFT size = 16384
-20
-40
-60
-80
-100
-120
-140
-160
0
5k
10k
15k
20k
24k
f - Frequency - Hz
D009
4 Ω, VREF = 21.21 V (1% Output power)
FFT = 16384
TC = 75°C
AUX-0025 filter, 80 kHz analyzer BW
图 9. Noise Amplitude vs Frequency
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7.10 Typical Characteristics, SE Configuration
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 30 V, GVDD_X = 12 V, RL = 3 Ω, fS = 600 kHz, ROC = 22 kΩ,
TC = 75°C, Output Filter: LDEM = 15 μH, CDEM = 680 nF, MODE = 11, AES17 + AUX-0025 measurement filters, unless
otherwise noted.
10
1
10
1
TC = 75èC
1W
5W
20W
2W
3W
4W
0.1
0.1
0.01
0.01
TC = 75èC
0.001
0.001
20
100
1k
10k 20k
10m
RL = 2Ω, 3Ω, 4Ω
100m
1
10
100
f - Frequency - Hz
D011
Po - Output Power - W
D010
RL = 3Ω
P = 1W, 5W, 20W
TC = 75°C
TC = 75°C
图 11. Total Harmonic Distortion+Noise vs Frequency
图 10. Total Harmonic Distortion+Noise vs Output Power
75
10
2W
3W
4W
TC = 75èC
1W
5W
20W
60
1
0.1
45
30
15
0.01
THD+N = 10%
TC = 75èC
0
10
15
20
25
30
33
0.001
PVDD - Supply Voltage - V
D013
20
100
1k
10k 20k
RL = 2Ω, 3Ω, 4Ω
THD+N = 10%
TC = 75°C
f - Frequency - Hz
D012
RL = 3Ω
P = 1W, 5W, 20W
TC = 75°C
AUX-0025 filter, 80 kHz analyzer BW
图 13. Output Power vs Supply Voltage
图 12. Total Harmonic Distortion+Noise vs Frequency
50
60
50
40
30
20
10
0
2W
3W
4W
40
30
20
10
2W
3W
4W
THD+N = 1%
TC = 75èC
THD+N = 10%
75 100
0
10
15
20
25
30
33
0
25
50
PVDD - Supply Voltage - V
TC - Case Temperature - èC
D014
D015
RL = 2Ω, 3Ω, 4Ω
THD+N = 1%
TC = 75°C
RL = 2Ω, 3Ω, 4Ω
THD+N = 10%
TC = 75°C
图 14. Output Power vs Supply Voltage
图 15. Output Power vs Case Temperature
12
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ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
7.11 Typical Characteristics, PBTL Configuration
All Measurements taken at audio frequency = 1kHz, PVDD_X = 30
V, GVDD_X = 12V, RL = 2Ω, fS = 600 kHz, ROC = 22kΩ, TC = 75°C, Output Filter: LDEM = 10μH, CDEM = 1 µF, MODE = 10,
outputs paralleled before LC filter, AES17 + AUX-0025 measurement filters, unless otherwise noted.
10
1
10
1
TC = 75èC
1W
40W
120W
2W
3W
4W
0.1
0.01
0.1
0.01
0.001
TC = 75èC
0.001
0.0004
10m
100m
1
10
100 300
20
100
1k
10k 20k
Po - Output Power - W
f - Frequency - Hz
D016
D017
RL = 2Ω, 3Ω, 4Ω
TC = 75°C
RL = 2Ω
P = 1W, 40W, 120W
TC = 75°C
图 16. Total Harmonic Distortion+Noise vs Output Power
图 17. Total Harmonic Distortion+Noise vs Frequency
260
10
2W
240
TC = 75èC
1W
3W
4W
40W
120W
220
200
180
160
140
120
100
80
1
0.1
60
0.01
40
THD+N = 10%
TC = 75èC
20
0
0.001
10
15
20
25
30
33
20
100
1k
10k
40k
PVDD - Supply Voltage - V
f - Frequency - Hz
D019
D018
RL = 2Ω, 3Ω, 4Ω
THD+N = 10%
TC = 75°C
RL = 2Ω
P = 1W, 40W, 120W
TC = 75°C
AUX-0025 filter, 80 kHz analyzer BW
图 19. Output Power vs Supply Voltage
图 18. Total Harmonic Distortion+Noise vs Frequency
220
250
200
150
100
50
2W
200
3W
4W
180
160
140
120
100
80
60
40
2W
3W
4W
THD+N = 1%
TC = 75èC
20
THD+N = 10%
75 100
0
10
0
15
20
25
30
33
0
25
50
PVDD - Supply Voltage - V
TC - Case Temperature - èC
D020
D021
RL = 2Ω, 3Ω, 4Ω
THD+N = 1%
TC = 75°C
RL = 2Ω, 3Ω, 4Ω
THD+N = 10%
TC = 75°C
图 20. Output Power vs Supply Voltage
图 21. Output Power vs Case Temperature
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8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Recommended Operating Conditions
and Typical Characteristics, BTL Configuration sections.
Most audio analyzers will not give correct readings of Class-D amplifiers’ performance due to their sensitivity to
out of band noise present at the amplifier output. AES-17 + AUX-0025 pre-analyzer filters are recommended to
use for Class-D amplifier measurements. In absence of such filters, a 30-kHz low-pass filter (10 Ω + 47 nF) can
be used to reduce the out of band noise remaining on the amplifier outputs.
9 Detailed Description
9.1 Overview
To facilitate system design, the TPA3245 needs only a 12-V supply in addition to the (typical) 30-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry, AVDD and DVDD. Additionally, all circuitry requiring a floating voltage supply, that is, the high-side gate
drive, is accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
The audio signal path including gate drive and output stage is designed as identical, independent half-bridges.
For this reason, each half-bridge has separate bootstrap pins (BST_X). Power-stage supply pins (PVDD_X) and
gate drive supply pins (GVDD_X) are separate for each full bridge. Although supplied from the same 12-V
source, separating to GVDD_AB, GVDD_CD, and VDD on the printed-circuit board (PCB) by RC filters (see
application diagram for details) is recommended. These RC filters provide the recommended high-frequency
isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as
possible. In general, the physical loop with the power supply pins, decoupling capacitors and GND return path to
the device pins must be kept as short as possible and with as little area as possible to minimize induction (see
reference board documentation for additional information).
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. It is recommended to use 33-
nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33nF capacitors ensure sufficient
energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully
turned on during the remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each full-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X node is
decoupled with 1-μF ceramic capacitor placed as close as possible to the supply pins. It is recommended to
follow the PCB layout of the TPA3245 reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 30-V power-
stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical
as facilitated by the internal power-on-reset circuit, but it is recommended to release RESET after the power
supply is settled for minimum turn on audible artefacts. Moreover, the TPA3245 is fully protected against
erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-
critical within the specified range (see the Recommended Operating Conditions table of this data sheet).
14
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TPA3245
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ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
9.2 Functional Block Diagrams
/CLIP_OTW
VDD
VBG
POWER-
UP
RESET
VREG
AVDD
DVDD
GND
/FAULT
UVP
M1
M2
TEMP
SENSE
GND
GVDD_AB
GVDD_CD
/RESET
DIFFOC
CB3C
STARTUP
CONTROL
C_START
OVER-LOAD
PROTECTIO
N
CURRENT
SENSE
OC_ADJ
OSC_IOM
OSCILLATO
OSC_IOP
PVDD_X
OUT_X
GND
R
PPSC
FREQ_ADJ
GVDD_AB
BST_A
PWM
ACTIVITY
DETECTOR
PVDD_AB
OUT_A
-
PWM
RECEIVER
TIMING
CONTROL
ANALOG
INPUT_A
CONTROL
GATE-DRIVE
GATE-DRIVE
GATE-DRIVE
GATE-DRIVE
+
LOOP
FILTER
GND
GVDD_AB
BST_B
PVDD_AB
OUT_B
-
PWM
RECEIVER
TIMING
CONTROL
ANALOG
LOOP
FILTER
INPUT_B
INPUT_C
INPUT_D
CONTROL
CONTROL
CONTROL
+
GND
GVDD_CD
BST_C
PVDD_CD
OUT_C
GND
-
PWM
RECEIVER
TIMING
CONTROL
ANALOG
LOOP
FILTER
+
GVDD_CD
BST_D
PVDD_CD
OUT_D
GND
-
PWM
RECEIVER
TIMING
CONTROL
ANALOG
LOOP
+
FILTER
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Functional Block Diagrams (接下页)
Capacitor for
External
Filtering
and
Startup/Stop
System
microcontroller or
Analog circuitry
BST_A
BST_B
OSC_IOP
OSC_IOM
Oscillator
Synchronization
Bootstrap
Capacitors
2nd Order
L-C Output
Filter for
Each
OUT_A
OUT_B
Output
H-Bridge 1
INPUT_A
Input DC
Blocking
Caps
ANALOG_IN_A
ANALOG_IN_B
Input
H-Bridge 1
INPUT_B
H-Bridge
2-CHANNEL
H-BRIDGE
BTL MODE
Hardwire PWM
Frame Adjust and
Master/Slave
Mode
FREQ_ADJ
2nd Order
L-C Output
Filter for
Each
OUT_C
OUT_D
INPUT_C
INPUT_D
Input DC
Blocking
Caps
ANALOG_IN_C
ANALOG_IN_D
Input
H-Bridge 2
Output
H-Bridge 2
H-Bridge
BST_C
BST_D
M1
M2
Hardwire
Mode
Control
Bootstrap
Capacitors
GVDD, VDD,
DVDD and
AVDD
Power Supply
Decoupling
Hardwire
PVDD
GND
PVDD
Power Supply
Decoupling
30V
Over-
Current
Limit
SYSTEM
Power
Supplies
GND
12V
GVDD (12V)/VDD (12V)
VAC
*NOTE1: Logic AND in or outside microcontroller
Copyright © 2016, Texas Instruments Incorporated
图 22. System Block Diagram
16
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TPA3245
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ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
9.3 Feature Description
9.3.1 Error Reporting
The FAULT, and CLIP_OTW, pins are active-low, open-drain outputs. The function is for protection-mode
signaling to a system-control device.
Any fault resulting in device shutdown is signaled by the FAULT pin going low. Also, CLIP_OTW goes low when
the device junction temperature exceeds 125°C (see 表 2).
表 2. Error Reporting
FAULT
CLIP_OTW
DESCRIPTION
Overtemperature (OTE) or overload (OLP) or undervoltage (UVP) Junction
temperature higher than 125°C (overtemperature warning)
0
0
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 125°C
(overtemperature warning)
0
0
0
1
1
1
0
1
Overload (OLP) or undervoltage (UVP). Junction temperature lower than 125°C
Junction temperature higher than 125°C (overtemperature warning)
Junction temperature lower than 125°C and no OLP or UVP faults (normal operation)
Note that asserting RESET low forces the FAULT signal high, independent of faults being present. TI
recommends monitoring the CLIP_OTW signal using the system microcontroller and responding to an
overtemperature warning signal by turning down the volume to prevent further heating of the device resulting in
device shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT and
CLIP_OTW outputs.
9.4 Device Protection System
The TPA3245 contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TPA3245 responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In situations other
than overload and overtemperature error (OTE), the device automatically recovers when the fault condition has
been removed, that is, the supply voltage has increased.
The device will handle errors, as shown in 表 3.
表 3. Device Protection
BTL MODE
PBTL MODE
SE MODE
LOCAL
ERROR IN
LOCAL
ERROR IN
LOCAL
ERROR IN
TURNS OFF
TURNS OFF
TURNS OFF
A
B
C
D
A
B
C
D
A
B
C
D
A+B
A+B
A+B+C+D
C+D
C+D
Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge (non-latching,
does not assert FAULT).
9.4.1 Overload and Short Circuit Current Protection
TPA3245 has fast reacting current sensors with a programmable trip threshold (OC threshold) on all high-side
and low-side FETs. To prevent output current from increasing beyond the programmed threshold, TPA3245 has
the option of either limiting the output current for each switching cycle (Cycle By Cycle Current Control, CB3C) or
to perform an immediate shutdown of the output in case of excess output current (Latching Shutdown). CB3C
prevents premature shutdown due to high output current transients caused by high level music transients and a
drop of real speaker’s load impedance, and allows the output current to be limited to a maximum programmed
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level. If the maximum output current persists, i.e. the power stage being overloaded with too low load impedance,
the device will shut down the affected output channel and the affected output is put in a high-impedance (Hi- Z)
state until a RESET cycle is initiated. CB3C works individually for each half bridge output. If an over current
event is triggered, CB3C performs a state flip of the half bridge output that is cleared upon beginning of next
PWM frame.
PWM_X
RISING EDGE PWM
SETS CB3C LATCH
HS PWM
LS PWM
OC EVENT RESETS
CB3C LATCH
OC THRESHOLD
OUTPUT CURRENT
OCH
HS GATE-DRIVE
LS GATE-DRIVE
图 23. CB3C Timing Example
During CB3C an over load counter increments for each over current event and decrease for each non-over
current PWM cycle. This allows full amplitude transients into a low speaker impedance without a shutdown
protection action. In the event of a short circuit condition, the over current protection limits the output current by
the CB3C operation and eventually shut down the affected output if the overload counter reaches its maximum
value. If a latched OC operation is required such that the device shuts down the affected output immediately
upon first detected over current event, this protection mode should be selected. The over current threshold and
mode (CB3C or Latched OC) is programmed by the OC_ADJ resistor value. The OC_ADJ resistor needs to be
within its intentional value range for either CB3C operation or Latched OC operation.
I_OC
IOC_max
IOC_min
Not Defined
ROC_ADJ
图 24. OC Threshold versus OC ADJ Resistor Value Example
OC_ADJ values outside specified value range for either CB3C or latched OC operation will result in minimum OC
threshold.
18
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TPA3245
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ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
表 4. Device Protection
OC_ADJ Resistor Value
Protection Mode
CB3C
OC Threshold
13.5A
22kΩ
24kΩ
27kΩ
30kΩ
47kΩ
51kΩ
56kΩ
64kΩ
CB3C
12.5A
CB3C
11.3A
CB3C
10.3A
Latched OC
Latched OC
Latched OC
Latched OC
13.5A
12.5A
11.3A
10.3A
9.4.2 Signal Clipping and Pulse Injector
A built in activity detector monitors the PWM activity of the OUT_X pins. TPA3245 is designed to drive
unclipped output signals all the way to PVDD and GND rails. In case of audio signal clipping when applying
excessive input signal voltage, or in case of CB3C current protection being active, the amplifier feedback
loop of the audio channel will respond to this condition with a saturated state, and the output PWM signals
will stop unless special circuitry is implemented to handle this situation. To prevent the output PWM signals
from stopping in a clipping or CB3C situation, narrow pulses are injejcted to the gate drive to maintain output
activity. The injected narrow pulses are injected at every 4th PWM frame, and thus the effective switching
frequency during this state is reduced to 1/4 of the normal switching frequency.
Signal clipping is signalled on the CLIP_OTW pin and is self clearing when signal level reduces and the
device reverts to normal operation. The CLIP_OTW pulses starts at the onset to output clipping, typically at a
THD level around 0.01%, resulting in narrow CLIP_OTW pulses starting with a pulse width of ~500ns.
图 25. Signal Clipping PWM and Speaker Output Signals
9.4.3 DC Speaker Protection
The output DC protection scheme protects a speaker from excess DC current in case one terminal of the
speaker is connected to the amplifier while the other is accidentally shorted to the chassis ground. Such a short
circuit results in a DC voltage of PVDD/2 across the speaker, which potentially can result in destructive current
levels. The output DC protection detects any unbalance of the output and input current of a BTL output, and in
the event of the unbalance exceeding a programmed threshold, the overload counter increments until its
maximum value and the affected output channel is shut down. DC Speaker Protection is disabled in PBTL and
SE mode operation.
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9.4.4 Pin-to-Pin Short Circuit Protection (PPSC)
The PPSC detection system protects the device from permanent damage in the case that a power output pin
(OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent
after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup i.e. when VDD is supplied, consequently a short to either GND_X or PVDD_X after system
startup does not activate the PPSC detection system. When PPSC detection is activated by a short on the
output, all half bridges are kept in a Hi-Z state until the short is removed; the device then continues the startup
sequence and starts switching. The detection is controlled globally by a two step sequence. The first step
ensures that there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from
OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC
filter. The typical duration is < 15 ms/μF. While the PPSC detection is in progress, FAULT is kept low, and the
device will not react to changes applied to the RESET pin. If no shorts are present the PPSC detection passes,
and FAULT is released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL
and PBTL output configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC
detection system it is recommended not to insert a resistive load to GND_X or PVDD_X.
9.4.5 Overtemperature Protection OTW and OTE
TPA3245 has a two-level temperature-protection system that asserts an active-low warning signal (CLIP_OTW)
when the device junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds
155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-
impedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To clear the OTE latch,
RESET must be asserted. Thereafter, the device resumes normal operation.
9.4.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
The UVP and POR circuits of the TPA3255 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit ensures that all circuits are fully operational when the GVDD_X and VDD
supply voltages reach values stated in the Electrical Characteristics table. Although GVDD_X and VDD are
independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in
all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low.
The device automatically resumes operation when all supply voltages have increased above the UVP threshold.
20
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TPA3245
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ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
9.4.7 Fault Handling
If a fault situation occurs while in operation, the device acts accordingly to the fault being a global or a channel
fault. A global fault is a chip-wide fault situation and causes all PWM activity of the device to be shut down, and
will assert FAULT low. A global fault is a latching fault and clearing FAULT and restarting operation requires
resetting the device by toggling RESET. Deasserting RESET should never be allowed with excessive system
temperature, so it is advised to monitor RESET by a system microcontroller and only allow releasing RESET
(RESET high) if the CLIP_OTW signal is cleared (high). A channel fault results in shutdown of the PWM activity
of the affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults
being present.
表 5. Error Reporting
Fault/Event
Description
Global or
Channel
Reporting
Method
Latched/Self
Clearing
Action needed
to Clear
Fault/Event
Output FETs
HI-Z
PVDD_X UVP
VDD UVP
Increase affected
supply voltage
Voltage Fault
Global
FAULT pin
Self Clearing
AVDD UVP
Allow DVDD to
rise
POR (DVDD UVP)
Power On Reset Global
FAULT pin
None
Self Clearing
Self Clearing
Self Clearing
HI-Z
Allow BST cap to
recharge (lowside HighSide off
ON, VDD 12V)
Channel (Half
Bridge)
BST_X UVP
Voltage Fault
Cool below OTW
threshold
OTW
OTE
Thermal Warning Global
OTW pin
Normal operation
Thermal
Global
FAULT pin
FAULT pin
Latched
Latched
Toggle RESET
Toggle RESET
HI-Z
HI-Z
Shutdown
OLP (CB3C>1.7ms) OC Shutdown
Channel
Channel
Latched OC
(47kΩ<ROC_ADJ<68 OC Shutdown
kΩ)
FAULT pin
None
Latched
Toggle RESET
HI-Z
CB3C
Reduce signal
level or remove
short
Flip state, cycle
by cycle at fs/3
(22kΩ<ROC_ADJ<30 OC Limiting
kΩ)
Channel
Global
Self Clearing
Self Clearing
No OSC_IO
activity in Slave
Mode
Resume OSC_IO
activity
Stuck at Fault(1)
None
HI-Z
(1) Stuck at Fault occurs when input OSC_IO input signal frequency drops below minimum frequency given in the Electrical Characteristics
table of this data sheet.
9.4.8 Device Reset
Asserting RESET low initiates the device ramp down. The output FETs go into a Hi-Z state after the ramp down
is complete. Output pull downs are active both in SE mode and BTL mode with RESET low.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs.
Asserting reset input low removes any fault information to be signaled on the FAULT output, that is, FAULT is
forced high. A rising-edge transition on reset input allows the device to resume operation after a fault. To ensure
thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of FAULT.
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ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
TPA3245 can be configured either in stereo BTL mode, 4 channel SE mode, mono PBTL mode, or in 2.1 mixed
1x BTL + 2x SE mode depending on output power conditions and system design.
10.2 Typical Applications
10.2.1 Stereo BTL Application
This section provides an example for configuring the TPA3245 in bridge-tied load (BTL) mode.
3R3
+12V
470uF
100nF
100nF
33nF
1
2
3
4
5
6
7
8
9
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
GVDD_AB
VDD
BST_A
BST_B
GND
10µH
10nF
33nF
M1
1nF
1nF
1µF
1µF
M2
GND
3w3
10µF
10µF
INPUT_A
INPUT_B
INPUT_A
INPUT_B
OC_ADJ
FREQ_ADJ
OSC_IOM
OSC_IOP
DVDD
OUT_A
OUT_A
PVDD_AB
PVDD_AB
PVDD_AB
OUT_B
GND
3R3
22k
10nF
1µF
10µH
10k
470uF
PVDD
GND
10
11
12
13
14
15
16
17
18
19
1µF
1µF
1µF
TPA3245
GND
GND
GND
OUT_C
PVDD_CD
PVDD_CD
PVDD_CD
OUT_D
OUT_D
GND
1µF
AVDD
10µH
10nF
C_START
INPUT_C
INPUT_D
/RESET
/FAULT
VBG
1µF 470uF
10nF
10µF
10µF
INPUT_C
INPUT_D
/RESET
/FAULT
1nF
1nF
1µF
1µF
3w3
26
25
24
23
3R3
100nF
20
21
22
10nF
GND
33nF
10µH
/CLIP_OTW
/CLIP_OTW
GVDD_CD
BST_C
BST_D
3R3
100nF
33nF
/opyright © 2016, Çexas Lnstruments Lncorporated
图 26. Typical Differential (2N) BTL Application
22
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ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
Typical Applications (接下页)
10.2.1.1 Design Requirements
For this design example, use the parameters in 表 6.
表 6. Design Requirements, BTL Application
DESIGN PARAMETER
Low Power (Pull-up) Supply
Mid Power Supply 12 V
High Power Supply
EXAMPLE
3.3 V
12 V
12 - 30 V
M2 = L
Mode Selection
M1 = L
INPUT_A = ±3.9 V (peak, max)
INPUT_B = ± 3.9V (peak, max)
INPUT_C = ±3.9 V (peak, max)
INPUT_D = ±3.9 V (peak, max)
Inductor-Capacitor Low Pass FIlter (10 µH + 1 µF)
3-8 Ω
Analog Inputs
Output Filters
Speaker Impedance
10.2.1.2 Detailed Design Procedures
A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.
The CLIP signal is indicating that the output is approaching clipping. The signal can be used either to decrease
audio volume or to control an intelligent power supply nominally operating at a low rail adjusting to a higher
supply rail.
The device is inverting the audio signal from input to output.
The DVDD and AVDD pins are not recommended to be used as a voltage sources for external circuitry.
10.2.1.2.1 Decoupling Capacitor Recommendations
In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
10.2.1.2.2 PVDD Capacitor Recommendation
The PVDD decoupling capacitors must be placed as close to the device pins a possible to insure short trace
length and low a low inductance path. Likewise the ground path for these capacitors must provide a good
reference and should be substantial. This will keep voltage ringing on PVDD to a minimum.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 1μF that is placed on the power supply to each full-bridge. It must withstand the voltage
overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple
current created by high power output. A minimum voltage rating of 50 V is required for use with a 30V power
supply.
The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 1000 μF, 50 V supports most applications.
The PVDD capacitors should be low ESR type because they are used in a circuit associated with high-speed
switching.
10.2.1.2.3 PCB Material Recommendation
FR-4 Glass Epoxy material with 2 oz. (70 μm) copper is recommended for use with the TPA3245. The use of this
material can provide for higher power output, improved thermal performance, and better EMI margin (due to
lower PCB trace inductance.
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10.2.1.2.4 Oscillator
The built in oscillator frequency can be trimmed by an external resistor from the FREQ_ADJ pin to GND.
Changes in the oscillator frequency should be made with resistor values specified in Recommended Operating
Conditions while RESET is low.
To reduce interference problems while using a radio receiver tuned within the AM band, the switching frequency
can be changed from nominal to lower or higher values. These values should be chosen such that the nominal
and the alternate switching frequencies together result in the fewest cases of interference throughout the AM
band. The oscillator frequency can be selected by the value of the FREQ_ADJ resistor connected to GND in
master mode.
For slave mode operation, turn off the oscillator by pulling the FREQ_ADJ pin to DVDD. This configures the
OSC_I/O pins as inputs to be slaved from an external differential clock. In a master/slave system inter-channel
delay is automatically set up between the switching of the audio channels, which can be illustrated by no idle
channels switching at the same time. This will not influence the audio output, but only the switch timing to
minimize noise coupling between audio channels through the power supply. Inter-channel delay is needed to
optimize audio performance and to get better operating conditions for the power supply. The inter-channel delay
will be set up for a slave device depending on the polarity of the OSC_I/O connection as follows:
•
•
Slave 1 mode has normal polarity (master + to slave + and master - to slave -)
Slave 2 mode has reverse polarity (master + to slave - and master - to slave +)
The interchannel delay for interleaved channel idle switching is given in the table below for the master/slave and
output configuration modes in degrees relative to the PWM frame.
表 7. Master/Slave Inter Channel Delay Settings
Master
M1 = 0, M2 = 0, 2 x M1 = 1, M2 = 0, 1 x M1 = 0, M2 = 1, 1 x M1 = 1, M2 = 1, 4 x
BTL mode
BTL + 2 x SE
mode
PBTL mode
SE mode
OUT_A
OUT_B
OUT_C
OUT_D
Slave 1
OUT_A
OUT_B
OUT_C
OUT_D
Slave 2
OUT_A
OUT_B
OUT_C
OUT_D
0°
0°
0°
180°
0°
0°
60°
0°
180°
60°
180°
60°
240°
120°
180°
60°
60°
60°
60°
240°
60°
60°
120°
60°
240°
120°
300°
240°
120°
180°
240°
120°
30°
210°
90°
30°
210°
90°
30°
210°
30°
30°
90°
30°
90°
270°
150°
210°
24
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TPA3245
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ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
10.2.2 Application Curves
Relevant performance plots for TPA3245 in BTL configuration are shown in Typical Characteristics, BTL
Configuration
表 8. Relevant Performance Plots, BTL Configuration
PLOT TITLE
Total Harmonic Distortion+Noise vs Frequency
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW
Total Harmonic Distortion + Noise vs Output Power
Output Power vs Supply Voltage, 10% THD+N
Output Power vs Supply Voltage, 10% THD+N
System Efficiency vs Output Power
FIGURE NUMBER
图 1
图 2
图 3
图 4
图 6
图 6
图 7
图 8
图 9
System Power Loss vs Output Power
Output Power vs Case Temperature
Noise Amplitude vs Frequency
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ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
10.2.3 Typical Application, Single Ended (1N) SE
This section provides an example for configuring the TPA3245 in single-ended output (SE) mode.
470uF
15µH
3R3
+12V
470uF
100nF
100nF
33nF
1
2
3
4
5
6
7
8
9
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
10nF
GVDD_AB
VDD
BST_A
BST_B
GND
1nF
1nF
680nF
680nF
3w3
33nF
M1
M2
GND
3R3
10µF
10µF
INPUT_A
INPUT_B
INPUT_A
INPUT_B
OC_ADJ
FREQ_ADJ
OSC_IOM
OSC_IOP
DVDD
OUT_A
OUT_A
PVDD_AB
PVDD_AB
PVDD_AB
OUT_B
GND
10nF
22k
1µF
470uF
15µH
10k
470uF
PVDD
GND
10
11
12
13
14
15
16
17
18
19
1µF
1µF
1µF
TPA3245
GND
GND
GND
OUT_C
PVDD_CD
PVDD_CD
PVDD_CD
OUT_D
OUT_D
GND
1µF
AVDD
470uF
15µH
470nF
C_START
INPUT_C
INPUT_D
/RESET
/FAULT
VBG
1µF 470uF
10µF
10µF
INPUT_C
INPUT_D
/RESET
/FAULT
10nF
1nF
1nF
680nF
680nF
26
25
24
23
3w3
100nF
20
21
22
GND
33nF
3R3
/CLIP_OTW
/CLIP_OTW
GVDD_CD
BST_C
BST_D
10nF
3R3
100nF
33nF
470uF
15µH
/opyright © 2016, Çexas Lnstruments Lncorporated
图 27. Typical Single Ended (1N) SE Application
10.2.3.1 Design Requirements
Refer to Stereo BTL Application for the Design Requirements.
表 9. Design Requirements, SE Application
DESIGN PARAMETER
Low Power (Pull-up) Supply
Mid Power Supply 1 2V
High Power Supply
EXAMPLE
3.3 V
12 V
12 - 30 V
M2 = H
M1 = H
Mode Selection
INPUT_A = ±3.9 V (peak, max)
INPUT_B = ±3.9 V (peak, max)
INPUT_C = ±3.9 V (peak, max)
INPUT_D = ±3.9 V (peak, max)
Inductor-Capacitor Low Pass FIlter (15 µH + 680 nF)
2 - 8 Ω
Analog Inputs
Output Filters
Speaker Impedance
10.2.3.2 Detailed Design Procedures
Refer to Stereo BTL Application for the Detailed Design Procedures.
26
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TPA3245
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ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
10.2.3.3 Application Curves
Relevant performance plots for TPA3245 in PBTL configuration are shown in Typical Characteristics, SE
Configuration
表 10. Relevant Performance Plots, SE Configuration
PLOT TITLE
FIGURE NUMBER
图 10
Total Harmonic Distortion+Noise vs Output Power
Total Harmonic Distortion+Noise vs Frequency
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW
Output Power vs Supply Voltage, 10% THD+N
Output Power vs Supply Voltage, 1% THD+N
Output Power vs Case Temperature
图 11
图 12
图 13
图 14
图 15
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TPA3245
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
10.2.4 Typical Application, Differential (2N), PBTL (Outputs Paralleled before LC filter)
TPA3245 can be configured in mono PBTL mode by paralleling the outputs before the LC filter or after the LC
filter (seeTypical Application, Differential (2N), PBTL (Outputs Paralleled after LC filter)). Paralleled outputs
before the LC filter is recommended for better performance and limiting the number of output LC filter inductors,
only two inductors required. This sections shows an example of paralleled outputs before the LC filter.
3R3
+12V
470uF
100nF
100nF
33nF
1
2
3
4
5
6
7
8
9
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
GVDD_AB
VDD
BST_A
BST_B
GND
33nF
M1
M2
GND
10µF
10µF
INPUT_A
INPUT_B
INPUT_A
INPUT_B
OC_ADJ
FREQ_ADJ
OSC_IOM
OSC_IOP
DVDD
OUT_A
OUT_A
PVDD_AB
PVDD_AB
PVDD_AB
OUT_B
GND
22k
PVDD
1µF
30k
10µH
470uF
10nF
1nF
1nF
10
11
12
13
14
15
16
17
18
19
470nF
470nF
470nF
470nF
1µF
1µF
1µF
3w3
TPA3245
GND
GND
3R3
GND
OUT_C
PVDD_CD
PVDD_CD
PVDD_CD
OUT_D
OUT_D
GND
10nF
1µF
10µH
AVDD
47nF
C_START
INPUT_C
INPUT_D
/RESET
/FAULT
VBG
1µF 470uF
GND
/RESET
/FAULT
26
25
24
23
1µF
20
21
22
GND
33nF
/CLIP_OTW
/CLIP_OTW
GVDD_CD
BST_C
BST_D
3R3
100nF
33nF
Copyright © 2016, Texas Instruments Incorporated
图 28. Typical Differential (2N) PBTL (Outputs Paralleled before LC filter) Application
10.2.4.1 Design Requirements
Refer to Stereo BTL Application for the Design Requirements.
表 11. Design Requirements, PBTL (Outputs Paralleled before LC filter) Application
DESIGN PARAMETER
Low Power (Pull-up) Supply
Mid Power Supply 12 V
High Power Supply
EXAMPLE
3.3 V
12 V
12 - 30 V
M2 = H
Mode Selection
M1 = L
INPUT_A = ±3.9V (peak, max)
INPUT_B = ±3.9V (peak, max)
INPUT_C = Grounded
INPUT_D = Grounded
Inductor-Capacitor Low Pass FIlter (10 µH + 1 µF)
2 - 4 Ω
Analog Inputs
Output Filters
Speaker Impedance
10.2.4.2 Detailed Design Procedures
Refer to Stereo BTL Application for the Detailed Design Procedures.
28
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TPA3245
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ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
10.2.4.3 Application Curves
Relevant performance plots for TPA3245 in PBTL configuration are shown in Typical Characteristics, PBTL
Configuration
表 12. Relevant Performance Plots, PBTL (Outputs Paralleled before LC filter)
Configuration
PLOT TITLE
FIGURE NUMBER
图 16
Total Harmonic Distortion+Noise vs Output Power
Total Harmonic Distortion+Noise vs Frequency
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW
Output Power vs Supply Voltage, 10% THD+N
Output Power vs Supply Voltage, 1% THD+N
Output Power vs Case Temperature
图 17
图 18
图 19
图 20
图 21
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www.ti.com.cn
10.2.5 Typical Application, Differential (2N), PBTL (Outputs Paralleled after LC filter)
TPA3245 can be configured in mono PBTL mode by paralleling the outputs before the LC filter (see Typical
Application, Differential (2N), PBTL (Outputs Paralleled before LC filter)) or after the LC filter. Paralleled outputs
after the LC filter may be preferred if: a single board design must support both PBTL and BTL, or in the case
multiple, smaller paralleled inductors are preferred due to size or cost. Paralleling after the LC filter requires four
inductors, one for each OUT_x. This section shows an example of paralleled outputs after the LC filter.
3R3
+12V
470uF
100nF
100nF
33nF
1
2
3
4
5
6
7
8
9
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
GVDD_AB
VDD
BST_A
BST_B
GND
10µH
33nF
M1
M2
GND
10µF
10µF
INPUT_A
INPUT_B
INPUT_A
INPUT_B
OC_ADJ
FREQ_ADJ
OSC_IOM
OSC_IOP
DVDD
OUT_A
OUT_A
PVDD_AB
PVDD_AB
PVDD_AB
OUT_B
GND
22k
PVDD
1µF
10µH
10k
470uF
10nF
1nF
1nF
10
11
12
13
14
15
16
17
18
19
1µF
1µF
1µF
1µF
1µF
3w3
TPA3245
GND
GND
3R3
GND
OUT_C
PVDD_CD
PVDD_CD
PVDD_CD
OUT_D
OUT_D
GND
10nF
1µF
AVDD
10µH
10nF
C_START
INPUT_C
INPUT_D
/RESET
/FAULT
VBG
1µF 470uF
GND
/RESET
/FAULT
26
25
24
23
100nF
20
21
22
GND
33nF
10µH
/CLIP_OTW
/CLIP_OTW
GVDD_CD
BST_C
BST_D
3R3
100nF
33nF
/opyright © 2016, Çexas Lnstruments Lncorporated
图 29. Typical Differential (2N) PBTL (Outputs Paralleled after LC filter) Application
10.2.5.1 Design Requirements
Refer to Stereo BTL Application for the Design Requirements.
表 13. Design Requirements, PBTL (Outputs Paralleled after LC filter) Application
DESIGN PARAMETER
Low Power (Pull-up) Supply
Mid Power Supply 12 V
High Power Supply
EXAMPLE
3.3 V
12 V
12 - 30 V
M2 = H
Mode Selection
M1 = L
INPUT_A = ±3.9V (peak, max)
INPUT_B = ±3.9V (peak, max)
INPUT_C = Grounded
INPUT_D = Grounded
Inductor-Capacitor Low Pass FIlter (10 µH + 1 µF)
2 - 4 Ω
Analog Inputs
Output Filters
Speaker Impedance
10.2.5.2 Detailed Design Procedures
Refer to Stereo BTL Application for the Detailed Design Procedures.
30
版权 © 2016, Texas Instruments Incorporated
TPA3245
www.ti.com.cn
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
11 Power Supply Recommendations
11.1 Power Supplies
The TPA3245 device requires two external power supplies for proper operation. A high-voltage supply called
PVDD is required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one
mid-voltage power supply for GVDD_X and VDD is required to power the gate-drive and other internal digital and
analog portions of the device. The allowable voltage range for both the PVDD and the GVDD_X/VDD supplies
are listed in the Recommended Operating Conditions table. Ensure both the PVDD and the GVDD_X/VDD
supplies can deliver more current than listed in the Electrical Characteristics table.
11.1.1 VDD Supply
The VDD supply required from the system is used to power several portions of the device. It provides power to
internal regulators DVDD and AVDD that are used to power digital and analog sections of the device,
respectively. Proper connection, routing, and decoupling techniques are highlighted in the TPA3245 device EVM
User's Guide SLVUAG8 (as well as the Application Information section and Layout Examples section) and must
be followed as closely as possible for proper operation and performance. Deviation from the guidance offered in
the TPA3245 device EVM User's Guide, which followed the same techniques as those shown in the Application
Information section, may result in reduced performance, errant functionality, or even damage to the TPA3245
device. Some portions of the device also require a separate power supply which is a lower voltage than the VDD
supply. To simplify the power supply requirements for the system, the TPA3245 device includes integrated low-
dropout (LDO) linear regulators to create these supplies. These linear regulators are internally connected to the
VDD supply and their outputs are presented on AVDD and DVDD pins, providing a connection point for an
external bypass capacitors. It is important to note that the linear regulators integrated in the device have only
been designed to support the current requirements of the internal circuitry, and should not be used to power any
additional external circuitry. Additional loading on these pins could cause the voltage to sag and increase noise
injection, which negatively affects the performance and operation of the device.
11.1.2 GVDD_X Supply
The GVDD_X supply required from the system is used to power the gate-drives for the output H-bridges. Proper
connection, routing, and decoupling techniques are highlighted in the TPA3245 device EVM User's Guide
SLVUAG8 (as well as the Application Information section and Layout Examples section) and must be followed as
closely as possible for proper operation and performance. Deviation from the guidance offered in the TPA3245
device EVM User's Guide, which followed the same techniques as those shown in the Application Information
section, may result in reduced performance, errant functionality, or even damage to the TPA3245 device.
11.1.3 PVDD Supply
The output stage of the amplifier drives the load using the PVDD supply. This is the power supply which provides
the drive current to the load during playback. Proper connection, routing, and decoupling techniques are
highlighted in the TPA3245 device EVM User's Guide SLVUAG8 (as well as the Application Information section
and Layout Examples section) and must be followed as closely as possible for proper operation and
performance. Due the high-voltage switching of the output stage, it is particularly important to properly decouple
the output power stages in the manner described in the TPA3245 device EVM User's Guide SLVUAG8. The lack
of proper decoupling, like that shown in the EVM User's Guide, can results in voltage spikes which can damage
the device, or cause poor audio performance and device shutdown faults.
11.2 Powering Up
The TPA3245 does not require a power-up sequence, but it is recommended to hold RESET low for at least 250
ms after PVDD supply voltage is turned ON. The outputs of the H-bridges remain in a high-impedance state until
the gate-drive supply voltage (GVDD_X) and VDD voltages are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). This allows an internal circuit to charge the
external bootstrap capacitors by enabling a weak pulldown of the half-bridge output as well as initiating a
controlled ramp up sequence of the output voltage.
版权 © 2016, Texas Instruments Incorporated
31
TPA3245
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
Powering Up (接下页)
të55
ë55
Dë55
5ë55
/w9{9Ç
!ë55
/C!Ü[Ç
ëLb_ó
hÜÇ_ó
ëhÜÇ_ó
C 70µs
ꢀ
trecꢁarge
C 200ms
ꢀ
{ꢀarꢀup ramp
ë_ꢂ{Ç!wÇ
图 30. Startup Timing
When RESET is released to turn on TPA3245, FAULT signal will turn low and AVDD voltage regulator will be
enabled. FAULT will stay low until AVDD reaches the undervoltage protection (UVP) voltage threshold (see the
Electrical Characteristics table of this data sheet). After a precharge time to stabilize the DC voltage across the
input AC coupling capacitors, the ramp up sequence starts.
11.3 Powering Down
The TPA3245 does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks by
initiating a controlled ramp down sequence of the output voltage.
12 Layout
12.1 Layout Guidelines
•
Use an unbroken ground plane to have good low impedance and inductance return path to the power supply
for power and audio signals.
•
Maintain a contiguous ground plane from the ground pins to the PCB area surrounding the device for as
many of the ground pins as possible, since the ground pins are the best conductors of heat in the package.
32
版权 © 2016, Texas Instruments Incorporated
TPA3245
www.ti.com.cn
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
Layout Guidelines (接下页)
•
•
•
•
•
PCB layout, audio performance and EMI are linked closely together.
Routing the audio input should be kept short and together with the accompanied audio source ground.
The small bypass capacitors on the PVDD lines of the DUT be placed as close the PVDD pins as possible.
A local ground area underneath the device is important to keep solid to minimize ground bounce.
Orient the passive component so that the narrow end of the passive component is facing the TPA3245
device, unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads.
•
•
Avoid placing other heat producing components or structures near the TPA3245 device.
Avoid cutting off the flow of heat from the TPA3245 device to the surrounding ground areas with traces or via
strings, especially on output side of device.
Netlist for this printed circuit board is generated from the schematic in 图 31.
版权 © 2016, Texas Instruments Incorporated
33
TPA3245
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
12.2 Layout Examples
12.2.1 BTL Application Printed Circuit Board Layout Example
Ç3
Ç1
1
2
44
43
42
41
40
39
38
37
3
4
5
6
7
8
Ç2
Ç2
9
36
35
34
33
32
31
30
29
28
27
26
25
24
23
10
11
12
13
14
15
16
17
18
19
20
21
22
Ç1
Ç3
{ystem ꢀrocessor
.ottom to top layer connection via
.ottom [ayer {ignal Çraces
ꢀad to top layer ground pour
Çop [ayer {ignal Çraces
A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat
sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without
going through vias. No vias or traces should be blocking the current path.
C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
D. Note T3: Heat sink needs to have a good connection to PCB ground.
图 31. BTL Application Printed Circuit Board - Composite
34
版权 © 2016, Texas Instruments Incorporated
TPA3245
www.ti.com.cn
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
Layout Examples (接下页)
12.2.2 SE Application Printed Circuit Board Layout Example
Ç3
Ç1
1
2
44
43
42
41
40
39
38
37
3
4
5
6
7
8
Ç2
Ç2
9
36
35
34
33
32
31
30
29
28
27
26
25
24
23
10
11
12
13
14
15
16
17
18
19
20
21
22
Ç1
Ç3
{ystem ꢀrocessor
.ottom to top layer connection via
.ottom [ayer {ignal Çraces
ꢀad to top layer ground pour
Çop [ayer {ignal Çraces
A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat
sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without
going through vias. No vias or traces should be blocking the current path.
C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
D. Note T3: Heat sink needs to have a good connection to PCB ground.
图 32. SE Application Printed Circuit Board - Composite
版权 © 2016, Texas Instruments Incorporated
35
TPA3245
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
Layout Examples (接下页)
12.2.3 PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board Layout Example
Ç3
Ç1
1
2
44
43
42
41
40
39
38
37
3
4
5
6
7
8
Ç2
Ç2
9
36
35
34
33
32
31
30
29
28
27
26
25
24
23
10
11
12
13
14
15
16
17
18
19
20
21
22
Drounded for ꢀ.Ç[
Drounded for ꢀ.Ç[
Ç1
Ç3
{ystem ꢀrocessor
.ottom to top layer connection via
.ottom [ayer {ignal Çraces
ꢀad to top layer ground pour
Çop [ayer {ignal Çraces
A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat
sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without
going through vias. No vias or traces should be blocking the current path.
C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
D. ote T3: Heat sink needs to have a good connection to PCB ground.
图 33. PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board - Composite
36
版权 © 2016, Texas Instruments Incorporated
TPA3245
www.ti.com.cn
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
Layout Examples (接下页)
12.2.4 PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board Layout Example
Ç3
Ç1
1
2
44
43
42
41
40
39
38
37
3
4
5
6
7
8
Ç2
Ç2
9
36
35
34
33
32
31
30
29
28
27
26
25
24
23
10
11
12
13
14
15
16
17
18
19
20
21
22
Drounded for ꢀ.Ç[
Drounded for ꢀ.Ç[
Ç1
Ç3
{ystem ꢀrocessor
.ottom to top layer connection via
.ottom [ayer {ignal Çraces
ꢀad to top layer ground pour
Çop [ayer {ignal Çraces
A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat
sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without
going through vias. No vias or traces should be blocking the current path.
C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
D. ote T3: Heat sink needs to have a good connection to PCB ground.
图 34. PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board - Composite
版权 © 2016, Texas Instruments Incorporated
37
TPA3245
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
13 器件和文档支持
13.1 文档支持
《TPA3245EVM 用户指南》，SLVUAG8
13.2 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录
13.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 商标
PurePath, E2E are trademarks of Texas Instruments.
Blu-Ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
13.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
38
版权 © 2016, Texas Instruments Incorporated
TPA3245
www.ti.com.cn
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
14 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
39
TPA3245
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
PACKAGE OUTLINE
DDV0044D
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
2
5
0
PLASTIC SMALL OUTLINE
C
8.3
7.9
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
42X 0.635
44
1
2X (0.3)
NOTE 6
14.1
13.9
NOTE 3
2X
13.335
7.30
6.72
EXPOSED
THERMAL
PAD
(0.15) TYP
NOTE 6
2X (0.6)
NOTE 6
23
22
0.27
0.17
4.43
3.85
44X
0.08
C A B
6.2
6.0
B
(0.15) TYP
0.25
GAGE PLANE
1.2
1.0
SEE DETAIL A
0.75
0.50
0.15
0.05
0 - 8
DETAIL A
TYPICAL
4218830/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. The exposed thermal pad is designed to be attached to an external heatsink.
6. Features may differ or may not be present.
www.ti.com
40
版权 © 2016, Texas Instruments Incorporated
TPA3245
www.ti.com.cn
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
EXAMPLE BOARD LAYOUT
DDV0044D
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
SEE DETAILS
SYMM
44X (1.45)
44X (0.4)
1
44
42X (0.635)
SYMM
(R0.05) TYP
23
22
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
METAL UNDER
SOLDER MASK
SOLDER MASK
METAL
SOLDER MASK
OPENING
OPENING
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4218830/A 08/2016
NOTES: (continued)
7. Publication IPC-7351 may have alternate designs.
8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
版权 © 2016, Texas Instruments Incorporated
41
TPA3245
ZHCSFM5A –SEPTEMBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
EXAMPLE STENCIL DESIGN
DDV0044D
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
44X (1.45)
1
SYMM
44
44X (0.4)
42X (0.635)
SYMM
23
22
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE :6X
4218830/A 08/2016
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
10. Board assembly site may have different recommendations for stencil design.
www.ti.com
42
版权 © 2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPA3245DDV
ACTIVE
ACTIVE
HTSSOP
HTSSOP
DDV
DDV
44
44
35
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
0 to 70
0 to 70
3245
3245
TPA3245DDVR
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA3245DDVR
HTSSOP DDV
44
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP DDV 44
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
TPA3245DDVR
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
DDV HTSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TPA3245DDV
44
35
530
11.89
3600
4.9
Pack Materials-Page 3
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