TPD2S300YFFR [TI]

用于 CC 的 USB Type-C™ VBUS 短路和 IEC ESD 保护器 | YFF | 9 | -40 to 85;


型号：	TPD2S300YFFR
厂家：	TEXAS INSTRUMENTS
描述：	用于 CC 的 USB Type-C™ VBUS 短路和 IEC ESD 保护器 \| YFF \| 9 \| -40 to 85 接口集成电路
文件：	总37页 (文件大小：1369K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPD2S300

ZHCSGS3 –APRIL 2017

TPD2S300 用于 CC 引脚的 USB Type C VBUS 短路和 IEC ESD 保护器

1 特性

这些非理想的设备和机械事件使得 CC 引脚必须能够

承受 20V 的电压，即使它们仅在 5V 或更低电压下工

作。通过在 CC 引脚上提供过压保护，TPD2S300 可

以使 CC 引脚耐受 20V 的电压，而不会干扰正常工

作。该器件将高压 FET 串联放置在 CC 线路上。当在

这些线路上检测到高于 OVP 阈值的电压时，高压开关

被打开，从而将系统的其余部分与连接器上存在的高压

状态隔离。

•

2 通道 V_BUS短路过压保护（CC1、CC2）：可承

受 24V_DC电压

•

2 通道 IEC 61000-4-2 ESD 保护（CC1、CC2）

低静态电流：3.23µA（典型值），V_PWR、V_M=

3.3V

•

支持 200mA 电流的 CC1、CC2 过压保护 FET，

可传递 V_CONN供电

集成 CC 无电电池电阻器，可用于处理移动设备中

的无电电池用例

最后，大多数系统都需要为其外部引脚应用

IEC61000-4-2 系统级 ESD 保护。TPD2S300 为 CC1

和 CC2 引脚集成 IEC 61000-4-2 ESD 保护，因此无

需在连接器上通过外部放置高压 TVS 二极管。

1.4mm × 1.4mm WCSP 封装

2 应用

•

智能手机

器件信息⁽¹⁾

笔记本电脑

平板电脑

壁式适配器

移动电源

电钻

器件型号

封装

WCSP (9)

封装尺寸（标称值）

TPD2S300

1.40mm × 1.40mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

应用图表

3 说明

Battery

Charger

5 V œ 20 V

Battery

DC/DC

FET

OVP

TPD2S300 是一种单芯片 USB Type-C 端口保护解决

方案，可提供针对 CC1 和 CC2 引脚的 20V V_BUS短路

过压保护和 IEC ESD 保护。

5 V

FET

OVP, OCP

自从 USB Type-C 连接器发布以来，市场上已经发布

了很多不符合 USB Type-C 规格的 USB Type-C 产品

和配件。其中的一个例子就是在 V_BUS线路上提供 20V

电压的 USB Type-C 电力输送适配器。关于 USB

Type-C 的另一个问题是，由于此小型连接器中的各引

脚极为靠近，因此连接器的机械扭转和滑动可能使引脚

短路。这可能导致 20V V_BUS与 CC 引脚短路。此外，

更为严重的是，由于 Type-C 连接器中的各引脚极为靠

近，碎屑和水气可能会导致 20V V_BUS引脚与 CC 引脚

短路。

TPD2S300

OVP and ESD

CC Analog

USB PD Phy and Controller

Power Switch Control

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSDL1

TPD2S300

ZHCSGS3 –APRIL 2017

www.ti.com.cn

7.3 Feature Description................................................. 13

7.4 Device Functional Modes........................................ 14

Application and Implementation ........................ 15

8.1 Application Information............................................ 15

8.2 Typical Application ................................................. 15

Power Supply Recommendations...................... 27

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings—JEDEC Specification......................... 4

6.3 ESD Ratings—IEC Specification .............................. 4

6.4 Recommended Operating Conditions....................... 4

6.5 Thermal Information.................................................. 5

6.6 Electrical Characteristics........................................... 5

6.7 Timing Requirements................................................ 7

6.8 Typical Characteristics.............................................. 8

Detailed Description ............................................ 12

7.1 Overview ................................................................. 12

7.2 Functional Block Diagram ....................................... 12

10 Layout................................................................... 28

10.1 Layout Guidelines ................................................. 28

10.2 Layout Example .................................................... 28

11 器件和文档支持 ..................................................... 29

11.1 文档支持................................................................ 29

11.2 接收文档更新通知 ................................................. 29

11.3 社区资源................................................................ 29

11.4 商标....................................................................... 29

11.5 静电放电警告......................................................... 29

11.6 Glossary................................................................ 29

12 机械、封装和可订购信息....................................... 30

4 修订历史记录

日期

修订版本

说明

2017 年 4 月

初始发行版。

TPD2S300

www.ti.com.cn

ZHCSGS3 –APRIL 2017

5 Pin Configuration and Functions

YFF Package

9-Pin WCSP

YFF Package

9-Pin WCSP

Top Side Marking View

Bottom, Bump View

C_CC2

VBIAS

C_CC1

VBIAS

C_CC2

CC2

GND

CC1

FLT

CC2

CC1

FLT

GND

VPWR

Pin Functions

TYPE

DESCRIPTION

NO.

NAME

C_CC1

VBIAS

C_CC2

Connector side of the CC1 OVP FET. Connect to either CC pin of the USB Type-C

connector

I/O

Power

I/O

Pin for ESD support capacitor. Place a 0.1-µF capacitor on this pin to ground

Connector side of the CC2 OVP FET. Connect to either CC pin of the USB Type-C

connector

System side of the CC1 OVP FET. Connect to either CC pin of the CC/PD

controller

CC1

GND

CC2

I/O

GND

I/O

Ground

System side of the CC2 OVP FET. Connect to either CC pin of the CC/PD

controller

FLT

Open drain for fault reporting

2.7 V–4.5 V power supply

VPWR

Power

Voltage mode pin. Place 2.7 V–4.5 V on pin to operate for CC, PD, and FRS. Place

8.7 V–22 V on pin to operate the device in low resistance mode as well

TPD2S300

ZHCSGS3 –APRIL 2017

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–40

MAX

5.5

UNIT

V_PWR

V_I

Input voltage

Output voltage

I/O voltage

FLT

V_O

V_IO

VBIAS

CC1, CC2

C_CC1, C_CC2

T_A

Operating free air temperature

Operating junction temperature

Storage temperature

°C

T_J

–40

105

150

T_stg

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings—JEDEC Specification

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000

V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V

may actually have higher performance.

6.3 ESD Ratings—IEC Specification

VALUE

±8000

UNIT

Contact discharge

Air-gap discharge

V_(ESD)

Electrostatic discharge

IEC 61000-4-2, C_CC1, C_CC2

±15000

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

4.5

UNIT

V_PWR

2.7

3.3

V_I

Input voltage

V_O

Output voltage

I/O voltage

FLT Pull-up resistor power rail

CC1, CC2, C_CC1, C_CC2

Current flowing from CCx to C_CCx

FLT Pull-up resistance

5.5

V_IO

5.5

I_VCONN

V_CONNcurrent

200

300

kΩ

µF

1.7

0.3

External components⁽¹⁾

VBIAS capacitance⁽²⁾

0.1

V_PWRcapacitance, V_Mcapacitance

(1) For recommended values for capacitors and resistors, the typical values assume a component placed on the board near the pin.

Minimum and maximum values listed are inclusive of manufacturing tolerances, voltage derating, board capacitance, and temperature

variation. The effective value presented must be within the minimum and maximums listed in the table.

(2) The VBIAS pin requires a minimum 35-V_DCrated capacitor. A 50-V_DCrated capacitor is recommended to reduce capacitance derating.

See the VBIAS Capacitor Selection section for more details on VBIAS capacitor selection.

TPD2S300

www.ti.com.cn

ZHCSGS3 –APRIL 2017

6.5 Thermal Information

TPD2S300

YFF (WCSP)

9 PINS

107.5

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

0.9

28.1

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

ψ_JB

28.2

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

CC OVP SWITCHES

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VM = 8.7 V, CCx = 3 V, I_CCx= 0.6

–40°C ≤ T_J≤ 105°C

R_{ON_VCONN_}On resistance of CC OVP FETs

0.560

VCONN operation

R_{ON_VCONN_}On resistance of CC OVP FETs

VM = 8.7 V, CCx = 4.87 V, I_CCx

0.2 A, –40°C ≤ T_J≤ 105°C

0.608

1.3

VCONN operation

On resistance of CC OVP FETs

R_{ON_FRS}

VM = 2.7 V, CCx = 0.49 V, I_CCx

30 mA, –40°C ≤ T_J≤ 105°C

fast role swap operation

On resistance of CC OVP FETs

R_{ON_CC_ANA}

VM = 2.7 V, CCx = 2.45 V, I_CCx

400 µA, –40°C ≤ T_J≤ 105°C

18.7

CC analog operation

On resistance of CC OVP FETs

R_{ON_PD}

VM = 2.7 V, CCx = 1.2 V, I_CCx=

250 µA, –20°C ≤ T_J≤ 105°C

CC USB-PD operation

VM = 8.7 V, sweep CCx from 0 V to

R_{ONFLAT_VC}On resistance flatness of CC OVP 5.5 V, measure the difference in

0.2

FETs VCONN operation

resistance. I_CCx= 0.2 A, –40°C ≤ T_J

≤ 105°C

ONN_1

Capacitance from C_CCx or CCx to

Equivalent on capacitance for CC GND when device is powered.

C_{ON_CC}

0.5

120

1.2

pins

V_{C_CCx}/V_CCx= 0 V to 1.2 V, f = 400

kHz, –40°C ≤ T_J≤ 105°C

Threshold voltage of the pull-down

FET in series with RD during dead I_C_CCx = 80 uA

battery

VTH_DB

R_D

0.9

5.1

Dead battery pull-down resistance

(only present when device is

unpowered). Effective resistance

of R_Dand FET in series

V_PWR= 0 V, V_{C_CCx}= 2.6 V

4.1

6.1

kΩ

Place 5.5 V on C_CCx pins. Step

up voltage until the FLT pin is

asserted .–20°C ≤ T_J≤ 105°C

Rising overvoltage protection

threshold on C_CCx pins

V_{OVPCC_RISE}

5.55

6.18

Place 6.5 V on C_CCx. Step down

the voltage on C_CCx until the FLT

pin is deasserted. Measure the

difference between rising and falling

OVP thresholds

V_{OVPCC_HYS}OVP threshold hysteresis

Measure the –3-dB bandwidth from

C_CCx to CCx. Single ended

measurement, 50-Ω system. Vcm =

0 V to 1.2 V

BW_ON

On bandwidth single ended (–3dB)

MHz

Hot-Plug C_CCx with a 1 meter

USB Type C Cable. Place a 30-Ω

load on CCx

Short-to-VBUS tolerance on the

C_CCx pins

V_{STBUS_CC}

TPD2S300

ZHCSGS3 –APRIL 2017

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Hot-Plug C_CCx with a 1-meter

USB Type C Cable. Hot-plug

clamping voltage on the CCx pins voltage C_CCx = 2 4V. VPWR = 3.3

V_{STBUS_CC_}Short-to-VBUS system-side

CLAMP

V. Place a 30-Ω load on CCx

POWER SUPPLY AND LEAKAGE CURRENTS

V_PWRundervoltage lockout

Place 1 V on VPWR and raise the

voltage until the CC FETs turn ON

V_{PWR_UVLO}

threshold

1.9

2.3

100

2.55

200

Place 3 V on VPWR and lower the

voltage until the CC FETs turn off.

Calculate the difference between

the rising and falling UVLO

threshold

V_{PWR_UVLO_}

HYS

V_PWRUVLO hysteresis

VPWR quiescent current for 1S

VPWR = 3.3 V, VM = 3.3 V, C_CCx

= 3.6 V, –40°C ≤ T_J≤ 105°C

I_{VPWR_1S}

battery

3.23

µA

VM quiescent current for 1S

battery

VPWR = 3.3 V, VM = 3.3 V, C_CCx

= 3.6 V, –40°C ≤ T_J≤ 105°C

I_{VM_1S}

I_{VPWR_1S_Ma}VPWR quiescent current for 1S

VPWR = 4.5 V, VM = 4.5 V, C_CCx

= 3.6 V, –40°C ≤ T_J≤ 105°C

battery max

VM quiescent current for 1S

battery max

VPWR = 4.5 V, VM = 4.5 V, C_CCx

= 3.6 V, –40°C ≤ T_J≤ 105°C

I_{VM_1S_Max}

VPWR quiescent current for 3S

VPWR = 3.6 V, VM = 13.5 V,

C_CCx = 3.6 V, –40°C ≤ T_J≤ 105°C

I_{VPWR_3S}

battery

VM quiescent current for 3S

battery

VPWR = 3.6 V, VM = 13.5 V,

C_CCx = 3.6 V, –40°C ≤ T_J≤ 105°C

I_{VM_3S}

3.5

VPWR quiescent current for 4S

VPWR = 3.6 V, VM = 18 V, C_CCx

= 3.6 V, –40°C ≤ T_J≤ 105°C

I_{VPWR_4S}

battery

VM quiescent current for 4S

battery

VPWR = 3.6 V, VM = 18 V, C_CCx

= 3.6 V, –40°C ≤ T_J≤ 105°C

I_{VM_4S}

4.5

VPWR = 3.3 V, VM = 3.3 V,

VC_CCx = 3.6 V, CCx pins are

Leakage current for CC pins when floating, measure leakage into

I_{CC_LEAK}

µA

device is powered

C_CCx pins. Result must be same if

CCx side is biased and C_CCx is

left floating

VPWR = VM = 0 V or 3.3 V,

VC_CCx = 24 V, CCx = 0 V,

measure leakage into C_CCx pins

I_{C_CC_LEAK_}Leakage current for C_CCx pins

1500

µA

when device is in OVP

OVP

VPWR = VM = 0 V or 3.3 V,

VC_CCx = 24 V, CCx = 0 V,

measure leakage flowing out of CCx

pins

I_{CC_LEAK_OV}Leakage current for CCx pins

when device is in OVP

FLT PIN

Low-level output voltage for FLT

IOL = 3 mA. Measure the voltage at

the FLT pin

V_OL

0.4

TPD2S300

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ZHCSGS3 –APRIL 2017

6.7 Timing Requirements

MIN

NOM

MAX

UNIT

POWER-ON AND POWER-OFF TIMINGS

Time from crossing rising VPWR UVLO until CC OVP FETs are on.

VPWR slew rate = 0.347 V/µs

t_ON

200

µs

dV_{PWR_OFF}

Minimum slew rate allowed to guarantee CC FETs turn off during a power

off

–0.5

V/µs

OVERVOLTAGE PROTECTION

OVP response time on the CC pins. Time from OVP asserted until OVP

FETs turn off. Hot-Plug C_CCx to 24 V with a 1-m cable. C_CCx slew rate

= 4 V/ns. Place a 30-Ω on CCx

t_{OVP_RESPON}

SE_CC

145

200

µs

OVP recovery time on the CC pins. Time from OVP removal until FET

turns back on.VM = 10.8 V. Step C_CCx down from 6.3 V to 3.3 V at a

0.343-V/µs slew rate

t_{OVP_RECOVE}

RY_CC

OVP recovery time on the CC pins. Time from OVP removal until FET

turns back on.VM = 3.3 V. Step C_CCx down from 6.3 V to 0.49 V at a

0.321-V/µs slew rate

t_{OVP_RECOVE}

RY_CC

Time from OVP asserted to FLT assertion.FLT assertion is when the FLT

pin reaches 10% of its starting value. C_CCx from 0 V to 6.3 V at a 0.645-

V/µs slew rate

t_{OVP_FLT_ASS}

ERTION

Time from OVP removal to FLT deassertion. FLT deassertion is when the

FLT pin reaches 90% of its final value. C_CCx from 6.3 V to 0 V at a

0.696-V/µs slew rate

t_{OVP_FLT_DE}

ASSERTION

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ZHCSGS3 –APRIL 2017

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6.8 Typical Characteristics

V_{C_CC1}

I_{C_CC1}

V_CC1

/FLT

-3

-6

-9

-1

-12

-0.8 -0.4

0.4 0.8 1.2 1.6

2.4 2.8 3.2

1E+7

1E+8

Frequency (Hz)

1E+9 2E+9

Time (ms)

D011

D025

图 2. CC Short-to-V_BUS20-V VM = 3.3 V

图 1. CC S21 BW

V_{C_CC1}

I_{C_CC1}

V_CC1

C_CC1

Current

CC1

V_/FLT

/FLT

-1

-5

-0.8 -0.4

0.4 0.8 1.2 1.6

2.4 2.8 3.2

-200 -100

100 200 300 400 500 600 700 800

Time (ms)

D012

D013

图 3. CC Short-to-V_BUS20-V VM = 13 V

图 4. CC OVP Recovery VM = 3.3 V

0.6

0.5

0.4

0.3

0.2

0.1

0.7

0.6

0.5

0.4

0.3

0.2

0.1

-40èC

25èC

85èC

125èC

25èC

85èC

125èC

0.5

1.5

2.5

3.5

4.5

5.5

0.07

0.14

0.21

0.28

0.35

0.42

0.49

V_CC1(V)

V_CC(V)

D003

D016

图 5. CC R_ONFlatness, V_M= 8.7 V

图 6. CC R_ONFlatness, V_M= 2.7 V

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ZHCSGS3 –APRIL 2017

Typical Characteristics (接下页)

1.2

-40èC

25èC

85èC

125èC

0.8

0.6

0.4

0.2

-40èC

25èC

85èC

125èC

0.2

0.4

0.6

0.8

1.2

2.15

2.2

2.25

2.3

2.35

2.4

2.45

V_CC(V)

D017

D018

图 7. CC R_ONFlatness, V_M= 2.7 V

图 8. CC R_ONFlatness, V_M= 2.7 V

140

C_CC

120

100

-20

-40

-60

-80

-100

-20

-40

-60

-80

-10

10 20 30 40 50 60 70 80 90 100 110

Time (ns)

-10

10 20 30 40 50 60 70 80 90 100 110

Time (ns)

D001

D002

图 9. CC IEC 61000-4-2 8-kV Response Waveform

图 10. CC IEC 61000-4-2 –8-kV Response Waveform

1280

1260

1240

1220

1200

1180

1160

1140

1120

1100

1080

C_CC1

C_CC2

C_CC1

C_CC2

-40

-20

100 120 140

-40

-20

100 120 140

Temperature (èC)

D001

D019

图 11. CC Path Leakage Current vs Ambient Temperature at

图 12. C_CC OVP Leakage Current vs Ambient Temperature

C_CC = 5.5 V

at C_CC = 24 V

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Typical Characteristics (接下页)

0.225

CC1: C_CC1 at 24 V

CC1: C_CC2 at 24 V

0.2

0.175

0.15

0.125

0.1

0.075

0.05

0.025

V_PWR

C_CC1

CC1

-0.025

-1

-40

-20

100 120 140

-300 -200 -100

100 200 300 400 500 600 700

Temperature (èC)

Time (ms)

D020

D007

图 13. CC OVP Leakage Current vs Ambient Temperature at

图 14. CC FET Turnon Timing

C_CC = 24 V

Voltage (V)

D005

D006

图 15. C_CC TLP Curve Unpowered

图 16. CC TLP Curve Unpowered

1.5

0.5

-0.5

-1

C_CC1

C_CC2

V_PWR= 3.6 V

V_PWR= 4.5 V

-1.5

-1

11 13 15 17 19 21 23 25

Voltage (V)

-40

-20

100

120130

Temperature (èC)

D021

D009

图 17. CC IV Curve

图 18. V_PWRSupply Leakage vs Ambient Temperature With

C_CC Floating or GND

TPD2S300

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ZHCSGS3 –APRIL 2017

Typical Characteristics (接下页)

4.5

VM = 3.6 V

VM = 4.5 V

VM = 18 V

3.5

2.5

1.5

0.5

-40

-20

100

120130

Temperature (èC)

D010

图 19. V_MSupply Leakage vs Ambient Temperature With C_CC Floating or GND

TPD2S300

ZHCSGS3 –APRIL 2017

www.ti.com.cn

7 Detailed Description

7.1 Overview

The TPD2S300 is a low quiescent current, single chip USB Type-C port protection solution that provides 24-V

Short-to-V_BUSovervoltage and IEC ESD protection. Due to the small pin pitch of the USB Type-C connector and

non-compliant USB Type-C cables and accessories, the V_BUSpins can get shorted to the CC pins inside the USB

Type-C connector. Because of this Short-to-V_BUSevent, the CC pins need to be short-to-V_BUStolerant, to support

protection on the full USB PD voltage range. Even if a device does not support 20-V operation on V_BUS, non

complaint adaptors can start out with 20-V V_BUScondition, making it necessary for any USB Type-C device to

support 20-V protection. Although the USB-PD specification has a maximum VBUS voltage of 21.5 V, non-

complaint adaptors could go outside this maximum. Therefore, the TPD2S300 integrates two channels of 24-V

Short-to-V_BUSovervoltage protection for the CC1 and CC2 pins of the USB Type-C connector.

Additionally, IEC 61000-4-2 system level ESD protection is required in order to protect a USB Type-C port from

ESD strikes generated by end product users. The TPD2S300 integrates two channels of IEC61000-4-2 ESD

protection for the CC1 and CC2 pins of the USB Type-C connector. Additionally, high voltage IEC ESD protection

that is at least 22-V DC tolerant is required for the CC lines in order to simultaneously support IEC ESD and

Short-to-V_BUSprotection (although 24-V DC tolerant is recommended, which the TPD2S300 integrates); there are

not many discrete market solutions that can provide this kind of protection. This high-voltage IEC ESD diode is

what the TPD2S300 integrates, specifically designed to guarantee it works in conjunction with the overvoltage

protection FETs inside the device. This sort of solution is very hard to generate with discrete components.

7.2 Functional Block Diagram

VPWR

Overvoltage

Control Logic

FLT

Protection

C_CC1

VBIAS

C_CC2

CC1

CC2

System

Clamps

ESD

Clamps

/V_PWR

R_D

/V_PWR

R_D

图 20. TPD2S300

TPD2S300

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7.3 Feature Description

7.3.1 2-Channels of Short-to-V_BUSOvervoltage Protection (CC1, CC2 Pins): 24-V_DCTolerant

The TPD2S300 provides 2-channels of Short-to-V_BUSOvervoltage Protection for the CC1 and CC2 pins of the

USB Type-C connector. The TPD2S300 is able to handle 24-V DC on its C_CC1 and C_CC2 pins. This is

necessary because according to the USB PD specification, with V_BUSset for 20-V operation, the V_BUSvoltage is

allowed to legally swing up to 21 V, and 21.5 V on voltage transitions from a different USB PD V_BUSvoltage. The

TPD2S300 builds in tolerance up to 24-V_BUSto provide margin above this 21.5 V specification to be able to

support USB PD adaptors that may break the USB PD specification.

When a short-to-V_BUSevent occurs, ringing happens due to the RLC elements in the hot-plug event. With very

low resistance in this RLC circuit, ringing up to twice the settling voltage can appear on the connector. More than

2x ringing can be generated if any capacitor on the line derates in capacitance value during the short-to-V_BUS

event. This means that more than 44 V could be seen on a USB Type-C pin during a Short-to-V_BUSevent. The

TPD2S300 has built in circuit protection to handle this ringing. The diode clamps used for IEC ESD protection

also clamp the ringing voltage during the short-to-V_BUSevent to limit the peak ringing to around 30 V.

Additionally, the overvoltage protection FETs integrated inside the TPD2S300 are 30-V tolerant, therefore being

capable of supporting the high voltage ringing waveform that is experienced during the short-to-V_BUSevent. The

well designed combination of voltage clamps and 30-V tolerant OVP FETs insures the TPD2S300 can handle

Short-to-V_BUShot-plug events with hot-plug voltages as high as 24-V_DC

The TPD2S300 has an extremely fast turnoff time of 145 ns typical. Furthermore, additional voltage clamps are

placed after the OVP FET on the system side (CC1, CC2) pins of the TPD2S300, to further limit the voltage and

current that is exposed to the USB Type-C CC/PD controller during the 145 ns interval while the OVP FET is

turning off. The combination of connector side voltage clamps, OVP FETs with extremely fast turnoff time, and

system side voltage clamps all work together to insure the level of stress seen on the CC1 and CC2 pin during a

short-to-V_BUSevent is comparable to an HBM ESD event. This is done by design, as any USB Type-C CC/PD

controller has built in HBM ESD protection.

7.3.2 2-Channels of IEC61000-4-2 ESD Protection (CC1, CC2 Pins)

The TPD2S300 integrates 2-Channels of IEC 61000-4-2 system level ESD protection for the CC1 and CC2 pins

of the USB Type-C connector. USB Type-C ports on end-products need system level IEC ESD protection in

order to provide adequate protection for the ESD events that the connector can be exposed to from end users.

High-voltage IEC ESD protection that is 24-V DC tolerant is required for the CC lines in order to simultaneously

support IEC ESD and Short-to-V_BUSprotection; there are not many discrete market solutions that can provide this

kind of protection. The TPD2S300 integrates this type of high-voltage ESD protection so a system designer can

meet both IEC ESD and Short-to-V_BUSprotection requirements in a single device.

7.3.3 Low Quiescent Current: 3.23 µA (Typical), V_PWR, V_M= 3.3 V

The TPD2S300 is designed with a very low quiescent current of 3.23 µA (typical) when V_PWR= 3.3 V and V_M

3.3 V. The TPD2S300 is designed to have a very low quiescent current to support applications like smart-phones

where device battery life is crucial. See the Electrical Characteristics table for complete range of quiescent

currents for different V_PWRand V_Mvoltages.

7.3.4 CC1, CC2 Overvoltage Protection FETs 200 mA Capable for Passing V_CONNPower

The CC pins on the USB Type-C connector serve many functions; one of the functions is to be a provider of

power to active cables. Active cables are required when desiring to pass greater than 3 A of current on the V_BUS

line or when the USB Type-C port uses the super-speed lines (TX1+, TX2–, RX1+, RX1–, TX2+, TX2–, RX2+,

RX2–). When CC is configured to provide power, it is called V_CONN. V_CONNis a DC voltage source in the range of

3 V–5.5 V. If supporting V_CONN, a V_CONNprovider must be able to provide 1 W of power to a cable; this translates

into a current range of 200 mA at 5-V V_CONN. Therefore, the TPD2S300 has been designed to handle 200 mA of

DC current and to have an RON low enough to provide a specification compliant V_CONNvoltage to the active

cable.

7.3.5 CC Dead Battery Resistors Integrated for Handling Dead Battery Use Case in Mobile Devices

An important feature of USB Type-C and USB PD is the ability for this connector to serve as the sole power

source to mobile devices. With support up to 100 W, the USB Type-C connector supporting USB PD can be

used to power a whole new range of mobile devices not previously possible with legacy USB connectors.

TPD2S300

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Feature Description (接下页)

When the USB Type-C connector is the sole power supply for a battery powered device, the device must be able

to charge from the USB Type-C connector even when its battery is dead. In order for a USB Type-C power

adapter to supply power on V_BUS, R_Dpull-down resistors must be exposed on the CC pins of the sink device.

These R_Dresistors are typically included inside a USB Type-C CC/PD controller. However, when the TPD2S300

is used to protect the USB Type-C port, the OVP FETs inside the device isolates these R_Dresistors in the

CC/PD controller when the mobile device has no power. This is because when the TPD2S300 has no power, the

OVP FETs are turned off to guarantee overvoltage protection in a dead battery condition. Therefore, the

TPD2S300 integrates high voltage, dead battery R_Dpull-down resistors to allow dead battery charging

simultaneously with high-voltage OVP protection.

When the TPD2S300 is unpowered, and the R_Ppull-up resistor is connected from a power adaptor, this R_Ppull-

up resistor activates the R_Dresistor inside the TPD2S300. This enables V_BUSto be applied from the power

adaptor even in a dead battery condition. Once power is restored back to the system and back to the TPD2S300

on its VPWR pin, the TPD2S300 removes its R_Dpull-down resistor and turns on its OVP FETs within 200 µs.

The amount of time the TPD2S300 does not have either its R_Dexposed or the PD controller's R_Dexposed on the

CC lines is even less, around 30µs in the worst case, to minimize the probability the USB-C/PD controller in the

source device interprets this as a disconnect from the sink. This way connection remains uninterrupted.

If desiring to power the CC/PD controller during dead battery mode and if the CC/PD Controller is configured as

a DRP, it is critical that the TPD2S300 be powered before or at the same time that the CC/PD controller is

powered. It is also critical that when unpowered, the CC/PD controller also expose its dead battery resistors.

When the TPD2S300 gets powered, it exposes the CC pins of the CC/PD controller within 200 µs. Once the

TPD2S300 turns on, the R_Dpull-down resistors of the CC/PD controller must be present immediately, in order to

guarantee the power adaptor connected to power the dead battery device keeps its V_BUSturned on. If the power

adaptor sees the CC voltage go high to the SRC.Open region, it can disconnect V_BUS. This removes power from

the device with its battery still not sufficiently charged, which consequently removes power from the CC/PD

controller and the TPD2S300. Then the R_Dresistors of the TPD2S300 are exposed again and connect the power

adaptor's V_BUSto start the cycle over. This creates an infinite loop, never or very slowly charging the mobile

device.

If the CC/PD Controller is configured for DRP and has started its DRP toggle before the TPD2S300 turns on, this

DRP toggle is unable to guarantee that the power adaptor does not disconnect from the port. Therefore, it is

recommended if the CC/PD controller is configured for DRP, that its dead battery resistors be exposed as well,

and that they remain exposed until the TPD2S300 turns on. This is typically accomplished by powering the

TPD2S300 at the same time as the CC/PD controller when powering the CC/PD controller in dead battery

operation.

7.3.6 1.4-mm × 1.4-mm WCSP Package

The TPD2S300 comes in a small, 1.4-mm × 1.4-mm WCSP package, greatly reducing the size of implementing a

similar protection solution discretely. Smart-phones and tablets need the smallest package size possible due to

the space constraints the PCBs have in these devices.

7.4 Device Functional Modes

表 1 describes all of the functional modes for the TPD2S300. The "X" in the below table are "do not care"

conditions, meaning any value can be present within the absolute maximum ratings of the datasheet and

maintain that functional mode.

表 1. Device Mode Table

Device Mode Table

MODE

Inputs

Outputs

CC FETs

Dead Battery

Resistors

VPWR

C_CCx

FLT

Normal

Operating

Conditions

Unpowered

Powered on

<UVLO

>UVLO

High-Z

OFF

≥VPWR

<OVP

OFF

Fault

Conditions

CC overvoltage

condition

Low (Fault

Asserted)

>UVLO

≥VPWR

>OVP

OFF

TPD2S300

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPD2S300 provides 2-channels of Short-to-V_BUSovervoltage protection for the CC1 and CC2 pins of the

USB Type-C connector, and 2-channels of IEC ESD protection for the CC1 and CC2 pins of the USB Type-C

connector. Care must be taken to insure that the TPD2S300 provides adequate system protection as well as

insuring that proper system operation is maintained. The following application examples explain how to properly

design the TPD2S300 into a USB Type-C system.

8.2 Typical Application

8.2.1 Smart-Phone Application

Battery

APU

I2C

1S BAT

Battery Charger

TUSB422

CC1

CC2

VBUS SRC/SNK

CC1

CC2

VPWR

TPD2S300

1S BAT

C_VPWR

R_/FLT

VBUS OVP

Protection

VBIAS

/FLT

To APU

C_VBIAS

C_CC1 C_CC2

V_BUS

CC1

CC2

图 21. TPD2S300 Typical Application Diagram

TPD2S300

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Typical Application (接下页)

8.2.1.1 Design Requirements

In this application example, we use the TPD2S300 to protect a USB Type-C port in a smart-phone application. In

this application, the smart-phone needs USB2.0 support and 20-V, 2-A charging. Because 20 V is required, USB-

PD needs to be used in this application to achieve this, as USB Type-C alone cannot support higher than 5 V. In

order to add USB-PD operation in a smart-phone application, the TUSB422 is used. This device is a TCPCi that

adds the USB Type C and USB-PD physical layer required to run USB PD over the USB Type-C connector. This

device can be connected to the APU in the system through I²C, and the APU can run the USB-PD code.

With USB-C with 20-V PD being used, a Short-to-V_BUSevent can occur in the system. This short can affect both

the CC and SBU pins. However, in this application, since only USB2.0 is required, the SBU pin is not used.

Therefore, only CC Short-to-V_BUSprotection is required to adequately protect the TUSB422 and the system. The

CC pins also needs IEC61000-4-2 system level ESD protection. Additionally, with this application being a smart-

phone, board space is crucial; a small protection device is required. Therefore, with these application

requirements, the TPD2S300 is used, a single-chip solution which integrates all the protection requirements

needed for the CC pins in this application.

表 2 shows the TPD2S300 design parameters for this application.

表 2. Design Parameters

DESIGN PARAMETER

V_BUSnominal operating voltage

Short-to-V_BUStolerance for the CC pins

VBIAS nominal capacitance

EXAMPLE VALUE

20 V

24 V

0.1 µF

Dead battery charging

40 W

TPD2S300 VPWR and VM power source

Quiescent current required for protection device

V_CONNrequirement

3.3-V LDO or 1S battery

≤ 20 µA

V_CONNnot required

85°C

Maximum ambient temperature requirement

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 VBIAS Capacitor Selection

As noted in the Recommended Operating Conditions table, a minimum of 35-VBUS rated capacitor is required

for the VBIAS pin, and a 50-VBUS capacitor is recommended. The VBIAS capacitor is in parallel with the central

IEC diode clamp integrated inside the TPD2S300. A forward biased hiding diode connects the VBIAS pin to the

C_CCx pins. Therefore, when a Short-to-V_BUSevent occurs at 20 V, 20-V_BUSminus a forward biased diode drop

is exposed to the VBIAS pin. Additionally, during the Short-to-V_BUSevent, ringing can occur almost double the

settling voltage of 20 V, allowing a potential 40 V to be exposed to the C_CCx pins. However, the internal IEC

clamps limits the voltage exposed to the C_CCx pins to around 30 V. Therefore, at least 35-VBUS capacitor is

required to insure the VBIAS capacitor does not get destroyed during Short-to-V_BUSevents.

A 50-V, X7R capacitor is recommended, however. This is to further improve the derating performance of the

capacitors. When the voltage across a real capacitor is increased, its capacitance value derates. The more the

capacitor derates, the greater than 2x ringing can occur in the Short-to-V_BUSRLC circuit. 50-V X7R capacitors

have great derating performance, allowing for the best Short-to-V_BUSperformance of the TPD2S300.

Additionally, the VBIAS capacitor helps pass IEC 61000-4-2 ESD strikes. The more capacitance present, the

better the IEC performance. So the less the VBIAS capacitor derates, the better the IEC performance. 表 3

shows the real capacitors recommended to achieve the best performance with the TPD2S300.

表 3. Design Parameters

CAPACITOR SIZE

PART NUMBER

0402

0603

CC0402KRX7R9BB104

GRM188R71H104KA93D

TPD2S300

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8.2.1.2.2 Dead Battery Operation

For this application, we want to support 40-W dead battery operation; when the smart-phone is out of battery, we

still want to charge the laptop at 20 V and 2 A. This means that the USB PD Controller must receive power in

dead battery mode. This means a dead battery LDO must be present in the system to power the TUSB422 and

the APU controlling TUSB422 during dead battery. Or, the system PMIC must be able to provide the 1S battery

to the APU and TUSB422 during dead battery conditions.

The TPD2S300s OVP FETs remain OFF when it is unpowered in order to insure in a dead battery situation

proper protection is still provided to the PD controller or TCPCi in the system, in this case the TUSB422.

However, when the OVP FETs are OFF, this isolates the TUSB422's dead battery resistors from the USB Type-

C ports CC pins. A USB Type-C power adaptor must see the R_Dpull-down dead battery resistors on the CC pins

or it does not turn on V_BUSto provide power. Since the TUSB422's dead battery resistors are isolated from the

USB Type-C connector's CC pins, the TPD2S300 integrates dead battery resistors on its C_CCx pins. The

TPD2S300 exposes these pins when it is unpowered.

Once the power adaptor sees the TPD2S300's dead battery resistors, it applies 5 V on the V_BUSpin. This

provides power to the dead battery LDO or PMIC, allowing power to be applied to the APU and TUSB422 to turn

them ON, and allowing the battery to begin to charge. However, this application requires 40-W charging in dead

battery mode, so V_BUSat 20 V and 2 A is required. USB PD negotiation is required to accomplish this, so the

APU through the TUSB422 needs to be able to communicate on the CC pins. This means the TPD2S300 needs

to be turned on in dead battery mode as well so the TUSB422 can be exposed to the CC lines. To accomplish

this, it is critical that the TPD2S300 is powered by the same dead battery LDO or battery voltage as the APU and

TUSB422 during dead battery. This way, the TPD2S300 is turned ON simultaneously with TUSB422.

It is critical that the TUSB422's dead battery resistors are also active on its CC pins for dead battery operation.

Once the TPD2S300 receives power, removes its dead battery resistors and turns on its OVP FETs, R_Dpull-

down resistors must be present on the CC line in order to guarantee the power adaptor stays connected. If RD is

not present and the voltage on CC increases into the SRC.Open range, the power adaptor can interpret this as a

port disconnect and remove V_BUS

Once this process has occured, the APU through the TUSB422 can start negotiating with the power adaptor

through USB PD for higher power levels, allowing for 40W operation in dead battery mode.

For more information on the TPD2S300 dead battery operation, see the CC Dead Battery Resistors Integrated

for Handling Dead Battery Use Case in Mobile Devices section in the description section of the datasheet. Also,

see 图 22 for a waveform of the CC line when the TPD2300 is turning on and exposing R_Ddead battery resistors

to the USB Type-C connector.

8.2.1.2.3 CC Line Capacitance

USB PD has a specification for the total amount of capacitance that is required for proper USB PD BMC

operation on the CC lines. The specification from section 5.8.6 of the USB PD Specification is given in 表 4.

表 4. USB PD cReceiver Specification

NAME

DESCRIPTION

MIN

MAX UNIT

COMMENT

The DFP or UFP system shall have

capacitance within this range when

not transmitting on the line

cReceiver

CC receiver capacitance

200

600 pF

Therefore, the capacitance on the CC lines must stay in between 200 pF and 600 pF when USB PD is being

used. Therefore, the combination of capacitances added to the system by the TUSB422, the TPD2S300, and any

external capacitor must fall within these limits. 表 5 shows that with TUSB422 + TPD2S300, no external capacitor

is required to meet the USB-PD specification.

表 5. CC Line Capacitor Calculation

CC Capacitance

MIN

MAX

UNIT

COMMENT

From the USB PD Specification section

(cReceiver, section 5.8.6)

CC line target capacitance

200

600

TUSB422 capacitance

TPD2S300 capacitance

TUSB422 + TPD2S300

200

450

120

570

From the TUSB422 Datasheet

From the Electrical Characteristics table

Meets USB PD cReceiver Specification

230

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8.2.1.2.4 FLT Pin Operation

A FLT pin is provided on the TPD2S300 to give the APU the ability to be notified that a Short-to-V_BUSevent

occured. Once a Short-to-V_BUSoccurs on the C_CCx pins, the FLT pin is asserted in 1 µs (typical) so the PD

controller can be notified quickly. If V_BUSis being shorted to CC, it is recommended to respond to the event by

forcing a detach in the USB PD controller to remove V_BUSfrom the port. Although the USB Type-C port using the

TPD2S300 is not damaged, as the TPD2S300 provides protection from these events, the other device connected

through the USB Type-C Cable or any active circuitry in the cable can be damaged. Although shutting the V_BUS

off through a detach does not guarantee it stops the other device or cable from being damaged, it can mitigate

any high current paths from causing further damage after the initial damage takes place. Additionally, even if the

active cable or other device does have proper protection, the Short-to-V_BUSevent may corrupt a configuration in

an active cable or in the other PD controller, so it is best to detach and reconfigure the port. Therefore, in this

application it is recommended that the APU monitor the FLT pin for Short-to-V_BUSfaults.

8.2.1.2.5 V_CONNOperation

In our current application example, V_CONNis not required. Therefore, a 3.3-V source or 1S battery can be

connected to the VPWR and VM pins of the TPD2S300 and provide adaqute resistance in order to support CC

analog and USB PD operation over the CC lines. In fact, the CC OVP FETs resistance specifications are set to

optimize the FET size and therefore the TPD2S300 size and still allow proper CC analog and USB PD operation.

See the Electrical Characteristics table for the specific resistances of the CC OVP FETs.

8.2.1.2.6 Low Quiescent Current

Smart-Phone applications require low quiescent current to meet long battery life specifications to provide the best

experience to end-users. The TPD2S300 is designed to have very low quiescent current in order to meet these

requirements. The lower the voltage kept on the C_CCx lines, and the lower the voltage kept on the VPWR and

VM pins, the lower the quiescent current is on the TPD2S300. If an LDO is used that keeps VPWR and VM

limited to 3.3 V, then the maximum quiescent current on VPWR is 7 µA, and the maximum current on VM is 1

µA. If the 1S battery is connected to the VPWR and VM pins, such that the maximum voltage applied to VPWR

and VM is 4.5 V, then the maximum quiescent current is going to be 12 µA for VPWR, and VM has 1 µA

maximum. Therefore, our application can achieve a very low total quiescent current for protection with the

TPD2S300, between 8 µA and 13 µA, depending on how the TPD2S300 is powered. For all details on quiescent

current values, see the Electrical Characteristics table.

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8.2.1.3 Application Curves

图 22. TPD2S300 Turning On in Dead Battery Mode With 5.1-kΩ on CC1

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8.2.2 Laptop Application

DC/DC

Battery

VCONN

VBUS_SRC

I2C

Battery Charger

VBUS_SINK

PP_CABLE

I2C

PP_HV1

PP_HV2

TPS65987

C_CC2

C_CC1 LDO_3V3

VBUS1 VBUS2

C_CC1

C_CC2

C_VM

CC1

CC2

VPWR

TPD2S300

VBIAS

BAT

R_/FLT

C_VPWR

/FLT

C_CC1 C_CC2

To EC

C_VBIAS

V_BUS

CC2

CC1

图 23. TPD2S300 Typical Application Diagram

8.2.2.1 Design Requirements

In this application example, we use the TPD2S300 to protect a USB Type-C port in a laptop application. In this

application, the laptop needs USB3.0 support and 20-V, 5-A charging. Because 20 V is required, USB-PD needs

to be used in this application to achieve this, as USB Type-C alone cannot support higher than 5 V. In order to

add USB-PD operation in a laptop application, the TPS65987 is used. This device is a full-featured USB Type-C

and USB PD controller that integrates all the analog and power paths needed to support 20-V, 5-A charging and

USB3.0.

With USB-C with 20-V PD being used, a Short-to-V_BUSevent can occur in the system. This short can affect both

the CC and SBU pins. However, in this application, since only USB3.0 is required, the SBU pin is not used.

Therefore, only CC Short-to-V_BUSprotection is required to adequately protect TPS65987 and the system. The CC

pins also need IEC61000-4-2 system level ESD protection. Additionally, with this application being a laptop,

board space is crucial; a small protection device is required. Therefore, with these application requirements, the

TPD2S300 is used, a single-chip solution which integrates all the protection requirements needed for the CC pins

in this application.

表 2 shows the TPD2S300 design parameters for this application.

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表 6. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

V_BUSnominal operating voltage

Short-to-V_BUStolerance for the CC pins

VBIAS nominal capacitance

20 V

24 V

0.1 µF

Dead battery charging

100 W

TPD2S300 VPWR power source

TPD2S300 VM power source

V_CONNrequirement

3.3-V LDO from TPS65987

3S or 4S Battery

1-W V_CONNrequired

85°C

Maximum ambient temperature requirement

8.2.2.2 Detailed Design Procedure

8.2.2.2.1 VBIAS Capacitor Selection

This VBIAS capacitor requirements for this application are identical to the Smart-Phone application; see the

VBIAS Capacitor Selection section for more details.

8.2.2.2.2 Dead Battery Operation

For this application, we want to support 100-W dead battery operation; when the laptop is out of battery, we still

want to charge the laptop at 20 V and 5 A. This means that the USB PD Controller must receive power in dead

battery mode. The TPS65987 has its own built in LDO in order to supply the TPS65987 power from V_BUSin a

dead battery condition. The TPS65987 can also provide power to its flash during this condition through its

LDO_3V3 pin.

The TPD2S300s OVP FETs remain OFF when it is unpowered in order to insure in a dead battery situation

proper protection is still provided to the PD controller in the system, in this case the TPS65987. However, when

the OVP FETs are OFF, this isolates the TPS65987's dead battery resistors from the USB Type-C ports CC pins.

A USB Type-C power adaptor must see the R_Dpull-down dead battery resistors on the CC pins or it does not

turn ON V_BUSto provide power. Since the TPS65987s dead battery resistors are isolated from the USB Type-C

connector's CC pins, the TPD2S300 integrates dead battery resistors on its C_CCx pins, and exposes them

when the device is unpowered.

Once the power adaptor sees the TPD2S300's dead battery resistors, it applies 5 V on the V_BUSpin. This

provides power to the TPS65987, turning the PD controller on, and allowing the battery to begin to charge.

However, this application requires 100-W charging in dead battery mode, so V_BUSat 20 V and 5 A is required.

USB PD negotiation is required to accomplish this, so the TPS65987 needs to be able to communicate on the

CC pins. This means the TPD2S300 needs to be turned on in dead battery mode as well so the TPD65987's PD

controller can be exposed to the CC lines. To accomplish this, it is critical that the TPD2S300 is powered by the

TPS65987's internal LDO, the LDO_3V3 pin. This way, when the TPS65987 receives power on V_BUS, the

TPD2S300 is turned on simultaneously. Additionally, for low resistance VCONN support, the VM pin needs to be

connected to the 3S battery, so TPD2S300 needs to be able to receive this voltage in the dead battery condition

as well.

It is critical that the TPS65987's dead battery resistors are present; once the TPD2S300 receives power,

removes its dead battery resistors and turns on its OVP FETs, R_Dpull-down resistors must be present on the CC

line in order to guarantee the power adaptor stays connected. If RD is not present and the voltage on CC

increases to Src.Open, the power adaptor can interpret this as a disconnect and remove V_BUS

Also, it is important that the TPS65987's dead battery resistors are present so it properly boots up in dead

battery operation with the correct voltages on its CC pins.

Once this process has occurred, the TPS65987 can start negotiating with the power adaptor through USB PD for

higher power levels, allowing 100-W operation in dead battery mode.

For more information on the TPD2S300 dead battery operation, see the CC Dead Battery Resistors Integrated

for Handling Dead Battery Use Case in Mobile Devices section in the description section of the datasheet. Also,

see 图 22 for a waveform of the CC line when the TPD2S300 is turning on and exposing the TPS65987's dead

battery resistors to the USB Type-C connector.

TPD2S300

ZHCSGS3 –APRIL 2017

www.ti.com.cn

8.2.2.2.3 CC Line Capacitance

USB PD has a specification for the total amount of capacitance that is required for proper USB PD BMC

operation on the CC lines. The specification from section 5.8.6 of the USB PD Specification is given in 表 4.

表 7. USB PD cReceiver Specification

NAME

DESCRIPTION

MIN

MAX UNIT

COMMENT

The DFP or UFP system shall have

capacitance within this range when

not transmitting on the line

cReceiver

CC receiver capacitance

200

600 pF

Therefore, the capacitance on the CC lines must stay in between 200 pF and 600 pF when USB PD is being

used. Therefore, the combination of capacitances added to the system by the TPS65987, the TPD2S300, and

any external capacitor must fall within these limits. 表 5 shows the analysis involved in choosing the correct

external CC capacitor for this system, and shows that an external CC capacitor is required.

表 8. CC Line Capacitor Calculation

CC Capacitance

MIN

MAX

UNIT

COMMENT

From the USB PD Specification section

(cReceiver, section 5.8.6)

CC line target capacitance

200

600

TPS65987 capacitance

TPD2S300 capacitance

120

From the TPS65987 Datasheet

From the Electrical Characteristics table

CAP, CERM, 220 pF, 25 V, ±10%, X7R,

0201 (For min and max, assume ±50%

capacitance change with temperature and

voltage derating to be overly conservative)

Proposed capacitor GRM033R71E221KA01D

110

210

330

570

TPS65987 + TPD2S300 +

GRM033R71E221KA01D

Meets USB PD cReceiver Specification

8.2.2.2.4 FLT Pin Operation

This FLT pin recommendation for this application are identical to the Smart-Phone application; see the FLT Pin

Operation section for more details.

8.2.2.2.5 V_CONNOperation

In our current application example, 1-W V_CONNis required. With a 5-V source on the TPS65987's PP_CABLE pin,

this means 200 mA of current is required. Therefore, it is ideal to put the TPD2S300 in low-resistance mode,

which is easy to do in this application because of the presence of a 3S battery in the laptop. Tie the VM pin to

the 3S battery voltage. With the VM pin tied to the 3S battery, the worst case resistance of TPD2S300 with 4.87

V on CCx is 608 mΩ. This way with 200 mA flowing through the TPD2S300, voltage drop is much lower across

the TPD2S300 and it is easier to achieve the VCONN voltage requirements given in the USB Type-C

Specification.

TPD2S300

www.ti.com.cn

ZHCSGS3 –APRIL 2017

8.2.2.3 Application Curves

图 24. TPD2S300 Protecting the TPS65982 During a Short-to-V_BUSEvent

TPD2S300

ZHCSGS3 –APRIL 2017

www.ti.com.cn

8.2.3 Power Adaptor Application

AC Mains

AC/DC

ADJ

VBUS_SRC

CTL1 CTL2

GDNG

GDNS

ISNS

TPS25740

VBUS

DSCG

CC1

CC2

C_CC1

C_CC2

5 V

CC2

VPWR

TPD2S300

VBIAS

R_/FLT

C_VPWR

/FLT

C_CC1 C_CC2

To EC

C_VBIAS

V_BUS

CC2

CC1

图 25. TPD2S300 Typical Application Diagram

8.2.3.1 Design Requirements

In this application example, we use the TPD2S300 to protect a USB Type-C port in a power adaptor application.

In this application, the power adaptor needs to supply 20 V, 3 A to the device it is charging. Because 20 V is

required, USB-PD needs to be used in this application to achieve this, as USB Type-C alone cannot support

higher than 5 V. In order to add USB-PD operation in a power adaptor application, the TPS25740 is used. This

device is a USB Type-C and USB PD Source Controller.

With USB-C with 20-V PD being used, a Short-to-V_BUSevent can occur in the system. This short can affect both

the CC and SBU pins. However, in this application, since only USB Type-C and PD charging is required, the

SBU pin is not used. Therefore, only CC Short-to-V_BUSprotection is required to adequately protect the TPS25740

and the system. The CC pins also need IEC61000-4-2 system level ESD protection. Additionally, with this

application being a power adaptor, board space is crucial; a small protection device is required. Therefore, with

these application requirements, the TPD2S300 is used, a single-chip solution which integrates all the protection

requirements needed for the CC pins in this application.

表 2 shows the TPD2S300 design parameters for this application.

表 9. Design Parameters

DESIGN PARAMETER

V_BUSnominal operating voltage

Short-to-V_BUStolerance for the CC pins

VBIAS nominal capacitance

EXAMPLE VALUE

20 V

24 V

0.1 µF

TPD2S300

www.ti.com.cn

ZHCSGS3 –APRIL 2017

表 9. Design Parameters (接下页)

DESIGN PARAMETER

EXAMPLE VALUE

Dead battery charging

TPD2S300 VPWR and VM power source

V_CONNrequirement

No dead battery mode; source only device

5-V source

V_CONNnot required

85°C

Maximum ambient temperature requirement

8.2.3.2 Detailed Design Procedure

8.2.3.2.1 VBIAS Capacitor Selection

This VBIAS capacitor requirements for this application are identical to the Smart-Phone application; please see

the VBIAS Capacitor Selection section for more details.

8.2.3.2.2 Dead Battery Operation

This application is source mode only. Therefore, dead battery operation is not required, and R_Dresistors must

not be exposed on the CC lines. However, because when the TPD2S300 is unpowered it exposes its dead

battery resistors, when the wall adaptor is not plugged into the wall, it has RDs present on its CC lines. If it is

plugged into a laptop at this point, then the laptop senses a connection and output 5-V V_BUS. Therefore, the

power switch that sources V_BUSin the wall adaptor must be able to block this 5-V V_BUSfrom entering the system

when it is unplugged from the wall. If this is maintained, there is not any issue. Once, the wall adaptor is plugged

into the wall, it turns ON the TPD2S300. This removes the TPD2S300's RD dead battery resistor, and then the

laptop stops sourcing V_BUS. Once the laptop starts its DRP toggle, it exposes its RD, which causes a connection

with the wall adaptor to occur, and the wall adaptor outputs V_BUS, and then PD is negotiated like normal.

8.2.3.2.3 CC Line Capacitance

USB PD has a specification for the total amount of capacitance that is required for proper USB PD BMC

operation on the CC lines. The specification from section 5.8.6 of the USB PD Specification is given in 表 10.

表 10. USB PD cReceiver Specification

NAME

DESCRIPTION

MIN

MAX UNIT

COMMENT

The DFP or UFP system shall have

capacitance within this range when

not transmitting on the line

cReceiver

CC receiver capacitance

200

600 pF

Therefore, the capacitance on the CC lines must stay in between 200 pF and 600 pF when USB PD is being

used. Therefore, the combination of capacitances added to the system by the TPS25740, the TPD2S300, and

any external capacitor must fall within these limits. 表 11 shows the analysis involved in choosing the correct

external CC capacitor for this system, and shows that an external CC capacitor is required.

表 11. CC Line Capacitor Calculation

CC Capacitance

MIN

MAX

UNIT

COMMENT

From the USB PD Specification section

(cReceiver, section 5.8.6)

CC line target capacitance

200

600

TPS25740 capacitance

TPD2S300 capacitance

From the TPS25740 Datasheet

120

From the Electrical Characteristics table

CAP, CERM, 330 pF, 25 V, ±10%, X7R,

0201 (For min and max, assume ±40%

capacitance change with temperature and

voltage derating to be overly conservative)

Proposed capacitor GRM033R71E331KA01D

198

228

462

592

TPS25740 + TPD2S300 +

GRM033R71E331KA01D

Meets USB PD cReceiver specification

TPD2S300

ZHCSGS3 –APRIL 2017

www.ti.com.cn

8.2.3.2.4 FLT Pin Operation

The FLT pin recommendation for this application are identical to the Smart-Phone application; see the FLT Pin

Operation section for more details.

8.2.3.2.5 V_CONNOperation

In our current application example, V_CONNis not required. Therefore, a 3.3-V source or 5-V source can be

connected to the VPWR and VM pins of the TPD2S300 to provide adequate resistance in order to support CC

analog and USB PD operation over the CC lines. In fact, the CC OVP FETs resistance specifications are set to

optimize the FET size and therefore the TPD2S300 size and still allow proper CC analog and USB PD operation.

See the Electrical Characteristics table for the specific resistances of the CC OVP FETs.

8.2.3.3 Application Curves

图 26. TPD2S300 Turning On in Dead Battery Mode With 5.1-kΩ on CC1

TPD2S300

www.ti.com.cn

ZHCSGS3 –APRIL 2017

9 Power Supply Recommendations

The VPWR pin provides power to all the circuitry in the TPD2S300. It is recommended a 1-µF decoupling

capacitor is placed as close as possible to the VPWR pin. If USB PD is desired to be operated in dead battery

conditions, it is critical that the TPD2S300 share the same power supply as the PD controller in dead battery

boot-up (such as sharing the same dead battery LDO). See the CC Dead Battery Resistors Integrated for

Handling Dead Battery Use Case in Mobile Devices section for more details.

The VM pin is used to control the resistance of the CC OVP FETs. If only CC analog and PD communications

are needed over the CC lines, short this pin to VPWR, and no extra capacitor is needed. However, if wanting to

use V_CONNon CC, and the lower resistance operation of the TPD2S300 is needed, then VM needs to be

connected to its own independent voltage source that is ≥ 9 V and ≤ 22 V. This is usually the 3S or 4S battery in

the system. If connected to its own independent voltage source, then VM with need its own 1-µF decoupling

capacitor; it is recommended to place this capacitor as close as possible to the VM pin.

TPD2S300

ZHCSGS3 –APRIL 2017

www.ti.com.cn

10 Layout

10.1 Layout Guidelines

Proper routing and placement is important to maintain the signal integrity the CC line signals. The following

guidelines apply to the TPD2S300:

•

Place the bypass capacitors as close as possible to the V_PWRand V_Mpins, and ESD protection capacitor as

close as possible to the V_BIASpin. Capacitors must be attached to a solid ground. This minimizes voltage

disturbances during transient events such as short-to-V_BUSand ESD strikes.

Standard ESD recommendations apply to the C_CC1 and C_CC2 pins:

•

The optimum placement for the device is as close to the connector as possible:

–

EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,

resulting in early system failures.

–

The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away

from the protected traces which are between the TPD2S300 and the connector.

•

Route the protected traces as straight as possible.

Eliminate any sharp corners on the protected traces between the TPD2S300 and the connector by using

rounded corners with the largest radii possible.

–

Electric fields tend to build up on corners, increasing EMI coupling.

10.2 Layout Example

图 27. TPD2S300 Typical Layout

TPD2S300

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ZHCSGS3 –APRIL 2017

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

请参阅如下相关文档：

《TPD2S300YFF 评估模块》

11.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

TPD2S300

ZHCSGS3 –APRIL 2017

www.ti.com.cn

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知

和修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPD2S300YFFR

ACTIVE

DSBGA

YFF

3000 RoHS & Green

SNAGCU

Level-1-260C-UNLIM

-40 to 85

17W

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Dec-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPD2S300YFFR

DSBGA

YFF

3000

180.0

8.4

1.45

0.8

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Dec-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

DSBGA YFF

SPQ

Length (mm) Width (mm) Height (mm)

182.0 182.0 20.0

TPD2S300YFFR

3000

Pack Materials-Page 2

PACKAGE OUTLINE

YFF0009

DSBGA - 0.625 mm max height

SCALE 10.000

DIE SIZE BALL GRID ARRAY

BALL A1

CORNER

0.625 MAX

SEATING PLANE

0.05 C

0.30

0.12

BALL TYP

0.8 TYP

SYMM

0.8

D: Max = 1.39 mm, Min = 1.33 mm

E: Max = 1.39 mm, Min = 1.33 mm

TYP

0.4 TYP

0.3

0.2

SYMM

0.015

C A B

0.4 TYP

4219552/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

YFF0009

DSBGA - 0.625 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

9X ( 0.23)

(0.4) TYP

SYMM

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MAX

0.05 MIN

METAL UNDER

SOLDER MASK

(

0.23)

METAL

(

0.23)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

NON-SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4219552/A 05/2016

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information,

see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

YFF0009

DSBGA - 0.625 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

(R0.05) TYP

9X ( 0.25)

(0.4) TYP

SYMM

METAL

TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:30X

4219552/A 05/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPD2S300YFFR [TI]

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TPD2S701QDGSRQ1

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TPD2S703QDGSRQ1

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TPD2XGKZRC00016G

TPD2XGKZRC00017G

TPD2XGKZRC00018G

TPD2XGKZRC00019G

TPD2XGKZRC00020G

TPD2XGKZRC00021G