TPD3S713QRVCRQ1 [TI]

Automotive USB 0.05-A to 0.6-A adjustable current limit and VBUS/D+/D- short-to-VBATT protection | RVC | 20 | -40 to 125;


型号：	TPD3S713QRVCRQ1
厂家：	TEXAS INSTRUMENTS
描述：	Automotive USB 0.05-A to 0.6-A adjustable current limit and VBUS/D+/D- short-to-VBATT protection \| RVC \| 20 \| -40 to 125
文件：	总38页 (文件大小：2795K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPD3S713-Q1, TPD3S713A-Q1

ZHCSLC3B –MAY 2020 –REVISED APRIL 2023

TPD3S713-Q1 和TPD3S713A-Q1 具有可调节限流和V_BATT短接保护功能的汽车

类USB 2.0 接口保护器件

1 特性

3 说明

• 符合面向汽车应用的AEC-Q100 标准：

TPD3S713x-Q1 是一款单芯片解决方案，在汽车 USB

集线器、音响主机、远程信息处理和媒体接口应用中为

高速数据和电力线提供电池短路、短路和 ESD 保护。

集成的数据开关提供了同类最佳的带宽，能够在 USB

发生电池短路时最大限度地减少信号衰减。高达

1.2GHz 的带宽可利用汽车 USB 环境中常见的长系留

线缆来实现干净的USB 2.0 高速480Mbps 眼图。

– 器件温度等级1：–40°C 至+125°C 环境工作

温度范围

– 器件HBM ESD 分类等级H2

– 器件CDM ESD 分类等级C5

• V_BUS引脚上的电池短路保护（高达18V）和接地短

路保护功能

• DM_IN、DP_IN 引脚上的电池短路保护（高达

18V）和V_BUS短路保护功能

• 符合IEC 61000-4-2 标准的DP_IN、DM_IN 和

电池短路保护可隔离内部系统电路，防止其受到

V_BUS、DP_IN 和 DM_IN 引脚上任何过压情况的影

响。在这些引脚上，TPD3S713x-Q1 可处理热插拔和

直流事件高达 18V 的过压，并关闭内部开关，保护上

游收发器免受有害电压和电流尖峰的影响。

V_BUS

– ±8kV 接触放电和±15kV 空气放电

• 符合ISO 10605（330pF，330Ω）标准的

DP_IN、DM_IN 和V_BUS

V_BUS引脚还提供灵活的可调节限流负载开关（从

50mA 到 600mA），如果端口只需要数十毫安的电

流，可节省系统功率预算。

– ±8kV 接触放电和±15kV 空气放电

• 高速数据开关（1230MHz 带宽）

• 4.5V 至5.5V 输入电压工作范围

• 50mA 至600mA 可调节电流限值（200mA 时精度

为±13.5%）

TPD3S713x-Q1 器件具有一个能够控制上行电源的电

流检测输出，因此可在连接长 USB 电缆的远程 USB

端口保持5V 的电压。

• 集成73mΩ（典型值）高侧MOSFET

• 500mA 最大连续输出电流

• V_BUS电缆补偿

封装信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

TPD3S713x-Q1

WQFN (20)

4.00mm × 3.00mm

• 20 引脚QFN (3mm × 4mm) 封装

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 汽车USB 接口

– 音响主机

– 远程信息处理

– 导航模块

• 汽车USB 充电端口

– 媒体接口

TPD3S713x-Q1

BUS

VBUS

D-

DM_IN

DP_IN

DM_OUT

DP_OUT

D+

GND

ILIM_SEL

BIAS

ILIM_SEL

FAULT1

FAULT

INT1

ILIM_LO

ILIM_HI

Up-stream DC-DC

ADC

IMON

GND

Rlim_Hi

Rlim_Lo

INT2

原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSDH1

TPD3S713-Q1, TPD3S713A-Q1

ZHCSLC3B –MAY 2020 –REVISED APRIL 2023

www.ti.com.cn

Table of Contents

8.3 Feature Description...................................................16

8.4 Device Functional Modes..........................................21

9 Application and Implementation..................................22

9.1 Application Information............................................. 22

9.2 Typical Application.................................................... 22

9.3 Power Supply Recommendations.............................26

9.4 Layout....................................................................... 26

10 Device and Documentation Support..........................29

10.1 Documentation Support.......................................... 29

10.2 接收文档更新通知................................................... 29

10.3 支持资源..................................................................29

10.4 Trademarks.............................................................29

10.5 静电放电警告.......................................................... 29

10.6 术语表..................................................................... 29

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Switching Characteristics............................................8

6.7 Typical Characteristics................................................9

7 Parameter Measurement Information..........................14

8 Detailed Description......................................................15

8.1 Overview...................................................................15

8.2 Functional Block Diagram.........................................16

Information.................................................................... 29

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (February 2022) to Revision B (April 2023)

Page

• 向数据表添加了 TPD3S713A-Q1....................................................................................................................... 1

• 通篇将TPD3S713-Q1 更改为TPD3S713x-Q1（如果适用）............................................................................ 1

• Added the TPD3S713A-Q1 Fault behavior in Fault Conditions section........................................................... 16

• Added the TPD3S713A-Q1 DP_IN or DM_IN OVP behavior in Output and DP or DM Discharge section......19

Changes from Revision * (May 2020) to Revision A (February 2022)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 为ESD 等级增加了 ISO 10605（330pF，330Ω）............................................................................................1

English Data Sheet: SLUSDH1

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ZHCSLC3B –MAY 2020 –REVISED APRIL 2023

www.ti.com.cn

5 Pin Configuration and Functions

BUS

IMON

14 DM_IN

13 DP_IN

Thermal Pad

DM_OUT

DP_OUT

BIAS

GND

图5-1. RVC Package 20-Pin WQFN Top View

表5-1. Pin Functions

NAME

TYPE⁽¹⁾

DESCRIPTION

NO.

This pin sources a scaled-down ratio of current through the internal FET. A resistor from this pin to

GND converts current to proportional voltage; used as an analog current monitor.

IMON

Input supply voltage; connect a 0.1-µF or greater ceramic capacitor from IN to GND as close to the

IC as possible.

2,3

PWR

DM_OUT

DP_OUT

I/O

DM data line to upstream USB host controller

DP data line to upstream USB host controller

Linear cable compensation current. Connect to divider resistor of front-end dc-dc converter.

Logic-level control input for turning the power and signal switches on or off. When EN is low, the

device is disabled, and the signal and power switches are OFF.

Logic-level control input for choosing the current limit resistor and current limit threshold. When

ILIM_SEL = High, ILIM_HI resistor is valid; When ILIM_SEL = Low, ILIM_LO resistor is valid.

ILIM_SEL

Logic-level control input, the device can be set in normal mode or client mode through pin

configuration. If INT1 = high, the device is in normal mode; If INT1 = low and ILIM_SEL = Low, the

device is in client mode.

INT1

INT2

GND

BIAS

DP_IN

DM_IN

BUS

For internal circuit, must connect to ground without a pull down resistor.

Ground connection; must be connected externally to the thermal pad.

Used for IEC protection. Typically, connect a 2.2-µF capacitor to ground and 5.1-kΩresistor to BUS.

DP data line to downstream connector

—

PWR

I/O

DM data line to downstream connector

15,16

PWR

Power-switch output

No connect, leave floating or connect to ground.

Active-low, open-drain output, asserted during overtemperature, overcurrent, and overvoltage

conditions.

FAULT

ILIM_LO

ILIM_HI

External resistor used to set the low current-limit threshold, selected by ILIM_SEL pin.

External resistor used to set the high current-limit threshold, selected by ILIM_SEL pin.

Thermal pad on the bottom of the package

Thermal pad

—

(1) I = Input, O = Output, I/O = Input and output, PWR = Power

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English Data Sheet: SLUSDH1

TPD3S713-Q1, TPD3S713A-Q1

ZHCSLC3B –MAY 2020 –REVISED APRIL 2023

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

Voltages are with respect to GND unless otherwise noted⁽¹⁾

MIN

MAX

UNIT

Voltage range

CS, ILIM_SEL, INT1, EN, FAULT, ILIM_HI, ILIM_LO,

–0.3

IN, IMON, INT2

DM_OUT, DP_OUT

5.7

–0.3

–100

BIAS, DM_IN, DP_IN, VBUS

Continuous current

DM_IN to DM_OUT or DP_IN to DP_OUT

100

IBUS

Internally limited

Continuous output source current, I_SRC

Continuous output sink current, I_SNK

ILIM_HI, LIM_LO, IMON

FAULT

Internally limited

Operating junction temperature, T_J

Storage temperature,T_stg

150

°C

–40

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

VALUE

±2000⁽²⁾

±750⁽³⁾

±8000

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

IEC 61000-4-2 contact discharge

IEC 61000-4-2 air di scharge

DP_IN, DM_IN and V_BUSpins⁽⁴⁾

±15000

Electrostatic

discharge

V_(ESD)

ISO 10605 (330 pF, 330 Ω),

contact discharge

DP_IN, DM_IN and V_BUSpins⁽⁵⁾

±8000

ISO 10605 (330 pF, 330 Ω), air

discharge

DP_IN, DM_IN and V_BUSpins⁽⁵⁾

±15000

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) The passing level per AEC-Q100 Classification H2.

(3) The passing level per AEC-Q100 Classification C5.

(4) Surges per IEC 61000-4-2, level 4, 1999 applied from DP_IN, DM_IN and V_BUSto output ground of the TPD3S713Q1EVM-103

evaluation module.

(5) Surges per ISO 10605 (330 pF, 330 Ω), applied from DP_IN, DM_IN and V_BUSto output ground of the TPD3S713Q1EVM-103

evaluation module.

6.3 Recommended Operating Conditions

Voltages are with respect to GND unless otherwise noted.

MIN

4.5

NOM

MAX

5.5

3.6

500

UNIT

V_(IN)

Supply voltage

Input voltage

EN, ILIM_SEL, INT1, INT2

DM_IN, DM_OUT, DP_IN, DP_OUT

IBUS

I_(BUS)

Output continuous current

kΩ

°C

DM_IN to DM_OUT or DP_IN to DP_OUT

FAULT

–30

Continuous output sink current

R_{(ILIM_xx)}Current-limit-set resistors

6.98

100

125

T_J

Operating junction temperature

–40

English Data Sheet: SLUSDH1

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ZHCSLC3B –MAY 2020 –REVISED APRIL 2023

www.ti.com.cn

6.4 Thermal Information

TPD3S713x-Q1

THERMAL METRIC⁽¹⁾

RVC (WQFN)

20 PINS

37.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

39.9

11.9

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

ψ_JT

11.8

ψ_JB

R_θJC(bot)

3.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

Unless otherwise noted, –40°C ≤T_J≤125°C and 4.5 V ≤V_(IN)≤5.5 V, V_(EN)= V_(INT1)= V_{(ILIM_SEL)}= V_(IN), V_(INT2)= GND,

R_(FAULT)= 10 kΩ, R_(IMON)= 2.55 kΩ, R_{(ILIM_HI)}= 52.3 kΩ. Positive currents are into pins. Typical values are at T_J= 25°C. All

voltages are with respect to GND.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

OUT –POWER SWITCH

T_J= 25°C

r_DS(on)

On-resistance⁽¹⁾

mΩ

120

–40°C ≤T_J≤125°C

V_BUS= 5 V, V_IN= V_EN= 0 V, –40°C ≤T_J≤

125°C, measure I_(IN)

I_lkg

Reverse leakage current

0.01

µA

OUT –DISCHARGE

Discharge resistance

(ILIM_SEL change)

R_(DCHG)

400

500

630

ENABLE, ILIM_SEL, INT1, INT2 INPUTS

Input pin rising logic

threshold voltage

0.8

0.7

1.35

Input pin falling logic

threshold voltage

1.15

200

1.65

Hysteresis⁽²⁾

µA

Input current

Pin voltage = 0 V or 5.5 V

–1

CURRENT LIMIT

102

R_{ILIM_HI}or R_{ILIM_LO}= 80.6 kΩ

R_{ILIM_HI}or R_{ILIM_LO}= 52.3 kΩ

R_{ILIM_HI}or R_{ILIM_LO}= 22.1 kΩ

R_{ILIM_HI}or R_{ILIM_LO}= 15.4 kΩ

R_{ILIM_HI}or R_{ILIM_LO}= 6.98 kΩ

R_{ILIM_HI}Shorted to GND

166

245

560

860

192

275

600

1150

218

VBUS short-circuit current

limit

I_OS

305

640

1440

R_{ILIM_HI}Shorted to GND

V_(EN)= 0 V, V_(BUS)= 0 V, –40°C ≤T_J≤125°C,

no 5.1-kΩ resistor (open) between BIAS and

VBUS

I_{(IN_OFF)}

I_{(IN_ON)}

Disabled IN supply current

Enabled IN supply current

0.1

µA

V_(INT1)= V_{(ILIM_SEL)}= High

200

280

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English Data Sheet: SLUSDH1

TPD3S713-Q1, TPD3S713A-Q1

ZHCSLC3B –MAY 2020 –REVISED APRIL 2023

www.ti.com.cn

6.5 Electrical Characteristics (continued)

Unless otherwise noted, –40°C ≤T_J≤125°C and 4.5 V ≤V_(IN)≤5.5 V, V_(EN)= V_(INT1)= V_{(ILIM_SEL)}= V_(IN), V_(INT2)= GND,

R_(FAULT)= 10 kΩ, R_(IMON)= 2.55 kΩ, R_{(ILIM_HI)}= 52.3 kΩ. Positive currents are into pins. Typical values are at T_J= 25°C. All

voltages are with respect to GND.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

UNDERVOLTAGE LOCKOUT, IN

IN rising

IN falling

3.9

3.3

4.1

3.5

4.3

3.7

V_(UVLO)

FAULT

UVLO threshold voltage

Output low voltage

Off-state leakage

I_(FAULT)= 1 mA

V_(FAULT)= 5.5 V

100 mV

µA

THERMAL SHUTDOWN

T_(OTSD2)Thermal shutdown threshold

155

135

°C

Thermal shutdown threshold

in current-limit

T_(OTSD1)

Hysteresis⁽³⁾

DM_IN AND DP_IN OVERVOLTAGE PROTECTION

V_{(OV_Data)}

Protection trip threshold

Hysteresis⁽³⁾

DP_IN and DM_IN rising

3.3

3.9

100

200

370

390

4.15

DP_IN = DM_IN = 18 V, IN = 5 V or 0 V

DP_IN = DM_IN = 5 V, IN = 5 V

DP_IN = DM_IN = 5 V, IN = 0

Discharge resistor after

OVP(3)

R_{(DCHG_Data)}

kΩ

BUS OVERVOLTAGE PROTECTION

V_{(OV_BUS)}

Protection trip threshold

Hysteresis⁽³⁾

VBUS rising

5.65

190

6.35

VBUS = 18 V, IN = 5 V

VBUS = 18 V, IN = 0

R_{(DCHG_BUS)}

Discharge resistor

kΩ

120

CABLE COMPENSATION

I_(CS)Sink current

210

230

µA

Load = 0.5 A, 2.5 V ≤V_(CS)≤5.5 V

English Data Sheet: SLUSDH1

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6.5 Electrical Characteristics (continued)

Unless otherwise noted, –40°C ≤T_J≤125°C and 4.5 V ≤V_(IN)≤5.5 V, V_(EN)= V_(INT1)= V_{(ILIM_SEL)}= V_(IN), V_(INT2)= GND,

R_(FAULT)= 10 kΩ, R_(IMON)= 2.55 kΩ, R_{(ILIM_HI)}= 52.3 kΩ. Positive currents are into pins. Typical values are at T_J= 25°C. All

voltages are with respect to GND.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

CURRENT MONITOR OUTPUT (IMON)

I_(IMON)

Source current

245

265

285

µA

Load = 0.5 A, 0 ≤V_(IMON)≤2.5 V

HIGH-BANDWIDTH ANALOG SWITCH

V_{(DP_OUT)}= V_{(DM_OUT)}= 0 V, I_{(DP_IN)}= I_{(DM_IN)}= 30

3.2

3.8

6.5

7.6

DP and DM switch on-

resistance

R_{(HS_ON)}

V_{(DP_OUT)}= V_{(DM_OUT)}= 2.4 V, I_{(DP_IN)}= I_{(DM_IN)}

–15 mA

V_{(DP_OUT)}= V_{(DM_OUT)}= 0 V, I_{(DP_IN)}= I_{(DM_IN)}= 30

0.05

8.8

0.15

Switch resistance mismatch

between DP and DM

channels

|ΔR_{(HS_ON)}

V_{(DP_OUT)}= V_{(DM_OUT)}= 2.4 V, I_{(DP_IN)}= I_{(DM_IN)}

–15 mA

DP and DM switch off-state V_EN= 0 V, V_{(DP_IN)}= V_{(DM_IN)}= 0.3 V, Vac = 0.03

capacitance⁽⁴⁾

V_PP, f = 1 MHz

C_{(IO_OFF)}

C_{(IO_ON)}

DP and DM switch on-state V_{(DP_IN)}= V_{(DM_IN)}= 0.3 V, Vac = 0.03 V_PP, f = 1

10.9

capacitance⁽⁴⁾

MHz

Off-state isolation(4)

V_(EN)= 0 V, f = 250 MHz

On-state cross-channel

isolation⁽⁴⁾

f = 250 MHz

V_EN= 0 V, V_{(DP_IN)}= V_{(DM_IN)}= 3.6 V, V_{(DP_OUT)}

V_{(DM_OUT)}= 0 V, measure I_{(DP_OUT)}and I_{(DM_OUT)}

I_lkg(OFF)

Off-state leakage current

0.1

1.5

µA

Bandwidth (–3 dB)⁽⁴⁾

R_(L)= 50 Ω

1230

MHz

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account

separately.

(2) This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's

product warranty.

(3) This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's

product warranty.

(4) This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's

product warranty.

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English Data Sheet: SLUSDH1

TPD3S713-Q1, TPD3S713A-Q1

ZHCSLC3B –MAY 2020 –REVISED APRIL 2023

www.ti.com.cn

6.6 Switching Characteristics

Unless otherwise noted, –40°C ≤T_J≤125°C and 4.5 V ≤V_(IN)≤5.5 V, V_(EN)= V_(INT1)= V_{(ILIM_SEL)}= V_(IN), V_(INT2)= GND,

R_(FAULT)= 10 kΩ, R_(IMON)= 2.55 kΩ, R_{(ILIM_HI)}= 52.3 kΩ. Positive currents are into pins. Typical values are at T_J= 25°C. All

voltages are with respect to GND.

PARAMETER

TEST CONDITIONS

MIN

1.05

0.27

TYP

1.75

0.47

7.5

MAX UNIT

t_r

BUS voltage rise time

BUS voltage fall time

BUS voltage turn-on time

BUS voltage turn-off time

3.1

0.82

V_(IN)= 5 V, C_(L)= 1 µF, R_(L)= 100 Ω

t_f

t_on

t_off

V_(IN)= 5 V, C_(L)= 1 µF, R_(L)= 100 Ω

2.7

Discharge hold time

(ILIM_SEL change)

t_{(DCHG_S)}

t_(IOS)

t_{(OC_BUS_FAULT)}

t_pd

Time V_(OUT)< 0.7V

1.1

5.5

2.9

BUS short-circuit response

time⁽¹⁾

µs

V_(IN)= 5 V, R_(SHORT)= 50 mΩ

Bidirectional deglitch applicable to current-limit

condition only (no deglitch assertion for OTSD)

BUS FAULT deglitch time

8.5

0.14

11.5

Analog switch propagation

delay ⁽¹⁾

V_(IN)= 5 V

Analog switch skew

between opposite transitions

t_(SK)

V_(IN)= 5 V

0.02

µs

of the same port (t_PHL

–

(1)

t_PLH

)

DP_IN and DM_IN

overvoltage protection

response time

t_{(OV_Data)}

BUS overvoltage protection

response time

t_{(OV_BUS)}

0.3

µs

DP_IN and DM_IN FAULT-

asserted degltich time

t_{(OV_Data_FAULT)}

BUS FAULT-asserted

degltich time

(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's

product warranty.

English Data Sheet: SLUSDH1

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6.7 Typical Characteristics

T_A= 25°C, V_(IN)= 5 V, V_(EN)= V_(IN), V_{(ILIM_SEL)}= V_(INT1)= V_(IN), V_(INT2)= GND, FAULT connect to V_(IN)via a 10-kΩpullup

resistor (unless stated otherwise)

105

100

41.8

41.6

41.4

41.2

40.8

40.6

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (èC)

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (èC)

V_(IN)= 5 V

V_(OUT)= 5 V

Measure I_(BUS)

图6-1. Power Switch On-Resistance vs Temperature

图6-2. Reverse Leakage Current vs Temperature

100

570

V_IN=5 V

V_IN=0 V

V_IN=4.5 V

V_IN=5 V

V_IN=5.5 V

560

550

540

530

520

510

500

490

480

-25 -10

95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (èC)

图6-3. BUS Discharge Resistance (OVP) vs Temperature

图6-4. BUS Discharge Resistance (Mode Change) vs

Temperature

600

RILIM_HI=15.5 K

RILIM_HI=80.6 K

500

RILIM_HI=22.1 K

RILIM_HI=52.3 K

RILIM_HI=7.3 K

400

300

200

100

-2

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (èC)

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (èC)

V_(IN)= 5 V

ILIM_SEL = High

图6-5. VBUS Short-Circuit Current Limit vs Temperature

图6-6. Disabled IN Supply Current vs Temperature

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6.7 Typical Characteristics (continued)

T_A= 25°C, V_(IN)= 5 V, V_(EN)= V_(IN), V_{(ILIM_SEL)}= V_(INT1)= V_(IN), V_(INT2)= GND, FAULT connect to V_(IN)via a 10-kΩpullup

resistor (unless stated otherwise)

205

195

185

175

165

155

4.2

4.1

3.9

3.8

3.7

3.6

V_IN=4.5 V

V_IN=5.0 V

V_IN=5.5 V

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (èC)

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (èC)

ILIM_SEL = High

V_(IN)= 5 V

图6-7. Enabled IN Supply Current vs Temperature

图6-8. DP_IN Overvoltage Protection Threshold vs Temperature

6.3

300

6.2

6.1

250

200

150

100

5.9

5.8

5.7

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (Cè)

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (èC)

V_(IN)= 5 V

I_BUS= 0.5 A

V_(CS)= 2.5 V

图6-9. BUS Overvoltage Protection Threshold vs Temperature

图6-10. I_(CS)vs Temperature

210.6

266

265.75

265.5

265.25

265

Vcs = 2.5 V

Vcs = 5.5 V

Vcs = 3.5 V

V_IN=4.5 V

V_IN=5.0 V

V_IN=5.5 V

210.4

210.2

210

209.8

209.6

209.4

209.2

209

264.75

264.5

264.25

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (èC)

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (èC)

V_IN= 5.5 V

I_BUS= 0.5 A

V_(IMON)= 2.5 V

图6-11. I_(CS)vs V_(CS)Voltage

图6-12. I_(IMON)vs Temperature

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6.7 Typical Characteristics

T_A= 25°C, V_(IN)= 5 V, V_(EN)= V_(IN), V_{(ILIM_SEL)}= V_(INT1)= V_(IN), V_(INT2)= GND, FAULT connect to V_(IN)via a 10-kΩpullup

resistor (unless stated otherwise)

265.75

Vcs = 2 V

Vcs = 1 V

Vcs = 0 V

265.5

265.25

265

264.75

264.5

264.25

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (èC)

V_IN= 4.5 V

I_BUS= 0.5 A

图6-13. I_(IMON)vs V_(CS)Voltage

Measured on EVM with 10-cm cable

图6-14. Bypassing the TPD3S713-Q1 Data Switch

图6-15. Through the TPD3S713-Q1 Data Switch

C_(LOAD)= 10 µF

t = 5 ms/div

C_(LOAD)= 10 µF

图6-17. Turn-off Response

t = 5 ms/div

R_(LOAD)= 68 Ω

图6-16. Turn-on Response

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6.7 Typical Characteristics (continued)

T_A= 25°C, V_(IN)= 5 V, V_(EN)= V_(IN), V_{(ILIM_SEL)}= V_(INT1)= V_(IN), V_(INT2)= GND, FAULT connect to V_(IN)via a 10-kΩpullup

resistor (unless stated otherwise)

R_{(ILIM_LO)}= 80.6

t = 5 ms/div

R_{(ILIM_HI)}= 80.6 kΩ

kΩ

图6-19. Short Circuit to No Load

图6-18. Enable Into Short

t = 5 ms/div

t =5 ms/div

R_{(ILIM_HI)}= 52.3 kΩ R(short) = 50 mΩ

图6-20. Hot Short

图6-21. VBUS Short-to-Battery

t = 20 ms/div

t = 5 ms/div

图6-22. VBUS Short-to-Battery Recovery

图6-23. DP_IN Short-to-Battery

English Data Sheet: SLUSDH1

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6.7 Typical Characteristics (continued)

T_A= 25°C, V_(IN)= 5 V, V_(EN)= V_(IN), V_{(ILIM_SEL)}= V_(INT1)= V_(IN), V_(INT2)= GND, FAULT connect to V_(IN)via a 10-kΩpullup

resistor (unless stated otherwise)

t = 5 ms/div

t = 20 ms/div

图6-24. DP_IN Short-to-Battery Recovery

R_(BIAS)= 5.1 kΩ

图6-25. DP_IN Short-to-V_BUS

t = 2 ms/div

R_(BIAS)= 5.1 kΩ

图6-27. Data Transmission Characteristics vs Frequency

图6-26. DP_IN Short-to-V_BUSand Recovery

图6-28. Off-State Data-Switch Isolation vs Frequency

图6-29. On-State Cross-Channel Isolation vs Frequency

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7 Parameter Measurement Information

图7-1. Short-to-Battery System Test Setup

English Data Sheet: SLUSDH1

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8 Detailed Description

8.1 Overview

The TPD3S713x-Q1 is a single-chip solution for short-to-battery, short-circuit, and ESD protection for high speed

data and power lines in automotive USB hub, head unit, telematics, and media interface applications. The

integrated data switches provide best-in-class bandwidth for minimal signal degradation during USB short-to-

battery events. The high bandwidth allows for a clean USB2.0 high-speed eye diagram which helps pass

stringent USB certification tests in the automotive USB environment.

The short-to-battery protection isolates the internal system circuits from any overvoltage conditions at the V_BUS

DP_IN, and DM_IN pins. On these pins, the TPD3S713x-Q1 can handle overvoltages up to 18 V for hot plug

and DC events. This feature protects the upstream voltage regulator, automotive processor, and hub when these

pins are exposed to fault conditions.

The V_BUSpin also provides an accurate current limited load switch from 55 mA to 600 mA. The leading

overcurrent protection automatically limits current to prevent drooping of the upstream rail during short-to-ground

events. Also TPD3S713x-Q1 can save power budget for the whole system.

The TPD3S713x-Q1 device integrates a cable compensation (CS) feature to compensate for long-cable voltage

drop. This feature keeps the remote USB port output voltage constant to enhance the user experience under

high-current charging conditions.

The TPD3S713x-Q1 device provides a current-monitor function (IMON) by connecting a resistor from the IMON

pin to GND to provide a positive voltage linearly with load current. This connection can be used for system power

or dynamic power management.

Additionally, the device provides ESD protection up to ±8 kV (contact discharge) and ±15 kV (air discharge) per

IEC 61000-4-2 on DP_IN and DM_IN.

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8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 FAULT Response

The device features an active-low, open-drain fault output. FAULT goes low when there is a fault condition. Fault

detection includes overtemperature, overcurrent, or overvoltage on V_BUS, DP_IN and DM_IN. Connect a 10-kΩ

pullup resistor from FAULT to IN.

表8-1 summarizes the conditions that generate a fault and actions taken by the device.

English Data Sheet: SLUSDH1

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表8-1. Fault Conditions

EVENT

CONDITION

TPD3S713-Q1

TPD3S713A-Q1

The device immediately shuts off the

USB data switches and the internal

V_{(DP_IN)}or V_{(DM_IN)}> 3.9 V power switch. The fault indicator asserts power switch keeps turn on. The fault

The device immediately shuts off the

USB data switches, and the internal

Overvoltage on the data

lines

with a 16-ms deglitch, and deasserts

without deglitch.

indicator asserts with a 16-ms deglitch,

and deasserts without deglitch.

The device immediately shuts off the

internal power switch and the USB data internal power switch and the USB data

Overvoltage on V_(BUS)

Overcurrent on V_(BUS)

V_(BUS)> 6 V

switches. The fault indicator asserts

with a 16-ms deglitch and deasserts

without deglitch.

switches. The fault indicator asserts

with a 16-ms deglitch and deasserts

without deglitch.

The device regulates switch current at

I_(OS)until thermal cycling occurs. The

fault indicator asserts and deasserts

with an 8-ms deglitch.

The device regulates switch current at

I_(OS)until thermal cycling occurs. The

fault indicator asserts and deasserts

with an 8-ms deglitch.

I_(BUS)> I_(OS)

The device immediately shuts off the

internal power switch and the USB data internal power switch and the USB data

switches. The fault indicator asserts

immediately when the junction

temperature exceeds OTSD2 or OTSD1 temperature exceeds OTSD2 or OTSD1

while in a current-limiting condition. The while in a current-limiting condition. The

switches. The fault indicator asserts

immediately when the junction

T_J> OTSD2 in non-current-

limited or T_J> OTSD1 in

current-limited mode.

Overtemperature

device has a thermal hysteresis of

20°C.

device has a thermal hysteresis of

20°C.

8.3.2 Cable Compensation

When a load draws current through a long or thin wire, there is an IR drop that reduces the voltage delivered to

the load. In the vehicle from the voltage regulator 5-V output to the loading, the total resistance of power switch

r_DS(on)and cable resistance causes an IR drop at the loading input. So the charging current of most portable

devices is less than their expected maximum charging current.

图8-1. Voltage Drop

The TPD3S713-Q1 device detects the load current and applies a proportional sink current that can be used to

adjust the output voltage of the upstream regulator to compensate for the IR drop in the charging path. The gain

G_(CS)of the sink current proportional to load current is 420 µA/A.

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图8-2. Cable Compensation Equivalent Circuit

8.3.2.1 Design Procedure

To start the procedure, the total resistance, including the power switch r_DS(on)and wire resistance R_(WIRE), must

be known.

1. Choose R_(G)following the voltage-regulator feedback resistor-divider design guideline.

2. Calculate R_(FA)according to 方程式1.

R_FA= (r_DS(on)+ R_(WIRE)) / G_(CS)

(1)

3. Calculate R_(FB)according to 方程式2.

(OUT)

R_(FB)

- R_(G)- R_(FA)

/ R_(G)

(FB)

(2)

4. C_(COMP)in parallel with R_(FA)is required to stabilize V_(OUT)when C_(BUS)is large. Start with C_(COMP)≥3 ×

G_(CS)× C_(OUT), then adjust C_(COMP)to optimize the load transient of the voltage regulator output. V_(OUT)

stability must always be verified in the end application circuit.

8.3.3 DP and DM Protection

DP and DM protection consists of ESD and OVP (overvoltage protection). The DP_IN and DM_IN pins provide

ESD protection up to ±15 kV (air discharge) and ±8 kV (contact discharge) per IEC 61000-4-2 (see the ESD

Ratings section for test conditions).

The ESD stress seen at DP_IN and DM_IN is impacted by many external factors, like the parasitic resistance

and inductance between ESD test points and the DP_IN and DM_IN pins. For air discharge, the temperature

and humidity of the environment can cause some difference, so the IEC performance must always be verified in

the end-application circuit.

The IEC ESD performance of the TPD3S713x-Q1 device depends on the capacitance connected from BIAS to

GND. TI recommends a 2.2-µF capacitor placed close to the BIAS pin. Connect the BIAS pin to BUS using a

5.1-kΩresistor as a discharge path for the ESD stress.

OVP protection is provided for short-to-V_BUSor short-to-battery conditions in the vehicle harness, preventing

damage to the upstream USB transceiver or hub. When the voltage on DP_IN or DM_IN exceeds 3.9 V (typical),

the TPD3S713x-Q1 device quickly responds to block the high-voltage reverse connection to DP_OUT and

DM_OUT. Overcurrent short-to-GND protection for DP and DM is provided by the upstream USB transceiver.

8.3.4 V_BUSOVP Protection

The TPD3S713x-Q1 BUS pin can withstand up to 18 V. The internal MOSFET turns off quickly when a short-to-

battery condition occurs.

The TPD3S713x-Q1 device OVP threshold is 6 V (typical).

English Data Sheet: SLUSDH1

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8.3.5 Output and DP or DM Discharge

When an OVP condition occurs on DP_IN or DM_IN, both TPD3S713x-Q1 devices enable an internal 200-kΩ

discharge resistance from DP_IN to ground, and from DM_IN to ground. The TPD3S713-Q1 turns off the power

switch and data switches. But the TPD3S713A-Q1 only turns off the data switches. Both TPD3S713x-Q1

devices automatically disable the discharge paths and turn on the switches after the OVP condition is removed.

When an OVP condition occurs on BUS, both TPD3S713x-Q1 devices turn on an internal discharge path (see 表

8-2 for the discharge resistance). The analog switches are also turned off. Both TPD3S713x-Q1 devices

automatically turn off the discharge path and turn on the analog switch after the OVP condition is removed.

表8-2. BUS Discharge Resistance

BUS DISCHARGE

VIN⁽¹⁾

EN⁽¹⁾

OVP⁽¹⁾

RESISTANCE⁽²⁾

—

80 kΩ

—

80 kΩ

500 Ω

55 kΩ

—

55 kΩ

(1) 0 = inactive, 1 = active

(2) —= no discharge resistance

8.3.6 Overcurrent Protection

When an overcurrent condition is detected, the device maintains a constant output current and reduces the

output voltage accordingly. Two possible overload conditions can occur. In the first condition, the output is

shorted before the device is enabled or before the application of V_(IN). The TPD3S713x-Q1 device senses the

short and immediately switches into a constant-current output. In the second condition, a short or an overload

occurs while the device is enabled. At the instant the overload occurs, high currents flow for 1 to 2 μs (typical)

before the current-limit circuit reacts. The device operates in constant-current mode after the current-limit circuit

has responded. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting.

The device remains off until the junction temperature cools approximately 20°C and then restarts. The device

continues to cycle on and off until the overcurrent condition is removed.

8.3.7 Undervoltage Lockout

The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO

turnon threshold. Built-in hysteresis prevents unwanted oscillations on the output due to input voltage drop from

large current surges.

8.3.8 Thermal Sensing

Two independent thermal-sensing circuits protect the TPD3S713x-Q1 device if the temperature exceeds

recommended operating conditions. These circuits monitor the operating temperature of the power-distribution

switch and disable operation. The power dissipation in the package is proportional to the voltage drop across the

power switch, so the junction temperature rises during an overcurrent condition. The first thermal sensor turns off

the power switch when the die temperature exceeds 135°C and the device is in current limit. The second thermal

sensor turns off the power switch when the die temperature exceeds 155°C regardless of whether the power

switch is in current limit. Hysteresis is built into both thermal sensors, and the switch turns on after the device

has cooled by approximately 20°C. The switch continues to cycle off and then on until the fault is removed. The

open-drain false-reporting output, FAULT, is asserted (low) during an overtemperature shutdown condition.

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8.3.9 Current-Limit Setting

The TPD3S713x-Q1 has two independent current-limit settings that are each adjusted externally with a resistor.

The ILIM_HI setting is adjusted with R_{(ILIM_HI)}connected between ILIM_HI and GND. The ILIM_LO setting is

adjusted with R_{(ILIM_LO)}connected between ILIM_LO and GND.

The current limit is selected by ILIM_SEL pin. If ILIM_SEL = high, ILIM_HI is selected; if ILIM_SEL = low,

ILIM_LO is selected.

The following equation calculates the value of resistor for adjusting the typical current limit (need update):

(3)

Many applications require that the current limit meet specific tolerance limits. When designing to these tolerance

limits, both the tolerance of the TPD3S713x-Q1 current limit and the tolerance of the external adjusting resistor

must be taken into account. The following equations approximate the TPD3S713x-Q1 minimum and maximum

current limits to within a few milliamperes and are appropriate for design purposes. The equations do not

constitute part of TI’s published device specifications for purposes of TI’s product warranty. These equations

assume an ideal—no variation—external adjusting resistor. To take resistor tolerance into account, first

determine the minimum and maximum resistor values based on its tolerance specifications and use these values

in the equations. Because of the inverse relation between the current limit and the adjusting resistor, use the

maximum resistor value in the I_OS(min)equation and the minimum resistor value in the I_OS(max)equation.

(4)

(5)

图8-3. Current-Limit Setting vs Adjusting Resistor

The routing of the traces to the R_{(ILIM_xx)}resistors must have a sufficiently low resistance so as not to affect the

current-limit accuracy. The ground connection for the R_{(ILIM_xx)}resistors is also very important. The resistors

must reference back to the TPD3S713x-Q1 GND pin. Follow normal board layout practices to ensure that

current flow from other parts of the board does not impact the ground potential between the resistors and the

TPD3S713x-Q1 GND pin.

English Data Sheet: SLUSDH1

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8.4 Device Functional Modes

8.4.1 Device Truth Table (TT)

The device truth table (表 8-3) lists all valid combinations for both ILIM_SEL and INT1 pins, and the

corresponding mode. The TPD3S713x-Q1 device monitors the INT1 and ILIMI_SEL input change, and there is

2s discharge on BUS pin during mode change.

表8-3. Truth Table

IMON FOR

CURRENT

MONITOR

CURRENT LIMIT

SELECTED

POWER

SWITCH

FAULT

REPORT

INT1

ILIM_SEL

MODE

DATA SWITCH

N/A

Client mode

OFF

ON⁽¹⁾

RESERVED, DO NOT USE

ILIM_LO

ILIM_HI

Normal mode

(1) In the client mode, the FAULT only reports in case of BUS,DP_IN and DM_IN OVP.

8.4.2 Client Mode

The TPD3S713x-Q1 device integrates client mode as shown in 图8-4. The internal power switch is OFF to block

current flow from BUS to IN, and the signal switches are ON. This mode can be used for software upgrades from

the USB port.

图8-4. Client-Mode Equivalent Circuit

In client mode, because the power switch is OFF, BUS must be 5 V so that the device can work normally (usually

properly.

8.4.3 High-Bandwidth Data-Line Switch

The DP and DM data lines pass through the device. A wide-bandwidth signal switch allows data to pass through

the device without corrupting signal integrity. The data-line switches are turned on in any of the operating modes.

The EN input must be at logic high for the data-line switches to be enabled.

备注

• While in client and normal mode, the data switches are ON.

• The data switches are only for the USB-2.0 differential pair. In the case of a USB-3.0 host, the

super-speed differential pairs must be routed directly to the USB connector without passing

through the TPD3S713x-Q1 device.

• Data switches are OFF during BUS (V_BUS) discharge.

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The TPD3S713x-Q1 device is a USB power switch with cable compensation and short-to-battery protection for

V_BUS, DP, and DM. The device is typically used for automotive USB port protection. The following design

procedure can be used to select components for the TPD3S713x-Q1 device. This section presents a simplified

discussion of how to choose external components for V_BUS, DP, and DM short-to-battery protection.

9.2 Typical Application

For an automotive USB charging port, the V_BUS, DP, and DM pins are exposed and require a protection device.

The protection required includes V_BUSovercurrent, DP and DM ESD protection, and short-to-battery protection.

This charging-port device protects the upstream dc-dc converter (bus line) and automotive SOC or hub chips

(DP and DM data lines). 图9-1 shows an application schematic of this circuit with short-to-battery protection.

TPD3S713x-Q1

BUS

VBUS

D-

DM_IN

DP_IN

DM_OUT

DP_OUT

D+

GND

ILIM_SEL

BIAS

ILIM_SEL

FAULT1

FAULT

INT1

ILIM_LO

ILIM_HI

Up-stream DC-DC

ADC

IMON

GND

Rlim_Hi

Rlim_Lo

INT2

图9-1. Typical Application Schematic

9.2.1 Design Requirements

For this design example, use the following as the input parameters.

DESIGN PARAMETER

Battery voltage, V_(BAT)

Short-circuit cable

EXAMPLE VALUE

18 V

0.5 m

9.2.2 Detailed Design Procedure

To begin the design process, the designer must know the following:

• The battery voltage.

English Data Sheet: SLUSDH1

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• The short-circuit cable length.

• The maximum continuous output current for the USB port. The minimum current-limit setting of TPD3S713x-

Q1 device must be higher than this current.

• The maximum output current of the upstream dc-dc converter. The maximum current-limit setting of

TPD3S713x-Q1 device must be lower than this current.

• For cable compensation, the total resistance including power switch r_DS(on), cable resistance, and connector

contact resistance must be specified.

9.2.2.1 Input Capacitance

Consider the following application situations when choosing the input capacitors.

For all applications, TI recommends a 0.1-µF or greater ceramic bypass capacitor between IN and GND, placed

as close as possible to the device for local noise decoupling.

During output short or hot plug-in of a capacitive load, high current flows through the TPD3S713x-Q1 device

back to the upstream dc-dc converter until the TPD3S713x-Q1 device responds (after t_(IOS)). During this

response time, the TPD3S713x-Q1 input capacitance and the dc-dc converter output capacitance source current

to keep V_INabove the UVLO of the TPD3S713x-Q1 device and any shared circuits. Size the input capacitance

for the expected transient conditions and keep the path between the TPD3S713x-Q1 device and the dc-dc

converter short to help minimize voltage drops.

Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input

voltage in conjunction with input power-bus inductance and input capacitance when the IN pin is in the high-

impedance state (before turnon). Theoretically, the peak voltage is 2 times the applied voltage. The second

cause is due to the abrupt reduction of output short-circuit current when the TPD3S713x-Q1 device turns off and

energy stored in the input inductance drives the input voltage high. Applications with large input inductance (for

example, a connection between the evaluation board and the bench power supply through long cables) may

require large input capacitance to prevent the voltage overshoot from exceeding the absolute-maximum voltage

of the device.

During the short-to-battery (EN = HIGH) condition, the input voltage follows the output voltage until OVP

protection is triggered (t_{(OV_BUS)}). After the TPD3S713x-Q1 device responds and turns off the power switch, the

stored energy in the input inductance can cause ringing.

Based on the three situations described, TI recommends 10-µF and 0.1-µF low-ESR ceramic capacitors, placed

close to the input.

9.2.2.2 Output Capacitance

Consider the following application situations when choosing the output capacitors.

After an output short occurs, the TPD3S713x-Q1 device abruptly reduces the BUS current, and the energy

stored in the output power-bus inductance causes voltage undershoot and potentially reverse voltage as it

discharges.

Applications with large output inductance (such as from a cable) benefit from the use of a high-value output

capacitor to control the voltage undershoot.

For USB port applications, because the V_BUSpin is exposed to IEC61000-4-2 level-4 ESD, use a low-ESR

capacitance to protect BUS.

The TPD3S713x-Q1 device is capable of handling up to 18-V battery voltage. When V_BUSis shorted to the

battery, the LCR tank circuit formed can induce ringing. The peak voltage seen on the BUS pin depends on the

short-circuit cable length. The parasitic inductance and resistance varies with length, causing the damping factor

and peak voltage to differ. Longer cables with larger resistance reduce the peak current and peak voltage.

Consider high-voltage derating for the ceramic capacitor, because the peak voltage can be higher than twice the

battery voltage.

Based on the three situations described, TI recommends a 10-µF, 35-V, X7R, 1210 low-ESR ceramic capacitor

placed close to BUS. If the battery voltage is 16 V and a 16-V transient voltage suppressor (TVS) is used, then

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ZHCSLC3B –MAY 2020 –REVISED APRIL 2023

www.ti.com.cn

the capacitor voltage can be reduced to 25 V. Considering temperature variation, placing an additional 35-V

aluminum electrolytic capacitor can lower the peak voltage and make the system more robust.

9.2.2.3 BIAS Capacitance

The capacitance on the BIAS pin helps the IEC ESD performance on the DM_IN and DP_IN pins.

When a short-to-battery on DP_IN, DM_IN, BUS, or both occurs, high voltage can be seen on the BIAS pin.

Place a 2.2-µF, 50-V, X7R, 0805, low-ESR ceramic capacitor close to the BIAS pin. The whole current path from

BIAS to GND must be as short as possible. Additionally, use a 5.1-kΩ discharge resistor from BIAS to BUS.

9.2.2.4 Output and BIAS TVS

The TPD3S713x-Q1 device can withstand high transient voltages up to 18 V. In real application, the ringing can

exceed 18 V due to LCR tank ringing, but to make BUS, DP_IN, and DM_IN robust, place one TVS close to the

BUS pin, and another TVS close to the BIAS pin. When choosing the TVS, the reverse standoff voltage V_R

depends on the battery voltage (16 V or 18 V). Considering the peak pulse power capability, TI recommends a

400-W device such as an SMAJ16 for a 16-V battery or an SMAJ18 for an 18-V battery.

English Data Sheet: SLUSDH1

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9.2.3 Application Curves

V_BAT= 16 V

t = 5 µs/div

V_BAT= 18 V

t = 5 µs/div

图9-2. Disabled, 25-V, 1206, X7R C_OUTCapacitor

图9-3. Disabled, 35-V, 1210, X7R C_OUTCapacitor

Without SMAJ16

Without SMAJ18

t = 20 µs/div

图9-4. Disabled, 25-V, 1206, X7R C_OUTCapacitor

图9-5. Disabled, 35-V, 1210, X7R C_OUTCapacitor

With SMAJ16, BUS Shorted to Battery

With SMAJ18, BUS Shorted to Battery

t = 20 µs/div

图9-7. Enable BUS Shorted to Battery

图9-6. DC-DC VIN Floating, BUS Shorted to Battery

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ZHCSLC3B –MAY 2020 –REVISED APRIL 2023

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t = 2 µs/div

R_BIAS= 5.1 kΩ

t = 2 µs/div

R_BIAS= 5.1 kΩ

图9-8. Disabled, DP_IN Shorted to Battery

图9-9. DC-DC VIN Floating, DP_IN Shorted to

Battery

t = 2 µs/div

R_(BIAS)= 5.1 kΩ

R_{(DP_OUT)}= 15 kΩ

图9-10. Enabled, DP_IN Shorted to Battery

9.3 Power Supply Recommendations

The TPD3S713x-Q1 device is designed for a supply voltage range of 4.5 V ≤V_IN≤5.5 V, with its power switch

used for protecting the upstream power supply when a fault such as overcurrent or short to ground occurs on the

USB port. Therefore, the power supply must be rated higher than the current-limit setting to avoid voltage drops

during overcurrent or short-circuit conditions.

9.4 Layout

9.4.1 Layout Guidelines

Layout best practices for the TPD3S713x-Q1 device are listed as follows:

• Considerations for input and output power traces:

– Make the power traces as short as possible.

– Make the power traces as wide as possible.

• Considerations for input-capacitor traces:

– For all applications, TI recommends 10-µF and 0.1-µF low-ESR ceramic capacitors, placed close to the IN

pin.

• The resistors attached to the ILIM_HI and ILIM_LO pins of the device have several requirements:

– TI recommends to use 1% low-temperature-coefficient resistors.

– The trace routing between these two pins and GND must be as short as possible to reduce parasitic

effects on current limit. These traces must not have any coupling to switching signals on the board.

English Data Sheet: SLUSDH1

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• Locate all TPD3S713x-Q1 pullup resistors for open-drain outputs close to their connection pin. Pullup

resistors must be 100 kΩ.

– If a particular open-drain output is not used or needed in the system, tie it to GND.

• ESD considerations:

– The TPD3S713x-Q1 device has built-in ESD protection for DP_IN and DM_IN. Keep trace lengths minimal

from the USB connector to the DP_IN and DM_IN pins on the TPD3S713x-Q1 device, and use minimal

vias along the traces.

– The capacitor on BIAS helps to improve the IEC ESD performance. A 2.2-µF capacitor must be placed

close to BIAS, and the current path from BIAS to GND across this capacitor must be as short as possible.

Do not use vias along the connection traces.

– A 10-µF output capacitor must be placed close to the BUS pin and TVS.

– See the ESD Protection Layout Guide for additional information.

• TVS Considerations (BUS, DP_IN and DM_IN exceed 18 V):

– For BUS, a TVS like SMAJ18 must be placed near the BUS pin.

– For BIAS, a TVS like SMAJ18 must be placed close to the BIAS pin, but behind the 2.2-µF capacitor.

– The whole path from BUS to GND or BIAS to GND across the TVS must be as short as possible.

• DP_IN, DM_IN, DP_OUT, and DM_OUT routing considerations

– Route these traces as microstrips with nominal differential impedance of 90 Ω.

– Minimize the use of vias on the high-speed data lines.

– Keep the reference GND plane devoid from cuts or splits above the differential pairs to prevent impedance

discontinuities.

– For more USB 2.0 high-speed D+ and D–differential routing information, see the High Speed USB

Platform Design Guideline from Intel.

• Thermal Considerations:

– When properly mounted, the thermal-pad package provides significantly greater cooling ability than an

ordinary package. To operate at rated power, the thermal pad must be soldered to the board GND plane

directly under the device. The thermal pad is at GND potential and can be connected using multiple vias to

inner-layer GND. Other planes, such as the bottom side of the circuit board, can be used to increase heat

sinking in higher-current applications. See the PowerPad™ Thermally Enhanced Package application

report) and (PowerPAD™ Made Easy application brief) for more information on using this thermal pad

package.

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ZHCSLC3B –MAY 2020 –REVISED APRIL 2023

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9.4.2 Layout Example

图9-11. TPD3S713x-Q1 Layout Diagram

English Data Sheet: SLUSDH1

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10 Device and Documentation Support

10.1 Documentation Support

10.1.1 Related Documentation

For related documentation see the following:

• High Speed USB Platform Design Guidelines Intel

• Texas Instruments, ESD Protection Layout Guide application note

• Texas Instruments, PowerPAD^™Thermally Enhanced Package application note

• Texas Instruments, PowerPAD^™Made Easy application brief

10.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.4 Trademarks

PowerPAD^™and TI E2E^™are trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

10.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

10.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most-

current data available for the designated device. This data is subject to change without notice and without

revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.

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Product Folder Links: TPD3S713-Q1 TPD3S713A-Q1

English Data Sheet: SLUSDH1

PACKAGE OPTION ADDENDUM

www.ti.com

3-May-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPD3S713AQRVCRQ1

TPD3S713QRVCRQ1

ACTIVE

WQFN

RVC

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

3S713AQ

3S713Q

Samples

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

3-May-2023

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

4-May-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPD3S713AQRVCRQ1

TPD3S713QRVCRQ1

WQFN

RVC

3000

330.0

12.4

3.3

4.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-May-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPD3S713AQRVCRQ1

TPD3S713QRVCRQ1

WQFN

RVC

3000

367.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

RVC0020A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

0.45

0.35

4.1

3.9

0.25

0.15

DETAIL

OPTIONAL TERMINAL

TYPICAL

0.8 MAX

SEATING PLANE

0.08

0.05

0.00

2X 1.5

SYMM

(0.2) TYP

EXPOSED

THERMAL PAD

16X 0.5

SYMM

2.5

2.6 0.1

SEE TERMINAL

DETAIL

0.25

20X

0.15

PIN 1 ID

(OPTIONAL)

0.1

C A B

1.6 0.1

0.05

0.45

0.35

20X

4219150/B 03/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RVC0020A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.6)

SYMM

(R0.05)

TYP

20X (0.6)

20X (0.2)

(1)

TYP

(3.8)

(2.6)

SYMM

16X (0.5)

(

0.2) TYP

VIA

(1 TYP)

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219150/B 03/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RVC0020A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

2X (1.47)

20X (0.6)

20X (0.2)

(R0.05) TYP

SYMM

(1.15)

(3.8)

(0.675)

TYP

16X (0.5)

METAL

TYP

SYMM

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD X

81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219150/B 03/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPD3S713QRVCRQ1 [TI]

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