TPD4E02B04 [TI]
适用于 USB 3.0、HDMI 2.0 和高速信号的四路 0.25pF、±3.6V、±12kV ESD 保护二极管;
| 型号： | TPD4E02B04 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 USB 3.0、HDMI 2.0 和高速信号的四路 0.25pF、±3.6V、±12kV ESD 保护二极管 二极管 |
| 文件： | 总23页 (文件大小：3057K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPD4E02B04
ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016
TPD4E02B04 用于 USB Type-C 和 HDMI 2.0 的 4 通道 ESD 保护二极管
1 特性
•
接口
–
–
–
–
–
–
USB Type-C
1
•
IEC 61000-4-2 4 级静电放电 (ESD) 保护
USB 3.1 第 2 代
高清多媒体接口 (HDMI) 2.0/1.4
USB 3.0
–
–
±12kV 接触放电
±15kV 气隙放电
•
•
IEC 61000-4-4 瞬态放电 (EFT) 保护
80A (5/50ns)
IEC 61000-4-5 浪涌保护
2A (8/20µs)
DisplayPort 1.3
–
PCI Express 3.0
–
3 说明
•
•
•
•
IO 电容：0.27pF（典型值）、0.37pF（最大值）
直流击穿电压：5.5V（最小值）
TPD4E02B04 是一款双向瞬态电压抑制器 (TVS) ESD
保护二极管阵列，用于为 USB Type-C 和 HDMI 2.0
电路提供保护。TPD4E02B04 的额定 ESD 冲击消散
值等于 IEC 61000-4-2（4 级）国际标准中规定的最高
水平。
超低泄漏电流：10nA（最大值）
低静电放电 (ESD) 钳位电压：5A 传输线路脉冲
(TLP) 时为 8.8V
•
•
•
支持速率高达 10Gbps 的高速接口
工业温度范围：–40°C 至 125°C
简易直通布线封装
该器件 的每条 通道具有一个 0.27pF IO 电容，适用于
保护速率高达 10Gbps 的高速接口（例如 USB 3.1 第
2 代）。低动态电阻和低钳位电压可针对瞬变事件提供
系统级保护。
2 应用
•
终端设备
TPD4E02B04 采用符合工业标准的 USON-10 (DQA)
封装。该封装 采用 直通布线，其引脚间距为 0.5mm，
能够简化应用实现并缩短设计时间。
–
–
–
–
–
便携式计算机和台式机
机顶盒
电视和监视器
手机和平板电脑
器件信息(1)
数字视频录像机 (DVR) 和网络视频录像机
器件型号
封装
封装尺寸（标称值）
(NVR)
TPD4E02B04
USON (10) 2.50mm x 1.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
典型应用电路原理图
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1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSD85
TPD4E02B04
ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 11
Power Supply Recommendations...................... 14
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 5
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
8
9
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Examples................................................... 14
11 器件和文档支持 ..................................................... 16
11.1 文档支持 ............................................................... 16
11.2 社区资源................................................................ 16
11.3 商标....................................................................... 16
11.4 静电放电警告......................................................... 16
11.5 Glossary................................................................ 16
12 机械、封装和可订购信息....................................... 16
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (Novemeber 2015) to Revision A
Page
•
已将器件状态由“产品预览”更改为“量产数据” .......................................................................................................................... 1
2
版权 © 2015–2016, Texas Instruments Incorporated
TPD4E02B04
www.ti.com.cn
ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016
5 Pin Configuration and Functions
DQA Package
10-Pin USON
Top View
IO1
IO2
1
2
3
4
5
10 NC
9
8
7
6
NC
GND
IO3
GND
NC
IO4
NC
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
GND
GND
IO1
NO.
3
Ground
Ground
Ground. Connect to ground.
ESD Protected Channel
8
1
IO2
2
I/O
NC
IO3
4
IO4
5
NC
6
NC
7
Not Connected; Used for optional straight-through routing. Can be left floating or
grounded.
NC
9
NC
10
Copyright © 2015–2016, Texas Instruments Incorporated
3
TPD4E02B04
ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
80
UNIT
A
Electrical Fast Transient
Peak Pulse
IEC 61000-4-5 (5/50 ns)
IEC 61000-4-5 Power (tp - 8/20 µs)
IEC 61000-4-5 Current (tp - 8/20 µs)
Operating free-air temperature
Storage temperature
17
W
2
A
TA
–40
–65
125
155
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1000
V(ESD)
Electrostatic discharge
V
IEC 61000-4-2 contact discharge
IEC 61000-4-2 air-gap discharge
±12000
±15000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
3.6
UNIT
VIO
TA
Input pin voltage
–3.6
–40
V
Operating free-air temperature
125
°C
6.4 Thermal Information
TPD4E02B04
THERMAL METRIC(1)
DQA (USON)
10 PINS
348.7
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
214.1
270.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
81.7
ψJB
270.7
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2015–2016, Texas Instruments Incorporated
TPD4E02B04
www.ti.com.cn
ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VRWM
VBRF
Reverse stand-off voltage
IIO < 10 nA
-3.6
3.6
V
Breakdown Voltage, any IO pin to
GND(1)
IIO = 1 mA, TA = 25°C
5.5
6.4
7.5
V
Breakdown Voltage, GND to any IO
pin(1)
VBRR
IIO = 1 mA, TA = 25°C
-5.5
-6.4
-7.5
V
V
VHOLD
Holding voltage(2)
Clamping voltage
IIO = 1 mA
5.8
6.6
8.8
6.6
8.8
IPP = 1 A, TLP, from IO to GND
IPP = 5 A, TLP, from IO to GND
IPP = 1 A, TLP, from GND to IO
IPP = 5A, TLP, from GND to IO
VIO = ±2.5 V
VCLAMP
V
ILEAK
RDYN
Leakage current, any IO to GND
Dynamic Resistance
10
nA
IO to GND
0.47
0.47
Ω
GND to IO
VIO = 0 V, f = 1 MHz, IO to GND, TA
= 25°C
CL
Line Capacitance
0.27
0.01
0.13
0.37
0.07
pF
pF
pF
Delta of capacitance between any
two IO pins, VIO = 0 V, f = 1 MHz, TA
= 25°C, GND = 0 V
ΔCL
Variation of Line Capacitance
Channel to Channel Capacitance
Capacitance from one IO to another,
VIO = 0 V, f = 1 MHz, GND = 0 V
CCROSS
(1) VBRF and VBRR are defined as the voltage when 1mA is applied in the positive-going direction, before the device latches into the
snapback state
(2) VHOLD is defined as the voltage when 1mA is applied in the negative-going direction, after the device has successfully latched into the
snapback state
6.6 Typical Characteristics
30
25
20
15
10
5
30
25
20
15
10
5
0
0
0
3
6
9
12
15
18
21
24
0
3
6
9
12
15
18
21
24
Voltage (V)
Voltage (V)
C001
C002
Figure 1. Positive TLP Curve
Figure 2. Negative TLP Curve
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ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016
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Typical Characteristics (continued)
3
24
20
16
12
8
160
140
120
100
80
Current
Power
2.5
2
1.5
1
60
40
20
0.5
4
0
0
0
-20
-5
0
5
10
15
20
25
30
35
40
45
-25
0
25
50
75 100 125 150 175 200 225
Time (ms)
Time (ns)
D001
D001
Figure 3. Surge Curve (tp = 8/20µs), any IO pin to GND
Figure 4. 8-kV IEC Waveform
20
0.5
0.45
0.4
0
-20
-40
-60
-80
0.35
0.3
0.25
0.2
-100
0.15
0.1
-120
-140
-160
0.05
0
-25
0
25
50
75 100 125 150 175 200 225
Time (ns)
-3.6 -3 -2.4 -1.8 -1.2 -0.6
0
0.6 1.2 1.8 2.4
3
3.6
Bias Voltage (V)
D001
D001
Figure 5. –8-kV IEC Waveform
Figure 6. Capacitance vs. Bias Voltage
0.5
0.45
0.4
0.6
0.5
0.4
0.3
0.2
0.1
0
Bias = -2.5V
Bias = 2.5V
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D001
D001
Figure 7. Capacitance vs. Ambient Temperature
Figure 8. Leakage Current vs. Temperature
6
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TPD4E02B04
www.ti.com.cn
ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016
Typical Characteristics (continued)
1
0.5
0.4
0.3
0.2
0.1
0
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
6E+8
1E+9
2E+9
3E+9
5E+9 7E+9 1E+10
Voltage (V)
Frequency (Hz)
D001
D001
Figure 9. DC Voltage Sweep I-V Curve
Figure 10. Capacitance vs. Frequency
40
35
30
25
20
15
10
5
5
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
0
-5
-10
0
10 20 30 40 50 60 70 80 90 100 110
Time (ns)
-10
0
10 20 30 40 50 60 70 80 90 100 110
Time (ns)
D001
D001
Figure 11. 8-kV IEC Waveform through 2m HDMI Cable
Figure 12. –8-kV IEC Waveform through 2m HDMI Cable
Figure 13. USB3.0 Eye Diagram (Bare Board)
Figure 14. USB3.0 Eye Diagram (with TPD4E02B04)
Copyright © 2015–2016, Texas Instruments Incorporated
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TPD4E02B04
ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016
www.ti.com.cn
Typical Characteristics (continued)
Figure 15. USB3.1 Gen 2 Eye Diagram (Bare Board)
Figure 16. USB3.1 Gen 2 Eye Diagram (with TPD4E02B04)
Figure 17. HDMI2.0 6Gbps TP2 Eye Diagram (Bare Board)
Figure 18. HDMI2.0 6Gbps TP2 Eye Diagram (with
TPD4E02B04)
0
-3
-6
-9
0
0
3E+5
1E+6
1E+7
1E+8
1E+9
1E+12E+1
D001
Frequency (Hz)
Figure 19. Differential Insertion Loss
8
Copyright © 2015–2016, Texas Instruments Incorporated
TPD4E02B04
www.ti.com.cn
ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016
7 Detailed Description
7.1 Overview
The TPD4E02B04 is a bidirectional ESD Protection Diode with ultra-low capacitance. This device can dissipate
ESD strikes above the maximum level specified by the IEC 61000-4-2 International Standard. The ultra-low
capacitance makes this device ideal for protecting any super high-speed signal pins.
7.2 Functional Block Diagram
Lh1
Lh2
Lh3
Lh4
Db5
7.3 Feature Description
7.3.1 IEC 61000-4-2 ESD Protection
The I/O pins can withstand ESD events up to ±12-kV contact and ±15-kV air gap. An ESD/surge clamp diverts
the current to ground.
7.3.2 IEC 61000-4-4 EFT Protection
The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50 Ω
impedance). An ESD/surge clamp diverts the current to ground.
7.3.3 IEC 61000-4-5 Surge Protection
The I/O pins can withstand surge events up to 2 A and 17 W (8/20 µs waveform). An ESD/surge clamp diverts
this current to ground.
7.3.4 IO Capacitance
The capacitance between each I/O pin to ground is 0.27 pF (typical) and 0.37 pF (maximum). This device
supports data rates up to 10 Gbps.
7.3.5 DC Breakdown Voltage
The DC breakdown voltage of each I/O pin is a minimum of ±5.5 V. This ensures that sensitive equipment is
protected from surges above the reverse standoff voltage of ±3.6 V.
7.3.6 Ultra Low Leakage Current
The I/O pins feature an ultra-low leakage current of 10 nA (max) with a bias of ±2.5 V
7.3.7 Low ESD Clamping Voltage
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 8.8 V (IPP = 5 A).
7.3.8 Supports High Speed Interfaces
This device is capable of supporting high speed interfaces up to 10 Gbps, because of the extremely low IO
capacitance.
Copyright © 2015–2016, Texas Instruments Incorporated
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TPD4E02B04
ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016
www.ti.com.cn
Feature Description (continued)
7.3.9 Industrial Temperature Range
This device features an industrial operating range of –40°C to 125°C.
7.3.10 Easy Flow-Through Routing Package
The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers
flow-through routing, requiring minimal modification to an existing layout.
7.4 Device Functional Modes
The TPD4E02B04 is a passive integrated circuit that triggers when voltages are above VBRF or below VBRR
.
During ESD events, voltages as high as ±15 kV (air) can be directed to ground via the internal diode network.
When the voltages on the protected line fall below the trigger levels of TPD4E02B04 (usually within 10s of nano-
seconds) the device reverts to passive.
10
Copyright © 2015–2016, Texas Instruments Incorporated
TPD4E02B04
www.ti.com.cn
ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPD4E02B04 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on
high-speed signal lines between a human interface connector and a system. As the current from ESD passes
through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the
protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
8.2 Typical Application
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Figure 20. USB 3.1 Gen 2 Type-C ESD Schematic
Copyright © 2015–2016, Texas Instruments Incorporated
11
TPD4E02B04
ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016
www.ti.com.cn
Typical Application (continued)
Figure 21. USB 3.1 Gen 2 SuperSpeed Layout
8.2.1 Design Requirements
For this design example two TPD4E02B04 devices and two TPD4E05U06 devices are being used in a USB 3.1
Gen 2 Type-C application. This will provide a complete ESD protection scheme.
Given the USB 3.1 Gen 2 Type-C application, the parameters listed in Table 1 are known.
Table 1. Design Parameters
DESIGN PARAMETER
VALUE
0 V to 3.6 V
5 GHz
Signal Range on SuperSpeed+ Lines
Operating Frequency on SuperSpeed+ Lines
Signal Range on CC, SBU, and DP/DM
Lines
0 V to 5 V
Operating Frequency on CC, SBU, and
DP/DM Lines
up to 480 MHz
12
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TPD4E02B04
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ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016
8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range
The TPD4E02B04 supports signal ranges between -3.6 V and 3.6 V, which supports the SuperSpeed+ pairs on
the USB Type-C application. The TPD4E05U06 supports signal ranges between 0 and 5.5 V, which supports the
CC, SBU, and DP/DM lines.
8.2.2.2 Operating Frequency
The TPD4E02B04 has a 0.27 pF (typ) capacitance, which supports the USB3.1 Gen 2 data rates of 10 Gbps.
The layout example in Figure 21 is intended to negate some of the loading capacitance of the TPD4E02B04 by
narrowing the traces slightly over the device itself. The TPD4E05U06 has a 0.5 pF (typical) capacitance, which
easily supports the CC, SBU, and DP/DM data rates.
8.2.3 Application Curves
Figure 22. USB 3.1 Gen 2 10Gbps Eye Diagram (Bare
Board)
Figure 23. USB 3.1 Gen 2 10Gbps Eye Diagram (with
TPD4E02B04)
Copyright © 2015–2016, Texas Instruments Incorporated
13
TPD4E02B04
ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016
www.ti.com.cn
9 Power Supply Recommendations
This device is a passive ESD device so there is no need to power it. Take care not to violate the recommended
I/O specification (-3.6 V to 3.6 V) to ensure the device functions properly.
10 Layout
10.1 Layout Guidelines
•
The optimum placement is as close to the connector as possible.
–
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
–
The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
•
•
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
–
Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Examples
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Figure 24. USB Type-C Mid-Mount, Hybrid Connector with One-Sided ESD Layout
14
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TPD4E02B04
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ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016
Layout Examples (continued)
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ëL! ꢁo hꢁꢂer [ꢃyer
ëL! ꢁo Db5 tlꢃne
/9/
ÜÇL[LÇò
ÜÇL[LÇò
55/_/[Y
Db5
55/_5!Ç
55/_/[Y
55/_5!Ç
Db5
ꢀë_hÜÇ
IhÇt[ÜD_59Ç
Ço DtLh
IhÇt[ÜD_59Ç
Db5
ꢀë_{Ütt[ò
Çt53{014
Figure 25. HDMI2.0 Type-A Transmitter Port Layout
版权 © 2015–2016, Texas Instruments Incorporated
15
TPD4E02B04
ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
相关文档请参见以下部分：
•
•
•
《阅读并理解 ESD 保护数据表》，SLLA305
《ESD 布局布线指南》，SLVA680
《TPD4E02B04EVM 用户指南》，SLVUAH6
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
16
版权 © 2015–2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPD4E02B04DQAR
ACTIVE
USON
DQA
10
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1SG
1SY
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD4E02B04DQAR
USON
DQA
10
3000
180.0
9.5
1.18
2.68
0.72
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
USON DQA 10
SPQ
Length (mm) Width (mm) Height (mm)
189.0 185.0 36.0
TPD4E02B04DQAR
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DQA0010A
USON - 0.55 mm max height
SCALE 6.000
PLASTIC SMALL OUTLINE - NO LEAD
1.1
0.9
A
B
PIN 1 INDEX AREA
2.6
2.4
C
0.55 MAX
SEATING PLANE
(0.13) TYP
0.08 C
0.05
0.00
5
6
4X 0.5
(R0.125)
2X
2
0.45
0.35
2X
0.1
C A
B
0.05
1
10
0.25
0.15
8X
PIN 1 ID
(OPTIONAL)
0.1
0.05
C A
B
0.43
0.30
10X
C
4220328/A 12/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DQA0010A
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.565)
8X (0.2)
1
10
SYMM
2X (0.4)
4X (0.5)
6
5
(R0.05) TYP
SYMM
(0.835)
LAND PATTERN EXAMPLE
SCALE:30X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220328/A 12/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DQA0010A
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.565)
8X (0.2)
1
10
METAL
TYP
SYMM
2X (0.36)
8
3
4X (0.5)
6
5
(R0.05) TYP
SYMM
(0.835)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PADS 3 & 8:
90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:40X
4220328/A 12/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
TPD4E02B04DQAR
适用于 USB 3.0、HDMI 2.0 和高速信号的四路 0.25pF、±3.6V、±12kV ESD 保护二极管 | DQA | 10 | -40 to 125
TI
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