TPD4E05U06QDQARQ1 [TI]
适用于 USB 和高速接口的汽车类四路 0.5pF、5.5V、±12kV ESD 保护二极管 | DQA | 10 | -40 to 125;
| 型号： | TPD4E05U06QDQARQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 USB 和高速接口的汽车类四路 0.5pF、5.5V、±12kV ESD 保护二极管 | DQA | 10 | -40 to 125 局域网 光电二极管 |
| 文件： | 总25页 (文件大小：1256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPD4E05U06-Q1, TPD1E05U06-Q1
ZHCSCQ5C –AUGUST 2014–REVISED SEPTEMBER 2017
用于 SuperSpeed（速率高达 6Gbps）接口的 TPDxE05U06-Q1 1 通道和
4 通道 ESD 保护二极管
1 特性
•
接口
–
–
–
–
–
–
USB 2.0
1
•
符合 AEC-Q101
USB 3.0
–
–
–
人体放电模型 (HBM) 分类等级 H3B
充电器件模型 (CDM) 分类等级 C5
器件温度范围：–40°C 至 +125°C
HDMI 1.4/2.0
低压差分信令 (LVDS)
DisplayPort
SIM 卡
•
IEC 61000-4-2 4 级 ESD 保护
（请参阅 ESD Ratings—IEC Specification 表）
–
–
±12kV 接触放电
±15kV 气隙放电
3 说明
TPDxE05U06-Q1 是一系列具有超低电容的单向瞬态
电压抑制器 (TVS) 静电放电 (ESD) 保护二极管。这些
器件旨在耗散那些高于 IEC61000-4-2 4 级国际标准中
规定的最高水平的 ESD 冲击。超低负载电容特性使得
这些器件非常适合保护任何高达 6Gbps 的高速 信号
应用。
•
•
IEC 61000-4-4 瞬态放电 (EFT) 保护
80A (5/50ns)
IEC 61000-4-5 浪涌保护
2.5A (8/20µs)
–
–
•
•
•
•
•
I/O 电容 0.42pF 至 0.5pF（典型值）
直流击穿电压 6.4V（最小值）
超低漏电流 10nA（最大值）
低 ESD 钳位电压（在 5A TLP 下为 14V）
简易直通路由封装
这些器件还具有未经过汽车认证的型
号：TPDxE05U06。
器件信息(1)
器件型号
封装
USON (10)
X1SON (2)
封装尺寸（标称值）
2.50mm x 1.00mm
0.60mm x 1.00mm
2 应用
TPD4E05U06-Q1
TPD1E05U06-Q1
•
终端设备
–
–
–
–
–
–
音响主机
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
后座娱乐系统
远程信息处理
USB 集线器
导航模块
媒体接口
TPD4E05U06-Q1 框图
TPD4E05U06-Q1 简化原理图
1
2
TPD4E05U06-Q1
4
5
3
8
D0+
D0-
D1+
D1-
D2+
D1+
D1-
D2+
D2-
D2-
CLK+
CLK-
1
GND
TPD4E05U06-Q1
2
4
5
3
8
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSCO7
TPD4E05U06-Q1, TPD1E05U06-Q1
ZHCSCQ5C –AUGUST 2014–REVISED SEPTEMBER 2017
www.ti.com.cn
目录
7.4 Device Functional Modes.......................................... 9
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application .................................................. 10
Layout ................................................................... 12
9.1 Layout Guidelines ................................................... 12
9.2 Layout Example ...................................................... 12
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings—AEC Specification ............................. 4
6.3 ESD Ratings—IEC Specification .............................. 4
6.4 Recommended Operating Conditions....................... 4
6.5 Thermal Information.................................................. 4
6.6 Electrical Characteristics........................................... 5
6.7 Typical Characteristics.............................................. 6
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
8
9
10 器件和文档支持 ..................................................... 13
10.1 文档支持................................................................ 13
10.2 接收文档更新通知 ................................................. 13
10.3 相关链接................................................................ 13
10.4 社区资源................................................................ 13
10.5 商标....................................................................... 13
10.6 静电放电警告......................................................... 13
10.7 Glossary................................................................ 13
11 机械、封装和可订购信息....................................... 13
7
4 修订历史记录
Changes from Revision A (August 2014) to Revision B
Page
•
•
•
•
添加了 1 通道 (TPD1E05U06-Q1) 封装.................................................................................................................................. 1
Added DPY package information in Thermal Information table ............................................................................................. 4
Added DPY package Dynamic resistance in Electrical Characteristics table ........................................................................ 5
Added DPY package Line capacitance in Electrical Characteristics table............................................................................. 5
Changes from Revision B (August 2016) to Revision C
Page
•
已更改 在引脚配置和功能 部分中添加了 DPY 封装引脚配置 ................................................................................................. 1
Changes from Original (August 2014) to Revision A
Page
•
在“特性”中添加了内容（请参阅 ESD Ratings—IEC Specification 表）：IEC 61000-4-2 4 级 ESD 保护.............................. 1
2
Copyright © 2014–2017, Texas Instruments Incorporated
TPD4E05U06-Q1, TPD1E05U06-Q1
www.ti.com.cn
ZHCSCQ5C –AUGUST 2014–REVISED SEPTEMBER 2017
5 Pin Configuration and Functions
DPY Package
2-Pin X1SON
Top View
I/O
1
2
GND
DQA Package
10-Pin USON
Top View
1
2
10
9
N.C.
N.C.
D1+
D1–
3
GND
8
GND
4
5
D2+
D2–
7
6
N.C.
N.C.
Pin Functions TPD1E05U06-Q1 DPY
PIN
TYPE
DESCRIPTION
NO.
NAME
I/O
1
2
I/O
ESD Protected Channel(1)
Ground; Connect to ground
GND
Ground
(1) Place as close to the connector as possible.
Pin Functions TPD4E05U06-Q1 DQA
PIN
TYPE
DESCRIPTION
NO.
NAME
D1+
1
2
4
5
I/O
I/O
I/O
I/O
ESD Protected Channel(1)
ESD Protected Channel(1)
ESD Protected Channel(1)
ESD Protected Channel(1)
D1–
D2+
D2–
Not Connected; Used for optional straight-through routing. Can be left floating or
grounded
6, 7, 9, 10
3, 8
NC
NC
GND
Ground
Ground; Connect to ground
(1) Place as close to the connector as possible.
Copyright © 2014–2017, Texas Instruments Incorporated
3
TPD4E05U06-Q1, TPD1E05U06-Q1
ZHCSCQ5C –AUGUST 2014–REVISED SEPTEMBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)(2)
MIN
MAX
80
UNIT
A
Electrical fast transient IEC 61000-4-4 (5/50 ns)
IEC 61000-4-5 Current (tp – 8/20 µs)
2.5
40
A
Peak pulse
IEC 61000-4-5 Power (tp – 8/20 µs) - TPD4E05U06-Q1(3)
W
IEC 61000-4-5 Power (tp – 8/20 µs) - TPD1E05U06-Q1(3)
30
W
TA
Operating temperature
–40
–65
125
150
°C
°C
Tstg
Storage temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltages are with respect to GND unless otherwise noted.
(3) Measured at 25°C
6.2 ESD Ratings—AEC Specification
VALUE
±8000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(2)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge(1)
V
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
into the device.
(2) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC Specification
VALUE
±12000
±12000
±15000
UNIT
(1)
IEC 61000-4-2 contact discharge - TPD4E05U06-Q1
IEC 61000-4-2 contact discharge - TPD1E05U06-Q1
IEC 61000-4-2 air-gap discharge
V(ESD)
Electrostatic Discharge
V
(1) Measured at 25°C, per IEC 61000.4.2 Ed. 2.0 Section 7.2.4.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0
MAX
UNIT
VIO
TA
Input pin voltage
5.5
V
Operating free-air temperature
–40
125
°C
6.5 Thermal Information
TPD1E05U06-Q1
DPY (X1SON)
2 PINS
TPD4E05U06-Q1
DQA (USON)
10 PINS
327
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
697.3
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
471
189.5
575.9
257.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
175.7
60.9
ψJB
575.1
257
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2014–2017, Texas Instruments Incorporated
TPD4E05U06-Q1, TPD1E05U06-Q1
www.ti.com.cn
ZHCSCQ5C –AUGUST 2014–REVISED SEPTEMBER 2017
6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT – OUTPUT RESISTANCE
VRWM
VBR
Reverse stand-off voltage
IIO < 10 µA
5.5
8.7
V
V
Break-down voltage
IIO = 1 mA
6.4
IPP = 1 A, TLP, from I/O to GND(1)
IPP = 5 A, TLP, from I/O to GND(1)
IPP = 1 A, TLP, from GND to I/O(1)
IPP = 5 A, TLP, from GND to I/O(1)
VIO = 2.5 V
10
14
VCLAMP
Clamp voltage
V
3
7.5
1
ILEAK
Leakage current
10 nA
I/O to GND(2)
GND to I/O(2)
I/O to GND(2)
GND to I/O(2)
0.8
0.7
0.96
0.9
DPY package
Dynamic
resistance
RDYN
Ω
DQA package
CAPACITANCE
TPD1E05U06-Q1
DPY package
0.42
0.5
VIO = 2.5 V, f = 1 MHz, I/O to
GND
CL
Line capacitance
pF
TPD4E05U06-Q1
DQA package
GND Pin = 0 V, f = 1 MHz, VBIAS = 2.5 V,
Channel x pin to GND – channel y pin to GND
Δ CIO-TO-GND Variation of input capacitance
0.05
0.04
0.08 pF
0.08 pF
Channel to channel input
GND Pin = 0 V, f = 1 MHz, VBIAS = 2.5 V, between
channel pins
CCROSS
capacitance
(1) Transition line pulse with 100 ns width, 200 ps rise time.
(2) Extraction of RDYN using least squares fit of TLP characteristics between I = 5 A and I = 10 A.
Copyright © 2014–2017, Texas Instruments Incorporated
5
TPD4E05U06-Q1, TPD1E05U06-Q1
ZHCSCQ5C –AUGUST 2014–REVISED SEPTEMBER 2017
www.ti.com.cn
6.7 Typical Characteristics
3.5
3
56
1.0
0.8
Current
Power
48
0.6
2.5
2
40
32
24
16
8
0.4
0.2
0.0
1.5
1
œ0.2
œ0.4
œ0.6
œ0.8
œ1.0
0.5
0
0
œ2 œ1
0
1
2
3
4
5
6
7
8
9
10
-5
0
5
10 15 20 25 30 35 40 45 50
C001
Voltage (V)
Time (µs)
D002
Figure 1. Current vs Voltage
Current vs Voltage DC Voltage Sweep I-V Curve
Figure 2. Current and Power vs Time
Surge Curve (tp = 8/20 µs), Pin I/O to GND
35
30
25
20
15
10
5
30
25
20
15
10
5
0
-5
0
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Voltage (V)
Voltage (V)
D001
D001
Figure 3. Current vs Voltage
Positive TLP Plot I/O to GND
Figure 4. Current vs Voltage
Negative TLP Plot I/O to GND
120
110
100
90
80
70
60
50
40
30
20
10
0
300
250
200
150
100
50
0
-10
œ40
œ20
0
20
40
60
80
100
120
0
25
50
75
100
Time (ns)
125
150
175
200
C004
Temperature (°C)
D005
Figure 5. Leakage Current vs Temperature
Figure 6. Voltage vs Time 8-kV IEC Waveform
6
Copyright © 2014–2017, Texas Instruments Incorporated
TPD4E05U06-Q1, TPD1E05U06-Q1
www.ti.com.cn
ZHCSCQ5C –AUGUST 2014–REVISED SEPTEMBER 2017
Typical Characteristics (continued)
10
0
0
œ1
œ2
œ3
œ4
œ5
œ6
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
100k
1M
10M
100M
1G
10G
0
25
50
75
100
Time (ns)
125
150
175
200
C009
Frequency (Hz)
D006
Figure 8. Insertion Loss vs Frequency
Figure 7. Voltage vs Time –8-kV IEC Waveform
Copyright © 2014–2017, Texas Instruments Incorporated
7
TPD4E05U06-Q1, TPD1E05U06-Q1
ZHCSCQ5C –AUGUST 2014–REVISED SEPTEMBER 2017
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPDxE05U06-Q1 is a family of unidirectional TVS ESD protection diode arrays with ultra-low capacitance
between 0.42 pF and 0.5 pF. They are rated to dissipate ESD strikes above the maximum level specified in the
IEC 61000-4-2 level 4 international standard (12-kV contact, 15-kV air gap). The ultra-low loading capacitance
makes them ideal for protecting any high-speed signal applications up to 6 Gbps.
7.2 Functional Block Diagram
D1+
D1-
D2+
D2-
GND
Figure 9. TPD4E05U06-Q1 Block Diagram
I/O
GND
Figure 10. TPD1E05U06-Q1 Block Diagram
7.3 Feature Description
7.3.1 AEC-Q101 Qualification
These devices are qualified to AEC-Q101 standards. They pass HBM H3B (±8 kV) and CDM C5 (±1 kV) ESD
ratings and are qualified to operate from –40°C to +125°C.
7.3.2 IEC 61000-4-2 Level 4 ESD Protection
The I/O pins can withstand ESD events up to ±12-kV contact and ±15-kV air. An ESD-surge clamp diverts the
current to ground.
7.3.3 IEC 61000-4-4 EFT Protection
The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ω
impedance). An ESD-surge clamp diverts the current to ground.
8
Copyright © 2014–2017, Texas Instruments Incorporated
TPD4E05U06-Q1, TPD1E05U06-Q1
www.ti.com.cn
ZHCSCQ5C –AUGUST 2014–REVISED SEPTEMBER 2017
Feature Description (continued)
7.3.4 IEC 61000-4-5 Surge Protection
The I/O pins can withstand surge events up to 2.5 A and 40 W (8/20 µs waveform). An ESD-surge clamp diverts
this current to ground.
7.3.5 I/O Capacitance
The capacitance between each I/O pin to ground is 0.5 pF. These capacitances support data rates up to 5 Gbps.
7.3.6 DC Breakdown Voltage
The DC breakdown voltage of each I/O pin is a minimum of 6.4 V. This ensures that sensitive equipment is
protected from surges above the reverse standoff voltage of 5 V.
7.3.7 Ultra-Low Leakage Current
The I/O pins feature an ultra-low leakage current of 10 nA (Maximum) with a bias of 2.5 V.
7.3.8 Low ESD Clamping Voltage
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 10 V (IPP = 1 A).
7.3.9 Easy Flow-Through Routing
The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers
flow-through routing, requiring minimal modification to an existing layout.
7.4 Device Functional Modes
The TPDxE05U06-Q1 are passive integrated circuits that triggers when voltages are above VBR or below the
lower diodes Vf (–0.6 V). During ESD events, voltages as high as ±15 kV (air) can be directed to ground via the
internal diode network. When the voltages on the protected line fall below the trigger levels of TPDxE05U06-Q1
(usually within 10s of nano-seconds) the devices reverts to passive.
Copyright © 2014–2017, Texas Instruments Incorporated
9
TPD4E05U06-Q1, TPD1E05U06-Q1
ZHCSCQ5C –AUGUST 2014–REVISED SEPTEMBER 2017
www.ti.com.cn
8 Application and Implementation
8.1 Application Information
The TPD4E05U06-Q1 is a diode type TVS which is typically used to provide a path to ground for dissipating ESD
events on hi-speed signal lines between a human interface connector and a system. As the current from ESD
passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to
the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected
IC.
8.2 Typical Application
TPD4E05U06DQA-Q1
D2+
D2+
D2-
1
10
9
HOT PLUG 1
UTILITY 2
D2-
2
UTI_CON
3
4
8
7
TMDS D2+ 3
D1+
D1-
5-V Source
D1+
D1-
TMDS_GND 4
TMDS D2- 5
5
6
TMDS D1+ 6
TPD4E05U06DQA-Q1
TMDS_GND 7
D0+
D0-
D0+
1
10
9
TMDS D1- 8
D0-
2
TMDS D0+ 9
8
7
3
4
TMDS_GND 10
CLK+
CLK-
CLK+
CLK-
TMDS D0- 11
TMDS CLK+ 12
TMDS_GND 13
TMDS CLK- 14
5
6
TPD5S116YFF
HDMI Controller
CEC_SYS
CEC_CON
CEC 15
SCL_SYS
SDA_SYS
VCCA
DDC/CEC GND 16
SCL 17
SCL_CON
SDA_CON
SDA 18
EN
5V_SYS
HPD_SYS
5V_CON
P 5V0 19
GND 20
HPD_CON
UTI_CON
GND
0.1 µF
0.1 µF
Copyright © 2016, Texas Instruments Incorporated
Figure 11. HDMI 1.4 Application
8.2.1 Design Requirements
For this design example, two TPD4E05U06-Q1 devices, and a TPD5S116 are being used in an HDMI 1.4
application. This provides a complete port protection scheme.
Given the HDMI 1.4 application, the parameters in Table 1 are known.
Table 1. Design Parameters
DESIGN PARAMETER
Signal range on pins 1, 2, 4, or 5
Operating frequency
VALUE
0 V to 5 V
1.7 GHz
8.2.2 Detailed Design Procedure
To begin the design process, some parameters must be decided upon; the designer needs to know the following:
•
•
Signal range on all the protected lines
Operating frequency
10
Copyright © 2014–2017, Texas Instruments Incorporated
TPD4E05U06-Q1, TPD1E05U06-Q1
www.ti.com.cn
ZHCSCQ5C –AUGUST 2014–REVISED SEPTEMBER 2017
8.2.2.1 Signal Range on Pin 1, 2, 4, or 5
The TPD4E05U06-Q1 has 4 identical protection channels for signal lines. The symmetry of the device provides
flexibility when selecting which of the 4 I/O channels protect which signal lines. Any I/O will support a signal
range of 0 to 5.5 V.
8.2.2.2 Operating Frequency
The TPD4E05U06-Q1 has a capacitance of 0.5 pF (Typical), supporting HDMI 1.4 data rates.
8.2.3 Application Curve
Figure 12. 3.4 Gbps HDMI Eye Diagram
Copyright © 2014–2017, Texas Instruments Incorporated
11
TPD4E05U06-Q1, TPD1E05U06-Q1
ZHCSCQ5C –AUGUST 2014–REVISED SEPTEMBER 2017
www.ti.com.cn
9 Layout
9.1 Layout Guidelines
•
The optimum placement is as close to the connector as possible.
–
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
–
The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
•
•
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
–
Electric fields tend to build up on corners, increasing EMI coupling.
9.2 Layout Example
This application is typical of an HDMI 1.4 layout.
VIA to GND Plane
Figure 13. TPD4E05U06-Q1 Layout
12
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TPD4E05U06-Q1, TPD1E05U06-Q1
www.ti.com.cn
ZHCSCQ5C –AUGUST 2014–REVISED SEPTEMBER 2017
10 器件和文档支持
10.1 文档支持
10.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
《TPD1E05U06-Q1 评估模块用户指南》
阅读和理解 ESD 保护数据表
《ESD 布局指南》
《TPD4E05U06DQA GUI 用户指南》
10.2 接收文档更新通知
如需接收文档更新通知，请访问 ti.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 相关链接
下面的表格列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的
快速链接。
表 2. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
TPD4E05U06-Q1
TPD1E05U06-Q1
10.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
10.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
10.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
10.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2014–2017, Texas Instruments Incorporated
13
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPD1E05U06QDPYRQ1
TPD4E05U06QDQARQ1
ACTIVE
ACTIVE
X1SON
USON
DPY
DQA
2
10000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
-40 to 125
4O
(BRH, CQ1)
10
3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD1E05U06QDPYRQ1 X1SON
TPD4E05U06QDQARQ1 USON
TPD4E05U06QDQARQ1 USON
DPY
DQA
DQA
2
10000
3000
3000
180.0
180.0
180.0
9.5
8.4
9.5
0.73
1.3
1.13
2.83
2.68
0.5
2.0
4.0
4.0
8.0
8.0
8.0
Q1
Q1
Q1
10
10
0.65
0.72
1.18
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPD1E05U06QDPYRQ1
TPD4E05U06QDQARQ1
TPD4E05U06QDQARQ1
X1SON
USON
USON
DPY
DQA
DQA
2
10000
3000
3000
189.0
213.0
189.0
185.0
191.0
185.0
36.0
35.0
36.0
10
10
Pack Materials-Page 2
PACKAGE OUTLINE
DQA0010A
USON - 0.55 mm max height
SCALE 6.000
PLASTIC SMALL OUTLINE - NO LEAD
1.1
0.9
A
B
PIN 1 INDEX AREA
2.6
2.4
C
0.55 MAX
SEATING PLANE
(0.13) TYP
0.08 C
0.05
0.00
5
6
4X 0.5
(R0.125)
2X
2
0.45
0.35
2X
0.1
C A
B
0.05
1
10
0.25
0.15
8X
PIN 1 ID
(OPTIONAL)
0.1
0.05
C A
B
0.43
0.30
10X
C
4220328/A 12/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DQA0010A
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.565)
8X (0.2)
1
10
SYMM
2X (0.4)
4X (0.5)
6
5
(R0.05) TYP
SYMM
(0.835)
LAND PATTERN EXAMPLE
SCALE:30X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220328/A 12/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DQA0010A
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.565)
8X (0.2)
1
10
METAL
TYP
SYMM
2X (0.36)
8
3
4X (0.5)
6
5
(R0.05) TYP
SYMM
(0.835)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PADS 3 & 8:
90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:40X
4220328/A 12/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DPY0002A
X1SON - 0.45 mm max height
S
C
A
L
E
1
1
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.1
0.9
B
A
PIN 1 INDEX AREA
0.7
0.5
0.45
0.30
C
SEATING PLANE
0.08 C
0.05
0.00
0.65
1
2
SYMM
0.55
0.45
2X
0.1
C A B
SYMM
0.3
0.2
2X
0.05
C A B
4224561/B 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (0.3)
SYMM
1
2
SYMM
2X (0.5)
(R0.05) TYP
(0.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL EDGE
METAL UNDER
SOLDER MASK
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224561/B 03/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0)
2X (0.3)
2X (0.5)
SYMM
PCB PAD METAL
UNDER SOLDER PASTE
SYMM
2
1
(R0.05) TYP
(0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:60X
4224561/B 03/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
TPD4E1B06DRLR
采用 SOT 和 SC70 封装且具有 0.5nA 最大泄漏电流的四路 0.7pF、±5.5V、±12kV ESD 保护二极管 | DRL | 6 | -40 to 125
TI
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