TPD4E110 [TI]
适用于高速接口且采用 0.64mm2 SON 封装的四路 0.5pF、5.5V、±12kV ESD 保护二极管;
| 型号： | TPD4E110 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于高速接口且采用 0.64mm2 SON 封装的四路 0.5pF、5.5V、±12kV ESD 保护二极管 二极管 |
| 文件： | 总21页 (文件大小：9734K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPD4E110
ZHCSCF2B –JULY 2013–REVISED APRIL 2014
TPD4E110 4 通道保护解决方案，用于超高速（高达 6GBPS）接口
1 特性
3 说明
1
•
为低压输入输出 (IO) 接口提供系统级静电放电
(ESD) 保护
TPD4E110 是一款具有超低电容值的单向静电放电
(ESD) 保护器件。 此器件由一个中央 ESD 钳位组成，
并且在每个通道中特有两个隐藏的二极管，以减少电容
负载。 每条通道额定 ESD 冲击消散值高于
IEC61000-4-2 4 级国际标准中规定的最高水平。
TPD4E110 的超低负载电容值使得此器件非常适合于
保护高速信号引脚。
•
•
IO 电容值 0.45pF（典型值）
IEC 61000-4-2 4 级
–
–
±12kV（接触放电）
±15kV（空气间隙放电)
•
•
•
•
•
•
IEC 61000-4-5（浪涌）：2.5A (8/20µs)
直流击穿电压 6.5V（最小值）
超低泄露电流 1nA（最大值）
器件信息
订货编号
封装
X2SON (4)
封装尺寸
低 ESD 钳位电压
TPD4E110DPW
0.8mm x 0.8mm
工业温度范围：-40°C 至 125°C
最大限度减少空间的 0.8mm x 0.8mm DPW 封装
空白
空白
空白
空白
空白
2 应用范围
•
•
•
•
•
•
USB 3.0
HDMI 2.0
低压差分信令 (LVDS)
DisplayPort
PCI Express 接口
eSata 接口
电路保护系统
IO2
IO3
IO4
IO1
4 简化电路原理图
插入损耗
1
0
Tx
-1
-2
-3
-4
-5
1
2
GND
3
4
Rx
-6
100000
1000000
1E+7
1E+8
1E+9
1E+10
Frequency (Hz)
D003
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLVSC54
TPD4E110
ZHCSCF2B –JULY 2013–REVISED APRIL 2014
www.ti.com.cn
目录
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
8.3 Feature Description................................................... 7
8.4 Device Functional Modes.......................................... 7
Applications and Implementation ........................ 8
9.1 Application Information.............................................. 8
9.2 Typical Application ................................................... 8
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Terminal Configuration and Functions................ 3
Specifications......................................................... 3
7.1 Absolute Maximum Ratings ...................................... 3
7.2 Handling Ratings....................................................... 3
7.3 Recommended Operating Conditions....................... 3
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 4
7.6 Typical Characteristics.............................................. 5
Detailed Description .............................................. 7
9
10 Layout................................................................... 10
10.1 Layout Guidelines ................................................. 10
10.2 Layout Example .................................................... 10
11 器件和文档支持 ..................................................... 12
11.1 Trademarks........................................................... 12
11.2 Electrostatic Discharge Caution............................ 12
11.3 Glossary................................................................ 12
12 机械封装和可订购信息 .......................................... 12
8
5 修订历史记录
Changes from Revision A (March 2014) to Revision B
Page
•
•
已修改超低泄露电流排印错误。 ............................................................................................................................................. 1
Updated ILEAK max value. ....................................................................................................................................................... 4
Changes from Original (July 2013) to Revision A
Page
•
已将首页数据表更新为完全版。 ............................................................................................................................................. 1
2
Copyright © 2013–2014, Texas Instruments Incorporated
TPD4E110
www.ti.com.cn
ZHCSCF2B –JULY 2013–REVISED APRIL 2014
6 Terminal Configuration and Functions
4 Terminal DPW Package
Bottom View
1
2
GND
3
4
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME
IOX
NO.
1, 2, 3, 4
5
IO
G
ESD-protected channel
Ground
GND
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
125
2.5
35
UNIT
°C
A
Operating temperature range
-40
IPP
Peak pulse current (tp = 8/20μs)
Peak pulse power (tp = 8/20μs)
Peak pulse power (tp = 8/20μs)
PPP(forward)
PPP(reverse)
W
18
W
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
MIN MAX
–65 155
±12
UNIT
°C
Tstg
Storage temperature
IEC 61000-4-2 contact ESD
IEC 61000-4-2 air-gap ESD
kV
ESD(1)
±15
kV
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIO
TA
0.0
5.5
V
Operating free-air temperature
–40
125
°C
Copyright © 2013–2014, Texas Instruments Incorporated
3
TPD4E110
ZHCSCF2B –JULY 2013–REVISED APRIL 2014
www.ti.com.cn
7.4 Thermal Information
TPD4E110
THERMAL METRIC(1)
UNIT
DPW
(4 TERMINALS)
RθJA
Junction-to-ambient thermal resistance
291.8
224.2
245.8
31.4
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
245.6
195.4
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
VRWM
Reverse stand-off voltage
IIO = 10 μA
5.5
V
V
I = 1A, TLP, I/O to GND
I = 5A, TLP, I/O to GND
I = 1A, TLP, GND to I/O
I = 5A, TLP, GND to I/O
IIO = 1mA
10
13
V
VCLAMP
Clamp voltage with ESD strike
3
V
6
V
VBR
Break-down voltage
Leakage current
6.5
7.5
0.02
0.8
0.7
0.45
8.5
1
V
ILEAK
VIO = 2.5V
nA
Ω
Ω
pF
Any I/O to GND Terminal(1)
GND to any I/O Terminal(1)
VIO = 2.5V, f = 1MHz, I/O to GND
RDYN
Dynamic resistance
Line capacitance
CL
0.55
GND Terminal = 0V, f = 1MHz, VBIAS = 2.5 V,
between channel terminals
Channel to channel input
capacitance
CCROSS
0.003
pF
GND Terminal = 0V, f = 1MHz, VBIAS = 2.5 V,
Channel_x terminal to GND – Channel_y terminal to
GND
Variation of channel input
capacitance
ΔCIO-TO-GND
0.05
pF
(1) Extraction of RDYN using least squares fit of TLP characteristics between I = 10A and I = 20A.
4
Copyright © 2013–2014, Texas Instruments Incorporated
TPD4E110
www.ti.com.cn
ZHCSCF2B –JULY 2013–REVISED APRIL 2014
7.6 Typical Characteristics
At TA = 25°C, unless otherwise noted
120
100
80
60
40
20
0
0
-20
-40
-60
-80
-100
0
25
50
75
100
125
150
0
25
50
75
100
125
150
Time (ns)
Time (ns)
D001
D002
Figure 1. IEC 61000-4-2 Clamping Voltage, +8kV Contact
Figure 2. IEC 61000-4-2 Clamping Voltage, -8kV Contact
1
0
1E-3
8E-4
6E-4
4E-4
2E-4
0
-1
-2
-3
-4
-5
-6
-2E-4
-4E-4
-6E-4
-8E-4
-1E-3
100000
1000000
1E+7
1E+8
1E+9
1E+10
-1
0
1
2
3
4
5
6
7
8
Frequency (Hz)
Voltage (V)
D003
D009
Figure 3. Insertion Loss
Figure 4. IV Curve
20
15
10
5
6E-10
5E-10
4E-10
3E-10
2E-10
1E-10
0
0
-5
-10
-15
-20
-40
-20
0
20
40
60
80
100
120
-30 -25 -20 -15 -10 -5
0
5
10 15 20 25 30
Temperature (ºC)
Voltage (V)
D005
D004
Figure 6. Leakage vs Temperature
Figure 5. TLP, tPW = 100 nS, tRISE = 10 nS
Copyright © 2013–2014, Texas Instruments Incorporated
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TPD4E110
ZHCSCF2B –JULY 2013–REVISED APRIL 2014
www.ti.com.cn
Typical Characteristics (continued)
At TA = 25°C, unless otherwise noted
3
40
36
32
28
24
20
16
12
8
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
40
Current
Power
Current
Power
36
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
32
28
24
20
16
12
8
4
4
0
0
45
-5
0
5
10 15 20 25 30 35 40 45 50
-5
0
5
10
15
20
Time (µs)
25
30
35
40
Time (µs)
D008
D006
Figure 8. Surge Curves, GND to IO
Figure 7. Surge Curves, IO to GND
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
2
3
4
5
Voltage (V)
D007
Figure 9. IO Terminal Capacitance vs VBIAS
6
Copyright © 2013–2014, Texas Instruments Incorporated
TPD4E110
www.ti.com.cn
ZHCSCF2B –JULY 2013–REVISED APRIL 2014
8 Detailed Description
8.1 Overview
TPD4E110DPW is a uni-directional ESD protection device with ultra-low capacitance. The device is constructed
with a central ESD clamp that features two hiding diodes per channel to reduce the capacitive loading. Each
channel is rated to dissipate ESD strikes above the maximum level specified in the IEC61000-4-2 level 4
international standard. The TPD4E110DPW's ultra-low loading capacitance makes the device ideal for protecting
high-speed signal terminals. The 0.8 mm x 0.8 mm package is designed for space saving designs. The pinout
allows for straight through routing of 2 differential pairs when PCB manufacturing which feature sizes of 2.8 mils
(0.071 mm).
8.2 Functional Block Diagram
IO1
IO2
IO3
IO4
8.3 Feature Description
TPD4E110 is a uni-directional Electrostatic Discharge (ESD) protection device with ultra-low capacitance. The
device is constructed with a central ESD clamp that features two hiding diodes per line to reduce the capacitive
loading. Each line is rated to dissipate ESD strikes above the maximum level specified in the IEC61000-4-2 level
4 international standard. The TPD4E110's ultra-low loading capacitance makes it ideal for protecting high-speed
signal terminals.
8.4 Device Functional Modes
TPD4E110 is a passive integrated circuit that activates whenever voltages above VBR or below the lower diodes
Vforward (–0.6V) are present upon the circuit being protected. During ESD events, voltages as high as ±15 kV can
be directed to ground via the internal diode network. Once the voltages on the protected line fall below the trigger
levels of TPD4E110 (usually within 10’s of nano-seconds) the device reverts to passive.
Copyright © 2013–2014, Texas Instruments Incorporated
7
TPD4E110
ZHCSCF2B –JULY 2013–REVISED APRIL 2014
www.ti.com.cn
9 Applications and Implementation
9.1 Application Information
TPD4E110 is a diode array type Transient Voltage Suppressor (TVS) which is typically used to provide a path to
ground for dissipating ESD events on hi-speed signal lines between a human interface connector and a system.
As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is
the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a
tolerable level to the protected IC.
9.2 Typical Application
Tx
1
2
GND
3
4
Rx
Figure 10. Protecting a Pair of Super-Speed Data Lines
9.2.1 Design Requirements
For this design example, use the following as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETER
Signal range on Pin 1, 2, 3, or 4
Operating Frequency
EXAMPLE VALUE
0V to 5.5V
3.0 GHz
9.2.2 Detailed Design Procedure
To begin the design process some parameters must be decided upon. The designer needs to know the following:
•
•
Signal range on all the protected lines
Operating frequency
9.2.2.1 Signal range on Terminal 1, 2, 3, or 4
TPD4E110 has 4 identical protection channels for signal lines. The symmetry of TPD4E110 provides flexibility
when selecting which of the 4 IO channels will protect which signal lines. Any IO will support a signal range of 0V
to 5.5V.
9.2.2.2 Operating Frequency
The 0.45pF capacitance of each IO channel supports data rates up to 6Gbps.
8
Copyright © 2013–2014, Texas Instruments Incorporated
TPD4E110
www.ti.com.cn
ZHCSCF2B –JULY 2013–REVISED APRIL 2014
9.2.3 Application Curves
Figure 12. Eye Diagram for USB 3.0 Super-Speed Data
Lines Using Single Layer Routing without Device Installed
Figure 11. Eye Diagram for USB 3.0 Super-Speed Data
Lines Using Single Layer Routing with Device Installed
Figure 14. Eye Diagram for USB 3.0 Super-Speed Data
Lines Using Double Layer Routing with Device Installed
Figure 13. Eye Diagram for USB 3.0 Super-Speed Data
Lines Using Double Layer Routing with Device Installed
Copyright © 2013–2014, Texas Instruments Incorporated
9
TPD4E110
ZHCSCF2B –JULY 2013–REVISED APRIL 2014
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
•
The optimum placement is as close to the connector as possible.
–
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
–
The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
•
•
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
–
Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
10.2.1 Single Layer Routing
PCB manufacturing technologies allowing 2.8 mil (0.071 mm) clearances can route two Super-Speed data line
pairs through TPD4E110 on a single layer.
1
USB 3.0 Type A
Connector PCB
TPD4E110DPW
Footprint
2
Figure 15. Example Layout for USB 3.0 Type A connector using two TPD4E110s
In Figure 15, Figure 16 and Figure 17 an example layout shows the use of two TPD4E110s to protect the USB
3.0 port. TPD4E110 Number 1 is protecting the two Super-Speed data pairs used for Super Speed data transfer,
and TPD4E110 Number 2 protects the USB 2.0 D+/D– Hi-Speed data lines. Number 2 uses two channels to
protect each line in the pair, thus affording a more robust protection and simpler layout.
10
Copyright © 2013–2014, Texas Instruments Incorporated
TPD4E110
www.ti.com.cn
ZHCSCF2B –JULY 2013–REVISED APRIL 2014
Layout Example (continued)
Figure 16. Close-up of Routing for TPD4E110 for
Super-Speed Data Lines
Figure 17. Close-up of Routing for TPD4E110 for
USB 2.0 D+/D– Hi-Speed Data Lines
10.2.2 Double Layer Routing
PCB manufacturing technologies allowing 4.0 mil (0.1 mm) clearances can route two Super-Speed data line pairs
through TPD4E110 using two layers.
Figure 18. Example Layout for USB 3.0 Type A Connector Using Two TPD4E110s
In Figure 18 an example layout shows the use of two TPD4E110s to protect the USB 3.0 port. TPD4E110
Number 1 is protecting the two Super-Speed data pairs used for high speed data transfer, and TPD4E110
Number 2 protects the USB 2.0 D+/D– Hi-Speed lines. Number 2 uses two channels to protect each line in the
pair, thus affording a more robust protection and simpler layout.
Copyright © 2013–2014, Texas Instruments Incorporated
11
TPD4E110
ZHCSCF2B –JULY 2013–REVISED APRIL 2014
www.ti.com.cn
11 器件和文档支持
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
12
Copyright © 2013–2014, Texas Instruments Incorporated
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Copyright © 2014, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPD4E110DPWR
ACTIVE
X2SON
DPW
4
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
D2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD4E110DPWR
X2SON
DPW
4
3000
180.0
9.5
0.91
0.91
0.5
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
X2SON DPW
SPQ
Length (mm) Width (mm) Height (mm)
184.0 184.0 19.0
TPD4E110DPWR
4
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DPW0004A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
A
B
PIN 1 INDEX AREA
0.85
0.75
0.4 MAX
C
SEATING PLANE
NOTE 4
(0.1)
0.25 0.1
0.05
0.00
THERMAL PAD
2
3
4
NOTE 4
5
2X
(45 ) TYP
0.48
1
0.27
4X
PIN 1 ID
(OPTIONAL)
NOTE 5
0.17
0.32
3X
0.1 C A
0.05 C
B
0.27
0.17
0.23
4218860/A 12/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. The size and shape of this feature may vary.
5. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
www.ti.com
EXAMPLE BOARD LAYOUT
DPW0004A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
(
0.1)
SYMM
4X (0.42)
VIA
0.05 MIN
ALL AROUND
TYP
1
4
4X (0.22)
5
SYMM
4X (0.26)
(0.48)
2
3
(R0.05) TYP
SOLDER MASK
OPENING, TYP
4X (0.06)
(
0.25)
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4218860/A 12/2015
NOTES: (continued)
6. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
7. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DPW0004A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.06)
4
1
4X (0.22)
SYMM
(
0.24)
4X (0.26)
5
(0.21)
(0.48)
TYP
SOLDER MASK
EDGE
2
3
(R0.05) TYP
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 5:
92% PRINTED SOLDER COVERAGE BY AREA
SCALE:100X
4218860/A 12/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
TPD4E1B06DRLR
采用 SOT 和 SC70 封装且具有 0.5nA 最大泄漏电流的四路 0.7pF、±5.5V、±12kV ESD 保护二极管 | DRL | 6 | -40 to 125
TI
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