TPD4E1B06DRLR [TI]
采用 SOT 和 SC70 封装且具有 0.5nA 最大泄漏电流的四路 0.7pF、±5.5V、±12kV ESD 保护二极管 | DRL | 6 | -40 to 125;
| 型号： | TPD4E1B06DRLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 SOT 和 SC70 封装且具有 0.5nA 最大泄漏电流的四路 0.7pF、±5.5V、±12kV ESD 保护二极管 | DRL | 6 | -40 to 125 局域网 光电二极管 瞬态抑制器 |
| 文件： | 总12页 (文件大小：831K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPD4E1B06
www.ti.com
SLVSBQ8A –DECEMBER 2012–REVISED JANUARY 2013
Quad Channel High Speed ESD Protection Device
Check for Samples: TPD4E1B06
1
FEATURES
APPLICATIONS
•
Provides System Level ESD Protection for
Low-Voltage IO Interfaces
•
USB2.0
HDMI control lines
•
•
IEC 61000-4-2 Level 4
•
•
•
MIPI Bus
LVDS
–
–
±12kV (Contact discharge)
±15kV (Air-gap discharge)
SATA
•
•
•
•
•
•
IO Capacitance 1.0pF (Typ)
DCK PACKAGE
2 mm x 2.1 mm x 0.95 mm
(0.65 mm pitch)
DC Breakdown Voltage 7V (Min)
Ultra low Leakage Current 10nA (Max)
Low ESD Clamping Voltage
NC
IO4
IO3
IO1
IO2
1
2
6
5
Industrial Temperature Range: –40°C to 125°C
Small, Easy-to-Route DCK package
3
4
GND
DESCRIPTION
The TPD4E1B06 is a quad channel ultra low cap ESD protection device. It offers ±12KV IEC air-gap and ±15KV
contact ESD protection. Its 1.0pF line capacitance makes it suitable for a wide range of applications. Typical
application areas are HDMI, USB2.0, Ethernet, and 1394 interfaces.
ORDERING INFORMATION
TA
PACKAGE(1)(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–40°C to 125°C
3000
Tape and reel
TPD4E1B06DCKR
BYI
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2012–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPD4E1B06
SLVSBQ8A –DECEMBER 2012–REVISED JANUARY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
IO1
IO2
IO4
IO3
GND
GND
Figure 1. Circuit Schematic Diagram
TERMINAL FUNCTIONS
PIN
DESCRIPTION
USAGE
NAME
NUMBER
TYPE
I/O
IO1
IO2
IO3
IO4
NC
1
2
4
5
6
3
I/O
ESD protected channel
Connect to data line as close to the connector as possible
I/O
I/O
NC
No connect
Ground
Can be left floating, grounded, or connected to Vcc
Connect to ground
GND
GND
2
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Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPD4E1B06
TPD4E1B06
www.ti.com
SLVSBQ8A –DECEMBER 2012–REVISED JANUARY 2013
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
MIN
–40
–65
MAX
125
155
±12
±15
3.5
UNIT
°C
°C
kV
kV
A
Operating temperature range
Storage temperature
IEC 61000-4-2 contact ESD
IEC 61000-4-2 air-gap ESD
IPP, peak pulse current (tp = 8/20 μs), IO pin to GND
PPP, peak pulse power (tp = 8/20 μs)
45
W
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN TYP MAX UNIT
VRWM
Reverse stand-off voltage
5.5
V
V
V
IPP = 1 A, tp = 8/20 μSec, from I/O to GND or GND to I/O
IPP = 3A, tp = 8/20 μSec, from I/O to GND or GND to I/O
ITLP = 10A to 20 A, I/O to GND
10.5
14.5
1
Clamp voltage with ESD strike,
IO to GND
VCLAMP
RDYN
Dynamic resistance
Ω
ITLP = 10A to 20 A, GND to I/O
0.8
1
CL
Line capacitance
Break-down voltage
Leakage current
f = 1 MHz, VBIAS = 2.5 V
pF
V
VBR
ILEAK
IIO = 1 mA, from I/O to GND or GND to I/O
VIO = 5.0 V
7
9.5
10
1
nA
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: TPD4E1B06
TPD4E1B06
SLVSBQ8A –DECEMBER 2012–REVISED JANUARY 2013
www.ti.com
TYPICAL CHARACTERISTICS
CURRENT
vs
CURRENT and POWER
vs
VOLTAGE
TIME
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
50
45
40
35
30
25
20
15
10
5
1.0
0.8
Current
Power
0.6
0.4
0.2
0.0
œ0.2
œ0.4
œ0.6
œ0.8
œ1.0
0
œ5
0
5
10 15 20 25 30 35 40 45 50
œ10 œ8
œ6
œ4
œ2
0
2
4
6
8
10
C002
Time (ꢀs)
C001
Voltage (V)
Figure 2. DC Voltage Sweep I-V Curve
Figure 3. Surge Curve (tp = 8/20μs), Pin IO to GND
CURRENT
vs
CURRENT
vs
VOLTAGE
TEMPERATURE
10
8
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
6
4
2
0
œ2
œ4
œ6
œ8
œ10
œ24 œ20 œ16 œ12 œ8 œ4
0
4
8
12 16 20 24
œ40
œ20
0
20
40
60
80
100
120
C003
C004
Voltage (V)
Temperature (°C)
Figure 4. TLP Plot IO to GND
Figure 5. Leakage vs Temperature
VOLTAGE
vs
VOLTAGE
vs
TIME
TIME
110
100
90
80
70
60
50
40
30
20
10
0
10
0
œ10
œ20
œ30
œ40
œ50
œ60
œ70
œ80
œ90
œ100
œ110
œ10
0
25
50
75
100
125
150
175
200
0
25
50
75
100
125
150
175
200
C005
C006
Time (ꢀs)
Time (ꢀs)
Figure 6. +8kV IEC Waveform
Figure 7. –8kV IEC Waveform
4
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Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPD4E1B06
TPD4E1B06
www.ti.com
SLVSBQ8A –DECEMBER 2012–REVISED JANUARY 2013
APPLICATION INFORMATION
The TPD4E1B06DCK offers a unique pinout that allows straight through routing with no stubs. Figure 8 shows an
example layout. Pins 1 & 2 and pins 4 & 5 are routed differentially. Pin 3 is routed to the ground plane. Pin 6 is
not bonded internally in the device and does not need to be routed anywhere on the board. It is also okay if pin 6
is connected to power plane or a capacitor.
Figure 8. TPD4E1B06 Layout Example
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: TPD4E1B06
TPD4E1B06
SLVSBQ8A –DECEMBER 2012–REVISED JANUARY 2013
www.ti.com
REVISION HISTORY
Changes from Original (December 2012) to Revision A
Page
•
Fixed "f" units typo from GHz to MHz for CL parameter in ELECTRICAL CHARACTERISTICS table. ............................... 3
6
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Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPD4E1B06
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
TPD4E1B06DCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD4E1B06DCKR
SC70
DCK
6
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SC70 DCK
SPQ
Length (mm) Width (mm) Height (mm)
180.0 180.0 18.0
TPD4E1B06DCKR
6
3000
Pack Materials-Page 2
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