TPD6E004RSERG4 [TI]

LOW-CAPACITANCE 6-CHANNEL ±15-kV ESD PROTECTION ARRAY FOR HIGH-SPEED DATA INTERFACES; 低电容6通道【 15千伏ESD保护阵列高速数据接口
TPD6E004RSERG4
型号: TPD6E004RSERG4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

LOW-CAPACITANCE 6-CHANNEL ±15-kV ESD PROTECTION ARRAY FOR HIGH-SPEED DATA INTERFACES
低电容6通道【 15千伏ESD保护阵列高速数据接口

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TPD6E004  
LOW-CAPACITANCE 6-CHANNEL ±15-kV ESD PROTECTION ARRAY  
FOR HIGH-SPEED DATA INTERFACES  
www.ti.com  
SLLS799AFEBRUARY 2008REVISED FEBRUARY 2008  
1
FEATURES  
RSE PACKAGE  
(BOTTOM VIEW)  
2
ESD Protection Exceeds JESD  
±15-kV Human-Body Model (HBM)  
±8-kV IEC 61000-4-2 Contact Discharge  
±12-kV IEC 61000-4-2 Air-Gap Discharge  
1
2
3
Low 1.6-pF IO Capacitance  
0.9-V to 5.5-V Supply-Voltage Range  
6-Channel Device  
V
4
8
GND  
CC  
7
6
5
Space-Saving QFN (RSE) Package  
APPLICATIONS  
USB  
Ethernet  
FireWire  
Video  
Cell Phones  
SVGA Video Connections  
Glucose Meters  
abc  
abc  
DESCRIPTION/ORDERING INFORMATION  
The TPD6E004 is a low-capacitance ±15-kV ESD-protection diode array designed to protect sensitive electronics  
attached to communication lines. Each channel consists of a pair of diodes that steers ESD current pulses to VCC  
or GND. The TPD6E004 protects against ESD pulses up to ±15-kV Human-Body Model (HBM), ±8-kV Contact  
Discharge, and ±12-kV Air-Gap Discharge, as specified in IEC 61000-4-2. This device has a typical 1.6-pF  
capacitance per channel, making it ideal for use in high-speed data IO interfaces.  
The TPD6E004 is a six-channel ESD structure designed for wthernet and FireWire applications.  
The TPD6E004 is available in the RSE package and is specified for –40°C to 85°C operation.  
ORDERING INFORMATION  
TA  
PACKAGE(1)(2)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
QFN – RSE  
–40°C to 85°C  
1.5 mm × 1.5 mm,  
Reel of 3000  
TPD6E004RSER  
2V  
Pitch = 0.5 mm, Height = 0.55 mm  
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008, Texas Instruments Incorporated  
TPD6E004  
LOW-CAPACITANCE 6-CHANNEL ±15-kV ESD PROTECTION ARRAY  
FOR HIGH-SPEED DATA INTERFACES  
www.ti.com  
SLLS799AFEBRUARY 2008REVISED FEBRUARY 2008  
LOGIC BLOCK DIAGRAM  
VCC  
IO1  
IO2  
IO3  
IO4  
IO5  
IO6  
GND  
PIN DESCRIPTION  
RSE NO.  
NAME  
IOx  
FUNCTION  
1-3, 5-7  
ESD-protected channel  
Ground  
4
8
GND  
VCC  
Power-supply input. Bypass VCC to GND with a 0.1-µF ceramic capacitor.  
ABSOLUTE MAXIMUM RATINGS(1)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
–0.3  
–0.3  
–65  
MAX UNIT  
VCC  
VIO  
5.5  
VCC + 0.3  
150  
V
V
Tstg  
TJ  
Storage temperature range  
Junction temperature  
°C  
°C  
150  
Infrared (15 s)  
220  
Bump temperature (soldering)  
°C  
°C  
Vapor phase (60 s)  
215  
Lead temperature (soldering, 10 s)  
300  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the  
specifications is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.  
2
Submit Documentation Feedback  
Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): TPD6E004  
TPD6E004  
LOW-CAPACITANCE 6-CHANNEL ±15-kV ESD PROTECTION ARRAY  
FOR HIGH-SPEED DATA INTERFACES  
www.ti.com  
SLLS799AFEBRUARY 2008REVISED FEBRUARY 2008  
ELECTRICAL CHARACTERISTICS  
VCC = 5 V ± 10%, TA = TMIN to TMAX (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN TYP(1)  
MAX UNIT  
VCC  
ICC  
VF  
Supply voltage  
0.9  
5.5  
V
nA  
V
Supply current  
500  
Diode forward voltage  
Channel leakage current  
Break-down Voltage  
Channel input capacitance  
IF = 1 mA  
0.8  
II  
±1  
nA  
V
VBR  
CI/O  
II = 10µA  
6
8
2
VCC = 5 V, Bias of VCC/2, f = 10MHz  
1.6  
pF  
(1) Typical values are at VCC = 5 V and TA = 25°C.  
ESD PROTECTION  
PARAMETER  
TYP UNIT  
HBM  
±15  
±8  
kV  
kV  
kV  
IEC 61000-4-2 Contact Discharge  
IEC 61000-4-2 Air-Gap Discharge  
±12  
Copyright © 2008, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s): TPD6E004  
TPD6E004  
LOW-CAPACITANCE 6-CHANNEL ±15-kV ESD PROTECTION ARRAY  
FOR HIGH-SPEED DATA INTERFACES  
www.ti.com  
SLLS799AFEBRUARY 2008REVISED FEBRUARY 2008  
TYPICAL OPERATING CHARACTERISTICS  
160  
140  
120  
100  
80  
70  
60  
50  
40  
30  
20  
10  
0
60  
40  
20  
0
1.05  
1.15  
1.25  
1.35  
1.45  
1.55  
–40  
25  
Temperature (°C)  
Figure 2. Leakage Current vs Temperature (VIO = 2.5 V)  
55  
85  
IO Voltage (V)  
Figure 1. Forward Diode Voltage (Upper Clamp Diode)  
(VCC = 0 V, DC Sweep Across the IO Pin)  
5.0  
16.0  
14.0  
12.0  
10.0  
8.0  
4.0  
3.0  
2.0  
1.0  
0.0  
6.0  
4.0  
2.0  
0.0  
1
2
3
4
5
0.0  
1.0  
2.0  
3.0  
4.0  
5.0  
6.0  
7.0  
IO Voltage (V)  
IO Voltage (V)  
Figure 3. Reverse Diode Curve Current IO to GND  
(VCC = Open)  
Figure 4. IO Capacitance vs Input Voltage  
(VCC = 5 V)  
4
Submit Documentation Feedback  
Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): TPD6E004  
TPD6E004  
LOW-CAPACITANCE 6-CHANNEL ±15-kV ESD PROTECTION ARRAY  
FOR HIGH-SPEED DATA INTERFACES  
www.ti.com  
SLLS799AFEBRUARY 2008REVISED FEBRUARY 2008  
TYPICAL OPERATING CHARACTERISTICS (continued)  
220  
200  
180  
160  
140  
120  
100  
80  
60  
40  
20  
0
–20  
0
25  
50  
75  
100 125 150 175 200 225 250  
Time (ns)  
Figure 5. IEC ESD Clamping Waveforms +8-kV Contact,  
Average of 10 Waveforms  
Copyright © 2008, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Link(s): TPD6E004  
TPD6E004  
LOW-CAPACITANCE 6-CHANNEL ±15-kV ESD PROTECTION ARRAY  
FOR HIGH-SPEED DATA INTERFACES  
www.ti.com  
SLLS799AFEBRUARY 2008REVISED FEBRUARY 2008  
APPLICATION INFORMATION  
VBUS  
D+  
0.1 µF  
VCC  
D–  
RT  
GND  
IO5  
IO3  
IO1  
USB  
Controller  
Open  
Open  
D1  
IO6  
IO4  
IO2  
VBUS  
D+  
D–  
GND  
GND  
Detailed Description  
When placed near the connector, the TPD6E004 ESD solution offers little or no signal distortion during normal  
operation due to low IO capacitance and ultra-low leakage current specifications. The TPD6E004 ensures that  
the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For proper  
operation, the following layout/design guidelines should be followed:  
1. Place the TPD6E004 solution close to the connector. This allows the TPD6E004 to take away the energy  
associated with ESD strike before it reaches the internal circuitry of the system board.  
2. Place a 0.1-µF capacitor very close to the VCC pin. This limits any momentary voltage surge at the IO pin  
during the ESD strike event.  
3. Make sure that there is enough metallization for the VCC and GND loop. During normal operation, the  
TPD6E004 consumes nA leakage current. But during the ESD event, VCC and GND may see 15 A to 30 A of  
current, depending on the ESD level. Sufficient current path enables safe discharge of all the energy  
associated with the ESD strike.  
4. Leave the unused IO pins floating.  
5. The VCC pin can be connected in two different ways:  
a. If the VCC pin is connected to the system power supply (a 0.1-µF capacitor at VCC is recommended for  
ESD bypass), the TPD6E004 works as a transient voltage suppressor for any signal swing above VCC  
Vd.  
+
b. If the VCC pin is not connected to system power supply (a 0.1-µF capacitor is still recommended at the  
VCC pin for ESD bypass), the TPD6E004 can tolerate higher signal swing in the range up to VBR. Note  
that initially the bypass capacitor is charged by the signals through clamp diode.  
6
Submit Documentation Feedback  
Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): TPD6E004  
PACKAGE OPTION ADDENDUM  
www.ti.com  
8-Dec-2009  
PACKAGING INFORMATION  
Orderable Device  
TPD6E004RSER  
TPD6E004RSERG4  
Status (1)  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
UQFN  
RSE  
8
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
UQFN  
RSE  
8
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
8-Dec-2009  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPD6E004RSER  
UQFN  
RSE  
8
3000  
179.0  
8.4  
1.7  
1.7  
0.76  
4.0  
8.0  
Q2  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
8-Dec-2009  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
UQFN RSE  
SPQ  
Length (mm) Width (mm) Height (mm)  
220.0 205.0 50.0  
TPD6E004RSER  
8
3000  
Pack Materials-Page 2  
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