TPD6F002QDSVRQ1 [TI]
适用于 LCD 显示屏应用的汽车类 6 通道、5.5V ESD 保护和 EMI 滤波器 | DSV | 12 | -40 to 125;
| 型号： | TPD6F002QDSVRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 LCD 显示屏应用的汽车类 6 通道、5.5V ESD 保护和 EMI 滤波器 | DSV | 12 | -40 to 125 LTE CD |
| 文件： | 总19页 (文件大小：1144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPD6F002-Q1
ZHCSDL8A –DECEMBER 2014–REVISED FEBRUARY 2015
TPD6F002-Q1 面向 LCD 显示屏和 FPD-Link 的汽车类 ESD 保护和 EMI
滤波器
1 特性
2 应用
1
•
•
符合 AEC-Q101 标准
针对数据端口的 6 通道电磁干扰 (EMI) 滤波
•
•
•
•
•
液晶显示屏 (LCD) 显示接口
通用输入/输出 (GPIO)
存储器接口
–
–
–
100MHz 频率下的串扰衰减为 –47dB
800MHz 频率下的插入损耗为 –30dB
100MHz 频率下的的带宽为 –3dB
采用柔性电缆的数据线
FPD-Link
•
•
Pi 型 (C-R-C) 滤波器配置
（R = 100Ω，CTOTAL = 34pF）
3 说明
TPD6F002-Q1 是一款高度集成的器件，该器件提供有
6 通道 EMI 滤波器和基于瞬态电压抑制器 (TVS) 的
ESD 保护二极管阵列。 低通滤波器阵列可为数据端口
抑制 EMI/射频干扰 (RFI) 辐射，防止其受到电磁干
扰。 TVS 二极管阵列的额定 ESD 冲击消散值高于
IEC 61000-4-2 国际标准中规定的最高水平。 此器件
高度集成，并且采用易于布线的小型 DSV 封装，可对
LCD 显示屏、存储器接口、GPIO 线和 FPD-Link 提供
强力的电路保护。
优异的静电放电 (ESD) 保护，超过了 IEC 61000-
4-2
标准（4 级）
–
–
±20kV IEC 61000-4-2 接触放电
±30kV IEC 61000-4-2 气隙放电
•
•
低泄漏电流 20nA（最大值）
采用节省空间的小外形尺寸无引线 (SON) 封装
(3mm × 1.35mm)
器件信息(1)
器件型号
封装
SON (12)
封装尺寸（标称值）
TPD6F002-Q1
3.00mm x 1.35mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
4 简化电路原理图
Ch_In
100 Ω
Ch_Out
C1 = 17 pF
C2 = 17 pF
GND
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLLSEK0
TPD6F002-Q1
ZHCSDL8A –DECEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
目录
8.2 Functional Block Diagram ......................................... 6
8.3 Feature Description................................................... 6
8.4 Device Functional Modes.......................................... 7
Application and Implementation .......................... 7
9.1 Application Information.............................................. 7
9.2 Typical Application ................................................... 8
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
7.1 Absolute Maximum Ratings ..................................... 3
7.2 ESD Ratings ............................................................ 3
7.3 Recommended Operating Conditions....................... 3
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 4
7.6 Typical Characteristics.............................................. 5
Detailed Description .............................................. 6
8.1 Overview ................................................................... 6
9
10 Power Supply Recommendations ..................... 10
11 Layout................................................................... 10
11.1 Layout Guidelines ................................................. 10
11.2 Layout Example .................................................... 10
12 器件和文档支持 ..................................................... 11
12.1 商标....................................................................... 11
12.2 静电放电警告......................................................... 11
12.3 术语表 ................................................................... 11
13 机械、封装和可订购信息....................................... 11
8
5 修订历史记录
Changes from Original (December 2014) to Revision A
Page
•
最初发布的完整版数据表。..................................................................................................................................................... 1
2
Copyright © 2014–2015, Texas Instruments Incorporated
TPD6F002-Q1
www.ti.com.cn
ZHCSDL8A –DECEMBER 2014–REVISED FEBRUARY 2015
6 Pin Configuration and Functions
DSV PACKAGE
(3.0 mm × 1.35 mm × 0.75 mm)
Ch1_In
Ch1_Out
Ch2_In
Ch3_In
Ch4_In
Ch5_In
Ch6_In
Ch2_Out
Ch3_Out
Ch4_Out
Ch5_Out
Ch6_Out
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
1, 2, 3, 4, 5,
6
ChX_In
IO
ESD-protected channel, connected to corresponding ChX_Out
7, 8, 9, 10,
11, 12
ChX_Out
GND
IO
G
ESD-protected channel, connected to corresponding ChX_In
Ground
G
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
VIO
TJ
IO to GND
5.75
125
150
V
Junction temperature
Storage temperature range
°C
°C
Tstg
–65
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±10
UNIT
Human body model (HBM), per AEC Q100-002, all pins(1)
Charged device model (CDM), per AEC Q101-005, all pins
IEC 61000-4-2 Contact Discharge
±1.5
±20
V(ESD)
Electrostatic discharge
kV
IEC 61000-4-2 Air-Gap Discharge
±30
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0
NOM
MAX
5.5
UNIT
VIO
TA
Input pin voltage
V
Operating free-air temperature
-40
125
°C
Copyright © 2014–2015, Texas Instruments Incorporated
3
TPD6F002-Q1
ZHCSDL8A –DECEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
7.4 Thermal Information
TPD6F002-Q1
DSV
THERMAL METRIC(1)
UNIT
12 PINS
120.7
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
104.4
78.5
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
13.0
ψJB
77.7
RθJC(bot)
66.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
TA = –40°C to 125°C (Unless otherwise noted)
PARAMETER
DC breakdown voltage
Resistance
TEST CONDITIONS
MIN
6
TYP(1)
MAX UNIT
VBR
R
IIO = 10 μA
V
VIN = 3.3 V, IIn-to-out = 1mA
VIO = 2.5 V
85
100
17
115
20
Ω
pF
C
Capacitance (C1 or C2)
Channel leakage current
Cut-off frequency
IIO
fC
VIO = 3.3 V
1
nA
ZSOURCE = 50 Ω, ZLOAD = 50 Ω
100
MHz
(1) Typical values are at TA = 25°C.
4
Copyright © 2014–2015, Texas Instruments Incorporated
TPD6F002-Q1
www.ti.com.cn
ZHCSDL8A –DECEMBER 2014–REVISED FEBRUARY 2015
7.6 Typical Characteristics
TA = 25°C unless otherwise noted
1E-5
8E-6
6E-6
4E-6
2E-6
0
100
99
98
97
96
95
-2E-6
-4E-6
-6E-6
-8E-6
-1E-5
Temperature
25qC
85qC
125qC
-40qC
-1
0
1
2
3
4
5
6
7
-50
-25
0
25
50
75
100
125
Voltage (V)
Temperature (qC)
D001
D002
Figure 1. DC Voltage-Current Sweep across Input, Output
Pins
Figure 2. Series Resistance vs Temperature
0
-3
28
26
24
22
20
18
16
14
12
-6
-9
-12
-15
-18
-21
-24
-27
-30
-33
100000
1000000
1E+7
1E+8
1E+9
5E+9
0
1
2
3
4
5
6
Frequency (Hz)
Bias Voltage (V)
D003
D004
Figure 3. Typical Insertion-loss Characteristics
Figure 4. Capacitance (C1 or C2) vs. Bias Voltage
(DC Bias = 0 V, 50 Ω Environment)
5
0
60
55
50
45
40
35
30
25
20
15
10
5
Input
Output
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
Input
Output
0
0
50
100
150
200
0
50
100
150
200
Time (ns)
Time (ns)
D006
D007
Figure 5. +8-kV IEC Waveform
Figure 6. -8-kV IEC Waveform
Copyright © 2014–2015, Texas Instruments Incorporated
5
TPD6F002-Q1
ZHCSDL8A –DECEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TPD6F002-Q1 is a highly integrated device that provides a six channel EMI filter and a TVS based ESD
protection diode array. The low-pass filter array suppresses EMI/RFI emissions for data ports subject to
electromagnetic interference. The TPD6F002-Q1 is rated to dissipate ESD strikes above the maximum level
specified in the IEC 61000-4-2 international standard. The high level of integration, combined with its small easy-
to-route DSV package, makes this device ideal for protecting interfaces like LCD displays, memory interfaces,
and FPD-Link.
8.2 Functional Block Diagram
100Ω
Ch_Out
Ch_In
C1 =17pF
C2=17pF
GND
8.3 Feature Description
The TPD6F002-Q1 is a highly integrated device that provides a six channel EMI filter and a TVS based ESD
protection diode array. The low-pass filter array suppresses EMI/RFI emissions for data ports subject to
electromagnetic interference. The TVS diode array is rated to dissipate ESD strikes above the maximum level
specified in the IEC 61000-4-2 international standard. The high level of integration, combined with its small easy-
to-route DSV package, allows this device to provide great circuit protection for LCD displays, memory interfaces,
GPIO lines, and FPD-Link.
8.3.1 AEC-Q101 Qualified
This device is qualified to AEC-Q101 standards. It passes HBM H3B (±8 kV) and CDM C5 (±1 kV) ESD ratings
and is qualified to operate from –40°C to 125°C.
8.3.2 Six-Channel EMI Filtering
This device provides six channels for EMI filtering of data lines with the following parameters:
•
•
•
–47 dB Crosstalk Attenuation at 100 MHz
–30 dB Insertion Loss at 800 MHz
–3 dB Bandwidth: 100 MHz
8.3.3 Pi-Style Filter Configuration
This device has a pi-style filtering configuration composed of a series resistor and two capacitors in parallel with
the I/O pins. The typical resistor value is 100 Ω and the typical capacitor values are 17 pF each.
8.3.4 Robust ESD Protection
The ESD protection on all pins exceeds the IEC 61000-4-2 level 4 standard. Contact ESD is rated at ±20 kV and
Air-gap ESD is rated at ±30 kV.
6
Copyright © 2014–2015, Texas Instruments Incorporated
TPD6F002-Q1
www.ti.com.cn
ZHCSDL8A –DECEMBER 2014–REVISED FEBRUARY 2015
Feature Description (continued)
8.3.5 Low Leakage Current
The I/O pins feature an ultra-low leakage current of 20-nA (max) with a bias of 3.3 V
8.3.6 Space-Saving SON Package
The layout of this device makes it easy to add protection to existing layouts. The packages offer flow-through
routing which requires minimal changes to existing layout for addition of these devices. Additionally, the device
offers a small space-saving package that takes a minimal footprint on the board.
8.4 Device Functional Modes
The TPD6F002-Q1 is a passive integrated circuit that passively filters EMI and triggers when voltages are above
VBR or below the lower diode voltage (–0.6 V). During ESD events, voltages as high as ±30 kV (air) can be
directed to ground via the internal diode network. Once the voltages on the protected line fall below the trigger
levels, the device reverts to passive.
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPD6F002-Q1 is a highly integrated device that provides a six channel EMI filter and a TVS based ESD
protection diode array. The low-pass filter array suppresses EMI/RFI emissions for data ports subject to
electromagnetic interference. The TVS diode array is rated to dissipate ESD strikes above the maximum level
specified in the IEC 61000-4-2 international standard. The high level of integration, combined with its small easy-
to-route DSV package, allows this device to provide great circuit protection for LCD displays, memory interfaces,
GPIO lines, and FPD-Link.
Copyright © 2014–2015, Texas Instruments Incorporated
7
TPD6F002-Q1
ZHCSDL8A –DECEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
9.2 Typical Application
TPD6F002-Q1
R0
1
2
3
4
5
6
12
11
10
9
R1
R2
R3
R4
R5
8
7
TPD6F002-Q1
GND
1
2
3
4
5
6
12
11
10
9
G0
G1
G2
G3
G4
G5
8
7
TPD6F002-Q1
GND
1
2
3
4
5
6
12
11
10
9
B0
B1
B2
B3
B4
B5
8
7
GND
Figure 7. Display Panel Schematic
8
Copyright © 2014–2015, Texas Instruments Incorporated
TPD6F002-Q1
www.ti.com.cn
ZHCSDL8A –DECEMBER 2014–REVISED FEBRUARY 2015
Typical Application (continued)
9.2.1 Design Requirements
For this design example, three TPD6F002-Q1 devices are being used in an 18-bit display panel application. This
will provide a complete ESD and EMI protection solution for the display connector.
Given the display panel application, the following parameters are known.
DESIGN PARAMETER
Signal range on all pins except GND
Operating Frequency
VALUE
0 V to 5 V
50 MHz
9.2.2 Detailed Design Procedure
To begin the design process, some design parameters must be decided; the designer needs to know the
following:
•
•
•
Signal range of all the protected lines
Operating frequency
Crosstalk response
9.2.2.1 Signal Range on All Protected Lines
The TPD6F002-Q1 has 6 identical protection channels for signal lines. All I/O pins will support a signal range
from 0 to 5.5 V.
9.2.2.2 Operating Frequency
The TPD6F002-Q1 has a 100 MHz –3 dB bandwidth, which supports the operating frequency for this display.
9.2.2.3 Crosstalk Response
The TPD6F002-Q1 has a –47 dB near-side crosstalk attenuation at 100 MHz, sufficient for this display.
9.2.3 Application Curves
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
100000
1000000
1E+7
1E+8
1E+9
5E+9
Frequency (Hz)
D005
Figure 8. Near-Side Crosstalk
Copyright © 2014–2015, Texas Instruments Incorporated
9
TPD6F002-Q1
ZHCSDL8A –DECEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
10 Power Supply Recommendations
This device is a passive EMI and ESD device so there is no need to power it. Care should be taken to not violate
the recommended VIO specification (5.5 V) to ensure the device functions properly.
11 Layout
11.1 Layout Guidelines
•
The optimum placement is as close to the connector as possible.
–
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
–
The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
•
•
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
–
Electric fields tend to build up on corners, increasing EMI coupling.
11.2 Layout Example
This application is typical of an 18-bit RGB display panel layout.
VIA to GND Plane
GND
GND
GND
Figure 9. TPD6F002-Q1 Layout
10
版权 © 2014–2015, Texas Instruments Incorporated
TPD6F002-Q1
www.ti.com.cn
ZHCSDL8A –DECEMBER 2014–REVISED FEBRUARY 2015
12 器件和文档支持
12.1 商标
All trademarks are the property of their respective owners.
12.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.3 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2014–2015, Texas Instruments Incorporated
11
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Copyright © 2015, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPD6F002QDSVRQ1
ACTIVE
SON
DSV
12
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
UNS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jan-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD6F002QDSVRQ1
SON
DSV
12
3000
180.0
8.4
1.74
3.33
1.05
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jan-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SON DSV 12
SPQ
Length (mm) Width (mm) Height (mm)
213.0 191.0 35.0
TPD6F002QDSVRQ1
3000
Pack Materials-Page 2
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Copyright © 2020 德州仪器半导体技术（上海）有限公司
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