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TPD6S300A

ZHCSIE6 –JUNE 2018

TPD6S300A USB Type-C™端口保护器：V_BUS短路过压和 IEC ESD 保护

1 特性

这些非理想的设备和机械事件使得 CC 和 SBU 引脚必

须能够承受 20V 的电压，即使这些引脚仅在 5V 或更

低电压下工作。通过在 CC 和 SBU 引脚上提供过压保

护，TPD6S300A 可以使 CC 和 SBU 引脚耐受 20V 的

电压，同时不会干扰正常工作。该器件将高压 FET 串

联放置在 SBU 和 CC 线路上。当在这些线路上检测到

高于 OVP 阈值的电压时，高压开关被打开，并且将系

统的其余部分与连接器上存在的高压状态隔离。

1

•

4 通道 V_BUS短路过压保护（CC1、CC2、SBU1、

SBU2 或

CC1、CC2、DP、DM）：耐受 24V 直流电

•

6 通道 IEC 61000-4-2 ESD 保护（CC1、CC2、

SBU1、SBU2、DP、DM）

CC1 和 CC2 过压保护 FET 可处理最高 600mA 的

电流，因此可支持 V_CONN电源电流通过

集成 CC 死电池电阻器，可用于处理移动设备中的

死电池用例

最后，大多数系统都需要为其外部引脚应用 IEC

61000-4-2 系统级 ESD 保护。TPD6S300A 为 CC1、

CC2、SBU1、SBU2、DP 和 DM 引脚集成了 IEC

61000-4-2 ESD 保护，无需再在连接器上（外部）放

置高电压 TVS 二极管。

相较 TPD6S300 所具有的优势

–

更高的死电池性能

USB Type-C 端口在 IEC 61000-4-2 ESD 冲击

期间保持连接

•

3mm × 3mm WQFN 封装

器件信息⁽¹⁾

器件型号

TPD6S300A

封装

WQFN (20)

封装尺寸（标称值）

2 应用

3.00mm × 3.00mm

•

笔记本电脑

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

平板电脑

智能手机

监视器和电视

扩展坞

CC 和 SBU 过压保护

Battery

DC/DC

FET

OVP

3 说明

FET

OVP, OCP

5V

TPD6S300A 是一种单芯片 USB Type-C 端口保护器

件，可提供 20V V_BUS短路过压保护和 IEC ESD 保

护。

CC Analog

USB PD Phy &

Controller

TPD6S300A

OVP & ESD

Power Switch Control

SBU Mux

自从 USB Type-C 连接器发布以来，市场上已经发布

了很多不符合 USB Type-C 规格的 USB Type-C 产品

和配件。其中的一个示例就是仅在 V_BUS线路上布设

20V 电压的 USB Type-C 电力输送适配器。USB

Type-C 的另一个问题是，由于此小型连接器中的各引

脚极为靠近，因此连接器的机械扭转和滑动可能使引脚

短路。这可能导致 20V V_BUS与 CC 和 SBU 引脚短

路。此外，由于 Type-C 连接器中的各引脚极为靠近，

所以存在碎屑和水气导致 20V V_BUS引脚与 CC 和

SBU 引脚短路的严重问题。

CC 和 DP/DM 过压保护

Battery

DC/DC

FET

OVP

FET

OVP, OCP

5V

CC Analog

USB PD Phy &

Controller

TPD6S300A

OVP & ESD

Power Switch Control

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。 TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSEL8

TPD6S300A

ZHCSIE6 –JUNE 2018

www.ti.com.cn

8.3 Feature Description................................................. 17

8.4 Device Functional Modes........................................ 20

Application and Implementation ........................ 21

9.1 Application Information............................................ 21

9.2 Typical Application ................................................. 21

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 6

7.1 Absolute Maximum Ratings ...................................... 6

7.2 ESD Ratings—JEDEC Specification......................... 6

7.3 ESD Ratings—IEC Specification .............................. 6

7.4 Recommended Operating Conditions....................... 6

7.5 Thermal Information.................................................. 7

7.6 Electrical Characteristics........................................... 7

7.7 Timing Requirements ............................................... 9

7.8 Typical Characteristics............................................ 11

Detailed Description ............................................ 16

8.1 Overview ................................................................. 16

8.2 Functional Block Diagram ....................................... 16

9

10 Power Supply Recommendations ..................... 26

11 Layout................................................................... 27

11.1 Layout Guidelines ................................................. 27

11.2 Layout Example .................................................... 27

12 器件和文档支持 ..................................................... 28

12.1 文档支持................................................................ 28

12.2 接收文档更新通知 ................................................. 28

12.3 社区资源................................................................ 28

12.4 商标....................................................................... 28

12.5 静电放电警告......................................................... 28

12.6 术语表 ................................................................... 28

13 机械、封装和可订购信息....................................... 28

8

4 修订历史记录

日期

修订版本

说明

2018 年 6 月

*

初始发行版。

2

TPD6S300A

www.ti.com.cn

ZHCSIE6 –JUNE 2018

5 Device Comparison Table

Part Number

TPD6S300A

TPD8S300A

Over Voltage Protected Channels

IEC 61000-4-2 ESD Protected

Channels

4-Ch (CC1, CC2, SBU1, SBU2 or

CC1, CC2, DP, DM)

6-Ch (CC1, CC2, SBU1, SBU2, DP,

DM)

4-Ch (CC1, CC2, SBU1, SBU2 or

CC1, CC2, DP, DM)

8-Ch (CC1, CC2, SBU1, SBU2, DP_T,

DM_T, DP_B, DM_B)

3

TPD6S300A

ZHCSIE6 –JUNE 2018

www.ti.com.cn

6 Pin Configuration and Functions

RUK Package

20-Pin WQFN

Top View

15

11

N.C.

GND

D2

16

VPWR 10

FLT

GND

Thermal Pad

RPD_G1

RPD_G2

6

D1

20

1

5

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

Connector side of the SBU1 OVP FET. Connect to either SBU pin of the USB Type-C

connector. Alternatively, connect to either USB2.0 pin of the USB Type-C connector to

protect the USB2.0 pins instead of the SBU pins

1

2

C_SBU1

I/O

Connector side of the SBU2 OVP FET. Connect to either SBU pin of the USB Type-C

connector. Alternatively, connect to either USB2.0 pin of the USB Type-C connector to

protect the USB2.0 pins instead of the SBU pins

C_SBU2

I/O

3

4

VBIAS

P

Pin for ESD support capacitor. Place a 0.1-µF capacitor on this pin to ground

Connector side of the CC1 OVP FET. Connect to either CC pin of the USB Type-C

connector

C_CC1

I/O

Connector side of the CC2 OVP FET. Connect to either CC pin of the USB Type-C

connector

5

6

7

C_CC2

RPD_G2

RPD_G1

I/O

Short to C_CC2 if dead battery resistors are needed. If dead battery resistors are not

needed, short pin to GND

Short to C_CC1 if dead battery resistors are needed. If dead battery resistors are not

needed, short pin to GND

8

GND

FLT

GND

O

Ground

9

Open drain for fault reporting

10

11

12

13

V_PWR

CC2

CC1

GND

P

2.7-V to 4.5-V power supply

I/O

GND

System side of the CC2 OVP FET. Connect to either CC pin of the CC/PD controller

System side of the CC1 OVP FET. Connect to either CC pin of the CC/PD controller

Ground

System side of the SBU2 OVP FET. Connect to either SBU pin of the SBU MUX.

Alternatively, connect to either USB2.0 pin of the USB2.0 Phy when protecting the

USB2.0 pins instead of protecting the SBU pins

14

15

SBU2

SBU1

I/O

System side of the SBU1 OVP FET. Connect to either SBU pin of the SBU MUX.

Alternatively, connect to either USB2.0 pin of the USB2.0 Phy when protecting the

USB2.0 pins instead of protecting the SBU pins

(1) I = input, O = output, I/O = input and output, GND = ground, P = power

4

TPD6S300A

www.ti.com.cn

ZHCSIE6 –JUNE 2018

Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

N.C.

16

17

18

I/O

Unused pin. Connect to Ground

Ground

N.C.

GND

USB2.0 IEC ESD protection. Connect to any of the USB2.0 pins of the USB Type-C

connector

19

D2

D1

I/O

USB2.0 IEC ESD protection. Connect to any of the USB2.0 pins of the USB Type-C

connector

20

—

I/O

Thermal Pad

GND

Internally connected to GND. Used as a heatsink. Connect to the PCB GND plane

5

TPD6S300A

ZHCSIE6 –JUNE 2018

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–40

MAX

5

UNIT

V

V_PWR

V_I

Input voltage

RPD_G1, RPD_G2

24

6

V

FLT

V

V_O

Output voltage

VBIAS

24

6

V

D1, D2

V

V_IO

I/O voltage

CC1, CC2, SBU1, SBU2

C_CC1, C_CC2, C_SBU1, C_SBU2

6

V

24

85

150

V

T_A

Operating free air temperature

Storage temperature

°C

T_stg

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings—JEDEC Specification

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification

JESD22-C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000

V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V

may actually have higher performance.

7.3 ESD Ratings—IEC Specification

VALUE

±8000

UNIT

Contact discharge

Air-gap discharge

Contact discharge

Air-gap discharge

IEC 61000-4-2, C_CC1, C_CC2, D1, D2

IEC 61000-4-2, C_SBU1, C_SBU2

±15000

±6000

V_(ESD)

Electrostatic discharge⁽¹⁾

V

±15000

(1) Tested on the TPD6S300 EVM connected to the TPS65982 EVM.

7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.7

0

NOM

MAX

4.5

5.5

4.3

UNIT

V_PWR

3.3

V

V_I

Input voltage

RPD_G1, RPD_G2

V_O

Output voltage

FLT pull-up resistor power rail

D1, D2

2.7

–0.3

0

V_IO

I/O voltage

CC1, CC2, C_CC1, C_CC2

SBU1, SBU2, C_SBU1, C_SBU2

0

Current flowing into CC1/2 and flowing

out of C_CC1/2, VCCx – VC_CCx ≤

250 mV

I_VCONN

V_CONNcurrent

600

mA

Current flowing into CC1/2 and flowing

out of C_CC1/2, T_J≤ 105°C

I_VCONN

V_CONNcurrent

600

mA

A

Current flowing into CC1/2 and flowing

out of C_CC1/2, T_J≤ 85°C

1.25

6

TPD6S300A

www.ti.com.cn

ZHCSIE6 –JUNE 2018

Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

kΩ

FLT pullup resistance

1.7

300

External components⁽¹⁾

VBIAS capacitance⁽²⁾

0.1

1

µF

V_PWRcapacitance

0.3

µF

(1) For recommended values for capacitors and resistors, the typical values assume a component placed on the board near the pin.

Minimum and maximum values listed are inclusive of manufacturing tolerances, voltage derating, board capacitance, and temperature

variation. The effective value presented must be within the minimum and maximums listed in the table.

(2) The VBIAS pin requires a minimum 35-V_DCrated capacitor. A 50-V_DCrated capacitor is recommended to reduce capacitance derating.

See the VBIAS Capacitor Selection section for more information on selecting the VBIAS capacitor.

7.5 Thermal Information

TPD6S300A

THERMAL METRIC⁽¹⁾

RUK (WQFN)

20 PINS

45.2

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

48.8

17.1

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.6

ψ_JB

17.1

R_θJC(bot)

3.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

CC OVP SWITCHES

TEST CONDITIONS

MIN

TYP

MAX

UNIT

On resistance of CC OVP FETs, T_J≤

85°C

CCx = 5.5 V

278

392

415

5

mΩ

R_ON

On resistance of CC OVP FETs, T_J≤

105°C

CCx = 5.5 V

Sweep CCx voltage between 0 V and

1.2 V

R_ON(FLAT)

On resistance flatness

Capacitance from C_CCx or CCx to

GND when device is powered.

VC_CCx/VCCx = 0 V to 1.2 V, f = 400

kHz

C_{ON_CC}

Equivalent on capacitance

60

74

120

6.1

pF

Dead battery pull-down resistance

(only present when device is

unpowered). Effective resistance of

R_Dand FET in series

R_D

V_C_CCx = 2.6 V

I_CC = 80 µA

4.1

5.1

kΩ

Threshold voltage of the pulldown

FET in series with RD during dead

battery

VTH_DB

V_OVPCC

0.5

0.9

6

1.2

6.2

V

Place 5.5 V on C_CCx. Step up

C_CCx until the FLT pin is asserted

OVP threshold on CC pins

5.75

Place 6.5 V on C_CCx. Step down the

voltage on C_CCx until the FLT pin is

deasserted. Measure difference

between rising and falling OVP

threshold for C_CCx

V_{OVPCC_HYS}

Hysteresis on CC OVP

50

mV

Measure the –3-dB bandwidth from

C_CCx to CCx. Single ended

measurement, 50-Ω system. Vcm = 0.1

V to 1.2 V

BW_ON

On bandwidth single ended (–3 dB)

100

MHz

7

TPD6S300A

ZHCSIE6 –JUNE 2018

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Hot-Plug C_CCx with a 1 meter USB

Type C Cable, place a 30-Ω load on

CCx

Short-to-VBUS tolerance on the CC

pins

V_{STBUS_CC}

24

V

Hot-Plug C_CCx with a 1 meter USB

V_{STBUS_CC_CL}Short-to-VBUS system-side clamping Type C Cable. Hot-Plug voltage

8

V

voltage on the CC pins (CCx)

C_CCx = 24 V. VPWR = 3.3 V. Place

AMP

a 30-Ω load on CCx

SBU OVP SWITCHES

R_ON

On resistance of SBU OVP FETs

SBUx = 3.6 V. –40°C ≤ T_J≤ +85°C

4

6.5

1.5

Ω

Sweep SBUx voltage between 0 V and

3.6 V. –40°C ≤ T_J≤ +85°C

R_ON(FLAT)

On resistance flatness

0.7

Capacitance from SBUx or C_SBUx to

GND when device is powered.

Measure at VC_SBUx/VSBUx = 0.3 V

to 3.6 V

C_{ON_SBU}

Equivalent on capacitance

OVP threshold on SBU pins

6

pF

V

Place 3.6 V on C_SBUx. Step up

C_SBUx until the FLT pin is asserted

V_OVPSBU

4.35

4.5

4.7

Place 5 V on C_CCx. Step down the

voltage on C_CCx until the FLT pin is

deasserted. Measure difference

between rising and falling OVP

threshold for C_SBUx

V_{OVPSBU_HYS}Hysteresis on SBU OVP

50

1000

–80

mV

MHz

dB

V

Measure the –3-dB bandwidth from

C_SBUx to SBUx. Single ended

measurement, 50-Ω system. Vcm = 0.1

V to 3.6 V

BW_ON

On bandwidth single ended (–3 dB)

Measure crosstalk at f = 1 MHz from

SBU1 to C_SBU2 or SBU2 to

C_SBU1. Vcm1 = 3.6 V, Vcm2 = 0.3 V.

Be sure to terminate open sides to 50

Ω

X_TALK

Crosstalk

Hot-Plug C_SBUx with a 1 meter USB

Short-to-VBUS tolerance on the SBU Type C Cable. Put a 100-nF capacitor

V_{STBUS_SBU}

24

pins

in series with a 40-Ω resistor to GND

on SBUx

Hot-Plug C_SBUx with a 1 meter USB

Type C Cable. Hot-Plug voltage

C_SBUx = 24 V. VPWR = 3.3 V. Put a

150-nF capacitor in series with a 40-Ω

resistor to GND on SBUx

V_{STBUS_SBU_C}Short-to-VBUS system-side clamping

8

V

voltage on the SBU pins (SBUx)

LAMP

POWER SUPPLY and LEAKAGE CURRENTS

Place 1 V on VPWR and raise voltage

until SBU or CC FETs turnon

V_{PWR_UVLO}

V_PWRunder voltage lockout

V_PWRUVLO hysteresis

V_PWRsupply current

2.1

2.3

150

90

2.5

200

135

V

Place 3 V on VPWR and lower voltage

until SBU or CC FETs turnoff; measure

difference between rising and falling

UVLO to calculate hysteresis

V_{PWR_UVLO_H}

YS

100

mV

µA

VPWR = 3.3 V (typical), VPWR = 4.5 V

(maximum). –40°C ≤ T_J≤ +85°C.

I_VPWR

VPWR = 3.3 V, VC_CCx = 3.6 V, CCx

pins are floating, measure leakage into

C_CCx pins. Result must be same if

CCx side is biased and C_CCx is left

floating

Leakage current for CC pins when

device is powered

I_{CC_LEAK}

5

µA

8

TPD6S300A

www.ti.com.cn

ZHCSIE6 –JUNE 2018

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VPWR = 3.3 V, VC_SBUx = 3.6 V,

SBUx pins are floating, measure

leakge into C_SBUx pins. Result must

be same if SBUx side is biased and

C_SBUx is left floating. –40°C ≤ T_J≤

+85°C

Leakage current for SBU pins when

device is powered

I_{SBU_LEAK}

3

µA

VPWR = 0 V or 3.3 V, VC_CCx = 24

V, CCx pins are set to 0 V, measure

leakage into C_CCx pins

I_{C_CC_LEAK_OV}Leakage current for CC pins when

1200

400

30

µA

device is in OVP

P

VPWR = 0 V or 3.3 V, VC_SBUx = 24

V, SBUx pins are set to 0 V, measure

leakage into C_SBUx pins

I_{C_SBU_LEAK_O}Leakage current for SBU pins when

device is in OVP

VP

VPWR = 0 V or 3.3 V, VC_CCx = 24

V, CCx pins are set to 0 V, measure

leakage out of CCx pins

Leakage current for CC pins when

I_{CC_LEAK_OVP}

device is in OVP

VPWR = 0 V or 3.3 V, VC_SBUx = 24

V, SBUx pins are set to 0 V, measure

leakage out of SBUx pins

Leakage current for SBU pins when

I_{SBU_LEAK_OVP}

–1

1

µA

device is in OVP

V_Dx = 3.6 V, measure leakage into

Dx pins

I_{Dx_LEAK}

FLT PIN

V_OL

Leakage current for Dx pins

Low-level output voltage

IOL = 3 mA. Measure the voltage at

the FLT pin

0.4

V

OVER TEMPERATURE PROTECTION

The rising over-temperature

T_{SD_RISING}

150

130

175

140

35

°C

protection shutdown threshold

The falling over-temperature

T_{SD_FALLING}

protection shutdown threshold

The over-temperature protection

T_{SD_HYST}

shutdown threshold hysteresis

Dx ESD PROTECTION

Reverse stand-off voltage from Dx to

V_{RWM_POS}

GND

Dx to GND. I_DX≤ 1 µA

5.5

0

V

Reverse stand-off voltage from GND

to Dx

V_{RWM_NEG}

GND to Dx

V_{BR_POS}

V_{BR_NEG}

C_IO

Break-down voltage from Dx to GND Dx to GND. I_BR= 1 mA

Break-down voltage from GND to Dx GND to Dx. I_BR= 8 mA

7

V

0.6

Dx to GND or GND to Dx

f = 1 MHz, VIO = 2.5 V

1.7

pF

Differential capacitance between two

Dx pins

ΔC_IO

f = 1 MHz, VIO = 2.5 V

0.02

pF

Dynamic on-resistance Dx IEC

clamps

R_DYN

Dx to GND or GND to Dx

0.4

Ω

7.7 Timing Requirements

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

POWER-ON and Off TIMINGS

Time from crossing rising VPWR UVLO until CC and SBU

OVP FETs are on

t_{ON_FET}

1.3

5.7

3.5

9.5

ms

Time from crossing rising VPWR UVLO until CC and SBU

OVP FETs are on and the dead battery resistors are

turned off

t_{ON_FET_DB}

Minimum Slew rate allowed to guarantee CC and SBU

FETs turnoff during a power off

dV_{PWR_OFF}/dt

–0.5

V/µs

9

TPD6S300A

ZHCSIE6 –JUNE 2018

www.ti.com.cn

Timing Requirements (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

OVER VOLTAGE PROTECTION

OVP response time on the CC pins. Time from OVP

t_{OVP_RESPONSE_CC}

70

80

ns

asserted until OVP FETs turnoff

OVP response time on the SBU pins. Time from OVP

t_{OVP_RESPONSE_SBU}

asserted until OVP FETs turnoff

OVP recovery time on the CC pins. Once an OVP has

occurred, the minimum time duration until the CC FETs

turn back on. OVP must be removed for CC FETs to turn

back on

t_{OVP_RECOVERY_CC_1_FET}

0.93

5

ms

OVP recovery time on the CC pins. Once an OVP has

occurred, the minimum time duration until the CC FETs

turn back on and the dead battery resistors turn off. OVP

must be removed for CC FETs to turn back on

t_{OVP_RECOVERY_CC_1_DB}

OVP recovery time on the SBU pins. Once an OVP has

occurred, the minimum time duration until the SBU FETs

turn back on. OVP must be removed for SBU FETs to turn

t_{OVP_RECOVERY_SBU_1}

0.62

back on

OVP recovery time on the CC pins. Time from OVP

t_{OVP_RECOVERY_CC_2_FET}

t_{OVP_RECOVERY_CC_2_DB}

t_{OVP_RECOVERY_SBU_2}

Removal until CC FETs turn back on, if device has been in

OVP > 0.6 ms

0.61

4.75

0.3

ms

OVP recovery time on the CC pins. Time from OVP

Removal until CC FETs turn back on and dead battery

resistors turn off, if device has been in OVP > 0.6 ms

OVP recovery time on the SBU pins. Time from OVP

Removal until SBU FETs turn back on, if device has been

in OVP > 0.6 ms

t_{OVP_FLT_ASSERTION}

Time from OVP asserted to FLT assertion

20

µs

Time from CC FET turnon after an OVP to FLT

deassertion

t_{OVP_FLT_DEASSERTION}

4.1

ms

10

TPD6S300A

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ZHCSIE6 –JUNE 2018

7.8 Typical Characteristics

0

-10

-20

-30

-40

-50

-60

-70

-80

-3

-6

-9

SBUx to C_SBUx

-12

1E+7

1E+8

1E+9

3E+9

0

1E+9

2E+9

3E+9

Frequency (Hz)

D016

D017

图 1. SBU S21 BW

图 2. SBU Crosstalk

30.5

10.5

8.5

6.5

4.5

2.5

0.5

-1.5

V_{C_SBU1}

I_{C_SBU1}

V_SBU1

V_{C_SBU1}

I_{C_SBU1}

V_SBU1

28.5

26.5

24.5

22.5

20.5

18.5

16.5

14.5

12.5

10.5

8.5

V_/FLT

6.5

4.5

2.5

0.5

-1.5

-0.05 0.2

0.45

0.7

0.95

1.2

1.45

1.7

1.95

-2.2 -0.2 1.8 3.8 5.8 7.8 9.8 11.8 13.8 15.8 17.8

Time (ms)

D014

图 3. SBU Short-to-V_BUS20 V

图 4. SBU Short-to-V_BUS5 V

140

120

100

80

7

6

5

4

3

2

-40èC

25èC

85èC

125èC

60

40

20

0

-20

-40

-60

-80

C_SBU

SBU

0

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7

V_SBU1(V)

3

3.3 3.6

-10

0

10 20 30 40 50 60 70 80 90 100 110

Time (ns)

D014

D001

图 5. SBU R_ONFlatness

图 6. SBU IEC 61000-4-2 4-kV Response Waveform

11

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Typical Characteristics (接下页)

80

2.5

2

C_SBU1

C_SBU2

60

40

20

1.5

1

0

-20

-40

-60

-80

-100

0.5

C_SBU

SBU

0

-10

0

10 20 30 40 50 60 70 80 90 100 110

Time (ns)

-40 -30 -20 -10

0

10 20 30 40 50 60 70 8085

Temperature (èC)

D001

D014

图 7. SBU IEC 61000-4-2 –4-kV Response Waveform

图 8. SBU Path Leakage Current vs Ambient Temperature at

3.6 V

500

450

400

350

300

250

200

150

100

50

0.000125

C_SBU1 at 24 V

C_SBU2 at 24 V

C_SBU1 at 5.5 V

C_SBU2 at 5.5 V

SBU1: C_SBU1 at 24 V

SBU2: C_SBU2 at 24 V

SBU1: C_SBU1 at 5.5 V

0.0001

SBU2: C_SBU2 at 5.5 V

7.5E-5

5E-5

2.5E-5

0

-40 -30 -20 -10

0

10 20 30 40 50 60 70 8085

-40 -30 -20 -10

0

10 20 30 40 50 60 70 8085

Temperature (èC)

D014

图 9. C_SBU OVP Leakage Current vs Ambient Temperature

图 10. SBU OVP Leakage Current vs Ambient Temperature

at 5.5 V and 24 V

3.6

3.3

3

30

C_SBU

25

20

15

10

5

2.7

2.4

2.1

1.8

1.5

1.2

0.9

V_PWR

C_SBU1

SBU1

0.6

0.3

0

-3

-2

-1

0

1

2

3

4

5

6

7

0

5

10

15

20

25

30

35

40

Time (ms)

Voltage (V)

D014

D005

图 11. SBU FET Turnon Timing

图 12. C_SBU TLP Curve Unpowered

12

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ZHCSIE6 –JUNE 2018

Typical Characteristics (接下页)

0

-3

1

0.75

0.5

0.25

0

-6

-0.25

-0.5

-0.75

-1

-9

C_SBU

30 35

-12

1E+7

-5

0

5

10

15

20

25

1E+8

1E+9

3E+9

Voltage (V)

Frequency (Hz)

D003

D016

图 13. SBU IV Curve

图 14. CC S21 BW

30.5

28.5

26.5

24.5

22.5

20.5

18.5

16.5

14.5

12.5

10.5

8.5

0.6

0.5

0.4

0.3

0.2

0.1

0

V_{C_CC1}

I_{C_CC1}

V_CC1

-40èC

25èC

85èC

125èC

V_/FLT

6.5

4.5

2.5

0.5

-1.5

-0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.71.8

0

0.2

0.4

0.6

0.8

1

1.2

Time (ms)

V_CC1(V)

D014

图 15. CC Short-to-V_BUS20 V

图 16. CC R_ONFlatness

140

120

100

80

60

40

20

60

0

40

20

-20

-40

-60

-80

-100

0

-20

-40

-60

-80

C_CC

CC

C_CC

CC

-10

0

10 20 30 40 50 60 70 80 90 100 110

Time (ns)

-10

0

10 20 30 40 50 60 70 80 90 100 110

Time (ns)

D001

图 17. CC IEC 61000-4-2 8-kV Response Waveform

图 18. CC IEC 61000-4-2 –8-kV Response Waveform

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ZHCSIE6 –JUNE 2018

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Typical Characteristics (接下页)

1030

1025

1020

1015

1010

1005

1000

20

C_CC1

C_CC2

C_CC1

19

C_CC2

18

17

16

15

14

13

12

11

10

9

8

-40 -30 -20 -10

0

10 20 30 40 50 60 70 8085

-40 -30 -20 -10

0

10 20 30 40 50 60 70 8085

Temperature (èC)

D014

图 19. C_CC Path Leakage Current vs Ambient Temperature

图 20. C_CC OVP Leakage Current vs Ambient Temperature

at C_CC = 5.5 V

at C_CC = 24 V

4.3E-4

5.5

5

CC1: C_CC1 at 24 V

CC2: C_CC2 at 24 V

3.8E-4

3.3E-4

2.8E-4

2.3E-4

1.8E-4

1.3E-4

8E-5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

V_PWR

C_CC1

CC1

3E-5

-40 -30 -20 -10

0

10 20 30 40 50 60 70 8085

Temperature (èC)

-3

-2

-1

0

1

2

3

4

5

6

7

Time (ms)

D014

图 21. CC OVP Leakage Current vs Ambient Temperature at

图 22. CC FET Turnon Timing

C_CC = 24 V

30

1

0.75

0.5

C_CC

25

20

15

10

5

0.25

0

-0.25

-0.5

-0.75

-1

C_CC

25 30

0

5

10

15

20

25

30

35

40

45

-5

0

5

10

15

20

Voltage (V)

D0035

D003

图 23. C_CC TLP Curve Unpowered

图 24. C_CC IV Curve

14

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Typical Characteristics (接下页)

100

7

6

5

4

3

2

1

0

I_VPWR

Dx at 3.6 V

Dx at 0.4 V

97.5

95

92.5

90

87.5

85

82.5

80

-40 -30 -20 -10

0

10 20 30 40 50 60 70 8085

-40 -30 -20 -10

0

10 20 30 40 50 60 70 8085

Temperature (èC)

D014

图 25. V_PWRSupply Leakage vs Ambient Temperature at 3.6

图 26. Dx Leakage Current vs Ambient Temperature at 0.4 V

V

and 3.6 V

1

0.75

0.5

30

Dx

25

20

15

10

5

0.25

0

-0.25

-0.5

-0.75

Dx

10

-1

-2

0

2

4

6

8

0

2

4

6

8

10

12

14

16

18

Voltage (V)

D003

D0035

图 27. Dx IV Curve

图 28. Dx TLP Curve

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8 Detailed Description

8.1 Overview

The TPD6S300A is a single chip USB Type-C port protection solution that provides 20-V Short-to-V_BUS

overvoltage and IEC ESD protection. Due to the small pin pitch of the USB Type-C connector and non-compliant

USB Type-C cables and accessories, the V_BUSpins can get shorted to the CC and SBU pins inside the USB

Type-C connector. Because of this short-to-V_BUSevent, the CC and SBU pins need to be 20-V tolerant, to

support protection on the full USB PD voltage range. Even if a device does not support 20-V operation on V_BUS

,

non complaint adaptors can start out with 20-V V_BUScondition, making it necessary for any USB Type-C device

to support 20 V protection. The TPD6S300A integrates four channels of 20-V Short-to-V_BUSovervoltage

protection for the CC1, CC2, SBU1, and SBU2 pins of the USB Type-C connector.

Additionally, IEC 61000-4-2 system level ESD protection is required in order to protect a USB Type-C port from

ESD strikes generated by end product users. The TPD6S300A integrates six channels of IEC61000-4-2 ESD

protection for the CC1, CC2, SBU1, SBU2, DP, and DM pins of the USB Type-C connector. This means IEC

ESD protection is provided for all of the low-speed pins on the USB Type-C connector in a single chip in the

TPD6S300A. Additionally, high-voltage IEC ESD protection that is 22-V DC tolerant is required for the CC and

SBU lines in order to simultaneously support IEC ESD and Short-to-V_BUSprotection; there are not many discrete

market solutions that can provide this kind of protection. This high-voltage IEC ESD diode is what the

TPD6S300A integrates, specifically designed to guarantee it works in conjunction with the overvoltage protection

FETs inside the device. This sort of solution is very hard to generate with discrete components.

8.2 Functional Block Diagram

Control Logic and

Charge Pumps

Over-voltage

Protection

VPWR

FLT

C_SBU1

SBU1

ESD

Clamps

System

Clamps

C_SBU2

VBIAS

SBU2

CC1

C_CC1

ESD

Clamps

System

Clamps

C_CC2

CC2

/V_PWR

R_D

/V_PWR

RPD_G1

RPD_G2

R_D

D2

D1

16

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8.3 Feature Description

8.3.1 4-Channels of Short-to-V_BUSOvervoltage Protection (CC1, CC2, SBU1, SBU2 Pins or CC1, CC2, DP,

DM Pins): 24-V_DCTolerant

The TPD6S300A provides 4-channels of Short-to-V_BUSOvervoltage Protection for the CC1, CC2, SBU1, and

SBU2 pins (or the CC1, CC2, DP, and DM pins) of the USB Type-C connector. The TPD6S300A is able to

handle 24-V_DCon its C_CC1, C_CC2, C_SBU1, and C_SBU2 pins. This is necessary because according to the

USB PD specification, with V_BUSset for 20-V operation, the V_BUSvoltage is allowed to legally swing up to 21 V

and 21.5 V on voltage transitions from a different USB PD V_BUSvoltage. The TPD6S300A builds in tolerance up

to 24-V_BUSto provide margin above this 21.5-V specification to be able to support USB PD adaptors that may

break the USB PD specification.

When a short-to-V_BUSevent occurs, ringing happens due to the RLC elements in the hot-plug event. With very

low resistance in this RLC circuit, ringing up to twice the settling voltage can appear on the connector. More than

2x ringing can be generated if any capacitor on the line derates in capacitance value during the short-to-V_BUS

event. This means that more than 44 V could be seen on a USB Type-C pin during a Short-to-V_BUSevent. The

TPD6S300A has built in circuit protection to handle this ringing. The diode clamps used for IEC ESD protection

also clamp the ringing voltage during the short-to-V_BUSevent to limit the peak ringing to approximately 30 V.

Additionally, the overvoltage protection FETs integrated inside the TPD6S300A are 30-V tolerant, therefore being

capable of supporting the high-voltage ringing waveform that is experienced during the short-to-V_BUSevent. The

well designed combination of voltage clamps and 30-V tolerant OVP FETs insures the TPD6S300A can handle

Short-to-V_BUShot-plug events with hot-plug voltages as high as 24-V_DC

.

The TPD6S300A has an extremely fast turnoff time of 70 ns typical. Furthermore, additional voltage clamps are

placed after the OVP FET on the system side (CC1, CC2, SBU1, SBU2) pins of the TPD6S300A, to further limit

the voltage and current that are exposed to the USB Type-C CC/PD controller during the 70 ns interval while the

OVP FET is turning off. The combination of connector side voltage clamps, OVP FETs with extremely fast turnoff

time, and system side voltage clamps all work together to insure the level of stress seen on a CC1, CC2, SBU1,

or SBU2 pin during a short-to-V_BUSevent is less than or equal to an HBM event. This is done by design, as any

USB Type-C CC/PD controller will have built in HBM ESD protection.

The SBU OVP FETs where designed with a 1-GHz bandwidth to be able to be used to protect the DP, DM

(USB2.0) pins in addition to the SBU pins. Some systems designers also prefer to protect the DP, DM pins from

Short-to-V_BUSevents due to the potential for moisture/water in the connector to short the V_BUSpins to DP, DM

pins. This can be especially applicable in cases where the end equipment with a USB Type-C connector is trying

to be made water-proof. If desiring to protect the DP, DM pins on the USB Type-C connector from a Short-to-

V_BUSevent, connect the C_SBUx pins to the DP, DM pins on the USB Type-C connector, and the SBUx pins to

the USB2.0 pins of the system device being protected from the Short-to-V_BUSevent.

图 29 is an example of the TPD6S300A successfully protecting the TPS65982, the world's first fully integrated,

full-featured USB Type-C and PD controller.

图 29. TPD6S300A Protecting the TPS65982 During a Short-to-V_BUSEvent

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Feature Description (接下页)

8.3.2 6-Channels of IEC 61000-4-2 ESD Protection (CC1, CC2, SBU1, SBU2, DP, DM Pins)

The TPD6S300A integrates 6-Channels of IEC 61000-4-2 system level ESD protection for the CC1, CC2, SBU1,

SBU2, DP, and DM pins. USB Type-C ports on end-products need system level IEC ESD protection in order to

provide adequate protection for the ESD events that the connector can be exposed to from end users. The

TPD6S300A integrates IEC ESD protection for all of the low-speed pins on the USB Type-C connector in a

single chip. Also note, that while the RPD_Gx pins are not individually rated for IEC ESD, when they are shorted

to the C_CCx pins, the C_CCx pins provide protection for both the C_CCx pins and the RPD_Gx pins.

Additionally, high-voltage IEC ESD protection that is 24-V DC tolerant is required for the CC and SBU lines in

order to simultaneously support IEC ESD and Short-to-V_BUSprotection; there are not many discrete market

solutions that can provide this kind of protection. The TPD6S300A integrates this type of high-voltage ESD

protection so a system designer can meet both IEC ESD and Short-to-V_BUSprotection requirements in a single

device.

8.3.3 CC1, CC2 Overvoltage Protection FETs 600 mA Capable for Passing VCONN Power

The CC pins on the USB Type-C connector serve many functions; one of the functions is to be a provider of

power to active cables. Active cables are required when desiring to pass greater than 3 A of current on the V_BUS

line or when the USB Type-C port uses the super-speed lines (TX1+, TX2–, RX1+, RX1–, TX2+, TX2–, RX2+,

RX2–). When CC is configured to provide power, it is called VCONN. VCONN is a DC voltage source in the

range of 3 V to 5.5 V. If supporting VCONN, a VCONN provider must be able to provide 1 W of power to a cable;

this translates into a current range of 200 mA to 333 mA (depending on your VCONN voltage level). Additionally,

if operating in a USB PD alternate mode, greater power levels are allowed on the VCONN line.

When a USB Type-C port is configured for VCONN and using the TPD6S300A, this VCONN current flows

through the OVP FETs of the TPD6S300A. Therefore, the TPD6S300A has been designed to handle these

currents and have an RON low enough to provide a specification compliant VCONN voltage to the active cable.

The TPD6S300A is designed to handle up to 600 mA of DC current to allow for alternate mode support in

addition to the standard 1 W required by the USB Type-C specification.

8.3.4 CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices

An important feature of USB Type-C and USB PD is the ability for this connector to serve as the sole power

source to mobile devices. With support up to 100 W, the USB Type-C connector supporting USB PD can be

used to power a whole new range of mobile devices not previously possible with legacy USB connectors.

When the USB Type-C connector is the sole power supply for a battery powered device, the device must be able

to charge from the USB Type-C connector even when its battery is dead. In order for a USB Type-C power

adapter to supply power on V_BUS, RD pulldown resistors must be exposed on the CC pins. These RD resistors

are typically included inside a USB Type-C CC/PD controller. However, when the TPD6S300A is used to protect

the USB Type-C port, the OVP FETs inside the device isolate these RD resistors in the CC/PD controller when

the mobile device has no power. This is because when the TPD6S300A has no power, the OVP FETs are turned

off to guarantee overvoltage protection in a dead battery condition. Therefore, the TPD6S300A integrates high-

voltage, dead battery RD pull-down resistors to allow dead battery charging simultaneously with high-voltage

OVP protection.

If dead battery support is required, short the RPD_G1 pin to the C_CC1 pin, and short the RPD_G2 pin to the

C_CC2 pin. This connects the dead battery resistors to the connector CC pins. When the TPD6S300A is

unpowered, and the RP pull-up resistor is connected from a power adaptor, this RP pull-up resistor activates the

RD resistor inside the TPD6S300A. This enables V_BUSto be applied from the power adaptor even in a dead

battery condition. Once power is restored back to the system and back to the TPD6S300A on its VPWR pin, the

TPD6S300A turns ON its OVP FETs in 3.5 ms and then turns OFF its dead battery RD. The TPD6S300A first

turns ON its CC OVP FETs fully, and then removes its dead battery RDs. This is to make sure the PD controller

RD is fully exposed before removing the RD of the TPD6S300A. This is to help ensure the USB Type-C source

remains attached because a USB Type-C sink must have an RD present on CC at all times to guarantee

according to the USB Type-C spec that the USB Type-C source remains attached.

18

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Feature Description (接下页)

If desiring to power the CC/PD controller during dead battery mode and if the CC/PD Controller is configured as

a DRP, it is critical that the TPD6S300A be powered before or at the same time that the CC/PD controller is

powered. It is also critical that when unpowered, the CC/PD controller also expose its dead battery resistors.

When the TPD6S300A gets powered, it exposes the CC pins of the CC/PD controller within 3.5 ms, and then

removes its own RD dead battery resistors. Once the TPD6S300A turns on, the RD pull-down resistors of the

CC/PD controller must be present immediately, in order to guarantee the power adaptor connected to power the

dead battery device keeps its V_BUSturned on. If the power adaptor does not see RD present, it can disconnect

V_BUS. This removes power from the device with its battery still not sufficiently charged, which consequently

removes power from the CC/PD controller and the TPD6S300A. Then the RD resistors of the TPD6S300A are

exposed again, and connects the power adaptor's V_BUSto start the cycle over. This creates an infinite loop, never

or very slowly charging the mobile device.

If the CC/PD Controller is configured for DRP and has started its DRP toggle before the TPD6S300A turns on,

this DRP toggle is unable to guarantee that the power adaptor does not disconnect from the port. Therefore, it is

recommended if the CC/PD controller is configured for DRP, that its dead battery resistors be exposed as well,

and that they remain exposed until the TPD6S300A turns on. This is typically accomplished by powering the

TPD6S300A at the same time as the CC/PD controller when powering the CC/PD controller in dead battery

operation. When protecting the TPS6598x family of PD controllers with TPD6S300A, this is accomplished by

powering TPD6S300A from TPS6598x's LDO_3V3 pin (connect TPS6598x's LDO_3V3 pin to TPD6S300A's

V_PWRpin).

If dead battery charging is not required in your application, connect the RPD_G1 and RPD_G2 pins to ground.

8.3.5 Advantages over TPD6S300

8.3.5.1 Improved Dead Battery Performance

The TPD6S300A has improved dead battery performance over TPD6S300. In the TPD6S300 when the device is

first powered (VPWR pin goes from 0V to 3.3V), the CC RD dead battery resistors are disabled at the same time

the CC OVP FETs are enabled. This leads to a small ~400us time window where the CC pin can float up above

the SRC.RD voltage threshold because the CC OVP FETs are still too resistive for the source to detect RD from

the USB-PD controller. If the tSRCDisconnect debounce time of the USB Type-C source is less than ~400us, this

could cause a USB Type-C disconnect for the source port during the dead battery boot-up event. Many USB

Type-C Sources do not have a tSRCDisconnect debounce time less than ~400us; however, the USB Type-C

spec allows the tSRCDisconnect time to be as low as 0ms, so some USB Type-C sources may have a

tSRCDisconnect debounce time that is less than ~400us. TPD6S300A solves this problem. When the

TPD6S300A is first powered (VPWR pin goes from 0V to 3.3V), TPD6S300A waits for its CC OVP FETs to be

completely ON before it removes its RD dead battery resistors. This guarantees that an RD resistor will always

be present on the CC line during the dead battery boot-up, and that the USB Type-C source's CC voltage will

always stay in the SRC.RD range; therefore, even if a source had a tSRCDisconnect debounce time of 0ms, it

will remain connected. See 图 32 for an oscilloscope capture of TPD6S300A's proper dead battery boot-up

behavior.

8.3.5.2 USB Type-C Port Stays Connected during an IEC 61000-4-2 ESD Strike

The TPD6S300A will also make sure the USB Type-C ports stay connected, even during an IEC 61000-4-2 ESD

strike, whereas the TPD6S300 has the potential to cause a USB Type-C port disconnect during an IEC 61000-4-

2 ESD strike. In TPD6S300, in some PCB layouts an IEC 61000-4-2 ESD strike would cause TPD6S300 to go

into the OVP state. In TPD6S300, the CC OVP recovery time was 21ms minimum. This means that if an OVP

happened in TPD6S300, a USB-C disconnect was guaranteed to happen, because the maximum USB Type-C

port disconnect time for sources and sinks is 20ms max in the USB Type-C specification. However, in

TPD6S300A, the CC OVP recovery time is 0.93ms typical. For TPD6S300A, the OVP FET will turn back ON

much faster than a sinks minimum disconnect time, which is 10ms. So even if an IEC 61000-4-2 ESD strike

causes an OVP in TPD6S300A, the new CC OVP FET recovery time of 0.93ms will not cause a disconnect on

the USB Type-C port for a sink.

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TPD6S300A

ZHCSIE6 –JUNE 2018

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Feature Description (接下页)

For a source port connected to a sink with a TPD6S300A, if an IEC 61000-4-2 ESD strike occurs that causes an

OVP event, even an OVP recovery time of 0.93ms could cause a disconnect, because for source USB Type-C

ports, they have a minimum disconnect time of 0ms in the USB Type-C specification. So the CC OVP FET in

TPD6S300A would open up and hide the PD controllers RD for 0.93ms, causing a potential for a disconnect on

the source USB Type-C port. To solve this problem, TPD6S300A turns on its dead battery RD resistor in an OVP

event caused by an IEC 61000-4-2 ESD strike while the CC OVP FET is OFF. This makes it so even during this

OVP event caused by IEC ESD, the source port connected to the sink port with TPD6S300A will always see an

RD resistor. Therefore, even if the source port has an extremely low tSrcDisconnect time close to 0ms, it will

remain connected because an RD resistor is always present on its CC pin.

8.3.6 3-mm × 3-mm WQFN Package

The TPD6S300A comes in a small, 3-mm × 3-mm WQFN package, greatly reducing the size of implementing a

similar protection solution discretely. The WQFN package allows support for a wider range of PCB designs.

8.4 Device Functional Modes

表 1 describes all of the functional modes for the TPD6S300A. The "X" in the below table are "do not care"

conditions, meaning any value can be present within the absolute maximum ratings of the datasheet and

maintain that functional mode. Also note the D1 and D2 pins are not listed, because these pins have IEC ESD

protection diodes that are always present, regardless of whether the device is powered and regardless of the

conditions on any of the other pins.

表 1. Device Mode Table

Device Mode Table

MODE

Inputs

C_SBUx

Outputs

CC FETs

VPWR C_CCx

RPD_Gx

T_J

FLT

SBU FETs

Unpowered,

no dead

battery

<UVLO

X

Grounded

X

High-Z

OFF

support

Normal

Operating Unpowered,

Conditions dead battery <UVLO

Shorted to

C_CCx

X

High-Z

OFF

support

X, forced

OFF

Powered on >UVLO <OVP

<OVP

X

<TSD

>TSD

ON

Thermal

shutdown

X, forced

OFF

Low (Fault

Asserted)

>UVLO

X

OFF

CC over

voltage

condition

X, forced

OFF

Low (Fault

Asserted)

>UVLO >OVP

X

<TSD

OFF

Fault

Conditions

SBU over

voltage

condition

X, forced

OFF

Low (Fault

Asserted)

>UVLO

X

>OVP

IEC ESD

generated

over voltage

condition⁽¹⁾

R_DON if

RPD_Gx is

shorted to

C_CCx

Low (Fault

Asserted)

X

<TSD

OFF

(1) This row describes the state of the device while still in OVP after the IEC ESD strike which put the device into OVP is over, and the

voltages on the C_CCx and C_SBUx pins have returned to their normal voltage levels.

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9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPD6S300A provides 4-channels of Short-to-V_BUSovervoltage protection for the CC1, CC2, SBU1, and

SBU2 pins of the USB Type-C connector, and 6-channels of IEC ESD protection for the CC1, CC2, SBU1,

SBU2, DP, and DM pins of the USB Type-C connector. Care must be taken to insure that the TPD6S300A

provides adequate system protection as well as insuring that proper system operation is maintained. The

following application example explains how to properly design the TPD6S300A into a USB Type-C system.

9.2 Typical Application

DC/DC

Battery

EC

VCONN VBUS_SRC

Battery

Charger

USB_DP

Controller

USB_DP

Controller

VBUS_SINK

DM

DP

AUX_N AUX_P

PP_CABLE

PP_5V

I2C

HV_GATE1

HV_GATE2

TPS65982

VBUS

DM_B DP_B

DM_T DP_T C_SBU2

C_SBU1 C_CC2

C_CC1

LDO_3V3

C_CC2

C_CC1

N.C.

C_VPWR

CC1

SBU1

CC2

SBU2

D1

VPWR

R_/FLT

D2

/FLT

To EC or 82

C_VBIAS

TPD6S300A

VBIAS

N.C.

RPD_G2

RPD_G1

C_CC1

N.C.

C_SBU2 C_SBU1

C_CC2

V_BUS

DM_B DP_B DM_T DP_T SBU2 SBU1 CC2

CC1

图 30. TPD6S300A Typical Application Diagram

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ZHCSIE6 –JUNE 2018

www.ti.com.cn

Typical Application (接下页)

图 31. TPD6S300A Reference Schematic

9.2.1 Design Requirements

In this application example we study the protection requirements for a full-featured USB Type-C DRP Port, fully

equipped with USB-PD, USB2.0, USB3.0, Display Port, and 100 W charging. The TPS65982 is used to easily

enable a full-featured port with a single chip solution. In this application, all the pins of the USB Type-C connector

are utilized. Both the CC and SBU pins are susceptible to shorting to the V_BUSpin. With 100 W charging, V_BUS

operates at 20 V, requiring the CC and SBU pins to tolerate 20-V_DC. Additionally, the CC, SBU, and USB2.0 pins

require IEC system level ESD protection. With these protection requirements present for the USB Type-C

connector, the TPD6S300A is utilized. The TPD6S300A is a single chip solution that provides all the required

protection for the low speed and USB2.0 pins in the USB Type-C connector.

表 2 lists the TPD6S300A design parameters.

表 2. Design Parameters

DESIGN PARAMETER

V_BUSnominal operating voltage

EXAMPLE VALUE

20 V

24 V

Short-to-V_BUStolerance for the CC and SBU pins

22

TPD6S300A

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ZHCSIE6 –JUNE 2018

表 2. Design Parameters (接下页)

DESIGN PARAMETER

EXAMPLE VALUE

0.1 µF

VBIAS nominal capacitance

Dead battery charging

100 W

Maximum ambient temperature requirement

85°C

9.2.2 Detailed Design Procedure

9.2.2.1 VBIAS Capacitor Selection

As noted in the Recommended Operating Conditions table, a minimum of 35-V_BUSrated capacitor is required for

the VBIAS pin, and a 50-V_BUScapacitor is recommended. The VBIAS capacitor is in parallel with the central IEC

diode clamp integrated inside the TPD6S300A. A forward biased hiding diode connects the VBIAS pin to the

C_CCx and C_SBUx pins. Therefore, when a Short-to-V_BUSevent occurs at 20 V, 20-V_BUSminus a forward

biased diode drop is exposed to the VBIAS pin. Additionally, during the short-to-V_BUSevent, ringing can occur

almost double the settling voltage of 20 V, allowing a potential 40 V to be exposed to the C_CCx and C_SBUx

pins. However, the internal IEC clamps limit the voltage exposed to the C_CCx and C_SBUx pins to around 30

V. Therefore, at least 35-V_BUScapacitor is required to insure the VBIAS capacitor does not get destroyed during

Short-to-V_BUSevents.

A 50-V, X7R capacitor is recommended, however. This is to further improve the derating performance of the

capacitors. When the voltage across a real capacitor is increased, its capacitance value derates. The more the

capacitor derates, the greater than 2x ringing can occur in the short-to-V_BUSRLC circuit. 50-V X7R capacitors

have great derating performance, allowing for the best short-to-V_BUSperformance of the TPD6S300A.

Additionally, the VBIAS capacitor helps pass IEC 61000-4-2 ESD strikes. The more capacitance present, the

better the IEC performance. So the less the VBIAS capacitor derates, the better the IEC performance. 表 3

shows real capacitors recommended to achieve the best performance with the TPD6S300A.

表 3. Design Parameters

CAPACITOR SIZE

PART NUMBER

0402

0603

CC0402KRX7R9BB104

GRM188R71H104KA93D

9.2.2.2 Dead Battery Operation

For this application, we want to support 100-W dead battery operation; when the laptop is out of battery, we still

want to charge the laptop at 20 V and 5 A. This means that the USB PD Controller must receive power in dead

battery mode. The TPS65982 has its own built in LDO in order to supply the TPS65982 power from V_BUSin a

dead battery condition. The TPS65982 can also provide power to its flash during this condition through its

LDO_3V3 pin.

The OVP FETs of the TPD6S300A remain OFF when it is unpowered in order to insure in a dead battery

situation proper protection is still provided to the PD controller in the system, in this case the TPS65982.

However, when the OVP FETs are OFF, this isolates the TPS65982s dead battery resistors from the USB Type-

C ports CC pins. A USB Type-C power adaptor must see the RD pull-down dead battery resistors on the CC pins

or it does not provide power on V_BUS. Since the TPS65982s dead battery resistors are isolated from the USB

Type-C connector's CC pins, the built-in, dead battery resistors of the TPD6S300A must be connected. Short the

RPD_G1 pin to the C_CC1 pin, and short the RPD_G2 pin to the C_CC2 pin.

Once the power adaptor sees the dead battery resistors of the TPD6S300A, it applies 5 V on the V_BUSpin. This

provides power to the TPS65982, turning the PD controller on, and allowing the battery to begin to charge.

However, this application requires 100 W charging in dead battery mode, so V_BUSat 20 V and 5 A is required.

USB PD negotiation is required to accomplish this, so the TPS65982 needs to be able to communicate on the

CC pins. This means the TPD6S300A needs to be turned on in dead battery mode as well so the TPS65982s

PD controller can be exposed to the CC lines. To accomplish this, it is critical that the TPD6S300A is powered by

the TPS65982s internal LDO, the LDO_3V3 pin. This way, when the TPS65982 receives power on V_BUS, the

TPD6S300A is turned on simultaneously.

23

TPD6S300A

ZHCSIE6 –JUNE 2018

www.ti.com.cn

It is critical that the TPS65982's dead battery resistors are also connected to its CC pins for dead battery

operation. Short the TPS65982s RPD_G1 pin to its C_CC1 pin, and its RPD_G2 pin to its C_CC2 pin. It is critical

that the TPS65982s dead battery resistors are present; once the TPD6S300A receives power, turns on its OVP

FETs and then removes its dead battery RD resistor, TPS65982's RD pull-down resistors must be present on the

CC line in order to guarantee the power adaptor stays connected. If RD is not present the power adaptor will

eventually interpret this as a disconnect and remove V_BUS

.

Also, it is important that the TPS65982's dead battery resistors are present so it properly boots up in dead

battery operation with the correct voltages on its CC pins.

Once this process has occurred, the TPS65982 can start negotiating with the power adaptor through USB PD for

higher power levels, allowing 100-W operation in dead battery mode.

For more information on the TPD6S300A dead battery operation, see the CC Dead Battery Resistors Integrated

for Handling the Dead Battery Use Case in Mobile Devices section of the datasheet.

9.2.2.3 CC Line Capacitance

USB PD has a specification for the total amount of capacitance that is required for proper USB PD BMC

operation on the CC lines. The specification from section 5.8.6 of the USB PD Specification is given below in 表

4.

表 4. USB PD cReceiver Specification

NAME

DESCRIPTION

MIN

MAX

UNIT

COMMENT

The DFP or UFP system shall have

capacitance within this range when

not transmitting on the line

cReceiver

CC receiver capacitance

200

600

pF

Therefore, the capacitance on the CC lines must stay in between 200 pF and 600 pF when USB PD is being

used. Therefore, the combination of capacitances added to the system by the TPS65982, the TPD6S300A, and

any external capacitor must fall within these limits. 表 5 shows the analysis involved in choosing the correct

external CC capacitor for this system, and shows that an external CC capacitor is required.

表 5. CC Line Capacitor Calculation

CC Capacitance

MIN

200

70

MAX UNIT COMMENT

CC line target capacitance

TPS65982 capacitance

TPD6S300A capacitance

600

120

pF

From the USB PD Specification section

From the TPS65982 Datasheet

60

From the Electrical Characteristics table.

CAP, CERM, 220 pF, 25 V, ±10%, X7R,

0201 (For min and max, assume ±50%

capacitance change with temperature and

voltage derating to be overly conservative)

Proposed capacitor GRM033R71E221KA01D

110

240

330

570

pF

TPS65982 + TPD6S300A + GRM033R71E221KA01D

Meets USB PD cReceiver specification

9.2.2.4 Additional ESD Protection on CC and SBU Lines

If additional IEC ESD protection is desired to be placed on either the CC or SBU lines, it is important that high-

voltage ESD protection diodes be used. The maximum DC voltage that can be seen in USB PD is 21-V_BUS, with

21.5 V allowed during voltage transitions. Therefore, an ESD protection diode must have a reverse stand off

voltage higher than 21.5 V in order to guarantee the diode does not breakdown during a short-to-V_BUSevent and

have large amounts of current flowing through it indefinitely, destroying the diode. A reverse stand off voltage of

24 V is recommended to give margin above 21.5 V in case USB Type-C power adaptors are released in the

market which break the USB Type-C specification.

Furthermore, due to the fact that the Short-to-V_BUSevent applies a DC voltage to the CC and SBU pins, a deep-

snap-back diode cannot be used unless its minimum trigger voltage is above 42 V. During a Short-to-V_BUSevent,

RLC ringing of up to 2x the settling voltage can be exposed to CC and SBU, allowing for up to 42 V to be

exposed. Furthermore, if any capacitor derates on the CC or SBU line, greater than 2x ringing can occur. Since

this ringing is hard to bound, it is recommended to not use deep-snap-back diodes. If the deep-snap-back diode

triggers during the short-to-V_BUShot-plug event, it begins to operate in its conduction region. With a 20-V_BUS

source present on the CC or SBU line, this allows the diode to conduct indefinitely, destroying the diode.

24

TPD6S300A

www.ti.com.cn

ZHCSIE6 –JUNE 2018

9.2.2.5 FLT Pin Operation

Once a Short-to-V_BUSoccurs on the C_CCx or C_SBUx pins, the FLT pin is asserted in 20 µs (typical) so the PD

controller can be notified quickly. If V_BUSis being shorted to CC or SBU, it is recommended to respond to the

event by forcing a detach in the USB PD controller to remove V_BUSfrom the port. Although the USB Type-C port

using the TPD6S300A is not damaged, as the TPD6S300A provides protection from these events, the other

device connected through the USB Type-C Cable or any active circuitry in the cable can be damaged. Although

shutting the V_BUSoff through a detach does not guarantee it stops the other device or cable from being

damaged, it can mitigate any high current paths from causing further damage after the initial damage takes

place. Additionally, even if the active cable or other device does have proper protection, the short-to-V_BUSevent

may corrupt a configuration in an active cable or in the other PD controller, so it is best to detach and reconfigure

the port.

9.2.2.6 How to Connect Unused Pins

If either the RPD_Gx pins or any of the Dx pins are unused in a design, they must be connected to GND.

9.2.3 Application Curves

图 32. TPD6S300A Turning On in Dead Battery

图 33. TPD6S300A Protecting the TPS65982 During

Mode with R_Don CC1

a Short-to-V_BUSEvent

25

TPD6S300A

ZHCSIE6 –JUNE 2018

www.ti.com.cn

10 Power Supply Recommendations

The V_PWRpin provides power to all the circuitry in the TPD6S300A. It is recommended a 1-µF decoupling

capacitor is placed as close as possible to the VPWR pin. If USB PD is desired to be operated in dead battery

conditions, it is critical that the TPD6S300A share the same power supply as the PD controller in dead battery

boot-up (such as sharing the same dead battery LDO). See the CC Dead Battery Resistors Integrated for

Handling the Dead Battery Use Case in Mobile Devices section for more details.

26

TPD6S300A

www.ti.com.cn

ZHCSIE6 –JUNE 2018

11 Layout

11.1 Layout Guidelines

Proper routing and placement is important to maintain the signal integrity the USB2.0, SBU, CC line signals. The

following guidelines apply to the TPD6S300A:

•

Place the bypass capacitors as close as possible to the V_PWRpin, and ESD protection capacitor as close as

possible to the V_BIASpin. Capacitors must be attached to a solid ground. This minimizes voltage disturbances

during transient events such as short-to-V_BUSand ESD strikes.

•

The USB2.0 and SBU lines must be routed as straight as possible and any sharp bends must be minimized.

Standard ESD recommendations apply to the C_CC1, C_CC2, C_SBU1, C_SBU2, D1, and D2 pins as well:

•

The optimum placement for the device is as close to the connector as possible:

–

EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,

resulting in early system failures.

–

The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away

from the protected traces which are between the TPD6S300A and the connector.

•

Route the protected traces as straight as possible.

Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded

corners with the largest radii possible.

–

Electric fields tend to build up on corners, increasing EMI coupling.

•

It is best practice to not via up to the D1 and D2 pins from a trace routed on another layer. Rather, it is better

to via the trace to the layer with the Dx pin, and to continue that trace on that same layer. See the ESD

Protection Layout Guide application report, section 1.3 for more details.

11.2 Layout Example

GND

TX1+

RX1+

RX1-

VBUS

SBU2

D-

TX1-

VBUS

CC1

D+

RPD_G1

RPD_G2

GND

D1

D2

D+

D-

CC2

GND

N.C

N.C.

SBU1

VBUS

RX2-

/FLT

VBUS

TX2-

VPWR

TX2+

GND

RX2+

GND

图 34. TPD6S300A Typical Layout

27

TPD6S300A

ZHCSIE6 –JUNE 2018

www.ti.com.cn

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

请参阅如下相关文档：

《TPD6S300 评估模块用户指南》

12.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.4 商标

E2E is a trademark of Texas Instruments.

USB Type-C is a trademark of USB Implementers Forum.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.6 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

28

PACKAGE OUTLINE

RUK0020B

WQFN - 0.8 mm max height

S

C

A

L

E

4

.

0

PLASTIC QUAD FLATPACK - NO LEAD

3.1

2.9

B

A

0.5

0.3

PIN 1 INDEX AREA

3.1

2.9

0.25

0.15

DETAIL

OPTIONAL TERMINAL

TYPICAL

DIMENSION A

OPTION 01

OPTION 02

(0.1)

(0.2)

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

(DIM A) TYP

OPT 02 SHOWN

1.7 0.05

6

10

EXPOSED

THERMAL PAD

16X 0.4

5

11

21

SYMM

4X

1.6

1

15

SEE TERMINAL

DETAIL

0.25

20X

0.15

0.1

C A

B

20

16

PIN 1 ID

SYMM

0.05

(OPTIONAL)

0.5

0.3

20X

4222676/A 02/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RUK0020B

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.7)

SYMM

20

16

20X (0.6)

1

15

20X (0.2)

(0.6)

TYP

21

SYMM

(2.8)

16X (0.4)

5

11

(R0.05)

TYP

(

0.2) TYP

VIA

6

10

(2.8)

LAND PATTERN EXAMPLE

SCALE:20X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222676/A 02/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RUK0020B

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

(0.47) TYP

16

(R0.05) TYP

20

20X (0.6)

1

15

21

20X (0.2)

(0.47)

TYP

SYMM

(2.8)

16X (0.4)

11

5

METAL

TYP

6

10

4X ( 0.75)

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 21:

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4222676/A 02/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

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型号：	TPD6S300A
厂家：	TEXAS INSTRUMENTS
描述：	USB Type-C™ 端口保护器：VBUS 短路过压和 6 通道 ESD 保护，带改进的过压保护
文件：	总33页 (文件大小：1400K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPD6S300A [TI]

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