TPD7000AF [TOSHIBA]

IC 0.02 A 4 CHANNEL, BUF OR INV BASED MOSFET DRIVER, PDSO24, SSOP-24, MOSFET Driver;
TPD7000AF
型号: TPD7000AF
厂家: TOSHIBA    TOSHIBA
描述:

IC 0.02 A 4 CHANNEL, BUF OR INV BASED MOSFET DRIVER, PDSO24, SSOP-24, MOSFET Driver

驱动 光电二极管 接口集成电路 驱动器
文件: 总2页 (文件大小:73K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
TP D7 0 0 0 AF  
4-channel Low-Side N-ch Power-MOSFET Driver for ABS Applications  
The IC incorporates a circuit which monitors the voltage between the power MOSFET drain and source.  
It supports an intelligent function for power MOSFET protection and diagnosis.  
(T = 25°C)  
Maximum Rating  
a
Features  
Characteristic  
Symbol  
Rating  
Unit  
Low-side N-channel power MOSFET driver  
(input capacitance: 15 nF max)  
Incorporates a power MOSFET overcurrent  
protection function.  
Incorporates induction load energy clamping  
function.  
INHIBIT option using enable input, open collector  
output.  
SSOP 24-pin package for packing in embossed-  
tape  
DC  
V
V
V
V
V
25  
DH (1)  
DH (2)  
DL  
Supply Voltage  
V
(
)
Pulse  
30 1 s  
Supply Voltage  
Output Voltage  
Input Voltage  
10  
10  
V
V
OPOUT  
IN  
0.5 to 7  
20  
V
Output Current  
Power Dissipation  
I
mA  
W
°C  
°C  
°C  
OPOUT  
T
= 25°C  
P
0.5  
a
D
Operating Temperature  
Junction Temperature  
Storage Temperature  
T
T
T
40 to 110  
150  
opr  
j
55 to 150  
stg  
SSOP-24PIN  
(T = 40 to 110°C, V  
j
= 13 V, V  
= 5 ± 0.5 V)  
Electrical Characteristics  
DH  
DL  
Characteristic  
Symbol  
Terminal  
Test Condition  
Min  
Typ.  
Max  
Unit  
V
V
V
V
8
4.5  
13  
18  
5.5  
5
DH  
DL  
DH  
DL  
V
Operating Voltage  
5
2
I
I
I
I
V
V
= 0 V, V  
= 0 V, V  
= 13 V, Output Off  
= 5 V, Output Off  
DH  
DL  
DH  
DL  
IN  
IN  
DH  
DL  
Current Dissipation  
mA  
V
8
12  
1.5  
V
V
IN / ENB  
/ OPIN  
When Output Off  
When Output On  
100  
IL  
IH  
IL  
Input Voltage  
Input Current  
3.5  
I
I
IN / ENB  
/ OPIN  
V
V
= 0 V  
= 5 V  
1
IN  
IN  
µA  
V
200  
IH  
High-Level  
Output Voltage 1  
V
V
V
V
V
= 5 V, I = 0 A, V  
< 14 V  
V
OH 1  
OH 2  
GS  
GS  
IN  
O
DH  
DH  
DH  
High-Level  
Output Voltage 2  
V
V
= 5 V, I = 0 A, V  
O
14 V  
12  
15  
V
IN  
V
V
V
V
1.0  
10  
0.5  
V
V
Low-Level Output Voltage  
= 0 V, I = 0 A  
O
OL  
DS  
GS  
DS  
IN  
V
Detection Voltage  
DS  
Diagnostic Resistance  
kΩ  
R
DIAG  
DIAG  
Diagnostic Output  
Voltage  
V
LLevel  
HLevel  
DIAG  
V
= 5 V  
= 5 V  
0.4  
10  
V
DIAG  
DIAG  
DL  
Diagnostic Output  
Current  
I
DIAG  
V
I
µA  
DIAG  
V
I
Optional Output Voltage  
Optional Off Current  
OPOUT  
OPOUT  
= 10 mA  
30  
35  
0.4  
10  
V
µA  
V
OPL  
OP  
V
I
= 5 V  
OPH  
OPOUT  
V
V
Zener Voltage between Drain and Gates  
= 5 mA, V  
= V V  
40  
CLAMP  
DS  
DS  
CLAMP  
DS GS  
t
t
C
= 3000 pF  
100  
100  
PLH  
When On  
L
µs  
Switching Time  
V
GS  
(
)
capacitance between V  
and GND pins  
GS  
PLH  
When Off  
32  
Operation  
(1)  
When normal  
(2) At Overcurrent  
If the V pin voltage (the voltage between the  
DS  
power MOS drain and source) is around 1.0 V or  
above (V typical detection voltage) while high  
At external power MOS on  
When 3.5 V or more is applied to the IN and ENB  
DS  
pins, the V  
pin goes high and 1 mA (Typ.)  
GS  
level input voltage is applied to the IN and ENB  
pins, overcurrent to the external power MOS is  
constant current drives the power MOS gate.  
A V mask circuit is built in to prevent erroneous  
GS  
detected and the V  
output is a instantly shut  
GS  
detection of overcurrent in the transient area  
before the power MOS comes sufficiency on from  
off state. This circuit is set so that overcurrent is  
down and latched. Setting the input voltage back  
to low level releases the latch.  
When the voltage reaches the V  
voltage or above, DIAG outputs low level.  
detection  
DS  
not erroneously detected before the V  
6.5 V (Typ.).  
rises to  
GS  
DIAG output a voltage that is the inverse of the  
state. The power MOS and its load state can  
be checked by monitoring the input voltage and the  
DIAG output.  
(3) At load open  
V
As a pull-down resistor is connected to the V  
pin, when the load is open the V  
low and high level is output to DIAG.  
DS  
DS  
pin is always  
DS  
(4)  
External power MOS off  
OPTION function  
When the input voltage of IN or ENB falls to 1.5 V  
The OPTION function is controlled by two input  
pins: OPIN and ENB. ENB has priority over  
OPIN. When high level voltage is input to OPIN or  
ENB, the OPOUT pin goes low. This function can  
be used as a pre-diver for lamps and mechanical  
relays.  
or below, the V  
pin goes low, the external  
GS  
power MOS gate is discharged, and the MOSFET  
turns off.  
The ENB pin has priority over the IN pin. When  
ENB is low, the V  
GS  
pin does not go on even if a  
high level input voltage is applied to IN.  
(5) At VDL low voltage  
TPD7000AF incorporates a low-voltage lock circuit  
for locking the V  
and DIAG outputs when V  
GS  
DL  
falls. This circuit is designed to operate around  
= 2.8 V (Typ.) or lower. When the circuit is in  
V
DL  
operation, ENB is locked at low level to cut off the  
output.  
V
GS  
Truth table  
State  
OPIN  
ENB  
OUTPUT  
IN  
ENB  
H
L
V
DIAG  
DS  
L
H
L
H
L
L
H
L
L
H
L
H
H
L
HZ  
L
Normal  
HZ  
HZ  
H
H
H
H
H
H
H
H
H
H
L
H
L
H
L
L
L
H
L
H
L
L
Overcurrent  
L
H
L
L
L
H
L
H
L
L
Load Short Circuit  
Power MOS Short Circuit  
Load Open  
L
H
L
L
H
H
H
H
H
H
H
H
H
L
H
L
L
L
H
L
L
L
H
L
H
L
L
*OPOUT is an NPN open collector.  
*HZ: High impedance  
*ENB is active high.  
L
H
L
*DIAG monitors V  
regardless of IN or ENB.  
DS  
33  

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