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TPIC2040

ZHCSEG2 –DECEMBER 2015

TPIC2040 用于 ODD 驱动、由串行接口控制的 7 通道电机驱动器

1 特性

–

CSW 输出具有可选 OCP 阈值电平

硬件器件禁用引脚 XMUTE

1

•

串行外设接口 (SPI)

具有欠压闭锁 (UVLO) 和过压保护 (OVP) 的电

源监视器

–

最大读写频率 35MHz

3.3V 数字输入输出 (I/O)

•

执行器和电机驱动器

2 应用

–

具有 H 桥输出的脉冲宽度调制 (PWM) 控制

•

DVD 播放器

具有 12 位数模转换器 (DAC) 控制的聚焦/跟踪/

倾斜执行器驱动器

CD 播放器

光盘驱动器

–

具有电流模式、10 位 DAC 控制的滑动电机驱

动器

3 说明

–

具有 12 位 DAC 控制的负载驱动器

TPIC2040 是一款适用于薄型或超薄 DVD 读/写器的超

低噪声电机驱动器集成电路 (IC)。该 IC 集成有电流感

测电阻，能够测量 SPM 电流并降低驱动系统成本。该

驱动器 IC 有 7 条通道且由串行接口控制，非常适用于

驱动主轴电机、滑动电机、负载电机和聚焦/跟踪/倾斜

执行器。主轴电机驱动器利用 BEMF 检测（无需传感

器）来启动并控制主轴电机

无需位置传感器即可检测滑动结束位置

•

主轴电机驱动器

–

集成主轴电流感测电阻

可通过设置寄存器来选择 0.20Ω 至 0.27Ω 的电

流感测电阻值，从而将 SPM 电流限制在

725mA 至 980mA

–

无传感器：通过电机反电动势 (BEMF) 感测转

子位置

器件信息⁽¹⁾

–

通过串行端口编程 12 位主轴 DAC

器件型号

封装

封装尺寸（标称值）

独立的感应位置感测和启动

TPIC2040DBT

TSSOP (38)

9.70mm x 4.40mm

通过名为自动短制动的自动控制制动实现急停

（短制动和主动制动）

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

–

最大持续电流为 0.7A，不存在散热问题

低速 (LS) 模式：限制在正常速度的 25%

简化框图

MCOM

TPIC2040

U

V

5 V

SPM

5 V

•

实用功能

–

XRESET 信号，具有 20ms 数字延时（上电复

Driver

3.3 V

W

位 (POR)）

SLED1+

5 V

SPI

–

状态锁存器：执行器定时器、SIF 错误、电源监

视器、热保护和过流保护 (OCP) 故障

SLED1-

SLED2+

SLED1

5 V

SLED2-

SLED2

•

开关

1PX V

output

TLT+

TLT-

–

CSW：软件控制电流输出端口

5 V

TLT

低压降 (LDO) 前置驱动器

FCS+

FCS-

LIN9VG

LINFB

5 V

LDO

Control

9Vout

–

具有外部晶体管的 3.3V 或 1.2V 电压输出的单

通道 LDO 前置驱动器

FCS

TRK+

TRK-

5 V

TRK

•

保护

LOAD+

LOAD-

5 V

LOAD

–

CSW、SPM 和执行器通道上均配有独立热保护

电路

–

两个警报级别：热保护中的预检测和检测

负载驱动器中配有过流保护电路

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLIS172

TPIC2040

ZHCSEG2 –DECEMBER 2015

www.ti.com.cn

7.15 Serial Port I/F Write Timing Requirements ........... 10

7.16 Serial I/F Read Timing Requirements................... 10

7.17 Typical Characteristics.......................................... 11

Detailed Description ............................................ 12

8.1 Overview ................................................................. 12

8.2 Functional Block Diagram ....................................... 13

8.3 Feature Description................................................. 14

8.4 Device Functional Modes........................................ 19

8.5 Programming .......................................................... 21

8.6 Register Maps......................................................... 23

Application and Implementation ........................ 39

9.1 Application Information............................................ 39

9.2 Typical Application ................................................. 48

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）............................................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics – Common Part ................ 7

7.6 Electrical Characteristics – Charge Pump ................ 7

7.7 Electrical Characteristics – LDO Pre Driver Part ...... 8

8

9

10 Power Supply Recommendations ..................... 50

11 Layout................................................................... 50

11.1 Layout Guidelines ................................................. 50

11.2 Layout Example .................................................... 50

12 器件和文档支持 ..................................................... 51

12.1 器件支持 ............................................................... 51

12.2 社区资源................................................................ 51

12.3 商标....................................................................... 51

12.4 静电放电警告......................................................... 51

12.5 Glossary................................................................ 51

13 机械、封装和可订购信息....................................... 51

7.8 Electrical Characteristics – Spindle Motor Driver

Part............................................................................. 8

7.9 Electrical Characteristics – Sled Motor Driver Part... 8

7.10 Electrical Characteristics – Focus/

Tilt/Tracking/Driver Part ............................................. 9

7.11 Electrical Characteristics – Load Driver Part .......... 9

7.12 Electrical Characteristics – Current Switch Part ..... 9

7.13 Electrical Characteristics – Actuator Protection...... 9

7.14 Electrical Characteristics – Serial Port Voltage

Levels ...................................................................... 10

4 修订历史记录

日期

修订版本

注释

2015 年 12 月

*

最初发布。

2

TPIC2040

www.ti.com.cn

ZHCSEG2 –DECEMBER 2015

5 说明（续）

由于所有通道的输出级均在高效的 PWM 驱动下工作，因此可通过 PWM 控制实现低功率运行。可以对聚焦/跟踪/

倾斜执行器驱动器进行无死区控制。此外，该器件还内置有主轴部件输出电流限制电路、热关断电路、滑动结束位

置检测电路、执行器保护和电源复位电路。

6 Pin Configuration and Functions

DBT Package

38-Pin TSSOP

Top View

1

2

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

LOAD+

LOAD-

SLED2-

SLED2+

SLED1-

3

PGND_1

SIOV

4

SLED1+

CSWO

SSZ

5

SCLK

SIMO

SOMI

XMUTE

XFG

6

P5V_1

7

P5V_SPM

8

W

9

U

V

10

11

12

13

14

XRESET

CP1

PGND_SPM

MCOM

PGND_2

CP2

CP3

TRK-

TRK+

FCS-

FCS+

TLT-

15 LIN3VG

16

17

18

19

LINFB/GPOUT

AGND/DGND

CV3P3

TLT+

P5V_2/A5V

Pin Functions

I/O

DESCRIPTION

NO.

1

NAME

LOAD+

LOAD–

PGND_1

SIOV

O

PS

I

Load positive output terminal

Load negative output terminal

GND terminal

2

3

4

Power supply terminal for serial port typical 3.3 V

SIO slave select low active input terminal

SIO serial clock input terminal

5

SSZ

6

SCLK

SIMO

I

7

I

SIO slave input master output terminal

SIO slave output master input terminal

8

SOMI

O

3

TPIC2040

ZHCSEG2 –DECEMBER 2015

www.ti.com.cn

Pin Functions (continued)

I/O

DESCRIPTION

NO.

9

NAME

XMUTE

IN

O

XMUTE input terminal to disable driver output

Motor speed signal output

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

XFG

XRESET

CP1

O

Power-on reset output. Internally pulled up to SIOV

Capacitance connection for charge pump

3.3-V predriver output control signal for external N-channel FET

Voltage feedback of 3.3-V predriver (be controlled to LINFB = 1.215 V)

Ground terminal for internal logic

MISC

O

CP2

CP3

LIN3VG

LINFB/GPOUT

AGND/DGND

CV3P3

P5V_2/A5V

TLT+

I/O

PS

MISC

PS

O

Capacitance terminal for internal 3.3-V regulator

Power supply terminal

Tilt positive output terminal

TLT–

O

Tilt negative output terminal

FCS+

O

Focus positive output terminal

FCS–

O

Focus negative output terminal

TRK+

O

Tracking positive output terminal

TRK-–

O

Tracking negative output terminal

GND terminal

PGND_2

MCOM

PGND_SPM

V

PS

IN

Motor center tap connection

PS

O

GND terminal for spindle driver

V phase output terminal for spindle motor

U phase output terminal for spindle motor

W phase output terminal for spindle motor

Power supply terminal for spindle driver

Power supply terminal

U

O

W

O

P5V_SPM

P5V_1

CSWO

SLED1+

SLED1–

SLED2+

SLED2–

PS

O

Power switch output for 5-V OEIC in OPU

Sled1 positive output terminal

O

Sled1 negative output terminal

O

Sled2 positive output terminal

O

Sled2 negative output terminal

4

TPIC2040

www.ti.com.cn

ZHCSEG2 –DECEMBER 2015

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

V

+ 5 V supply voltage P5V, P5V_SPM

Spindle output peak voltage

Input/output voltage

6

7

V_CC+ 0.3 V

1.0

V

–0.3

V

Spindle output current

A

Spindle output peak current (PW ≦ 2 ms, Duty ≦ 30%)

Sled output peak current

2.5

A

0.8

A

Focus/tilt/tracking driver output peak current

Load driver output peak current

Power dissipation

1.5

A

0.8

A

See Thermal Information

Operating temperature

–20

–50

75

°C

T_stg

Storage temperature

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5

TPIC2040

ZHCSEG2 –DECEMBER 2015

www.ti.com.cn

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

NOM

5.0

MAX

5.5

UNIT

V

P5V

Operating supply voltage (apply for P5V)

SIOV voltage

V_SIOV

V_SIFH

V_SIFL

I_SPMOA

I_SPMO

I_SLDOA

I_ACTOA

I_CSWOA

F_ck

3.0

3.3

3.6

V

XMUTE, SIMO, SSZ, SCLK pin H level input voltage range

XMUTE, SIMO, SSZ, SCLK pin L level input voltage range

Spindle output average current (U, V, W total)

Spindle output current

2.2

SIOV + 0.2

0.8

V

–0.2

V

700

mA

MHz

°C

700

Sled output average current

400

Focus / tracking / tilt / loading output average current

CSWO output average current

400

500

SCLK frequency

30

33.8688

25

35

T_O

Operating temperature

–20

75

7.4 Thermal Information

TPIC2040

THERMAL METRIC⁽¹⁾

DBT (TSSOP)

38 PINS

81.2

UNIT

R_θJA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

27.2

42.3

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.7

ψ_JB

41.7

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) The JEDEC specification low K (1 s) board design used to derive this data.

6

TPIC2040

www.ti.com.cn

ZHCSEG2 –DECEMBER 2015

7.5 Electrical Characteristics – Common Part

over recommended operating free-air temperature range (P5V ≈ 4.5 to 5.5 V, T_A≈ –20℃ to 75℃, unless otherwise noted)

PARAMETER

TEST CONDITIONS

LIN3P3_DIS = 1, XSLEEP = L

Iload = 25 mA

MIN

TYP

MAX UNIT

ISTBY

VCV3

Stand by supply current

CV3P3 output voltage

XMUTE pulldown resistor

XRESET pullup resistor

XRESET low level output voltage

Power-on reset delay

XFG output resistor

1.0

3.63

320

52.8

0.3

mA

V

2.97

80

3.3

200

33

RXM

kΩ

V

RXRST

VXRSTL

TPOR

RXFG

13.2

SIOV = 3.3 V, I_OL= –100 µA

15

20

25

ms

Ω

100

200

300

SIOV = 3.3 V, XSLEEP = 1,

I_OH= 100 µA

VXFGH

XFG high-level output voltage

SIOV – 0.3

V

SIOV = 3.3 V, XSLEEP = 1,

I_OL= –100 µA

VXFGL

RGPO

XFG low-level output voltage

GPOUT output resistor

0.3

V

100

200

300

Ω

SIOV = 3.3 V, XSLEEP = 1,

GPOUT_ENA = 1,GPOUT_HL = 1,

I_OH= 100 µA

VGPOH

VGPOL

GPOUT high-level output voltage

SIOV – 0.3

V

SIOV = 3.3 V, XSLEEP = 1,

GPOUT_ENA = 1, GPOUT_HL = 0,

I_OH= 100 µA

GPOUT low-level output voltage

Thermal protect on temperature

0.3

tTSD

Design specified value

135

5

150

15

165

25

ºC

Thermal protect hysteresis

temperature

hytTSD

Vonvcc

Voffvcc

Vhysvcc

VonCV3

VoffCV3

VonSIO

VoffSIO

VhysSIO

P5V reset on voltage

3.3

3.5

100

2.4

2.5

2.4

2.5

20

3.5

3.7

200

2.5

2.6

2.5

2.6

100

6.2

6.0

200

3.7

3.9

300

2.6

2.7

2.6

2.7

140

6.4

6.2

300

V

P5V reset off voltage

P5V reset voltage hysteresis

CV3P3 reset on voltage

CV3P3 reset off voltage

SIOV reset on voltage

SIOV reset off voltage

SIOV reset voltage hysteresis

mV

V

mV

V

(1)

VovpspmOn OVP detection voltage (spindle)

5.9

5.7

50

(1)

VovpspmOff

OVP release voltage (spindle)

V

(1)

VovpSpmHys OVP voltage hysteresis (spindle)

mV

OVP detection voltage

VovpOn

6.2

6.0

50

6.5

6.3

6.7

6.5

V

(except spindle)⁽¹⁾

OVP release voltage

VovpOff

(except spindle)⁽¹⁾

OVP voltage hysteresis

VovpHys

200

300

mV

(except spindle)⁽¹⁾

VonLinF

VoffLinF

VhysLINF

LINFB reset on voltage

0.83

0.88

20

0.93

0.98

50

1.03

1.08

80

V

LINFB reset off voltage

LINFB reset voltage hysteresis

mV

(1) Those are value as protection functions only, and stress beyond those listed under Recommended Operating Conditions may cause

permanent damage to the device.

7.6 Electrical Characteristics – Charge Pump

over recommended operating free-air temperature range (P5V ≈ 4.5 to 5.5 V, T_A≈ –20℃ to 75℃, unless otherwise noted)

PARAMETER

Frequency

TEST CONDITIONS

XSLEEP = 1

MIN

TYP

MAX

UNIT

FCHGP

132.6

156

179.4

kHz

7

TPIC2040

ZHCSEG2 –DECEMBER 2015

www.ti.com.cn

Electrical Characteristics – Charge Pump (continued)

over recommended operating free-air temperature range (P5V ≈ 4.5 to 5.5 V, T_A≈ –20℃ to 75℃, unless otherwise noted)

PARAMETER

TEST CONDITIONS

Ccp1 = Ccp3 = 0.1 µF

I_O= –1 mA

MIN

TYP

MAX

UNIT

VCHGP

Output voltage

7.76

9.7

11.64

V

7.7 Electrical Characteristics – LDO Pre Driver Part

over recommended operating free-air temperature range (P5V ≈ 4.5 to 5.5 V, T_A≈ –20℃ to 75℃, unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LINFB_Vth LINFB threshold voltage

1.175

1.215

1.255

V

7.8 Electrical Characteristics – Spindle Motor Driver Part

over recommended operating free-air temperature range (P5V ≈ 4.5 to 5.5 V, T_A≈ –20℃ to 75℃, unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Total output resistance

High side + low side⁽¹⁾

RttlSPM

I_OUT= 0.5 A

0.37

0.7

Ω

ResSPM

GnSPM

Resolution

Gain

12

6.0

bit

Magnification to 1.0 input

Forward

5.2

12h

6.8

92h

times

52h

–52h

0h

WidDZSPM

Spindle dead band

Reverse

–92h

–40h

801

–12h

40h

WidDZSPMLS

Spindle dead band (LS mode)

SPM_RCOM_SEL = 00

SPM_RCOM_SEL = 01

SPM_RCOM_SEL = 10

SPM_RCOM_SEL = 11

890

980

725

784

979

mA

882

1078

798

SPMClim

Current limit

652

705

863

(1) IncldRcs

7.9 Electrical Characteristics – Sled Motor Driver Part

over recommended operating free-air temperature range (P5V ≈ 4.5 to 5.5 V, T_A≈ –20℃ to 75℃, unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Total output resistance

High side + low side

RttlSLD

ResSLD

I_O= 0.5 A

0.9

1.3

Ω

Resolution

10

1Fh

bit

Forward

Reverse

2h

60h

–2h

WidDZSLD

GnSLD

Input dead band

–60h

–1Fh

P5V = 5 V

R_L= 10 Ω, 2.2 mH

VSLED = 7FFh

Sled current gain

380

440

500

mA

SLEDENDTH<2:0> = 000

SLEDENDTH<2:0> = 010

SLEDENDTH<2:0> = 011

SLEDENDTH<2:0> = 100

SLEDENDTH<2:0> = 101

SLEDENDTH<2:0> = 111

26

42

9

46

82

66

122

35

mV

22

END_DET BEMF threshold

voltage

VthEdetSLD

65

55

70

125

105

145

185

155

220

8

TPIC2040

www.ti.com.cn

ZHCSEG2 –DECEMBER 2015

7.10 Electrical Characteristics – Focus/ Tilt/Tracking/Driver Part

over recommended operating free-air temperature range (P5V ≈ 4.5 to 5.5 V, T_A≈ –20℃ to 75℃, unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_O= 0.5 A

MIN

TYP

MAX

UNIT

Total output resistance

High Side + Low Side

(Focus±, Track±, Tilt±)

RttlAct

0.9

1.3

Ω

ResACT

VOfstACT

VOfstDACT

GnDAct

Resolution

12

0

bit

mV

db

Each channel output offset voltage

Output offset voltage Focus and Tilt

Difference gain Focus and Tilt

Gain

DAC_code = 000h

DIFF_TLT = 1

–20

–50

–1

20

50

1

0

DIFF_TLT = 1

0

GnAct

Magnification to 1.0 input

5.2

6

6.8

times

7.11 Electrical Characteristics – Load Driver Part

over recommended operating free-air temperature range (P5V ≈ 4.5 to 5.5 V, T_A≈ –20℃ to 75℃, unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Total output resistance

High side + low side

(Load±)

RttlLOD

I_O= 0.5 A

0.9

1.3

Ω

ResLOD

GnLOD

Resolution

Gain

12

6

bit

Magnification to 1.0 input

Forward

5.2

6.8

times

1Fh

–20h

0.8

WidDZLOD

TocpLOD

IocpLOD

Dead band

Reverse

Output 100% limit time

Overcurrent protective level

LOAD_05CH = 0

0.64

120

215

0.96

400

645

s

LOAD_05CH = 1 at Load_OCP_IUP = 0

LOAD_05CH = 1 at Load_OCP_IUP = 1

240

430

mA

Overcurrent protection delay

time

DlyocpLOD

LOAD_05CH = 1

0.64

0.8

0.96

s

7.12 Electrical Characteristics – Current Switch Part

over recommended operating free-air temperature range (P5V ≈ 4.5 to 5.5 V, T_A≈ –20℃ to 75℃, unless otherwise noted)

PARAMETER

Rds(on)

TEST CONDITIONS

I_O= 0.2 A

MIN

TYP

200

0.5

MAX

500

UNIT

mΩ

A

RdsCSW

IlmtCSW

ThlCSW

CSW_OCP = 0

CSW_OCP = 1

CSW_OCP = 2

0.25

0.375

0.5

0.75

1.125

1.5

Current limit threshold level

Protection hold time

0.75

1.0

A

1.47

1.6

2.0

ms

7.13 Electrical Characteristics – Actuator Protection

over recommended operating free-air temperature range (P5V ≈ 4.5 to 5.5 V, T_A≈ –20℃ to 75℃, unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TintACTTEMP

Update cycle

21

26

31

ms

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7.14 Electrical Characteristics – Serial Port Voltage Levels

over recommended operating free-air temperature range (P5V ≈ 4.5 to 5.5 V, T_A≈ –20℃ to 75℃, unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

80 %

SIOV

SOMI

SIMO

High-level output voltage, V_OH

I_OH= 1 mA

V

20%

SIOV

Low-level output voltage, V_OL

High-level input voltage, V_IH

Low level input voltage, VIL

I_OL= 1 mA

V

70%

SIOV

20%

SIOV

SIMO

SOMI

SCLK

SIMO

SSZ

Input rise/fall time

Output rise/fall time⁽¹⁾

10% 90% SIOV

3.5

10

ns

Cload = 30 pF, 10% 90% SIOV

Internal pulldown resistance

80

200

320

kΩ

Internal pullup resistance

(1) Specified by design

7.15 Serial Port I/F Write Timing Requirements

(1)

see

MIN

NOM

MAX

UNIT

MHz

ns

F_ck

t_ckl

SCLK clock frequency

SCLK low time

SIOV = 3.3 V

35

11

7

t_ckh

t_sens

t_senh

t_sl

SCLK high time

ns

SSZ setup time

ns

SSZ hold time

7

ns

SSZ disable high time

SIMO setup time (Write)

SIMO hold time (Write)

11

7

ns

t_ds

ns

t_dh

7

ns

(1) Specified by design

7.16 Serial I/F Read Timing Requirements

MIN

NOM

MAX

UNIT

MHz

ns

F_ck

t_ckl

SCLK clock frequency

SCLK low time

SIOV = 3.3 V

35

11

7

t_ckh

t_sens

t_senh

t_sl

SCLK high time

ns

SSZ setup time

ns

SSZ hold time

7

ns

SSZ disable high time

SIMO setup time (Write)

SIMO hold time (Write)

SOMI delay time (Read)

SOMI hold time (Read)

11

7

ns

t_ds

ns

t_dh

7

ns

t_rdly

t_sendl

CLOAD = 10 pF, SIOV = 3.3 V

2

9

ns

2

ns

CLOAD = 10 pF, SIOV = 3.3 V

From SSZ rise to SOMI HIZ

t_rls

SOMI release time (Read)

0

9

ns

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Tsl

SSZ

Tsens

Fck

Tsenh

SCLK

Tckh

Tckl

SIMO

SOMI

Tds

Tdh

Hi-Z

Figure 1. Serial Port Write Timing

Tsl

SSZ

Tsenh

Fck

Tsens

Trls

SCLK

Tckl

Tds

Tckh

Tdh

R

SIMO

SOMI

Hi-Z

Tsendl

Trdly

Figure 2. Serial Port Read Timings

7.17 Typical Characteristics

120

100

80

60

40

20

0

120

100

80

60

LOAD-

TRK-

40

LOAD+

TRK+

20

0

-3000

-2000

-1000

0

1000

2000

3000

D003

-3000

-2000

-1000

0

1000

2000

3000

D004

DAC Code

Figure 3. DAC Code vs Duty Cycle for LOAD Outputs

Figure 4. DAC Code vs Duty Cycle for TRK Outputs

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8 Detailed Description

8.1 Overview

TPIC2040 is low noise type motor driver IC suitable for 5V optical disk drives. The 7-channel driver IC controlled

by serial I/F is optimum for driving a spindle motor, a sled motor (stepping motor applicable), a load motor, and

Focus / Tracking / Tilt actuators. This IC’s integrated current sense resistance to measure SPM current reduces

drive system cost in drastically. The spindle motor driver part uses integrated sensorless logic to attain very low-

noise operation during startup and runtime. By using BEMF feedback, external sensors, such as a Hall device,

are not needed to carry out self-starting by the starting circuit or perform position detection. By using the efficient

PWM drivers, low-power operation can be achieved by controlling the PWM outputs. Dead zone less control is

possible for a Focus / Tracking / Tilt actuator driver. In addition, the spindle part output current limiting circuit, the

thermal shut down circuit, and the sled end-detection circuit offer protection for all actuators and motors.

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8.2 Functional Block Diagram

5 V

0.1 µF 0.1 µF

PGND_SPM

Analog

10 V(P5Vx2)

XSLEEP

SPM_RCOM

Charge

Pump

3.3 V

SPM

Current Limit

SPM_ENA

SPM Logic

DAC PWM

MCOM

BEMF

Detector

XFG

U

XFG

Predriver

pwr FET

V

SIOV

3.3 V

W

200 kΩ

SSZ

SLED1+

SLED1–

SCLK

Predriver

pwr FET

SCLK

DAC PWM

SIMO

SLD_ ENA

I-F/B

SOMI

SLED END

Detection

ENDDET_ ENA

Digital Core

SLED2+

SLED2–

Predriver

DAC PWM

On-Chip

Themometer

pwr FET

XMUTE

InterLock

SLD_ ENA

I-F/B

F/B

TLT+

TLT–

Predriver

pwr FET

P5V

DAC PWM

CV3P3V

TLT_ENA

int 3.3-V

Regulator

0.1 µ

FCS+

FCS–

Predriver

pwr FET

P5V

SIOV

LINFB

SIOV

F/B

FCS_ ENA

Power

Monitor

XRESET

int 3p3

P5V

TRK+

TRK–

Predriver

pwr FET

ACTTEMPTH>0

TRK_ ENA

F/B

LOAD+

DAC PWM

5 V/3.3 V

Predriver

pwr FET

Charge Pump

LIN3P3_DIS

LIN3VG

LDO

Control

LOAD–

1.2/3.3 V

LOAD_ ENA

CSWO

CSW

CSW _ ON

CSWO

10 µ

LINFB/GPOUT

LIN3P3_DIS

and GPOUT_ENA

GPOUT

TPIC2040

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8.3 Feature Description

8.3.1 Protect Function

TPIC2040 has five protection features, undervoltage lockout (UVLO), over voltage protection (OVP), short circuit

protection (SCP), thermal protection (TSD), and actuator temperature protection (ACTTIMER) in order to protect

target equipment. A protect behavior differ by generated events.

8.3.1.1 Undervoltage Lockout (UVLO)

Power Faults are reported in the UVLOMon register. Each UVLOMon bit will be initialized to zero upon a cold

power up.

After a fault is detected the appropriate fault bit will be latched high. Writing to the RST_ERRFLG (REG77) will

clear all UVLOMon bits. The power device faults and actions are summarized in Table 1.

Table 1. Power Fault Monitor

FAULT TYPE

LATCHED

REGISTER

XRESET

CRITERIA

SPM

ACTUATOR

LDO PRE

DRIVER

P5V under voltage

UVLO_P5V

Yes

<3.5 V

<2.5 V

Hi-Z

internal 3.3V under voltage UVLO_INT3P3

(13-ms timeout

then 120-ms Hi-

Z)

LINFB under voltage

UVLO_1P2V

Yes

<0.93 V

Hi-Z

SIOV under voltage

P5V over voltage

UVLO_SIOV

OVP_P5V

<2.5 V

>6.2 V

>6.5 V

Hi-Z

Brake

Hi-Z

—

Hi-Z

8.3.1.2 Overvoltage Protection (OVP)

Over voltage protect function is aimed to protect the unit from the supplying hi-voltage.

When the supply voltage exceeds 6.5 V, all driver output goes Hi-Z. When the supply voltage falls below typical

6.2 V, (6.0 V for SPM) all output start to operate again. The OVP and POR (XRESET) function is not interlocking.

Moreover, when power supply exceeds 6.2 V, especially SPM enter short brake mode. This operation is offered

supposing a voltage rising by motor BEMF of the high velocity revolution.

This function is for insurance, so it cannot assure that the device is safety in the condition. Because the absolute

maximum ratings range of the supply voltage is 6 V. When this function works, the feedback terminals are not

shorted to GND.

Figure 5 shows the behavior of over voltage protection.

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5-V supply

6.5 V

6.3 V

6.2 V

6.0 V

SPM

Short Brake

Hi-Z

Actuator

LDO

CSW

Hi-Z

Figure 5. Overvoltage Protection

8.3.1.3 Overcurrent Protection (OCP)

The over current protect function serve to protect the device from break down by large current. The OCP is

provided for four circuit blocks, and each threshold are on Table 2.

Table 2. OCP Threshold

BLOCK

DETECTION CURRENT

continue 100% duty

240 mA/425 mA

MONITOR TIME

800 ms

PROTECTION TIME

Forever

LATCHED FLAG

OCP_LOAD

OCP_CSW

Load driver 1 channel

Load driver 0.5 channel

CSW driver

800 ms

Forever

500, 750, 1000 mA

20 µs

1.6 ms

When the large current is detected on each block, device put the output FET to Hi-Z.

The amounts of currents and time have specified the detection threshold for every circuit block.

When OCP occurs, it returns automatically after expiring set Hi-Z period.

OCPERR (REG7F) and OCP flag (REG7B) are set at OCP detection.

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8.3.1.3.1 OCP for Load Driver

LOAD current

0 mA

Hi-Z

LOAD+

100% duty

800 ms

LOAD–

XRESET

Figure 6. Overcurrent Protection Load 1 Channel

800 ms

240 mA

LOAD current

0 mA

Hi-Z

LOAD+

LOAD–

XRESET

Figure 7. Overcurrent Protection Load 0.5 Channel

8.3.1.3.2 OCP for CSW

CSW_ ON

20 µs

500 m A

CSW current

Hi-Z

0 m A

1.6 ms

CSW voltage

XRESET

Figure 8. Overcurrent Protection Current Switch

SCP function always monitors the output voltage of high-side and low-side FET of output driver, and when the

setting voltage is not outputted, it recognizes as SCP and changed output Hi-Z. It returns to the original state

automatically 1.6 ms after.

Table 3. SCP Condition

BLOCK

SPM driver

Sled driver

Load driver

Actuator driver

FUNCTION

DETECTION CONDITION

DETECT TIME

HI-Z HOLD TIME

Monitor driver output voltage

High-side FET output V = GND

Low-side FET output V = Supply V

SCP

0.8 to 1.6 µs

1.6 ms

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VDAC set

Driver current

Hi-Z

detect 1.6 µs

Short to GND

Driver voltage

XRESET

1.6 ms

Figure 9. Example of SCP (Driver Short to GND)

8.3.1.4 Thermal Protection (TSD)

The thermal protection (TSD) is a protection function which intercepts an output and suspends an operation

when the IC temperature exceed a maximum permissible on a safety. TSD makes an output Hi-Z when the

temperature rises up and a threshold value is exceeded. There are two levels for threshold Alert and Trip. An

alarm is given by status register TSD_FAULT_ on Alert level with 135°C. It continues rising up temperature, the

register TSD_ is set at 150°C and the driver output changes HI-Z. If temperature falls and is reached 135°C, it

will output again.

TPIC2040 has total 10 temperature sensors in each circuit block. Particular sensor is assigned to appropriate

status flag in Table 4.

Table 4. Thermal Sensor Assignment

CIRCUIT

U

ALERT (°C)

135

TRIP (°C)

150

RELEASE (°C)

ALERT FLAG

TRIP FLAG

TSD_SPM

TSD_ACT

135

TSD_FAULT_SPM

TSD_FAULT_ACT

V

135

150

W

135

150

TLT

135

150

FCS

TRK

SLED1

SLED2

LOAD

CSW

135

150

135

150

135

150

135

150

135

150

135

150

8.3.1.5 Actuator Temperature Protection (ACTTIMER)

TPIC2040 has Actuator protect function named ACTTIMER. This function enables to avoid from being broken by

setting actuator channel output to HIZ when actuator coil current exceeds the specific value. Up to now, be used

a simple actuator protect function such like exceeding max current with continuous time. However these types

were not accurate. This new protection enables to calculate heat accumulation and judge correctly. When this

function operates, and load channel output will be Hi-Z, too. And spindle channel will be forced Auto short brake

and disc motor will stop.

It is able to know the protection has occurred by checking Fault register ACTTIMER_FAULT (REG7F) and

ACT_TIMER_PROT (REG78). ACTTIMER_FAULT has a character of advance notice, is set before detecting

ACT_TIMER_PROT. Once an ACT_TIMER_PROT is set, even if temperature falls, it will not release protection

automatically. It is necessary to clear the flag by setting RST_ERR_FLAG (REG77) or setting 0 to ACTTEMPTH

(REG72). ACTTIMER function is able to disable by setting H to ACTPROT_OFF (REG72) or setting 0 to

ACTTEMPTH (REG72).

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In order to acquire the optimal value for ACTTEMPTH, you should set device into the condition of the detection

level, and reading the value of ACTTEMP. Because of the present value can be read from ACTTEMP (REG78).

(1)

RST_ERR_FLAG

ACTTIMER_FAULT

ACT_TIMER_PROT

ACTTEMPTH

ACTTEMPTH-1

ACTTEMP count

Hi-Z

FCS+, TRK+, TLT+

Hi-Z

FCS–, TRK–, TLT–

Sled1+, Sled2+

Sled1–, Sled2–

Hi-Z

Load+

Hi-Z

Load–

Motor rpm

0

Auto short brake

XFG

Disable 300 ms

Figure 10. Actuator Temperature Protections

(1) The ACTTEMP data is updated on Register in ACTPROT_OFF = 0 and ACTTEMPTH > 0.

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8.4 Device Functional Modes

8.4.1 Power-on Reset (POR)

8.4.1.1 Power-Up Sequences

In TPIC2040, the normal sequence is to wait for 5-V supply to come up to 2.2 V. After 5 V establish, the internal

3.3 V will start and wait until stabilize. Now the voltage monitors start to work and begin to look for the LDO

output. When LINFB pin over 0.98 V with SIOV over 2.6 V, the power up sequence finishes and the part starts to

function. Once the part finishes all of its power up tasks, it takes XRESET high to indicate that the part is no

longer in reset and ready to communicate to the outside world. Figure 11 is example of power-up sequence

which is set 3.3-V LDO output and output is used for SIOV supply.

P5V Supply

5.0 V

3.7 V

LDO output (3.3 V)

CV3P3

2.6 V

2.2 V

LINFB

0.98 V

XRESET

20 ms

1.6 ms

0 V

time

P5V >3.7 V && CV3P3 >2.6 V

&& SIOV >2.6 V && LINFB >0.98 V

Figure 11. POR (Enable LDO)

P5V Supply

5.0 V

3.7 V

CV3P3

SIOV = LINFB = 3.3 V

2.6 V

2.2 V

0.98 V

0 V

20 ms

XRESET

time

P5V >3.7 V && CV3P3 >2.6 V

&& SIOV >2.6 V && LINFB >0.98 V

LIN3P3_DIS

(Reduced ICC by LIN3P3_dis = 1)

Figure 12. POR (Disable LDO)

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Device Functional Modes (continued)

8.4.1.2 XRESET

TPIC2040 is preparing XRESET pin in order to notify an own status to DSP. TPIC2040 set XRESET to L when

the event which has a serious effect on DSP occurs such like the power failure, the over temperature. If all the

exception is removed, it will tell that XRESET pin would be set to H and it would be in the ready state. The POR

(Power on reset) condition is shown in Figure 23 POR block diagram. All the behavior of XRESET is shown in

Figure 14.

P5V

SIOV

< 6.5 V

> 3.7 V

> 2.6 V

Delay

timer

XRESET

> 0.98 V

int 3.3-V

Regulator

> 2.6 V

LINFB

Figure 13. POR Block Diagram

XRESET: High

(Write Data)

Register Reset

Register Valid Data

RST_REGS = 1

SIF_TIMEOUTERR_MON = 1

20 ms

P5V < 3.5 V

or CV3P3 < 2.5 V

or SIOV < 2.5 V

or LINFB < 0.93 V

P5V > 3.7 V

and CV3P3 > 2.6 V

and SIOV > 2.6 V

and LINFB > 0.98 V

XRESET: Low

Figure 14. XRESET Behavior

8.4.2 XMUTE

This IC has XMUTE pin which had fail-safe function in preparation for unexpected operation.

If XMUTE signal is inputted during operation, all the outputs will be suspended and the danger will be avoided.

TPIC2040 will turn off all enable bits, actuator (TLT_ENA/FCS_ENA/TRK_ENA), SPM_ENA, SLD_ENA,

LOAD_ENA and CSW_ON when XMUTE input change to L. LOAD_ENA bit will be disabled only when

LOAD_05CH = 1. Also log this event to error latch flag XMUTE_DETECT (REG79) and PWRERR (REG7F).

On the other hand, if it is set as XMUTE_NORST (REG7F) = 1, change of XMUTE will not influence to enable

bits.

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8.5 Programming

8.5.1 Serial Port Functional Description

The serial communication of TPIC2040 is based on a SPI communications protocol. TPIC2040 is put on the

slave side.

All 16-bit transmission data is effective in SSZ = L period.

The bit stream sent through SIMO from a master (DSP) is latched to an internal shift register by the rising edge

of SCLK. All the data is transmitted in a total of 16-bit format of a command and data. A format has two types of

data, 8 bits and 12 bits length. In order to access specific registers, an address and R/W flag are specified as a

command part. In addition, 12-bit data do not have R/W flag in the packet because DAC registerꢀ(= 12-bit data

form) are Write only. A transfer packet, command and data, is transmitted sequentially from MSB to LSB. A

packet is distinguished in MSB 2 bits of command. In the case of 11, it handles a packet for control register

access, and the other processed as a packet for a DAC data setting.

There are the following four kinds of serial-data communication packets.

1. Write 12 bits DAC data (MSB two bit ≠ 11)

2. Write 8 bits control register (MSB two bit = 11)

3. Read 8 bits control register (MSB two bit = 11)

4. Write 12 bits Focus DAC data＋Read 8 bits status register at the same time (MSB two bit ≠ 11)

8.5.2 Write Operation

For write operation, DSP transmits 16 bit (command + address + data) data a bit every in an order from MSB.

Only the 16-bit data which means 16 SCLK sent from the master during SSZ = L becomes effective. If more than

17 or less than 15 SCLK pulses are received during the time that SSZ is low, the whole packet will be ignored.

For all valid write operations, the data of the shift register is latched into its designated internal register at rising

edge of 16^thSCLK. All internal register bits, except indicated otherwise, are reset to their default states upon

power-on-reset.

SSZ

SCLK

SIMO

C3

C2

C1

C0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SOMI

Hi-Z

Figure 15. Write 12-Bits DAC Data

SSZ

SCLK

SIMO

SOMI

A6

A5

A4

A3

A2

A1

A0

W

D7

D6

D5

D4

D3

D2

D1

D0

Hi-Z

Figure 16. Write 8-Bits Control Register

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Programming (continued)

8.5.3 Read Operation

DSP sends 8-bit header through SIMO, in order to perform Read operation. TPIC2040 will start to drive the

SOMI line upon the eighth falling edge of SCLK and shift out eight data bits. The master DSP inputs 8bits data

from SOMI after the ninth rising edge of SCLK. There is optional read mode that SOMI data is advanced a half

clock cycle of SCLK. This mode becomes effective by setting ADVANCE_RD (REG74) = H.

SSZ

SCLK

SIMO

SOMI

A6

A5

A4

A3

A2

A1

A0

R

D7

D6

D5

D4

D3

D2

D1

D0

Hi-Z

Figure 17. Read 8-Bits Control Register

8.5.4 Write and Read Operation

Optionally, the master DSP can read Status register during writing 12 bits DAC (Focus DAC) packet. It is

enabled by setting bit STATUS_ON_VFCS (REG74) = H.

SSZ

SCLK

SIMO

SOMI

C3

C2

C1

C0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Hi-Z

Figure 18. Write 12-Bits Focus DAC Data + Read 8-Bits Status Data

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8.6 Register Maps

All registers are in WRITE-protect mode after XRESET release. WRITE_ENA bit (REG76) = H is required before

writing data in register.

8.6.1 Register State Transition

Version Data

(REG7E)

Device PowerOn

Initial Value Set

P5V < 3.5 V

P5V < 3.7V

or CV3P3 < 2.5 V

or CV3P3 < 2.7V

XRESET= H

(TPIC2040 output)

or SIOV < 2.5 V

or SIOV < 2.5V

or DCDC converter < 80%

or LINFB < 0.93 V

or RST_REGS = 1

orP5V> 6.5V

or SIF_TIMEOUT_ERR = 1

or RST_ REGS= 1

P5V< 2.0 V

orCV3P3 < 2.0 V

or RST_ ERR_ FLAG = 1

W RITE_ ENABLE = 0

or XSLEEP= 0

or SIF_ TIMEOUT_ ERR= 1

Control Reg data

Driver Enable

(REG70 .. 7F, 6F)

(REG70 xxx_ ENA, REG71 CSW _ ON)

P5V < 3.5 V

disable (0)

or CV3P3 < 2.5 V

or SIOV < 2.5 V

or LINFB < 0.93 V

or P5V > 6.5 V

XMUTE = L

(@XMUTE_ NORST = 0

XMUTE_ NORST_CSW = 0) *

Write (1)

or

XMUTE = L

SIF_TIMEOUT_ERR = 1

RST_REGS = 1

enable (1)

*disable LOAD_ENA only Load05_CH = 1

Error latched Reg data

(REG78,79,7A,7B,7F [5:1])

VDAC Reg data

(REG01- 09)

Write(Vxxx)

Initial (000)

SetValue

(Error occur, xmute = L)

RST_ INDAC = 1

or XXX_ ENA= 0

Register Enable

Figure 19. Register State Transition Chart

Two difference forms are prepared in 12-bit DAC register, and the forms can be selected by setting

VDAC_MAPSW (REG74h).

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8.6.4 Detailed Description of Registers

8.6.4.1 REG01 12bit DAC for Tilt (VDAC_MAPSW = 0)

Figure 20. Tilt (REG01)

15

14

13

12

11

10

9

8

VTLT

w-0

3

w-0

2

w-0

1

w-0

0

7

6

5

4

VTLT

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. TILT (REG01) Field Descriptions

Bit

Field

Type

Default

Description

11-0

VTLT

w

0

Digital input code for Tilt.

2’s compliment format 0x800(-2048) to 0x7ff(+2047)

Output is changed by differential Tilt mode (REG74[7])

TLT_OUT = VTLT × (6.0 / 2048) (DIFF_TLT = 0)

TLT_OUT = (VFCS-VTLT) × (6.0 / 2048) (DIFF_TLT = 1)

TLT_OUT should be changed after writing VFCS.

In DIFF_TLT mode (DIFF_TLT = 1), TLT_OUT should be changed after

writing VFCS.

8.6.4.2 REG02 12bit DAC for Focus (VDAC_MAPSW = 0)

Figure 21. Focus (REG02)

15

14

13

12

11

10

9

8

VFCS

w-0

3

w-0

2

w-0

1

w-0

0

7

6

5

4

VFCS

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. Focus (REG02) Field Descriptions

Bit

Field

Type

Default

Description

11-0

VFCS

w

0

Digital input code for Focus.

2’s compliment format 0x800(-2048) to 0x7ff(+2047)

Output is changed by differential Tilt mode (REG74[7])

FCS_OUT = VFCS × (6.0 / 2048) (DIFF_TLT = 0)

FCS_OUT = (VFCS + VTLT) × (6.0 / 2048) (DIFF_TLT=1)

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ZHCSEG2 –DECEMBER 2015

8.6.4.3 REG03 12bit DAC for Tracking (VDAC_MAPSW = 0)

Figure 22. Tracking (REG03)

15

14

13

12

11

10

9

8

VTRK

w-0

3

w-0

2

w-0

1

w-0

0

7

6

5

4

VTRK

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. Tracking (REG03) Field Descriptions

Bit

Field

Type

Default

Description

11-0

VTRK

w

0

Digital input code for Tracking.

2’s compliment format 0x800(-2048) to 0x7ff(+2047)

TRK_OUT = VTRK × (6.0 / 2048)

8.6.4.4 REG04 10bit DAC for Sled1 (VDAC_MAPSW = 0)

Figure 23. Sled1 (REG04)

15

14

13

12

11

10

9

8

VSLD1

w-0

3

w-0

2

w-0

1

w-0

0

7

6

5

4

VSLD1

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. Sled1 (REG04) Field Descriptions

Bit

Field

Type

Default

Description

11-2

VSLD1

w

0

Digital input code for Sled1.

2’s compliment format 0x800(-2048) to 0x7ff(+2047)

Two bits on LSB, VSLD1[1:0], will be handled with zero.

SLD1_OUT = VSLD1 × (440 mA / 2048)

8.6.4.5 REG05 10bit DAC for Sled2 (VDAC_MAPSW = 0)

Figure 24. Sled2 (REG05)

15

14

13

12

11

10

9

8

VSLD2

w-0

3

w-0

2

w-0

1

w-0

0

7

6

5

4

VSLD2

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. Sled2 (REG05) Field Descriptions

Bit

Field

Type

Default

Description

11-2

VSLD2

w

0

Digital input code for Sled2.

2’s compliment format 0x800(-2048) to 0x7ff(+2047)

Two bits on LSB, VSLD2[1:0], will be handled with zero.

SLD2_OUT = VSLD2 × (440mA / 2048)

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8.6.4.6 REG08 12bit DAC for Spindle (VDAC_MAPSW = 0)

Figure 25. Spindle (REG08)

15

14

13

12

11

10

9

8

VSPM

w-0

3

w-0

2

w-0

1

w-0

0

7

6

5

4

VSPM

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. Spindle (REG08) Field Descriptions

Bit

Field

Type

Default

Description

11-0

VSPM

w

0

Digital input code for Spindle.

2’s compliment format 0x800(-2048) to 0x7ff(+2047)

SPM_OUT = VSPM × (6.0 / 2048)

8.6.4.7 REG09 12bit DAC for Load (VDAC_MAPSW = 0)

Figure 26. Load (REG09)

15

14

13

12

11

10

9

8

VLOAD

w-0

3

w-0

2

w-0

1

w-0

0

7

6

5

4

VLOAD

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. Load (REG09) Field Descriptions

Bit

Field

Type

Default

Description

11-0

VLOAD

w

0

Digital input code for Load.

2’s compliment format 0x800(-2048) to 0x7ff(+2047)

LOAD_OUT = VLOAD × (6.0 / 2048)

8.6.4.8 REG6A 8-Bit Control Register for CSW_OCP (REG6A)

Figure 27. CSW_OCP (REG6A)

7

6

5

4

3

2

1

0

TI reserved

CSW_OCP

TI reserved

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. CSW_OCP (REG6A) Field Descriptions

Bit

7-6

5-4

Field

Type

rw

Default

Description

0

CSW_OCP

rw

CSW OCP current threshold selection

00: 0.5 A

01: 0.75 A

10: 1 A

11: OCP disable

3-0

TI reserved

rw

0

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8.6.4.9 REG6C 8-Bit Control Register for Parm1 (REG6C)

Figure 28. Parm1 (REG6C)

7

6

5

4

3

2

1

0

TI reserved

rw-0

EDET_DELAY

TI reserved

SLDENDTH[2]

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. Parm1 (REG6C) Field Descriptions

Bit

7-5

4-3

Field

Type

rw

Default

Description

TI reserved

EDET_DELAY

0

rw

Timing parameter of detection window for sled end detection. (delay

time / window width)

EDET_DELAY[1:0]

00: 0 ms/0.41 ms

01: 0.62 ms/0.20 ms

10: 0.93 ms/0.30 ms

11: 1.24 ms/0.41 ms

2-1

0

TI reserved

rw

0

SLDENDTH[2]

Sled end detection sensibility setting. Detection threshold for motor

BEMF

SLDENDTH[2:0]

000: 46 mV

010: 82 mV

011: 22 mV

100: 125 mV

101: 105 mV

111: 145 mV

8.6.4.10 REG6F 8-Bit Control Register for MonitorSet (REG6F)

Figure 29. MonitorSet (REG6F)

7

6

5

4

3

2

1

0

ACTTIMER_FL ENDDET_MON SIF_TIMEOUT PWRERR_MO TSDERR_MON OCPERR_MO TSDFAULT_M

TI reserved

T_MON

ERR_MON

N

ON

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. MonitorSet (REG6F) Field Descriptions

Bit

Field

Type

Default

Description

7

ACTTIMER_FLT_MON rw

0

Assign signal to GPIO pin

1: ACTTIMER fault output to GPOUT pin

6

5

4

3

2

1

0

ENDDET_MON

rw

0

Assign signal to GPIO pin

1: ENDDET monitor output to GPOUT pin

SIF_TIMEOUTERR_M rw

ON

Assign signal to GPIO pin

1: SIF timeout monitor output to GPOUT pin

PWRERR_MON

TSDERR_MON

OCPERR_MON

TSDFAULT_MON

TI reserved

rw

Assign signal to GPIO pin

1: PWRERR monitor output to GPOUT pin

Assign signal to GPIO pin

1: TSDERR fault output to GPOUT pin

Assign signal to GPIO pin

1: OCPERR fault output to GPOUT pin

Assign signal to GPIO pin

1: TSDFAULT fault output to GPOUT pin

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8.6.4.11 REG70 8-Bit Control Register for DriverEna (REG70)

Figure 30. DriverEna (REG70)

7

6

5

4

3

2

1

0

TLT_ENA

rw-0

FCS_ENA

rw-0

TRK_ENA

rw-0

SPM_ENA

rw-0

SLD_ENA

rw-0

TI reserved

rw-0

LOAD_ENA

rw-0

XSLEEP

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. DriverEna (REG70) Field Descriptions

Bit

Field

Type

Default

Description

7

TLT_ENA

rw

0

1 : Tilt enable (with XSLEEP=1)

It is reset when XMUTE changes to L.

6

5

4

3

1

FCS_ENA

TRK_ENA

SPM_ENA

SLD_ENA

LOAD_ENA

rw

0

1: Focus enable (with XSLEEP=1)

It is reset when XMUTE changes to L.

1: Track enable (with XSLEEP=1)

It is reset when XMUTE changes to L.

1: Spindle enable (with XSLEEP=1)

It is reset when XMUTE changes to L.

1: Sled enable (with XSLEEP=1)

It is reset when XMUTE changes to L.

1 : LOAD enable (with XSLEEP=1)

Track (bit5:TRK_ENA) will be disabled at LOAD_ENA=1 because of

sharing the DAC PWM module. Load priority is higher than TRK_ENA.

It is reset when XMUTE changes to L. (with LOAD_05CH=1)

0

XSLEEP

rw

0

1: Operation mode 0 : Power save mode

Charge pump enable bit when LIN3P3_DIS is 1.

All driver enable bit (Bit[7:1]) change disabled and output change to Hi-Z

(regardless of setting xxx_ENA bit is 1) when setting XSLEEP to 0.

Therefore set 1 to XSLEEP before setting each enable bits.

8.6.4.12 REG71 8-Bit Control Register for FuncEna (REG71)

Figure 31. FuncEna (REG71)

7

6

5

4

3

2

1

0

SPM_LSMODE ENDDET_ENA

LIN3P3_DIS

TI reserved

CSW_ON

XMUTE_NORS

T_CSW

TI reserved

rw-0 rw-0

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. FuncEna (REG71) Field Descriptions

Bit

Field

Type

Default

Description

7

SPM_LSMODE

rw

0

0 : Spindle Normal rotation mode

1 : Light Scribe mode (slow rotation mode)

6

5

ENDDET_ENA

LIN3P3_DIS

rw

0

1 : use Sled end detection enable ( with SLD_ENA=1)

1 : disable LIN3P3 pre-driver control. This bit will be set 1 when using

LINFB pin use for monitoring GPOUT signal. (with GPOUT_ENA) Also

the setting one is able to reduce ICC

3

2

CSW_ON

rw

0

1 : CSWO enable ( with XSLEEP=1)

It is reset when XMUTE changes to L

XMUTE_NORST_CSW rw

Reset option for CSW by XMUTE event

0: Reset CSW_ON bit register at XMUTE=L.

1: XMUTE status does not influence enable bit.

1-0

TI reserved

rw

0

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8.6.4.13 REG72 8-Bit Control Register for ACTCfg (REG72)

Figure 32. ACTCfg (REG72)

7

6

5

4

3

2

1

0

LOAD_O5CH_ LOADPROT_O ACTPROT_OF

ACTTEMPTH

HIGH

FF

F

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 20. ACTCfg (REG72) Field Descriptions

Bit

Field

Type

Default

Description

7

LOAD_05CH_HIGH

rw

0

LOAD output polarity at 0.5CH ( REG74h[6]=1 )

0: LOADP = Low

1: LOADP = High

6

5

LOADPROT_OFF

ACTPROT_OFF

rw

0

1: Load overcurrent protection OFF

0 : Actuator protection ON

1 : Actuator Fault monitor disable (No protection for ACT channel)

4-0

ACTTEMPTH

rw

0

Actuator thermal protection (=ACT Timer) threshold level

ACT Timer Protection enable except ACTTEMPTH[4:0] = 0x00

ACTTEMPTH = 0x00 equal to ACTPROT_OFF = 1

By writing value 0x00, ACTTIMER_PROT flag is cleared.

8.6.4.14 REG73 8-Bit Control Register for Parm0 (REG73)

Figure 33. Parm0 (REG73)

7

6

5

4

3

2

1

0

SIF_TIMEOUT_TH

SLEDEND_HZ

TIME

SLDENDTH[1:0]

SPM_RCOM_SEL

XMUTE_NORST

rw-0 rw-0

rw-0

rw-0 rw-0

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. Parm0 (REG73) Field Descriptions

Bit

Field

Type

Default

Description

7-6

SIF_TIMEOUT_TH

rw

0

Watch dog timer for Serial communication

0: disable 1: 1 ms 2: 100 µs 3: 10 µs

Set SIF_TIMEOUTERR (REG7F) if communication is suspended for this

time period. XRESET processing will be performed if a

SIF_TIMEOUTERR occurs.

5

SLEDEND_HZTIME

SLDENDTH[1:0]

rw

0

Time window for sled end detection.

0: 400 µs 1: 200 µs

Caution) Need to recycle ENDDET_ENA = 0 → 1 after writing this bit.

4-3

Sled end detection sensibility setting. Detection threshold for motor

BEMF

SLDENDTH[2:0]

000: 46 mV 010: 82 mV 011: 22 mV 100: 125 mV

101: 105 mV 111: 145 mV

2-1

0

SPM_RCOM_SEL

XMUTE_NORST

rw

0

Select resistor value of spindle current sense resistor. Current limit is set

as following current.

00: 890 mA; 01: 980 mA; 10: 725 mA; 11: 784 mA

Reset driver enable bit (XXX_ENA) register at XMUTE = L.

0: Reset enable bit at XMUTE = L

1: XMUTE status does not influence enable bit.

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8.6.4.15 REG74 8-Bit Control Register for OptSet (REG74)

Figure 34. OptSet (REG74)

7

6

5

4

3

2

1

0

DIFF_TLT

LOAD_05CH

RDSTAT_ON_

VFCS

VSLD2_POL

LOAD_OCP_IU

P

TI reserved

SOMI_HIZ

VDAC_MAPSW

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22. OptSet (REG74) Field Descriptions

Bit

Field

Type

Default

Description

7

DIFF_TLT

rw

0

1 : Differential Tilt mode enable (with TLT_ENA = FCS_ENA = 1)

Differential Tilt mode (DIFF_TLT = 1), DAC value setting as follows

FCS_OUT = (VFCS + VTLT) × 6 / 2048

TLT_OUT = (VFCS – VTLT) × 6 / 2048

In DIFF_TLT mode (DIFF_TLT = 1), TLT_OUT should be changed after

writing VFCS.

6

5

LOAD_05CH

rw

0

The setting of Load motor driving type. Load output changes as follow

0: Step down mode (LOAD output is controlled by DAC code, VLOAD)

Use for Slot-in model or step down tray model.

1: 0.5-channel mode (LOAD is only controlled by LOAD_05CH_HIGH)

Use for Tray model

RDSTAT_ON_VFCS

Set Read status data (REG7F) at VFCS write command (REG02)

1: Enable Write and Read mode

(Write 12-bits Focus DAC data + Read 8-bits status data)

4

3

VSLD2_POL

rw

0

change direction of SLED rotation

LOAD_OCP_IUP

Select overcurrent protection (OCP) threshold for Load channel current

0: 250 mA

1: 425 mA

1

0

SOMI_HIZ

rw

0

0: SOMI line High-Z at bus idling time.

1: SOMI line Pull Down at bus idling time.

VDAC_MAPSW

Selection of DAC register channel assignments (REG01~09)

8.6.4.16 REG75 8-Bit Control Register for TSD_TUP (REG75)

Figure 35. TSD_TUP (REG75)

7

6

5

4

3

2

1

0

TI reserved

rw-0

TSD_TUP

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23. TSD_TUP (REG75) Field Descriptions

Bit

7-1

0

Field

Type

rw

Default

Description

TI reserved

TSD_TUP

0

rw

TSD temperature threshold selection (Fault/Error)

0: 135/150°C

1: 155/170°C

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8.6.4.17 REG76 8-Bit Control Register for WriteEna (REG76)

Figure 36. WriteEna (REG76)

7

6

5

4

3

2

1

0

WRITE_ENABL

E

TI reserved

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. WriteEna (REG76) Field Descriptions

Bit

Field

Type

Default

Description

7

WRITE_ENABLE

rw

0

0: Register Write disable except REG76

1: Able to write all RW and W register

6-0

TI reserved

rw

0

8.6.4.18 REG77 8-Bit Control Register for ClrReg (REG77)

Figure 37. ClrReg (REG77)

7

6

5

4

3

2

1

0

RST_INDAC

RST_REGS

RST_ERR_FLA

G

TI reserved

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. ClrReg (REG77) Field Descriptions

Bit

Field

Type

Default

Description

7

RST_INDAC

w

0

1 : Reset all 12-bit input DAC register (REG01~0B)

Self clear bit

6

5

RST_REGS

w

0

1 : Reset all 8-bit R/W Registers (REG70h~77h, 60h-6Fh)

Self clear bit

RST_ERR_FLAG

TI reserved

1 : Reset Fault Flag Latch (REG7F[5:1], REG79~REG7B)

Self clear bit

4-0

8.6.4.19 REG78 8-Bit Control Register for ActTemp (REG78)

Figure 38. ActTemp (REG78)

7

6

5

4

3

2

1

0

TI reserved

ACT_TIMER_P

ROT

ACTTEMP

r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 26. ActTemp (REG78) Field Descriptions

Bit

7-6

5

Field

Type

Default

Description

TI reserved

ACT_TIMER_PROT

r

0

ACT timer protection flag

1: ACT Timer Protection has detected and latched.

(ACTTEMP > ACTTEMPTH)

This bit holds data after temperature change to low since this is a latch

bit. Also driver output keep Hi-Z until setting RST_ERR_FLAG or

ACTTEMPTH = 0.

4-0

ACTTEMP

r

0

An integrated value of ACT_TIMER counters at present.

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8.6.4.20 REG79 8-Bit Control Register for UVLOMon (REG79)

Figure 39. UVLOMon (REG79)

7

6

5

4

3

2

1

0

TI reserved

XMUTE_DETE

CT

UVLO_P5V

UVLO_INT3P3

UVLO_SIOV

UVLO_1P2V

OVP_P5V

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27. UVLOMon (REG79) Field Descriptions

Bit

7-6

5

Field

Type

Default

Description

TI reserved

XMUTE_DETECT

UVLO_P5V

UVLO_INT3P3

UVLO_SIOV

UVLO_1P2V

r

0

XMUTE flag for detection low input. (>20 µs)⁽¹⁾

UVLO flag for detection low P5V supply⁽¹⁾

UVLO flag for detection low internal 3.3-V regulator⁽¹⁾

UVLO flag for detection low SIOV⁽¹⁾

UVLO flag for detection low LINFB⁽¹⁾

No detection in LIN3P3_DIS = 1

4

3

2

1

0

OVP_P5V

r

0

Overvoltage protection flag for P5Vsply⁽¹⁾

(1) Latched 1 ^stevent only. Cleared by RST_ERR_FLG (REG77)

8.6.4.21 REG7A 8-Bit Control Register for TsdMon (REG7A)

Figure 40. TsdMon (REG7A)

7

6

5

4

3

2

1

0

TI reserved

TSD_FAULT_S TSD_FAULT_A

TI reserved

TSD_SPM

TSD_ACT

TI reserved

PM

CT

r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 28. TsdMon (REG7A) Field Descriptions

Bit

7

Field

Type

Default

Description

TI reserved

r

0

6

TSD_FAULT_SPM

TSD_FAULT_ACT

Pre alert of thermal protection of Spindle block⁽¹⁾

5

Pre alert of thermal protection of Focus /Track /Tilt Sled1 /Sled2 / /Load

/CSW⁽¹⁾

4-3

2

TI reserved

TSD_SPM

r

0

(1)

Thermal protection flag for Spindle

SPM output Hi-Z until temperature falls on release level

1: Detect (latch)

1

0

TSD_ACT

r

0

Thermal protection flag for Focus /Track /Tilt Sled1 /Sled2 /Load/CSW⁽¹⁾

Actuator output Hi-Z until temperature falls on release level

1: Detect (latch)

TI reserved

(1) Cleared by RST_ERR_FLAG bit (REG77)

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8.6.4.22 REG7B 8-Bit Control Register for ProtMon (REG7B)

Figure 41. ProtMon (REG7B)

7

TI reserved

r-0

6

OCP_LOAD

r-0

5

TI reserved

r-0

4

OCP_CSW

r-0

3

SCP_SPM

r-0

2

SCP_SLED

r-0

1

SCP_LOAD

r-0

0

SCP_ACT

r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 29. ProtMon (REG7B) Field Descriptions

Bit

7

Field

Type

Default

Description

TI reserved

OCP_LOAD

OCP_CSW

SCP_SPM

SCP_SLED

SCP_LOAD

SCP_ACT

r

0

6

Overcurrent protection flag bit for Load channel.⁽¹⁾

Overcurrent protection flag bit for CSW channel.⁽¹⁾

Short-circuit protection flag bit for spindle channel.⁽¹⁾

Short-circuit protection flag bit for sled channel.⁽¹⁾

Short-circuit protection flag bit for load channel.⁽¹⁾

Short-circuit protection flag bit for Fcs/Trk/Tilt channel.⁽¹⁾

4

3

2

1

0

(1) Cleared by RST_ERR_FLAG bit (REG77)

8.6.4.23 REG7E 8-Bit Control Register for Version (REG7E)

Figure 42. Version (REG7E)

7

6

5

4

3

2

1

0

Version

r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 30. Version (REG7E) Field Descriptions

Bit

Field

Type

Default

Description

7-0

Version

X

Version[7:4] = revision number of TPIC2040

Version[3:0] = option

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8.6.4.24 REG7F 8-Bit Control Register for Status (REG7F)

Figure 43. Status (REG7F)

7

6

5

4

3

2

1

0

ACTTIMER_

FAULT

ENDDET

SIF_TIMEOUT

ERR

PWRERR

TSDERR

OCPERR

TSDFAULT

FG

r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 31. Status (REG7F) Field Descriptions

Bit

Field

Type

Default

Description

7

ACTTIMER_FAULT

r

0

Status flag of ACTTIMER protection

1: Pre alert of ACTTIMER protection. It is close to the threshold level.

You can get current ACTTIMER value in REG78.

Both of this bit and ACT_TIMER_PROT (REG78) will be set when over

the threshold.

6

5

4

3

2

1

0

ENDDET

r

0

status flag of END detection

1: end position detected (not latch bit)

SIF_TIMEOUTERR

PWRERR

TSDERR

error flag of serial I/F watch dog timer

1: SIF communication was interrupted, expired watch dog timer

error flag of Power

1: Voltage problem occurred, details in REG79

error flag of any over thermal protections

1: Dispatched thermal protection, details in REG7A

OCPERR

TSDFAULT

FG

error flag of any over current protection

1: Dispatched OCP, details in REG7Bh

warning of TSD of any thermal protection

1: Detect pre thermal protection details in REG7A

FG signal. Spindle rotation pulse for speed monitor

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

NOTE

•

Operate every driver channel after 5-V power supplied and stable.

Appropriate capacity of de-coupling capacitor is required enough value of over 10 μF

due to reduce influence of PWM switching noise. And the P5V pin needs to connect a

filter of 1 μF. It is effective to put bypass capacitor(about 0.1 µF) near Power pin

(P5V_1, P5V_2, P5V_SPM) for PWM switching noise reduction on power and GND

line.

•

Much current flow to driver circuits, to consider as below matters.

–

ꢀPattern-layout, line-impedance, and noise influence from supply line.

9.1 Application Information

9.1.1 DAC Type

TPIC2040 has seven channels of Actuator. Each channel is assigned to the most suitable DAC engine with a

different type respectively. ACT(F/T/Ti) has 12-bit DAC. Upper 8 (MSB sign bit) are converted at a time in 5MHz

and LSB 4 bits are output in sequence with 1.25-MHz PWM. SPIN, SLED and Load DAC has same DAC types

and sampling rate with 312 kHz. All channel except SLED have x6 gain. Table 32 shows configuration of each

actuator.

Table 32. DAC Type

FCS/TRK/TLT

12 bit

SLED

10 bit

SPIN

12 bit

LOAD

12 bit

Resolution

Type

8-bit oversampling

10-bit voltage

8-bit Oversampling

312K

8-bit Oversampling

312K

Sampling

1.25M / 10bit

312K / 12bit

PWM frequency

Out range

312 kHz

±6 V

About 156 kHz(variable)

±440 mA

156 kHz

±6 V

312 kHz

±6 V

Feed back

Voltage feedback

Current feedback

Power supply

compensation

Voltage feedback

Shared with TRK

9.1.2 Example of 12-Bit DAC Sampling Rate for FCS/TRK/TLT

The input data is separated in the upper 8bits and the lower 4bits. Upper 8bits (MSB sign 1bit) will be put into

8bit current DAC in every 5 MHz. The lower 4bits will be put into one bit current DAC in sequence from upper to

lower bit. This one bit DAC output with PWM in 1.25 MHz. At any PWM duty, 100%, 75%, 50%, 25% or 0%, will

be summed in 8bit current DAC in every 1.25 MHz. Thus it takes 3.2 µs for all lower 4bits summing to PWM

output. As a result, 12-bit data is sampled in every PWM cycle. Example of sampling rate for FCS/TRK/TLT is

Figure 44.

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TPIC2040

ZHCSEG2 –DECEMBER 2015

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White DAC

8

5 MHz

1.25 MHz

625 kHz

312 kHz

10 bit

11 bit

12 bit

LSB 4 bit width

PWM duty

12 bit DAC (8 bit DAC + 4 bit PWM DAC) output

one PWM cycle (312 kHz = 3.2 µs)

Figure 44. Example of 12-Bit DAC Conversion Time (FCS/TRK/TLT)

9.1.3 Digital Input Coding

The output voltage (current) is commanded via programming to the DAC. All of the DAC input format is 12bit in

two’s complement though some DAC has a low resolution. When 12 bits data is input 8 bits DAC, TPIC2040

recognizes four subordinate position bits (LSB) as 0. To arrange for 12-bit DAC format, DSP should shift 8bit or

10 bit data to an appropriate bit position. The full scale is ±1.0 V and driver gain is set 6. The output voltage

(Vout) is given by the following equation:

6 .0

V o u t = D A C c o d e ì

2 0 4 8

(1)

V d a c = 1 .0 ì b it[1 0 ] ì 0 .5¹+ b it[9 ] ì 0 .5 ²+ b it[8 ] ì 0 .5 ³+ ... + b it[0 ] ì 0 .5 ^{1 1}

(

)

V d a c = (œ 1 .0 ) ì b it[1 0 ] ì 0 .5 ¹+ b it[9 ] ì 0 .5 ²+ b it[8 ] ì 0 .5 ³+ .. . + b it[0 ] ì 0 .5^{1 1}+ 0 .5^{1 2}

(

)

V o u t = V d a c ì 6 .0 ( V )

S L E D Io u t = V d a c ì 0 .4 4 ( A )

where

•

bit[11:0] is the digital input value, range 000000000000b to 111111111111b.

(2)

Table 33. DAC Format

LSB

^MSBDIGITAL INPUT (BIN)

1000_0000_0000

1000_0000_0001

1111_1111_1111

0000_0000_0000

0000_0000_0001

0111_1111_1110

0111_1111_1111

HEX

DEC

-2048

-2047

-1

VDAC

-0.9995

-0.0005

0

ANALOG OUTPUT

0x800

0x801

0xFFF

0x000

0x001

0x7FE

0x7FF

-5.997

-0.003

0.000

0

+1

+0.0005

+0.9990

+0.9995

+0.003

+5.994

+5.997

+2046

+2047

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Analog output (V)

+ 6.0

VDAC

+ 1.000

+ 5.0

*

800h

DAC code

7FFh

000

–5.0

–6.0

*

–1.000

* following P5V input voltage

Figure 45. Output Voltage vs DAC Code

9.1.4 Example Timing of Target Control System

TPIC2040 is designed for that meets the requirements updating control data in 400 kHz. The example of control

system parameter is listed in Table 34. It takes 0.51 µs for transmit a 16bit data packet to TPIC2040 with 35MHz

SCLK. Therefore, DSP can be sent four packets a 400-kHz interval. If SCLK is lower than 28.8MHz, it is required

reducing packet quantity under three. For example, Focus/Truck command is updating in every 2.5 µs (400 kHz),

and it is able to send another two kind of packet in this same slot. Figure 10 Example DAC control shows the

example of the control timing when TPIC2040 is used.

Table 34. Example Timing of Target Control System

SIGNAL

Focus

Track

Tilt

BIT

12

10

12

UPDATE CYCLE (kHz)

400

200

100

—

Sled1

Sled2

Spindle

Load

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312 kHz /3.2 µs(PWM 1cycle)

Track

R

Focus

Tilt

Sled1

Sled2

SPM

Load

400 kHz /2.5 µs

Control

register

100 kHz /10 µs(1control cycle)

PWM cycle

DAC command

0.51 µs (SCLK:35 MHz) for data transmit

R

DAC command w/ status read

Control register command

Figure 46. Example DAC Control

9.1.5 Spindle Motor Driver Part

When VSPM is set a positive DAC code then it will be into acceleration mode. IS mode operates then the start-

up circuit offers the special start-up pattern sequence to the driver in start-up, and then switches to spin-up mode

by detecting the rotor position by BEMF signal from the spindle motor coil.

The spin-down and brake function also be controlled by VSPM DAC value. When it is set the brake command to

VSPM, driver goes into active-brake mode, then switch to short-brake mode in slow revolution speed, and then

stop automatically. The FG signal is composed from EXOR of three-phase signal, and is output from XFG pin as

ꢀshown in Figure 47.

XRESET

WRITE_ENABLE

XSLEEP

SPM_ENA

VSPM

VSPM[11.0] > 0

VSPM[11.0] < 0

0

XFG

brake

speed

> 15 ms

Release

300 ms

130 rpm

time

Figure 47. Spindle Operating Sequence

•

TI recommends to use down-edge of FG signal for monitoring FG frequency. The FG terminal needs to be

pulled up to the appropriate supply voltage by external resistor.

•

Short brake mode is asserted after 300 ms of FG signal stays L-level in deceleration.

The FG output is set to H-level in sleep mode in order to reduce sleep mode current.

This value is the nominal number of using motor with 16-poles.

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•

First of all, power supply voltage of P5V must be supplied before any signals input.

9.1.5.1 Spindle PWM Control

The output PWM duty of Spindle is controlled by DAC code (VSPM). The gain in acceleration setting is always

six times. However, the maximum output is restricted to P5V_SPM voltage. A dead band which output = 0 exists

in the width of plus or minus 0x52 focusing on zero.

PWM Output Duty

Output (V)

60 V

5.0 V

SPM_LSMODE = 0

100%

Dead Band

Duty = 0%

25%

Slow Down

Speed Up

0%

VSPMx[11:0]

800h

FAEh

000

52h

7FFh

Figure 48. Spindle PWM Control

9.1.5.2 Auto Short Brake Function

TPIC2040 provides auto short brake function which is selecting brake mode automatically by motor speed.

Auto Short Brake is the intelligent brake function that includes two modes: short brake and active brake.

When VSPM value is controlled more than equivalent 75% duty brake, deceleration is done by short brake under

the rotation speed is over 3000 rpm. After deceleration, driver goes into Active-brake mode automatically by

internal logic circuit under rotation speed is lower 2000 rpm. This function enables low power consumption and

silent during braking.

Table 35. Brake Mode

ROTATION SPEED (RPM)

VSPM[11:0]

ABOUT 0 TO 2000

2-phase short brake

Active brake

ABOUT 3000

2-phase short brake

Active brake

0x000 - 0xFAE

0xFAE - 0xA00

0xA00 - 0x800

Active brake

3-phase short brake

rpm

4000

Slow down

3-phase

short

3000

2000

Active

1000

0

VSPM[11:0]

800h

A00h

FAEh

000

Figure 49. Brake Mode Selections

This value is the nominal number of using motor with 16-poles motor.

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9.1.5.3 Spindle Low-Speed Mode

LS mode is the low rotation mode which made the maximum 25% duty. When using SPM_LSMODE = 1, brake

mode is always short brake. Figure 50 shows the output duty of LS mode.

PWM Output Duty

Output (V)

SPM_LSMODE = 1

6.0 V

5.0 V

100%

25%

0%

Speed up

Duty = 0%

VSPM[11:0]

800h

000

7FFh

Figure 50. Spindle PWM Control (Low-Speed Mode)

9.1.5.4 Spindle Driver Current Limit Circuit

This IC builds in the SPM current sense resistor which can select resistor value.

The spindle current limit circuit monitors motor current which flows through this resistance, and limits the output

current by reducing PWM duty when detecting over current conditions. Table 36 shows resistor value.

A limit current value can be calculated from following formulas.

Limit current = 196 mV / resistor value

(3)

Table 36. SPM Current Sense Resistor

SPM_RCOM_SEL[1:0] RESISTOR VALUE (Ω)

LIMIT CURRENT

(mA)

00

01

10

11

0.22

0.20

0.27

0.25

890

980

725

784

9.1.6 Sled Driver Part

9.1.6.1 Sled Channel Input versus Output PWM Duty

The Sled driver outputs the PWM pulse set as DAC code (VSLDx) with current feed back. The maximum output

is restricted to 440 mA at 0x7FF and 0x800. A dead band which output = 0 exists in the width of plus or minus

focusing on zero.

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Output Current

Reverse

Forward

440 mA

Dead Band

ISLEDxP = ISLEDxN

ISLEDxP< ISLEDxN

FE0h

ISLEDxP> ISLEDxN

1Fh

0

VSLDx[11:0]

800h

000

7FFh

Figure 51. Sled Output Current

Both outputs of SLED1/2 are L when input code is in dead band.

•

9.1.6.2 Sled End Detect Function

This device has the function of end position detection for Sled. By this function aim to eliminate the position

switch at PUH inner. When this function is enabled, internal logic will detect the sled out zero-cross point and at

that time, internal BEMF detect circuit measures the BEMF level of stepping motor. There are six threshold

levels. If BEMF is lower than selected threshold, device recognizes motor at stop and ENDDET bit to 1. ENDDET

bit will be cleared at the BEMF voltage exceed threshold again.

I-SLED1

I-SLED2

BEMF1

BEMF2

Motor Stop

1

ENDDET

Figure 52. Timing of Sled End Detection

•

In order to perform high-precision detection, the sled motor needs to generate higher BEMF voltage. BEMF

level depends on the stepping motor characteristic and its speed.

BEMF detection level is selectable 22, 46, 82, 105, 125, 145 mV.

If the drive speed changes, the timing which BEMF voltage generates will also change. In TPIC2040, detection

window can be adjusted to the optimal value by setting EDET_DELAY parameter. Delay time from the point

which polarity reverses and width of detection window are adjustable with EDET_DELAY.

Width

I-SLED 1/2

Delay

Figure 53. Timing of End Detection Window

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9.1.7 Load Driver Part

Load driver outputs the voltage with voltage feedback corresponding to the input DAC value. This channel has

power voltage compensation thus it is suit for Slot-in type load control. This channel becomes active exclusively

to other actuator channels. Load driver is shared with the TRK driver.

PWM Output Duty

Output (V)

6.0 V

5.0 V

100%

Dead Band

Duty = 0%

Load+ < Load–

Load+ > load–

0%

VLOAD[11:0]

800h

FE0h 000 1Fh

7FFh

Figure 54. Load Output Duty

•

Output voltage is controlled by PWM

Both LOAD+ and LOAD– are connected to PGND through the internal clamp diode respectively.

9.1.8 Focus/Track/Tilt Driver Part

PW M output duty

100%

P5V

reverse

forw ard

ACT+ < ACT-

ACT+ > ACT-

0%

800h

000

7FFh

ACT(FCS/TRK/TLT)[11:0]

Figure 55. FCS/TRK/TLT Output Duty

9.1.8.1 Differential Tilt Mode

TPIC2040 support differential Tilt mode which output the value calculated from Focus and Tilt. Focus and Tilt can

be set in differential mode by DIFF_TLT (REG74) = 1. Because Focus and Tilt are updated at the same time, the

update interval of Tilt can be thinned out. Output data changes at after writing VFCS data. Therefore it is

necessary to write VFCS data when set VTLT. In differential mode, the output value is calculated as follows.

FCS_OUT = (VFCS + VTLT) × 6

TLT_OUT = (VFCS – VTLT) × 6

(4)

(5)

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9.1.9 9-V LDO

TPIC2040 built in function a pre-driver for LDO. The required voltage beyond 1.2 V can be outputted on N-

channel FET by choosing external resistance. Arbitrary current can be supplied by selecting the external N-

channel FET according to required current capacity. LIN3VG output (= N-channel FET gate control) is controlled

to Feedback voltage LINFB is set as 1.215 V. The 22-nF capacitor for phase compensation is certainly installed.

And the division resistance for FB is chosen so that it may become less than 3K in total. The example of external

components shows Figure 56. The accuracy of output voltage depends for tolerance of resistance.

When not using LDO, it should be open LIN3VG and LINFB should be connected to 3.3 V with LIN3P3_DIS = 1.

5 V

NFET

ZXMN2B14

1.215 V

LIN3VG

3.3 V

4.7 kΩ

Compensation

22 nF (5%, 16 V)

10 nF

2.7 kΩ

Storage

0.1 .... 10.1 µF (10% 10 V)

LINFB

1kΩ(1%)

Total resistance (to GND) < 3 kΩ

Figure 56. Example Circuit of 3.3-V LDO

9.1.10 Monitor Signal on GPOUT

Able to output a specific signal to GPOUT pin. In order to output a signal, set a signal from REG6F by enabling

first and then enable GPOUT_ENA. When two or more signals are set for GPOUT, an output is as logical sum.

It is required to set both LIN3P3_DIS and GPOUT_ENA to 1.

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9.2 Typical Application

Load Motor

1

2

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

LOAD+

SLED2–

SLED2+

SLED1–

SLED1+

CSWO

10000 pF

LOAD–

10000 pF

3

PGND_1

SIOV

Sled Motor

CSW

4

3.3 V

SSZ

5

10 µF

SCLK

SIMO

SOMI

XMUTE

XFG

SCLK

SIMO

6

5 V

P5V_1

0.1 µF

10 µF

0.1 µF

7

5 V

10 µF

P5V_SPM

SOMI

8

W

3.3 V

Spindle Motor

33 kΩ

XFG

InterLock

READY

9

U

V

10

11

12

13

14

XRESET

CP1

PGND_SPM

MCOM

0.1 µF

PGND_2

5 V

CP2

CP3

TRK–

TRK+

FCS–

5 V

TRACKING

15 LIN3VG

22 nF

3.3 V

2.2 µF

16

17

18

19

LINFB/GPOUT

AGND/DGND

CV3P3

FOCUS

TILT

FCS+ 22

10 nF

TLT–

21

20

1 kΩ

0.1 µF

TLT+

P5V_2/A5V

5 V

0.1 µF

10 µF

Figure 57. Example of Application Circuit

Table 37. Pin Connection When Specific Function is

not Applied

FUNCTION

NUMBER

CONNECTION

LDO

LIN3VG

LINFB

15

16

Open

3.3 V (SIOV)

9.2.1 Design Requirements

To begin the design process, determine the following:

1. Motor configuration: The user can use all motor channels or some of them.

2. Power up devices with a 5-V supply.

9.2.2 Detailed Design Procedure

After power up on 5-V supply, the following values may be written to the following registers to enable motors.

1. Set WRITE_ENABLE = 1 on REG76 via SPI.

2. Set XSLEEP = 1 at REG70

3. Enable motor channel by ENA_XXX bits on REG70

4. Change the DAC settings for each motor in REG01-0B. Then, output channels will start driving load.

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Table 38. Recommended External Components

P5V_1

P5V_2

P5V_SPM

SIOV

TO

FUNCTION

Noise decoupling

VALUE (RATE)

10.0 (10%16 V)

1.0 (10%10 V)

UNIT

μF

PGND

CP2

Noise decoupling

μF

Noise decoupling

μF

Noise decoupling

μF

LOAD_P

LOAD_N

CP1

Prevent surge current

Charge pump capacitor

10000(10% 16 V)

0.1 (10% 16 V)

pF

µF

Charge pump capacitor (P5V

only, prohibit other power

supply)

CP3

P5V

0.1 (10% 16 V)

µF

9.2.3 Application Curves

120

100

80

60

40

20

0

120

100

80

60

FCS-

TLT-

40

FCS+

TLT+

20

0

-3000

-2000

-1000

0

1000

2000

3000

D001

-3000

-2000

-1000

0

1000

2000

3000

D002

DAC Code

Figure 58. DAC Code vs Duty Cycle for FCS Outputs

Figure 59. DAC Code vs Duty Cycle for TLT Outputs

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10 Power Supply Recommendations

All driver channels should be operated after the required power is supplied and stable.

The appropriate capacity of the decoupling capacitor requires a value over 10 μF to reduce the influence of PWM

switching noise. The P5V_1, P5V_2, and P5V_SPM pins must connect to 10-μF decoupling capacitors.

Current flow to the driver circuits takes both pattern-layout, line-impedance, and noise influence from the supply

line into consideration.

11 Layout

11.1 Layout Guidelines

1. CV3P3V requires an external capacitor. Because these are reference voltage for device, locate the capacitor

as close to device as possible. Keep away from noise sources.

2. TI recommends SCLK ground shielding.

3. LINFB is feedback pin for LDO. External divided resistors should be located closer to LINFB pin.

11.2 Layout Example

To MPU

To 3.3-V supply

To MPU

GPOUT

To MPU

XFG

RDY

SSZ

GND Shield

SCLK

To MPU

GND Shield

SIMO

SOMI

To MPU

SIOV

To MPU

To 3.3-V supply

Figure 60. Layout Recommendation

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12 器件和文档支持

12.1 器件支持

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

51

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对 TI 及其代理造成的任何损失。

在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特有的可满足适用

的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。

TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使用的特别协议。

只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同意，对并非指定面

向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独力负责满足与此类使用相关的所有

法律和法规要求。

TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要

求，TI不承担任何责任。

产品

应用

www.ti.com.cn/telecom

数字音频

www.ti.com.cn/audio

www.ti.com.cn/amplifiers

www.ti.com.cn/dataconverters

www.dlp.com

通信与电信

计算机及周边

消费电子

能源

放大器和线性器件

数据转换器

DLP® 产品

DSP - 数字信号处理器

时钟和计时器

接口

www.ti.com.cn/computer

www.ti.com/consumer-apps

www.ti.com/energy

www.ti.com.cn/dsp

工业应用

医疗电子

安防应用

汽车电子

视频和影像

www.ti.com.cn/industrial

www.ti.com.cn/medical

www.ti.com.cn/security

www.ti.com.cn/automotive

www.ti.com.cn/video

www.ti.com.cn/clockandtimers

www.ti.com.cn/interface

www.ti.com.cn/logic

逻辑

电源管理

www.ti.com.cn/power

www.ti.com.cn/microcontrollers

www.ti.com.cn/rfidsys

www.ti.com/omap

微控制器 (MCU)

RFID 系统

OMAP应用处理器

无线连通性

www.ti.com.cn/wirelessconnectivity

德州仪器在线技术支持社区

www.deyisupport.com

IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122

PACKAGE OUTLINE

DBT0038A

TSSOP - 1.2 mm max height

S

C

A

L

E

2

.

0

SMALL OUTLINE PACKAGE

SEATING

PLANE

6.55

6.25

TYP

C

A

0.1 C

PIN 1 INDEX AREA

38 X 0.5

38

1

2X

9

9.75

9.65

NOTE 3

19

B

20

0.23

38 X

0.17

4.45

1.2 MAX

0.1

C A B

4.35

NOTE 4

0.25

GAGE PLANE

0.15

0.05

(0.15) TYP

SEE DETAIL A

0.75

0.50

0 -8

A

20

DETAIL A

TYPICAL

4220221/A 05/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

www.ti.com

EXAMPLE BOARD LAYOUT

DBT0038A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

38 X (1.5)

SYMM

(R0.05) TYP

38

1

38 X (0.3)

38 X (0.5)

SYMM

19

20

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4220221/A 05/2020

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBT0038A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

38 X (1.5)

SYMM

(R0.05) TYP

38

1

38 X (0.3)

38 X (0.5)

SYMM

19

20

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4220221/A 05/2020

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122


型号：	TPIC2040
厂家：	TEXAS INSTRUMENTS
描述：	TPIC2040 用于 ODD 驱动、由串行接口控制的 7 通道电机驱动器电机驱动驱动器
文件：	总57页 (文件大小：944K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPIC2040 [TI]

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