TPIC9201N [TI]
MICROCONTROLLER POWER SUPPLY AND MULTIPLE LOW SIDE DRIVER IC; 微控制器电源和多低侧驱动IC
| 型号： | TPIC9201N |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MICROCONTROLLER POWER SUPPLY AND MULTIPLE LOW SIDE DRIVER IC |
| 文件： | 总11页 (文件大小：394K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPIC9201N
www.ti.com
SLIS115–JULY 2005
MICROCONTROLLER POWER SUPPLY AND MULTIPLE LOW SIDE DRIVER IC
FEATURES
Microcontroller
•
Eight Low-Side Drivers With Internal Clamp
for Inductive Loads and Current Limiting for
Self Protection
•
Programmable Power On Reset Delay Before
RST is Asserted High, Once the 5 V is Within
Specified Range (Typically 6 ms)
– Seven Outputs are Rated at 150 mA and
Controlled Through the Serial Interface
•
•
•
Programmable De-glitch Timer Before nRST is
Asserted Low (typically 40 µs)
– One Output Rated at 150 mA and is
Controlled Through Serial and/or Parallel
Input
Zero Voltage Detection Signal With Built in
Filter of 20 µs
Thermal Shutdown for Self Protection
•
•
•
5-V ±5% Regulated Power Supply With
200-mA Load Capability at VIN Max of 18 V
APPLICATIONS
•
•
•
AC Unit
Washing Machines
Refrigeration Systems
Internal Voltage Supervisory for the Regulated
Output
Serial Communications for Control of Eight,
Low Side Drivers
•
•
Enable/Disable Input for Out1
5 V or 3.3 V, I/O Tolerant for Interface to
DESCRIPTION
The ac-unit power supply with low side drive output provides regulated 5-V output to power the system
microcontroller and drive up to eight inductive and/or resistive loads. The ac zero detect circuitry is monitoring the
cross-over voltage of the mains ac supply. The resultant signal is a low frequency clock output on the ZVS
terminal based on the ac line cycle. This information allows the microcontroller to reduce inrush current by
powering loads on the ac-line peak voltage.
A serial communications interface controls the eight low side outputs; each output has an internal snubber circuit
to absorb the energy in the inductor at turn OFF. Alternatively, the system can place a fly-back diode to VIN to
help recirculate the energy in an inductive load at turn OFF.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the forma-
Copyright © 2005, Texas Instruments Incorporated
tive or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.
TPIC9201N
www.ti.com
SLIS115–JULY 2005
PIN OUT CONFIGURATION
PIN NO.
PIN LABEL
ZVS
I/O
O
O
O
O
O
O
O
O
O
I
DESCRIPTION
1
2
Zero Voltage Synchronization
Low side Output #1
Out1
Out2
Out3
Out4
Out5
Out6
Out7
Out8
GND
GND
EN1
3
Low side Output #2
4
Low side Output #3
5
Low side Output #4
6
Low side Output #5
7
Low side Output #6
8
Low side Output #7
9
Low side Output #8
10(1)
11(1)
12
13
14
15
16
17
18
19
20
IC Ground
I
IC Ground
I
Enable/disable for Out1
Power up reset delay
Power On Reset output (open drain, active low)
Sesrial data input
Rdelay
RST
O
O
I
MOSI
NCS
I
Chip select
SCLK
5Vout
VIN
I
Serial clock for data synchronization
Regulated output
O
I
Unregulated Input voltage source
AC zero detect input
SYN
I
(1) Terminals 10 and 11 are internally fused in the lead frame for the 20-pin PDIP package.
2
TPIC9201N
www.ti.com
SLIS115–JULY 2005
IC FUNCTIONAL BLOCK
Out1
EN1
Enables
Out1
Out1
Enable
Out1 @
150 mA
Gate Control
for Outputs
1 Through 8
Out2
Out2
Out2 @150 mA
Out3
Out4
Out5
Out6
Out7
Out8
NCS
Out3 @150 mA
Out4 @150 mA
Out5 @150 mA
Out6 @150 mA
Out7 @150 mA
Out8 @150 mA
Out3
Out4
Out5
Out6
Out7
Out8
NCS
Parallel
Register
SCLK
Serial
SCLK
Register
MOSI
MOSI
V
IN
R
10 V
7V-18V
PMOS
5Vout
Gate Drive
and Control
Optional, dependent
on heat management
implementation
5 V
Bandgap
Ref
Comp
–
GND
+
Vref
GND
5 kÙ
Voltage
Supervisor
RST
Vref
GND
GND
I
const
R
delay
R
delay
20 ìs filter
ZVS
S
SYN
500 kÙ
25 kÙ
ZVS
Q
Syn i/p
10 kÙ
R
100 kÙ
B0036-01
The value R is chosen based on maximum 5-V out load and minimum operating voltage desired. The Zener on
the VIN line helps limit the excess power dissipation within the IC when the operating voltage exceeds 10 V
(starts conducting). For 12-V to 7-V operating input, the resistor and Zener are NOT required.
3
TPIC9201N
www.ti.com
SLIS115–JULY 2005
DESCRIPTION OF THE FUNCTION
The 5-V regulator is powered from the VIN line; the regulated output will be within 5 V ±5% over the operating
conditions. The power on reset line (open drain) remains low until the regulator exceeds the set threshold and
the timer value set by the capacitor on reset delay line expires. If both of these conditions are satisfied the POR
line is asserted high. This signifies to the microcontroller that serial communications can be initiated to the IC.
The serial communications will be an 8-bit format; with data transfer synchronized using a serial clock from the
microcontroller. A single register controls ALL the outputs (1-bit per output). The default value will be zero (OFF).
If an output requires PWM function the register will have to be update at a rate faster than the desired PWM
frequency. Out1 can be controlled by serial input bit OR the parallel input signal from EN1. The terminal will have
an internal pulldown for disabling the output (Out1) in the event there is an open on this terminal.
The SYN input translates the image of the mains voltage through the secondary of the transformer. The SYN
input has a resistor to protect from high currents into the IC. The zero voltage synchronization output translates
the ac-line cycle frequency into a low frequency clock, which can be used for a timing reference and help power
loads on the ac-line peak voltage (to reduce inrush currents).
If reset is asserted ALL outputs are turned OFF internally and the input register is reset to ALL zeroes. The
microcontroller will have to write to the register to turn the outputs ON again.
ABSOLUTE MAXIMUM RATINGS(1)(2)
VIN
Unregulated input(3)(4)
Unregulated input(3)(4)
Logic inputs(3)(4)
24 V
24 V
SYN
EN1, MOSI, SCLK, and NCS
7 V
(4)
RST and Rdelay
See (3) and
7 V
OUT(1:8)
θJC
Low side outputs
20 V
Thermal impedance junction-to-case(5)
Thermal impedance junction-to-ambient(5)
Continuous power dissipation
Electrostatic discharge(6)
67°C/W
137°C/W
0.912 W
2 kV
θJA
PD
ESD
TOP
Operating ambient temperature range
Storage temperature range
–40°C to 85°C
–65°C to 125°C
260°C
TS
TLEAD
Lead temperature (Soldering, 10 sec)
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Absolute negative voltage on these pins not to go below -1 V
(3) All voltage values are with respect to GND.
(4) Absolute negative voltage on these pins not to go below -0.5 V
(5) The thermal data is based on using 2 oz copper trace with at least four square inches of copper footprint for heat dissipation.
(6) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
DISSIPATION RATINGS
TC ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TC = 25°C
TC = 85°C
POWER RATING
PACKAGE
N
912.4 mW
7.3 mW/°C
474 mW
RECOMMENDED OPERATING CONDITIONS
MIN
7
NOM
MAX
18
UNIT
VIN
Unregulated input
SYN
V
0
15
EN1, RST, and Rdelay
Logic level (I/O)
0
5.25
5.25
85
V
MOSI, SCLK, and NCS
0
TOP
Operating ambient temperature range
–40
°C
4
TPIC9201N
www.ti.com
SLIS115–JULY 2005
ELECTRICAL CHARACTERISTICS
TA = –40°C to 85°C, VIN = 7 V to 18 V (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE AND CURRENT
VIN
Input voltage
(1)7
18
3
V
Enable = ON, Out1–8 = OFF
Enable = ON, Out1–8 = ON
IVIN
Input supply current
mA
5
LOGIC INPUT (MOSI, NCS, SCLK, and ENS)
VIL
Logic input low level
Logic input high level
IIL = 100 mA
IIL = 100 mA
0.8
V
VIH
2.4
RESET (RST)
VOL
VOH
VH
Logic level output
IOL = 1.6 mA
0.4
4.5
V
V
V
V
V
Logic level output
5-kΩ pullup to VCC
5-V reg ramps up
5-V ramps down
VCC– 0.8
Disabling reset threshold
Enabling reset threshold
Threshold hysteresis
4.25
3.75
0.5
VL
3.3
0.3
VHYS
RESET DELAY (Rdelay
)
IOUT
28
6
µA
ms
µs
TDW
TUP
Reset delay timer
C = 47 nF
C = 47 nF
1
Reset capacitor to low level
45
OUTPUT (OUT1 through OUT8)
VOL
IOH
Output ON
IOUT(x) = 150 mA
VOH = VIN
0.7
2
V
Output leakage
Output current limit
µA
mA
ILIMIT
OUT(X) = ON and shorted to VIN with low
impedance
350
REGULATOR OUTPUT (5Vout)
5Vout
Output supply
I5Vout = 5 mA to 200 mA, VIN = 7 V to 18 V
C5Vout = 1 µF
4.75
200
5
5.25
V
I5Vout limit
Output short circuit current
5 V = 0 V
mA
THERMAL SHUTDOWN
ISD
Thermal shutdown
Hysteresis
170
20
°C
°C
tHYS
ZERO VOLTAGE SYNCHRONIZATION (ZVS)
VSYNTH
ISYN
tD
Transition threshold
0.4
10
0.6
30
0.9
2
V
Input activating current
Transition filtering time
RZV = 10 kΩ and VSYN = 24 V
mA
µs
VTF = VCC rising and falling step
70
(1) There will be external high frequency noise suppression capacitors and filter capacitor on the VIN
.
OUTPUT CONTROL REGISTER
MSB
LSB
IN8
0
IN7
0
IN6
0
IN5
0
IN4
0
IN3
0
IN2
IN1
0
0
INX = 0; Output OFF
INX = 1; Output ON
5
TPIC9201N
www.ti.com
SLIS115–JULY 2005
To operate the output in a PWM mode the output control register has to be updated at a rate 2X the desired
PWM frequency of the output. Maximum PWM frequency is 5 kHz. The register is updated every 100 ms.
SERIAL COMMUNICATIONS INTERFACE
The serial communications will be an 8-bit format; with data transfer synchronized using a serial clock from the
microcontroller. A single register controls all the outputs. The signal gives the instruction to control the output of
TPIC9201N.
Signal NCS enables the SCLK and MOSI data when it is low. After NCS is set to low for T1, synchronization
clock and data begin to transmit and after the 8-bit data has been transmitted, NCS will be set to high again to
disable SCLK and MOSI and transfer the serial data to the control register. SCLK must be held low when NCS is
in the high state.
T2
T3
T8
T1
T4
T5
T1
NCS
SCLK
1
2
3
4
5
6
7
8
MSB
LSB
MOSI
XXX
IN8
IN7
IN6
IN5
IN4
IN3
IN2
IN1
T6
T7
T0054-01
6
TPIC9201N
www.ti.com
SLIS115–JULY 2005
TIMING REQUIREMENTS
TA = –40°C to 85°C, VIN = 7 V to 18 V (unless otherwise stated)
PARAMETER
MIN
TYP
MAX
UNIT
mHz
ns
FSPI
T1
T2
T3
T4
T5
T6
T7
T8
SPI frequency
4
Time from NCS falling edge to CLK rising edge
Time from NCS falling edge to CLK falling edge
Time for CLK to go high
10
80
ns
60
ns
Time for CLK to go low
60
ns
Time from last CLK falling edge to NCS rising edge
SDI setup time before CLK edge
SDI hold time after CLK edge
80
ns
10
ns
10
ns
Time between two words for transmitting
170
ns
RDELAY
THe RDELAY output provides a constant current source to charge an external capacitor to approximately 6.5 V.
The external capacitor is selected to provide a delay time based on the current equation for a capacitor, I = C
dv/dt and a 28 µA typical output current.
Therefore, the user should select a 47-nF capacitor to provide a 6 ms delay at 3.55 V.
I = C dv/dt
28 µA = C × (3.55 V / 6 ms)
C = 47 nF
7
TPIC9201N
www.ti.com
SLIS115–JULY 2005
APPLICATION INFORMATION
APPLICATIONS
1. Buzzer Driver
MOSI
2. Relay Driver
3. Relay Driver
4. Relay Driver
5. Relay Driver
6. Fan Driver
7. Fan Driver
8. Fan Driver
SCLK
MCU/DSP
NCS
8 Outputs
ZVS
TPIC9201N
20-Pin PDIP
RST
5Vout ±5% @ 150 mA
SYN, (AC Zero-Cross
Detect Input)
EN1
Reset Delay
DC Input 7 V to 18 V
GND (2´)
B0037-01
WASHING MACHINE APPLICATION
Display
(LED/LCD/VFD)
Key Pad
Water
Filters
AC
Supply
Valve
Water
Outlet
Softener
Supply
Volume
Sensor
M
Power
Switch
Water Level
Sensor
Controller
Driver
Optical
Sensor
SYN
SYN
Zero-Cross
Detection
Temperature
Sensor
Vout
Regulator
(Optional)
+
RST
~
~
POR/SYS
-
Cover
Switch
Appliance IC
B0038-01
8
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jul-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TPIC9201N
PREVIEW
PDIP
N
20
20
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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Products
Applications
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Amplifiers
amplifier.ti.com
www.ti.com/audio
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dataconverter.ti.com
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www.ti.com/automotive
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dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
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Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
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Security
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microcontroller.ti.com
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www.ti.com/wireless
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