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TPL0102-EP

SLIS149 –JUNE 2014

TPL0102-EP 256-Taps Dual-Channel Digital Potentiometer With Non-Volatile Memory

1 Features

2 Applications

1

•

Dual-Channel, 256-Position Resolution

Non-Volatile Memory Stores Wiper Settings

2-mm × 2-mm, 14-Pin TSSOP Package

100-kΩ End-to-End Resistance (TPL0102-100)

•

Adjustable Gain Amplifiers and Offset Trimming

Adjustable Power Supplies

Precision Calibration of Set Point Thresholds

Sensor Trimming and Calibration

Fast Power-Up Response Time to Wiper Setting:

<100 µs

Mechanical Potentiometer Replacement

3 Description

•

±0.5 LSB INL, ±0.25 LSB DNL (Voltage-Divider

Mode)

The TPL0102-EP is a two-channel, linear-taper digital

potentiometer with 256 wiper positions. Each

potentiometer can be used as a three-terminal

potentiometer or as a two-terminal rheostat. The

TPL0102-EP-100 has an end-to-end resistance of

100 kΩ.

•

4 ppm/°C Ratiometric Temperature Coefficient

I²C-Compatible Serial Interface

2.7- to 5.5-V Single-Supply Operation

±2.25 to ±2.75 V Dual-Supply Operation

The

TPL0102-EP

has

non-volatile

memory

Operating Temperature Range From

–40°C to 125°C

(EEPROM) which can be used to store the wiper

position. The internal registers of the TPL0102-EP

can be accessed using the I²C interface.

•

ESD Performance Tested Per JESD 22

–

2000-V Human Body Model

(A114-B, Class II)

The TPL0102-EP is available in a 14-pin TSSOP

package with a specified temperature range of –40°C

to 125°C.

Supports Defense, Aerospace, and Medical

Applications

Device Information⁽¹⁾

–

Controlled Baseline

ORDER NUMBER

PACKAGE

BODY SIZE (NOM)

One Assembly and Test Site

One Fabrication Site

TPL0102-

100QPWREP

TSSOP (14)

5.00 mm × 4.40 mm

Available in Extended (Q) Temperature –40°C

to 125°C

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

–

Extended Product Life Cycle

Extended Product-Change Notification

Product Traceability

4 Functional Block Diagram

A0 A1 A2

VDD

VSS

HA

HB

SCL

VOLATILE

I²C INTERFACE

WA

REGISTERS

SDA

WB

NON-VOLATILE

REGISTERS

GND

LA

LB

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPL0102-EP

SLIS149 –JUNE 2014

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Table of Contents

8.1 Overview ................................................................. 12

8.2 Functional Block Diagram ....................................... 12

8.3 Feature Description................................................. 13

8.4 Device Functional Modes........................................ 22

8.5 Register Maps......................................................... 23

Application and Implementation ........................ 26

9.1 Application Information............................................ 26

9.2 Typical Application ................................................. 26

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Functional Block Diagram .................................... 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 Handling Ratings....................................................... 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Operating Characteristics.......................................... 8

7.7 Timing Requirements................................................ 9

7.8 Typical Characteristics............................................ 10

Detailed Description ............................................ 12

9

10 Layout................................................................... 27

10.1 Layout Example .................................................... 27

11 Device and Documentation Support ................. 29

11.1 Trademarks........................................................... 29

11.2 Electrostatic Discharge Caution............................ 29

11.3 Glossary................................................................ 29

12 Mechanical, Packaging, and Orderable

Information ........................................................... 29

8

5 Revision History

DATE

REVISION

NOTES

June 2014

*

Initial release.

2

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6 Pin Configuration and Functions

TSSOP – PW Package

14 Pins

(Top View)

1

2

3

4

5

6

7

14

13

12

11

10

9

VDD

A0

HA

LA

A1

WA

HB

LB

GND

SCL

SDA

WB

A2

8

VSS

Pin Functions

I/O

DESCRIPTION

NAME

HA

NO.

1

I/O

I

High pin of potentiometer A

Low pin of potentiometer A

Wiper pin of potentiometer A

High pin of potentiometer B

Low pin of potentiometer B

Wiper pin of potentiometer B

Address bit 2

LA

2

WA

HB

3

4

LB

5

WB

A2

6

7

VSS

SDA

SCL

GND

A1

8

Power

I/O

I

Negative or GND power supply pin

I²C data I/O

I²C clock input

9

10

11

12

13

14

—

Ground

I

Address bit 1

A0

I

Address bit 0

VDD

Power

Positive power supply pin

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7 Specifications

7.1 Absolute Maximum Ratings^(1)(2)(3)

MIN

–0.3

–7

MAX

7

UNIT

V

V_DDto GND

V_SSto GND

V_DDto V_SS

V_H, V_L, V_W

V_I

Supply voltage

0.3

7

V

Voltage at resistor pins

Digital input voltage

Pulse current

V_SS– 0.3 V_DD+ 0.3

V

–0.3 V_DD+ 0.3

V

±20

±2

mA

I_H, I_L, I_W

Continuous current

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.

(3) All voltages are with respect to ground, unless otherwise specified.

7.2 Handling Ratings

MIN

MAX

UNIT

T_stg

Storage temperature range

–65

150

°C

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

5.5

UNIT

Single supply operation (V_SS= 0 V)

2.7

±2.25

V_SS

V_DD, V_SS

V

Dual supply operation

±2.75

V_DD

V_H, V_L

V_IH

V_IL

Pin voltage

V

Voltage input high (SCL, SDA, A0, A1, A2)

Voltage input low (SCL, SDA, A0, A1, A2)

Wiper current

0.7 × V_DD

0

5.5

0.3 × V_DD

±2

V

I_W

mA

°C

T_J

Junction temperature

–40

125

4

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7.4 Thermal Information

TPL0102-EP

PW

THERMAL METRIC⁽¹⁾

UNIT

14 PINS

112.9

39.9

R_θJA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

R_θJC(top)

R_θJB

55.9

°C/W

ψ_JT

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

3.5

ψ_JB

55.2

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

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7.5 Electrical Characteristics

V_DD= 2.7 to 5.5 V, V_SS= 0 V, V_H= V_DD, V_L= GND, T_J= –40°C to 125°C (unless otherwise noted). Typical values are at

V_DD= 5 V, T_J= 25°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

End-to-end resistance

(Between H and L pins)

R_TOT

TPL0102-100

80

100

120

kΩ

R_H, R_L

R_W

Pin resistance

60

25

22

16

200

120

Ω

Wiper resistance

Pin capacitance

Wiper capacitance

(1)(2)

C_H, C_L

pF

(1)(2)

C_W

V_H= V_SSto V_DD, V_L= Floating

or

I_LKG

Pin leakage current

0.1

1

µA

V_L= V_SSto V_DD, V_H= Floating

Resistance temperature

coefficient

TC_R

Input Code = 0x80h

92

ppm/°C

%

Channel-to-channel resistance

match

R_TOT,MATCH

0.1

VOLTAGE DIVIDER MODE

INL⁽³⁾⁽⁴⁾

DNL⁽³⁾⁽⁵⁾

ZS_ERROR

FS_ERROR

Integral non-linearity

–0.5

–0.25

0

0.5

0.25

2

LSB

Differential non-linearity

Zero-scale error

(6)(7)

(6)(8)

0.1

Full-scale error

–2

–0.1

0

Wiper at the same tap position, same voltage

at all H and same voltage at all L pins

(6)(9)

V_MATCH

TC_V

Channel-to-channel matching

–2

2

LSB

Ratiometric temperature

coefficient

Wiper set at mid-scale

4

ppm/°C

Wiper set at

BW

Bandwidth

TPL0102-100

midscale

C_LOAD= 10 pF

229

3.6

kHz

µS

%

T_SW

THD

Wiper setting time

Total harmonic distortion

V_H= 1 V_RMSat 1 kHz,

V_L= (V_DD– V_SS)/2,

Measurement at W

TPL0102-100

0.03

ƒ_H= 1 kHz,

X_TALK

Crosstalk

V_L= GND,

–82

dB

Measurement at W

(1) Pin and wiper capacitance extracted from self admittance of three port network measurement

I

i

Y =

ii

V_k=0 for k¹i

V

i

(2) Digital Potentiometer Macromodel

H

C_H

R

TOTAL

W

C_W

C_L

L

(3) LSB = (V_{MEAS[code 255]}– V_{MEAS[code 0]}) / 255

(4) INL = ((V_{MEAS[code x]}– V_{MEAS[code 0]}) / LSB) – [code x]

(5) DNL = ((V_{MEAS[code x]}– V_{MEAS[code x-1]}) / LSB) – 1

(6) IDEAL_LSB = (V_H– V_L) / 256

(7) ZS_ERROR= V_{MEAS[code 0]}/ IDEAL_LSB

(8) FS_ERROR= [(V_{MEAS[code 255]}– (V_H– V_L)) / IDEAL_LSB] + 1

(9) V_MATCH= (V_{MEAS_A[code x]}– V_{MEAS_B[code x]}) / IDEAL_LSB

6

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Electrical Characteristics (continued)

V_DD= 2.7 to 5.5 V, V_SS= 0 V, V_H= V_DD, V_L= GND, T_J= –40°C to 125°C (unless otherwise noted). Typical values are at

V_DD= 5 V, T_J= 25°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

RHEOSTAT MODE (Measurements between W and L with H not connected, or between W and H with L not connected)

RINL^(10)(11)

RDNL^(10)(12)

Integral non-linearity

Differential non-linearity

Offset

–1

–0.5

0

1

0.5

2

LSB

(13)(14)

R_OFFSET

0.2

54

(13)(15)

R_MATCH

RBW

Channel-to-channel matching

–2

2

Code = 0x00h,

L Floating,

Input applied to W, Measure

at H, C_LOAD= 10 pF

Bandwidth

TPL0102-100

kHz

(10) RLSB = (R_{MEAS[code 255]}– R_{MEAS[code 0]}) / 255

(11) RINL =( (R_{MEAS[code x]}– R_{MEAS[code 0]}) / RLSB) – [code x]

(12) RDNL =( (R_{MEAS[code x]}– R_{MEAS[code x-1]}) / RLSB ) – 1

(13) IDEAL_RLSB = R_TOT/ 256

(14) R_OFFSET= R_{MEAS[code 0]}/ IDEAL_RLSB

(15) R_MATCH= (R_{MEAS_A[code x]}– R_{MEAS_B[code x]}) / IDEAL_RLSB

100

10

1

85

95

105

Operating Junction Temperature (ºC)

115

125

C020

(1) See data sheet for absolute maximum and minimum recommended operating conditions.

(2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect

life).

(3) Enhanced plastic product disclaimer applies.

Figure 1. TPL0102-EP Electromigration Fail Mode/Wirebond Life Derating Chart

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7.6 Operating Characteristics

V_DD= 2.7 to 5.5 V, V_SS= 0 V, V_H= V_DD, V_L= GND, T_J= –40°C to 125°C (unless otherwise noted). Typical values are at

V_DD= 5 V, T_J= 25°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

1.5

1

UNIT

–40°C

25°C

0.2

V_DD= 2.75 V, V_SS= –2.75 V,

I²C interface in standby mode

I_DD(STBY)

V_DDstandby current

µA

125°C

–40°C

25°C

16

–1.5

–1

–0.2

0.2

V_DD= 2.75 V, V_SS= –2.75 V,

I²C interface in standby mode

I_SS(STBY)

V_SSstandby current

V_DDshutdown current

V_SSshutdown current

µA

125°C

–40°C

25°C

–16

1.5

1

V_DD= 2.75 V, V_SS= –2.75 V,

I²C interface in standby mode

I_DD(SHUTDOWN)

125°C

–40°C

25°C

16

–1.5

–1

–0.2

V_DD= 2.75 V, V_SS= –2.75 V,

I²C interface in standby mode

I_SS(SHUTDOWN)

125°C

–16

I_DD

I_SS

V_DDcurrent during non-volatile write V_DD= 2.75 V, V_SS= –2.75 V

350

1

µA

V_SScurrent during non-volatile write

V_DD= 2.75 V, V_SS= –2.75 V

-350

–1

Digital pins leakage current (A0, A1,

A2, SDA, and SCL)

I_LKG-DIG

V_POR

µA

V

Power-on recall voltage

Minimum V_DDat which memory recall occurs

2

EEPROM SPECIFICATION

EEPROM endurance

1000

100000

20

Cycles

Hours

ms

EEPROM retention

t_WC

Non-volatile write cycle time

WIPER TIMING CHARACTERISTICS

t_WRT

Wiper response time

SCL falling edge of last bit of wiper data byte to wiper

new position

600

800

ns

t_SHUTDOWNREC

Wiper position recall time from shut- SCL falling edge of last bit of ACR data byte to wiper

down mode

stored position and H connection

t_D

Power-up delay

V_DDabove V_POR, to wiper initial value register recall

completed, and I²C interface in standby mode

35

7

100

5.5

µs

pF

C_IN

Pin capacitance

A0, A1, A2, SDA SCL pins

I²C INTERFACE SPECIFICATIONS

V_IH

Input high voltage

0.7 ×

V_DD

V

V_IL

Input low voltage

0.3 ×

V_DD

0

V_OL

C_IN

Output low voltage

Pin capacitance

SDA pin, I_OL= 4 mA

0.4

V

A0, A1, A2, SDA SCL pins

7

pF

8

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7.7 Timing Requirements

V_DD= 2.7 to 5.5 V, V_SS= 0 V, V_H= V_DD, V_L= GND, T_J= –40°C to 125°C (unless otherwise noted). Typical values are at

V_DD= 5 V, T_J= 25°C (unless otherwise noted).

STANDARD MODE I²C BUS

FAST MODE I²C BUS

UNIT

MIN

MAX

MIN MAX

I²C INTERFACE TIMING REQUIREMENTS

ƒ_SCL

t_SCH

t_SCL

t_sp

I²C clock frequency

I²C clock high time

I²C clock low time

I²C spike time

I²C serial data setup time

I²C serial data hold time

I²C input rise time

0

4

100

50

0

0.6

1.3

0

400 kHz

µs

4.7

0

50

ns

µs

t_SDS

t_SDH

t_ICR

t_ICF

250

0

100

0

(1)

1000

300

20 + 0.1C_b

300

I²C input fall time

20 + 0.1C_b

(1)

t_ICF

I²C output fall time, 10- to 400-pF bus

I²C bus free time between stop and start

I²C start or repeater start conditions setup time

I²C start or repeater start condition hold time

I²C stop condition setup time

300

20 + 0.1C_b

t_BUF

t_STS

t_STH

t_SPS

4.7

4

1.3

0.6

4

t_VD(DATA)Valid data time, SCL low to SDA output valid

1

t_VD(DATA)Valid data time of ACK condition, ACK signal from

SCL low to SDA (out) low

(1) C_b= total capacitance of one bus line in pF

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7.8 Typical Characteristics

6

5

0.0

±0.5

±1.0

±1.5

±2.0

±2.5

4

3

2

1

0

±1

±2

IDD(STBY) Current

ISS(STBY) Current

0

20

40

60

80

100

120

±40

±20

0

20

40

60

80

100

120

±40

±20

Free-Air Temperature (C)

C001

C002

Figure 2. IDD Standby Current vs Temperature

Figure 3. ISS Standby Current vs Temperature

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

±0.2

0.0

±0.5

±1.0

±1.5

±2.0

±2.5

IDD(SHUTDOWN) Current

ISS(SHUTDOWN) Current

0

20

40

60

80

100

120

0

20

40

60

80

100

120

±40

±20

±40

±20

Free-Air Temperature (C)

C003

C004

Figure 4. IDD Shutdown Current vs Temperature

Figure 5. ISS Shutdown Current vs Temperature

0.17

0.16

0.15

0.14

0.13

0.12

0.11

0.10

±0.145

±0.150

±0.155

±0.160

±0.165

±0.170

0

20

40

60

80

100

120

0

20

40

60

80

100

120

±40

±20

±40

±20

Free-Air Temperature (C)

C005

C006

Figure 6. IDD Current (Non-Volatile Write) vs Temperature

Figure 7. ISS Current (Non-Volatile Write) vs Temperature

10

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Typical Characteristics (continued)

90

80

70

60

50

40

30

20

10

2.7 V

5.5 V

2.7 V

5.5 V

80

70

60

50

40

30

20

10

0

20

40

60

80

100

120

0

20

40

60

80

100

120

±40

±20

±40

±20

Free-Air Temperature (C)

C007

Figure 8. Wiper Resistance (RW) vs Temperature

Figure 9. End-to-End Resistance (Between H and L Pins) vs

Temperature

0.32

0.28

0.24

0.20

0.16

0.12

0.08

0.04

±0.40

±0.50

±0.60

±0.70

±0.80

±0.90

±1.00

2.7 V

5.5 V

2.7 V

5.5 V

0

20

40

60

80

100

120

0

20

40

60

80

100

120

±40

±20

±40

±20

Free-Air Temperature (C)

C009

C010

Figure 10. Zero-Scale Error vs Temperature

Figure 11. Full-Scale Error vs Temperature

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

2.7 V

5.5 V

0

20

40

60

80

100

120

±40

±20

Free-Air Temperature (C)

C011

Figure 12. Offset vs Temperature

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8 Detailed Description

8.1 Overview

The TPL0102-EP is a two-channel, linear-taper digital potentiometer with 256 wiper positions. Each

potentiometer can be used as a three-pin potentiometer or as a two-pin rheostat. The TPL0102-EP-100 has an

end-to-end resistance of 100 kΩ.

The TPL0102-EP has non-volatile memory (EEPROM) which can be used to store the wiper position. When the

device is powered down, the last value stored in the IVR register will be maintained in the non-volatile memory.

When power is restored, the contents of the IVR register are recalled and loaded into the corresponding WR

register to set the wipers to the initial position. The internal registers of the TPL0102-EP can be accessed using

the I²C interface.

The position of the wiper pin is controlled by the value in the WR 8-bit register. When the WR contains all zeroes,

the wiper pin W is closest to its L (low) pin. As the value of the WR increases from all zeroes to all ones (255

decimal), the wiper moves monotonically from the position closest to L to the position closest to H. At the same

time, the resistance between W and L increases monotonically, whereas the resistance between W and H

decreases monotonically.

8.2 Functional Block Diagram

A0 A1 A2

VDD

VSS

HA

HB

SCL

SDA

VOLATILE

I²C INTERFACE

WA

REGISTERS

WB

NON-VOLATILE

REGISTERS

GND

LA

LB

12

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8.3 Feature Description

Table 1. Summary of Features

Feature

Number of potentiometers

TPL0102-EP

2

I²C

Digital interface

Steps

256

Wiper memory

Taper

Non-volatile

Linear

100 kΩ

20%

End-to-end resistance

End-to-end resistance tolerance

Wiper resistance

25 Ω (typ)

8.3.1 Potentiometer Pin Description

8.3.1.1 HA, HB, LA, LB

The high (HA, HB) and low (LA, LB) pins of the TPL0102-EP are equivalent to the fixed pins of a mechanical

potentiometer. The H and L pins do not have any polarity restrictions, i.e. H can be at a higher voltage than L, or

L can be at a higher voltage than H. The WA and WB pins are the wipers and equivalent to the movable pin of a

mechanical potentiometer. The position of the wiper is set using the WR register. With the WR register set to 255

decimal, the wiper is closest to the H pin, and with the WR register set to 0, the wiper is closest to the L pin.

8.3.1.2 SDA, SCL

SDA is a bi-directional serial data input/output pin for I²C communication. SDA is an open drain output and

requires an external pull-up resistor.

SCL is the serial clock input for I²C communication. SCL requires an external pull-up resistor.

8.3.1.3 A0, A1, A2

These inputs are used to set the last three bits of the I²C address of the device. By using different values for A0,

A1, A2, up to eight TPL0102-EP devices can be used on the same I²C bus.

From Processor to DPOT

From DPOT to Processor

I²C Write to A Register

Address (1010_ _ _)

Start

0

Ack

Register Addr

DataN

Ack

Stop

Ack

Data1

I²C Read From A Register

Address (1010_ _ _)

Start

0

1

Ack

Register Addr

Ack

reStart

Ack

Address (1010_ _ _)

First Read Data Byte

Ack

noAck

Last Read Data Byte

Stop

Figure 13. I²C Interface

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The following is a sample sequence to set wipers of both potentiometers at mid-scale. Assume A0, A1, and A2

are 0 and device has just been powered up.

From Processor to DPOT

From DPOT to Processor

Method 1: First Write 0x80 to IVRA and then write 0x80 to IVRB Register

Address (1010000b)

IVRA Register (0x00h)

Start

0

Ack

Data (0x80)

Ack

Stop

Address (1010 000b)

IVRB Register (0x01h)

Start

0

Ack

Data (0x80h)

Ack

Stop

Method 2: Perform a multi byte write to IVRA and IVRB Register

Address (1010000b)

IVRA Register (0x00h)

Start

0

Ack

Data (0x80h)

Ack

Data (0x80h)

Ack

Stop

Data written to Register 0x00h

Data written to Register 0x01h

Figure 14. tI²C Interface Example

8.3.2 Standard I²C Interface Details

The bidirectional I²C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be

connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

I²C communication with this device is initiated by the master sending a start condition, a high-to-low transition on

the SDA input/output while the SCL input is high (see Figure 15). After the start condition, the device address

byte is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call

address. After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output

during the high of the ACK-related clock pulse

Figure 15. Definition of Start and Stop Conditions

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The data byte follows the address ACK. The R/W bit is kept low for transfer from the master to the slave. The

data byte is followed by an ACK sent from this device. Data are output only if complete bytes are received and

acknowledged. The output data is valid at time (tpv) after the low-to-high transition of SCL, during the clock cycle

for the ACK. On the I²C bus, only one data bit is transferred during each clock pulse. The data on the SDA line

must remain stable during the high pulse of the clock period, as changes in the data line at this time are

interpreted as control commands (start or stop) (see Figure 16).

Figure 16. Bit Transfer

A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 15).

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not

limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the

receiver can send an ACK bit.

A slave receiver that is addressed must generate an ACK after the reception of each byte. The device that

acknowledges has to pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during

the high pulse of the ACK-related clock period (see Figure 17). Setup and hold times must be taken into account.

Figure 17. Acknowledgment on the I²C Bus

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8.3.3 Ideal Resistance Values

H

R_HW

R_WL= R_TOTx D/256

R_TOT

W

R_HW= R_TOTx (1 –(D/256))

R_WL

Where D = Decimal Value of Wiper Code

L

Figure 18.

Table 2 shows the ideal values for DPOT with end-to-end resistance of 100 kΩ. The absolute values of

resistance can vary significantly, but the ratio (R_WL/ R_HW) is extremely accurate.

Table 2.

Step

0

Binary

0

R_WL(kΩ)

0.00

0.39

0.78

1.17

1.56

1.95

2.34

2.73

3.13

3.52

3.91

4.30

4.69

5.08

5.47

5.86

6.25

6.64

7.03

7.42

7.81

8.20

8.59

8.98

9.38

9.77

10.16

10.55

10.94

11.33

11.72

12.11

R_HW(kΩ)

100.00

99.61

99.22

98.83

98.44

98.05

97.66

97.27

96.88

96.48

96.09

95.70

95.31

94.92

94.53

94.14

93.75

93.36

92.97

92.58

92.19

91.80

91.41

91.02

90.63

90.23

89.84

89.45

89.06

88.67

88.28

87.89

R_WL/ R_HW

0.00

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.10

0.11

0.12

0.13

0.14

1

2

10

3

11

4

100

5

101

6

110

7

111

8

1000

1001

1010

1011

1100

1101

1110

1111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

16

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Table 2. (continued)

Step

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

Binary

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

1000000

1000001

1000010

1000011

1000100

1000101

1000110

1000111

1001000

1001001

1001010

1001011

1001100

1001101

1001110

R_WL(kΩ)

12.50

12.89

13.28

13.67

14.06

14.45

14.84

15.23

15.63

16.02

16.41

16.80

17.19

17.58

17.97

18.36

18.75

19.14

19.53

19.92

20.31

20.70

21.09

21.48

21.88

22.27

22.66

23.05

23.44

23.83

24.22

24.61

25.00

25.39

25.78

26.17

26.56

26.95

27.34

27.73

28.13

28.52

28.91

29.30

29.69

30.08

30.47

R_HW(kΩ)

87.50

87.11

86.72

86.33

85.94

85.55

85.16

84.77

84.38

83.98

83.59

83.20

82.81

82.42

82.03

81.64

81.25

80.86

80.47

80.08

79.69

79.30

78.91

78.52

78.13

77.73

77.34

76.95

76.56

76.17

75.78

75.39

75.00

74.61

74.22

73.83

73.44

73.05

72.66

72.27

71.88

71.48

71.09

70.70

70.31

69.92

69.53

R_WL/ R_HW

0.14

0.15

0.16

0.17

0.18

0.19

0.20

0.21

0.22

0.23

0.24

0.25

0.26

0.27

0.28

0.29

0.30

0.31

0.32

0.33

0.34

0.35

0.36

0.37

0.38

0.39

0.40

0.41

0.42

0.43

0.44

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Table 2. (continued)

Step

79

Binary

R_WL(kΩ)

30.86

31.25

31.64

32.03

32.42

32.81

33.20

33.59

33.98

34.38

34.77

35.16

35.55

35.94

36.33

36.72

37.11

37.50

37.89

38.28

38.67

39.06

39.45

39.84

40.23

40.63

41.02

41.41

41.80

42.19

42.58

42.97

43.36

43.75

44.14

44.53

44.92

45.31

45.70

46.09

46.48

46.88

47.27

47.66

48.05

48.44

48.83

R_HW(kΩ)

69.14

68.75

68.36

67.97

67.58

67.19

66.80

66.41

66.02

65.63

65.23

64.84

64.45

64.06

63.67

63.28

62.89

62.50

62.11

61.72

61.33

60.94

60.55

60.16

59.77

59.38

58.98

58.59

58.20

57.81

57.42

57.03

56.64

56.25

55.86

55.47

55.08

54.69

54.30

53.91

53.52

53.13

52.73

52.34

51.95

51.56

51.17

R_WL/ R_HW

0.45

0.46

0.47

0.48

0.49

0.50

0.51

0.52

0.53

0.54

0.55

0.56

0.57

0.58

0.59

0.60

0.61

0.62

0.63

0.64

0.65

0.66

0.67

0.68

0.70

0.71

0.72

0.73

0.74

0.75

0.77

0.78

0.79

0.80

0.82

0.83

0.84

0.86

0.87

0.88

0.90

0.91

0.92

0.94

0.95

1001111

1010000

1010001

1010010

1010011

1010100

1010101

1010110

1010111

1011000

1011001

1011010

1011011

1011100

1011101

1011110

1011111

1100000

1100001

1100010

1100011

1100100

1100101

1100110

1100111

1101000

1101001

1101010

1101011

1101100

1101101

1101110

1101111

1110000

1110001

1110010

1110011

1110100

1110101

1110110

1110111

1111000

1111001

1111010

1111011

1111100

1111101

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

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Table 2. (continued)

Step

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

Binary

R_WL(kΩ)

49.22

49.61

50.00

50.39

50.78

51.17

51.56

51.95

52.34

52.73

53.13

53.52

53.91

54.30

54.69

55.08

55.47

55.86

56.25

56.64

57.03

57.42

57.81

58.20

58.59

58.98

59.38

59.77

60.16

60.55

60.94

61.33

61.72

62.11

62.50

62.89

63.28

63.67

64.06

64.45

64.84

65.23

65.63

66.02

66.41

66.80

67.19

R_HW(kΩ)

50.78

50.39

50.00

49.61

49.22

48.83

48.44

48.05

47.66

47.27

46.88

46.48

46.09

45.70

45.31

44.92

44.53

44.14

43.75

43.36

42.97

42.58

42.19

41.80

41.41

41.02

40.63

40.23

39.84

39.45

39.06

38.67

38.28

37.89

37.50

37.11

36.72

36.33

35.94

35.55

35.16

34.77

34.38

33.98

33.59

33.20

32.81

R_WL/ R_HW

0.97

0.98

1.00

1.02

1.03

1.05

1.06

1.08

1.10

1.12

1.13

1.15

1.17

1.19

1.21

1.23

1.25

1.27

1.29

1.31

1.33

1.35

1.37

1.39

1.42

1.44

1.46

1.49

1.51

1.53

1.56

1.59

1.61

1.64

1.67

1.69

1.72

1.75

1.78

1.81

1.84

1.88

1.91

1.94

1.98

2.01

2.05

1111110

1111111

10000000

10000001

10000010

10000011

10000100

10000101

10000110

10000111

10001000

10001001

10001010

10001011

10001100

10001101

10001110

10001111

10010000

10010001

10010010

10010011

10010100

10010101

10010110

10010111

10011000

10011001

10011010

10011011

10011100

10011101

10011110

10011111

10100000

10100001

10100010

10100011

10100100

10100101

10100110

10100111

10101000

10101001

10101010

10101011

10101100

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Table 2. (continued)

Step

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

Binary

R_WL(kΩ)

67.58

67.97

68.36

68.75

69.14

69.53

69.92

70.31

70.70

71.09

71.48

71.88

72.27

72.66

73.05

73.44

73.83

74.22

74.61

75.00

75.39

75.78

76.17

76.56

76.95

77.34

77.73

78.13

78.52

78.91

79.30

79.69

80.08

80.47

80.86

81.25

81.64

82.03

82.42

82.81

83.20

83.59

83.98

84.38

84.77

85.16

85.55

R_HW(kΩ)

32.42

32.03

31.64

31.25

30.86

30.47

30.08

29.69

29.30

28.91

28.52

28.13

27.73

27.34

26.95

26.56

26.17

25.78

25.39

25.00

24.61

24.22

23.83

23.44

23.05

22.66

22.27

21.88

21.48

21.09

20.70

20.31

19.92

19.53

19.14

18.75

18.36

17.97

17.58

17.19

16.80

16.41

16.02

15.63

15.23

14.84

14.45

R_WL/ R_HW

2.08

2.12

2.16

2.20

2.24

2.28

2.32

2.37

2.41

2.46

2.51

2.56

2.61

2.66

2.71

2.76

2.82

2.88

2.94

3.00

3.06

3.13

3.20

3.27

3.34

3.41

3.49

3.57

3.65

3.74

3.83

3.92

4.02

4.12

4.22

4.33

4.45

4.57

4.69

4.82

4.95

5.10

5.24

5.40

5.56

5.74

5.92

10101101

10101110

10101111

10110000

10110001

10110010

10110011

10110100

10110101

10110110

10110111

10111000

10111001

10111010

10111011

10111100

10111101

10111110

10111111

11000000

11000001

11000010

11000011

11000100

11000101

11000110

11000111

11001000

11001001

11001010

11001011

11001100

11001101

11001110

11001111

11010000

11010001

11010010

11010011

11010100

11010101

11010110

11010111

11011000

11011001

11011010

11011011

20

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Table 2. (continued)

Step

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

Binary

R_WL(kΩ)

85.94

86.33

86.72

87.11

87.50

87.89

88.28

88.67

89.06

89.45

89.84

90.23

90.63

91.02

91.41

91.80

92.19

92.58

92.97

93.36

93.75

94.14

94.53

94.92

95.31

95.70

96.09

96.48

96.88

97.27

97.66

98.05

98.44

98.83

99.22

99.61

R_HW(kΩ)

14.06

13.67

13.28

12.89

12.50

12.11

11.72

11.33

10.94

10.55

10.16

9.77

R_WL/ R_HW

6.11

11011100

11011101

11011110

11011111

11100000

11100001

11100010

11100011

11100100

11100101

11100110

11100111

11101000

11101001

11101010

11101011

11101100

11101101

11101110

11101111

11110000

11110001

11110010

11110011

11110100

11110101

11110110

11110111

11111000

11111001

11111010

11111011

11111100

11111101

11111110

11111111

6.31

6.53

6.76

7.00

7.26

7.53

7.83

8.14

8.48

8.85

9.24

9.38

9.67

8.98

10.13

10.64

11.19

11.80

12.47

13.22

14.06

15.00

16.07

17.29

18.69

20.33

22.27

24.60

27.44

31.00

35.57

41.67

50.20

63.00

84.33

127.00

255.00

8.59

8.20

7.81

7.42

7.03

6.64

6.25

5.86

5.47

5.08

4.69

4.30

3.91

3.52

3.13

2.73

2.34

1.95

1.56

1.17

0.78

0.3

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8.4 Device Functional Modes

VOLTAGE DIVIDER MODE

V_H

V_HW

V_HW= (V_H– V_L) x (1 – (D/256))

V_H- V_L

W

V_WL= (V_H– V_L) x D/256

V_WL

Where D = Decimal Value of Wiper Code

V_L

RHEOSTAT MODE A

H

H (Floating)

R_WL= R_TOTx D/256

R_TOT

OR

R_TOT

W

Where D = Decimal Value of Wiper Code

R_WL

L

RHEOSTAT MODE B

H

R_HW

R_HW= R_TOTx (1 – (D/256))

R_TOT

OR

R_TOT

Where D = Decimal Value of Wiper Code

W

L

L (Floating)

Figure 19. Digital Potentiometer Configurations

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8.5 Register Maps

8.5.1 Slave Address

Bit 7

(MSB)

Bit 0

(LSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

1

0

1

0

A2

A1

A0

R/W

8.5.2 TPL0102-EP Register Maps

REGISTER ADDRESS (HEX)

NON-VOLATILE

IVRA

VOLATILE

WRA

WRB

N/A

0

1

IVRB

2

General purpose

3

N/A

4

N/A

5

N/A

6

N/A

7

N/A

8

N/A

9

N/A

A

B

C

E

D

F

10

N/A

Reserved

N/A

ACR

8.5.3 IVRA (Initial Value Register for Potentiometer A)

•

Register address: 00H

Factory programmed value: 80H

Type: non-volatile write/read

NAME

SIZE (BITS)

DESCRIPTION

Non-volatile register to store wiper position for potentiometer A

IVRA

8

8.5.4 WRA (Wiper Resistance Register for Potentiometer A)

•

Register address: 00H

Reset value: same as IVRA

Type: volatile write/read

NAME

SIZE (BITS)

DESCRIPTION

WRA

8

Volatile register to change wiper position for potentiometer A

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8.5.5 IVRB (Initial Value Register for Potentiometer B)

•

Register address: 01H

Factory programmed value: 80H

Type: non-volatile write/read

NAME

SIZE (BITS)

DESCRIPTION

IVRB

8

Non-volatile register to store wiper position for potentiometer B

8.5.6 WRB (Wiper Resistance Register for Potentiometer B)

•

Register address: 01H

Reset value: same as IVRB

Type: volatile write/read

NAME

SIZE (BITS)

DESCRIPTION

WRB

8

Volatile register to change wiper position for potentiometer B

8.5.7 ACR (Access Control Register)

•

Register address: 00H

Reset value: 40H

Type: non-volatile write/read

NAME

SIZE (BITS)

DESCRIPTION

IVRA

8

Non-volatile register to store wiper position for potentiometer A

Bit 7

VOL

0

Bit 6

SHDN

1

Bit 5

WIP

0

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ACR

8

0

Default Value

NAME

SIZE (BITS)

DESCRIPTION

0: Non-volatile registers (IVRA, IVRB) are accessible. Value written to IVRi register is

also written to the corresponding WRi.

VOL

1

1: Only volatile registers (WRi) are accessible.

0: Shut-down mode is enabled. Potentiometers are in shut-down mode.

(see Figure 20)

SHDN

1

1: Shut-down mode is disabled

0: Non-volatile write operation is not in progress

WIP (read-only bit)

1: Non-volatile write operation is in progress (it is not possible to write to the WRi or

ACR while WIP = 1)

24

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H

SHDN

Switch Open when SHDN = Low,

Switch Closed when SHDN = High

SHDN

Switch Open when SHDN = Low,

Switch Closed when SHDN = High

W

L

Figure 20. Potentiometer in Shut-Down Mode

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9 Application and Implementation

9.1 Application Information

In a simple operational amplifier configuration, like the one found in Figure 21, the TPL0102-EP is used to control

the gain and offset voltage of the operational amplifier. Using the TPL0102-EP in a rheostat mode (like Rheostat

Mode A in Figure 19), the gain setting of the negative feedback loop can be adjusted freely. To have maximum

control of the offset voltage correction of the operational amplifier, the voltage divider mode can be used; giving

the user an increased amount of control and precision for systems sensitive to DC offset.

9.2 Typical Application

5V

WA

½ TPL0102-EP

LA

to Nullify Offset Voltage

HA

1

7

3

2

V_IN

+

8

TLE2027

V_OUT

-

4

R1

HB

LB

½ TPL0102-EP

to Adjust Gain

WB

Figure 21. Offset Voltage and Gain Adjustment

26

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10 Layout

10.1 Layout Example

Positive Power

Supply Pin

Negative Power

Supply Pin

Address Bit 2 Address Bit1 Address Bit 0

High pin of

Potentiometer A

Wiper pin of

Potentiometer A

Low pin of

Potentiometer A

High pin of

Potentiometer B

Wiper pin of

Potentiometer B

I2C Clock Input

I2C Data I/O

Low pin of

Potentiometer B

Figure 22. TPL0102-EP Layout (Top Layer)

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Layout Example (continued)

Positive Power

Supply Pin

Negative Power

Supply Pin

Address Bit 2 Address Bit1 Address Bit 0

High pin of

Potentiometer A

Wiper pin of

Potentiometer A

Low pin of

Potentiometer A

Highpin of

Potentiometer B

Wiper pin of

Potentiometer B

I2C Clock Input

I2C Data I/O

Low pin of

Potentiometer B

Figure 23. TPL0102-EP Layout (Bottom Layer)

28

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11 Device and Documentation Support

11.1 Trademarks

All trademarks are the property of their respective owners.

11.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jun-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPL0102-100QPWREP TSSOP

PW

14

2000

330.0

12.4

6.9

5.6

1.6

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jun-2014

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TSSOP PW 14

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

TPL0102-100QPWREP

2000

Pack Materials-Page 2

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

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型号：	TPL0102-EP_15
厂家：	TEXAS INSTRUMENTS
描述：	TPL0102-EP 256-Taps Dual-Channel Digital Potentiometer With Non-Volatile Memory
文件：	总36页 (文件大小：1049K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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