TPL5010QDDCTQ1 [TI]
具有看门狗功能的汽车 AEC-Q100 毫微功耗系统计时器 | DDC | 6 | -40 to 125;
| 型号： | TPL5010QDDCTQ1 |
| 厂家： | 
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| 描述： | 具有看门狗功能的汽车 AEC-Q100 毫微功耗系统计时器 | DDC | 6 | -40 to 125 |
| 文件： | 总25页 (文件大小：785K) |
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TPL5010-Q1
ZHCSFH0 –SEPTEMBER 2016
TPL5010-Q1 具有看门狗功能、符合 AEC-Q100 标准的毫微功耗系统定时
器
1 特性
2 应用
1
•
•
适用于汽车电子 应用
具有符合 AEC-Q100 的下列结果：
•
•
•
•
•
•
•
•
电动汽车
常开系统
由电池供电的系统
离合致动器电路
车门把手电路
智能钥匙
–
–
–
器件温度 1 级：-40°C 至 125°C 的环境运行温
度范围
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 2
器件组件充电模式 (CDM) ESD 分类等级 C5
远程电流传感器
出入检测
•
•
•
•
•
•
•
•
电流消耗为 35nA（2.5V 时的典型值）
电源电压范围：1.8V 至 5.5V
可选时间间隔范围：100ms 至 7200s
定时器精度：1%（典型值）
可通过电阻选择时间间隔
看门狗功能
3 说明
TPL5010-Q1 是一款具有看门狗功能且符合 AEC-
Q100 标准的低功耗毫微定时器，非常适用于在占空比
或电池供电应用中进行系统 唤醒。在此类系统中，可
使用微控制器定时器唤醒系统，但如果定时器休眠电流
较高，则微控制器定时器在此休眠模式下会消耗高达
60%-80% 的总系统电流。TPL5010-Q1 仅消耗 35nA
电流，可替代集成微控制器定时器执行相应功能，从而
使微控制器处于功耗较低的模式下。这种节能效果延长
电池使用寿命并显著缩小电池尺寸，使得 TPL5010-
Q1 成为功率敏感型 应用的理想选择。TPL5010-Q1 提
供 100ms 至 7200s 可选时间间隔，适用于由中断驱动
的 应用。出于安全考虑，某些标准（如 EN50271）要
求实现看门狗功能。TPL5010-Q1 不仅实现了看门狗
功能，而且几乎没有增加任何功耗。TPL5010-Q1 采
用 6 引脚小外形尺寸晶体管 (SOT)-23 封装。
手动复位
TPL5x10Q 系列符合 AEC-Q100 标准的毫微功耗
系统定时器：
–
TPL5010-Q1：延迟范围可通过编程设定的看门
狗功能
–
TPL5110-Q1：延迟范围可通过编程设定且具有
单次触发功能的金属氧化物半导体 (MOS) 驱动
器
器件信息(1)
器件型号
封装
SOT23 (6)
封装尺寸（标称值）
TPL5010-Q1
3.00mm x 3.00mm
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNAS679
TPL5010-Q1
ZHCSFH0 –SEPTEMBER 2016
www.ti.com.cn
简化应用
µC
VOUT
VIN
wp
TPL5010-Q1
VDD
VDD
GND
RSTn
WAKE
DONE
RSTn
GPIO
GPIO
.attery
POWER MANAGEMENT
DELAY/
M_RST
w9óÇ
GND
GND
2
版权 © 2016, Texas Instruments Incorporated
TPL5010-Q1
www.ti.com.cn
ZHCSFH0 –SEPTEMBER 2016
目录
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
8.5 Programming .......................................................... 10
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 3
器件比较表............................................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions ...................... 5
7.4 Thermal Information ................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Timing Requirements ............................................... 7
7.7 Typical Characteristics.............................................. 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
9
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
12 器件和文档支持 ..................................................... 19
12.1 接收文档更新通知 ................................................. 19
12.2 社区资源................................................................ 19
12.3 商标....................................................................... 19
12.4 静电放电警告......................................................... 19
12.5 Glossary................................................................ 19
13 机械、封装和可订购信息....................................... 19
8
4 修订历史记录
日期
修订版本
注释
2016 年 9 月
*
最初发布版本。
5 器件比较表
TPL5x10Q 系列符合 AEC-Q100 标准的毫微功耗系统定时器
器件编号
电源电流（典型值）
特殊 功能
低功耗计时器
看门狗功能
TPL5010-Q1
TPL5110-Q1
35nA
可编程延迟范围
手动复位
低功耗计时器
MOS 驱动器
可编程延迟范围
手动复位
35nA
单次触发功能
Copyright © 2016, Texas Instruments Incorporated
3
TPL5010-Q1
ZHCSFH0 –SEPTEMBER 2016
www.ti.com.cn
6 Pin Configuration and Functions
SOT23
6-Pin DDC
Top View
TPL5010-Q1
1
2
3
VDD
RSTn
WAKE
DONE
6
5
4
GND
DELAY/
M_RST
Table 1. Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
APPLICATION INFORMATION
NO.
1
VDD
GND
P
G
I
Supply voltage
2
Ground
3
DELAY/
M_RST
Time Interval set and Manual Reset
Resistance between this pin and GND is used to
select the time interval. The reset switch is also
connected to this pin.
4
5
6
DONE
WAKE
RSTn
I
Logic Input for watchdog functionality
Digital signal driven by the µC to indicate successful
processing of the WAKE signal.
O
O
Timer output signal generated every tIP
period.
Digital pulsed signal to wake up the µC at the end of
the programmed time interval.
Reset Output (open drain output)
Digital signal to RESET the µC, pull-up resistance is
required
(1) G= Ground, P= Power, O= Output, I= Input.
4
Copyright © 2016, Texas Instruments Incorporated
TPL5010-Q1
www.ti.com.cn
ZHCSFH0 –SEPTEMBER 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–5
MAX
6.0
UNIT
V
Supply voltage (VDD-GND)
Input voltage at any pin(2)
Input current on any pin
VDD + 0.3
5
V
mA
°C
Tstg
TJ
Storage temperature
–65
150
Junction temperature(3)
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The voltage between any two pins should not exceed 6V.
(3) The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC
board.
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model, per AEC Q100-002(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q10-011
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.8
NOM
MAX
5.5
UNIT
V
Supply voltage (VDD-GND)
Temperature
–40
125
°C
7.4 Thermal Information
TPL5010-Q1
THERMAL METRIC(1)
SOT23
6 PINS
163
26
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-board thermal resistance
57
Junction-to-top characterization parameter
Junction-to-board characterization parameter
7.5
ψJB
57
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2016, Texas Instruments Incorporated
5
TPL5010-Q1
ZHCSFH0 –SEPTEMBER 2016
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7.5 Electrical Characteristics
TA= 25°C, VDD-GND=2.5 V (unless otherwise stated)(1)
PARAMETER
TEST CONDITIONS
MIN(2)
TYP(3)
MAX(2) UNIT
POWER SUPPLY
IDD
Supply current(4)
Operation mode
35
50
nA
µA
Digital conversion of external
resistance (Rext)
200
400
TIMER
tIP
Time interval period(5)
1650 selectable time Min time interval
100
ms
s
Intervals
Max time
7200
interval
Time interval setting accuracy(6)
Excluding the precision of Rext
±0.6%
±25
Timer interval setting accuracy over 1.8 V ≤ VDD ≤ 5.5 V
ppm/V
supply voltage
tOSC
Oscillator accuracy
–0.5%
0.5%
Oscillator accuracy over
temperature(5)
-40°C ≤ TA ≤ 125°C
1.8 V ≤ VDD ≤ 5.5 V
150
ppm/°C
%/V
Oscillator accuracy over supply
voltage(5)
±0.4
Oscillator accuracy over life time(7)
0.24%
100
320
20
(5)
tDONE
tRSTn
Minimum DONE pulse width
ns
ms
ms
ms
RSTn pulse width
tWAKE
t_Rext
WAKE pulse width
Time to convert Rext(5)
100
DIGITAL LOGIC LEVELS
VIH
Minimum logic high threshold DONE
pin
0.7 ×
VDD
V
V
VIL
Maximum logic low threshold DONE
pin
0.3 ×
VDD
Iout = 100 µA
Iout = 1 mA
VDD – 0.3
VDD – 0.7
V
V
VOH
VOL
Logic output high-level WAKE pin
Logic output low-level WAKE pin
Iout = –100 µA
Iout = –1 mA
IOL= –1 mA
0.3
0.7
0.3
V
V
VOLRSTn
IOHRSTn
VIHM_RST
RSTn logic output low-level
V
RSTn high-level output current
VOHRSTn = VDD
1
nA
V
Minimum logic high threshold
DELAY/M_RST pin(5)
1.5
(1) Values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating
of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of
internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be
permanently degraded, either mechanically or electrically.
(2) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through
correlations using statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
(4) The supply current excludes load and pull-up resistor current. Input pins are at GND or VDD.
(5) This parameter is specified by design and/or characterization and is not tested in production.
(6) The accuracy for time interval settings below 1 second is ±100 ms.
(7) Operational life time test procedure equivalent to 10 years.
6
Copyright © 2016, Texas Instruments Incorporated
TPL5010-Q1
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ZHCSFH0 –SEPTEMBER 2016
7.6 Timing Requirements
MIN(1)
NOM(2) MAX(1) UNIT
(3)
trRSTn
tfRSTn
trWAKE
tfWAKE
Rise Time RSTn
Capacitive load 50 pF, Rpull-up 100 kΩ
Capacitive load 50 pF, Rpull-up 100 kΩ
Capacitive load 50 pF
11
µs
ns
(3)
Fall time RSTn
Rise time WAKE
Fall time WAKE
50
50
(3)
(3)
ns
Capacitive load 50 pF
50
ns
Min delay(4)
100
tIP–20
20
ns
DONE to RSTn or WAKE to
DONE delay
tDDONE
(4)
Max delay
ms
ms
ms
(3)
tM_RST
tDB
Minimum valid manual reset
De-bounce manual reset
Observation time 30 ms
20
(1) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through
correlations using statistical quality control (SQC) method.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
(3) This parameter is specified by design and/or characterization and is not tested in production.
(4) In case of RSTn from its falling edge, in case of WAKE, from its rising edge.
VDD
ttWAKE
t
trWAKE
WAKE
DONE
RSTn
ttIPt
ttDDONEt
tfWAKE
tDONE
ttRSTn+ tIP
t
trRSTn
ttRSTn+tDB
t
ttRSTnt
ttR_EXT + tRSTn
t
tfRSTn
DELAY/
M_RST
ttM_RST
Figure 1. TPL5010-Q1 Timing
Copyright © 2016, Texas Instruments Incorporated
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TPL5010-Q1
ZHCSFH0 –SEPTEMBER 2016
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7.7 Typical Characteristics
100
100
90
80
70
60
50
40
30
20
TA= -40°C
TA= 25°C
TA= 70°C
TA= 105°C
TA = 125°C
VDD= 1.8V
VDD= 2.5V
VDD= 3.3V
VDD= 5.5V
90
80
70
60
50
40
30
20
1.5
1.9
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
-40
-25
-10
5
20
35
50
65
80
95
110
125
Supply Voltage (V)
D00
Temperature (°C)
Figure 2. IDD vs VDD
Figure 3. IDD vs Temperature
2
1.5
1
2
1.5
1
TA= -40°C
TA= 25°C
TA= 70°C
TA= 105°C
TA= 125°C
VDD= 1.8V
VDD= 2.5V
VDD= 3.3V
VDD= 5.5V
0.5
0
0.5
0
-0.5
-1
-0.5
-1
1.5
1.9
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
-40
-25
-10
5
20
35
50
65
80
95
110
125
Supply Voltage (V)
Temperature (°C)
Figure 4. Oscillator Accuracy vs VDD
Figure 5. Oscillator Accuracy vs Temperature
1000
100
10
40%
POR
REXT READING
35%
30%
25%
20%
15%
10%
5%
1
TIMER MODE
0.1
0.01
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
Time (s)
Accuracy (%)
number of
1 s < tIP ≤ 7200 s
observations >
20000
Figure 7. Time Interval Setting Accuracy
Figure 6. IDD vs Time
8
Copyright © 2016, Texas Instruments Incorporated
TPL5010-Q1
www.ti.com.cn
ZHCSFH0 –SEPTEMBER 2016
8 Detailed Description
8.1 Overview
The TPL5010-Q1 is a system wakeup timer with a watchdog feature, ideal for low power applications. TPL5010-
Q1 is ideal for use in interrupt-driven applications and provides selectable timing from 100 ms to 7200 s.
8.2 Functional Block Diagram
VDD
RSTn
LOW FREQUENCY
OSCILLATOR
FREQUENCY
DIVIDER
LOGIC
CONTROL
WAKE
DONE
DELAY/
M_RST
DECODER
&
MANUAL RESET
DETECTOR
GND
8.3 Feature Description
The DONE, WAKE and RSTn signals are used to implement the watchdog function. The TPL5010-Q1 is
programmed to issue a periodic WAKE pulse to a µC which is in sleep or standby mode. After receiving the
WAKE pulse, the µC must issue a DONE signal to the TPL5010-Q1 at least 20 ms before the rising edge of the
next WAKE pulse. If the DONE signal is not asserted, the TPL5010-Q1 asserts the RSTn signal to reset the µC.
A manual reset function is realized by momentarily pulling the DELAY/M_RST pin to VDD.
ttIPt
ttIPt
WAKE
DONE
RSTn
MISSED
DONE
ttRSTn+ tIPt
DELAY/
M_RST
Figure 8. Watchdog
8.3.1 WAKE
The WAKE pulse is sent out from the TPL5010-Q1 when the programmed time interval starts (except at the
beginning of the first cycle or if in the previous interval the DONE has not been received).
This signal is normally low.
8.3.2 DONE
The DONE pin is driven by a µC to signal successful processing of the WAKE signal. The TPL5010-Q1
recognizes a valid DONE signal as a low to high transition; if two or more DONE signals are received within the
time interval, only the first DONE signal is processed.
The DONE signal resets the counter of the watchdog only. If the DONE signal is received when the WAKE is still
high, the WAKE will go low as soon as the DONE is recognized.
Copyright © 2016, Texas Instruments Incorporated
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TPL5010-Q1
ZHCSFH0 –SEPTEMBER 2016
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Feature Description (continued)
8.3.3 RSTn
To implement the reset interface between the TPL5010-Q1 and the µC a pull-up resistance is required. 100 kΩ is
recommended, to minimize current.
During the POR and the reading of the REXT the RSTn signal is LOW.
RSTn is asserted (LOW) for either one of the following conditions:
•
•
1. If the DELAY/M_RST pin is high for at least two consecutive cycles of the internal oscillator (approximately
20 ms).
2. At the beginning of a new time interval if DONE is not received at least 20 ms before the next WAKE rising
edge (see Figure 8).
8.4 Device Functional Modes
8.4.1 Startup
During startup, after POR, the TPL5010-Q1 executes a one-time measurement of the resistance attached to the
DELAY/M_RST pin in order to determine the desired time interval for WAKE. This measurement interval is
tR_EXT. During this measurement a constant current is temporarily flowing into REXT
.
ttR_EXT + tRSTn + tIPt
ttIPt
WAKE
DONE
RSTn
DELAY/
M_RST
RESISTANCE
READING
POR
Figure 9. Startup
8.4.2 Normal Operating Mode
During normal operating mode, the TPL5010-Q1 asserts periodic WAKE pulses in response to valid DONE
pulses from the µC. If either a manual reset is applied (logic HIGH on DELAY/M_RST pin) or the µC does not
issue a DONE pulse within the required time, the TPL5010-Q1 asserts the RSTn signal to the µC and restarts its
internal counters. See Figure 8 and Figure 10 .
8.5 Programming
8.5.1 Configuring the WAKE Interval with the DELAY/M_RST Pin
The time interval between 2 adjacent WAKE pulses (rising edges) is selectable through an external resistance
(REXT) between the DELAY/M_RST pin and ground. The value of the resistance REXT is converted one time after
POR. The allowable range of REXT is 500 Ω to 170 kΩ. At least a 1% precision resistance is recommended. See
Timer Interval Selection Using External Resistance for how to set the WAKE pulse interval using REXT
.
The time between 2 adjacent RESET signals (falling edges) or between a RESET (falling edge) and a WAKE
(rising edge) is given by the sum of the programmed time interval and the tRSTn (reset pulse width).
10
Copyright © 2016, Texas Instruments Incorporated
TPL5010-Q1
www.ti.com.cn
ZHCSFH0 –SEPTEMBER 2016
Programming (continued)
8.5.2 Manual Reset
If VDD is connected to the DELAY/M_RST pin, the TPL5010-Q1 recognizes this as a manual reset condition. In
this case the time interval is not set. If the manual reset is asserted during the POR or during the reading
procedure, the reading procedure is aborted and is re-started as soon as the manual reset switch is released. A
pulse on the DELAY/M_RST pin is recognized as a valid manual reset only if it lasts at least 20 ms (observation
time is 30 ms).
A valid manual reset resets all the counters inside the TPL5010-Q1. The counters restart only when the high
digital voltage at DELAY/M_RST is removed and the next tRSTn is elapsed.
ttIPt
WAKE
DONE
ttRSTn+ tIPt
RSTn
ANY RESET
ttM_RST
t
ttDB
t
ttM_RSTt
DELAY/
M_RST
VALID M_RST
NOT VALID M_RST
Figure 10. Manual Reset
8.5.2.1 DELAY/M_RST
A resistance in the range between 500 Ω and 170 kΩ needs to be connected in order to select a valid time
interval. At the POR and during the reading of the resistance the DELAY/M_RST is connected to an analog
signal chain though a mux. After the reading of the resistance the analog circuit is switched off and the
DELAY/RST is connected to a digital circuit.
The manual reset detection is supported with a de-bounce feature which makes the TPL5010-Q1 insensitive to
the glitches on the DELAY/M_RST pin. When a valid manual reset signal is asserted on the DELAY/M_RST pin,
the RSTn signal is asserted LOW after a delay of tM_RST. It remains LOW after a valid manual reset is asserted +
tDB + tRSTn. Due to the asynchronous nature of the manual reset signal and its arbitrary duration, the LOW status
of the RSTn signal maybe affected by an uncertainty of about ±5 ms.
A valid manual reset puts all the digital output signals at their default values:
•
•
WAKE = LOW
RSTn = asserted LOW
8.5.2.2 Circuitry
The manual reset may be implemented using a switch (momentary mechanical action). The TPL5010-Q1 offers 2
possible approaches according to the power consumption constraints of the application.
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Programming (continued)
µC
VOUT
VIN
wp
TPL5010-Q1
VDD
VDD
RSTn
WAKE
DONE
RSTn
GPIO
GPIO
.attery
POWER MANAGEMENT
GND
DELAY/
M_RST
w9óÇ
GND
GND
Figure 11. Manual Reset with SPST Switch
For use cases that do not require the lowest power consumption, using a single pole single throw switch may
offer a lower cost solution. The DELAY/M_RST pin may be directly connected to VDD with REXT in the circuit.
The current drawn from the supply voltage during the reset is given by VDD/REXT
.
µC
VOUT
wp
TPL5010-Q1
VIN
VDD
VDD
RSTn
WAKE
DONE
RSTn
GPIO
GPIO
.attery
POWER MANAGEMENT
GND
GND
DELAY/
M_RST
w9óÇ
GND
Figure 12. Manual Reset with SPDT Switch
The reset function may also be asserted by switching DELAY/M_RST from REXT to VDD using a single pole
double throw switch, which will provide a lower power solution for the manual reset, because no current flows.
8.5.3 Timer Interval Selection Using External Resistance
In order to set the time interval, the external resistance REXT is selected according the following formula:
- b + b 2 - 4a
2a
(
c -100 T
)
≈
∆
’
÷
REXT =100
∆
«
÷
◊
where
•
•
•
T is the desired time interval in seconds
REXT is the resistance value to use in Ω
a, b, c are coefficients depending on the range of the time interval
(1)
12
Copyright © 2016, Texas Instruments Incorporated
TPL5010-Q1
www.ti.com.cn
ZHCSFH0 –SEPTEMBER 2016
Programming (continued)
Table 2. Coefficients for Equation 1
TIME
SET
INTERVAL
RANGE (s)
a
b
c
1
2
1 < T ≤ 5
0.2253
–0.1284
0.1972
0.2617
0.3177
–20.7654
46.9861
570.5679
–2651.8889
692.1201
5 < T ≤ 10
3
4
5
10 < T ≤ 100
100 < T ≤ 1000
T > 1000
–19.3450
–56.2407
–136.2571
5957.7934
34522.4680
EXAMPLE
Required time interval: 8 s
The coefficient set to be selected is the number 2. The formula becomes:
2
≈
’
46.9861- 46.9861 +4*0.1284
(
-2561.8889-100*8
)
∆
÷
REXT =100
∆
÷
◊
2*0.1284
«
(2)
The resistance value is 10.18 kΩ.
Table 3 and Table 4 contain example values of tIP and their corresponding value of REXT
.
Table 3. First 9 Time Intervals
PARALLEL OF TWO 1% TOLERANCE
tIP (ms)
RESISTANCE (Ω)
CLOSEST REAL VALUE (Ω)
RESISTORS (kΩ)
100
200
300
400
500
600
700
800
900
500
500
1.0 // 1.0
-
1000
1500
2000
2500
3000
3500
4000
4500
1000
1500
2000
2500
3000
3500
4000
4501
2.43 // 3.92
-
4.42 // 5.76
5.36 // 6.81
4.75 // 13.5
6.19 // 11.3
6.19 // 16.5
Table 4. Most Common Time Intervals Between 1 s to 2 h
CLOSEST REAL
VALUE (kΩ)
PARALLEL OF TWO 1% TOLERANCE
tIP
CALCULATED RESISTANCE (kΩ)
RESISTORS (kΩ)
7.15 // 19.1
12.4 // 15.0
12.7// 19.1
1 s
2 s
5.20
6.79
5.202
6.788
7.628
8.306
8.852
9.223
9.673
10.180
10.68
11.199
14.405
16.778
18.748
3 s
7.64
4 s
8.30
14.7 // 19.1
16.5 // 19.1
18.2 // 18.7
19.1 // 19.6
11.5 // 8.87
17.8 // 26.7
15.0 // 44.2
16.9 // 97.6
32.4 // 34.8
22.6 // 110.0
5 s
8.85
6 s
9.27
7 s
9.71
8 s
10.18
10.68
11.20
14.41
16.78
18.75
9 s
10 s
20 s
30 s
40 s
Copyright © 2016, Texas Instruments Incorporated
13
TPL5010-Q1
ZHCSFH0 –SEPTEMBER 2016
www.ti.com.cn
Table 4. Most Common Time Intervals Between 1 s to 2 h (continued)
CLOSEST REAL
VALUE (kΩ)
PARALLEL OF TWO 1% TOLERANCE
tIP
CALCULATED RESISTANCE (kΩ)
RESISTORS (kΩ)
50 s
1 min
2 min
3 min
4 min
5 min
6 min
7 min
8 min
9 min
10 min
20 min
30 min
40 min
50 min
1 h
20.047
22.02
29.35
34.73
39.11
42.90
46.29
49.38
52.24
54.92
57.44
77.57
92.43
104.67
115.33
124.91
149.39
170.00
20.047
22.021
29.349
34.729
39.097
42.887
46.301
49.392
52.224
54.902
57.437
77.579
92.233
104.625
115.331
124.856
149.398
170.00
28.7 // 66.5
40.2 // 48.7
35.7 // 165.0
63.4 // 76.8
63.4 // 102.0
54.9 // 196.0
75.0 // 121.0
97.6 // 100.0
88.7 // 127.0
86.6 // 150.0
107.0 // 124.0
140.0 // 174.0
182.0 // 187.0
130.0 // 536.00
150.0 // 499.00
221.0 // 287.00
165.0 // 1580.0
340.0 // 340.0
1 h 30 min
2 h
8.5.4 Quantization Error
The TPL5010-Q1 can generate 1650 discrete timer intervals in the range of 100 ms to 7200 s. The first 9
intervals are multiples of 100 ms. The remaining 1641 intervals cover the range between 1 s to 7200 s. Because
they are discrete intervals, there is a quantization error associated with each value.
The quantization error can be evaluated according to the following formula:
(
TDESIRED -TADC
)
Err =100
Where:
TDESIRED
(3)
(4)
R D2
R D
»
…
ÿ
Ÿ
⁄
≈
’
1
∆
∆
÷
÷
T ADC = INT
a
+ b
+ c
2
100
100
100
«
◊
R
»
…
ÿ
EXT
R D = INT
Ÿ
⁄
100
where
•
•
REXT is the resistance calculated with Equation 1
a, b, c are the coefficients of the equation listed in Table 2
(5)
8.5.5 Error Due to Real External Resistance
REXT is a theoretical value and may not be available in standard commercial resistor values. It is possible to
closely approach the theoretical REXT using two or more standard values in parallel. However, standard values
are characterized by a certain tolerance. This tolerance will affect the accuracy of the time interval.
The accuracy can be evaluated using the following procedure:
1. Evaluate the min and max values of REXT (REXT_MIN, REXT_MAX with Equation 1 using the selected commercial
resistance values and their tolerances.
2. Evaluate the time intervals (TADC_MIN[REXT_MIN], TADC_MAX[REXT_MAX]) with Equation 4.
3. Find the errors using Equation 3 with TADC_MIN, TADC_MAX
.
The results of the formula indicate the accuracy of the time interval.
14
Copyright © 2016, Texas Instruments Incorporated
TPL5010-Q1
www.ti.com.cn
ZHCSFH0 –SEPTEMBER 2016
The example below illustrates the procedure.
•
•
Desired time interval , T_desired = 600 s
Required REXT, from Equation 1, REXT= 57.44 kΩ
From Table 4, REXT can be built with a parallel combination of two commercial values with 1% tolerance: R1=107
kΩ, R2=124 kΩ. The uncertainty of the equivalent parallel resistance can be found using Equation 6.
2
2
u
u
R2
≈
∆
’
÷
≈
∆
’
÷
R1
uR =R//
+
//
R1
R2
«
◊
«
◊
(6)
Where uRn (n=1,2) represent the uncertainty of a resistance,
Tolerance
uR =Rn
n
3
(7)
=
The uncertainty of the parallel resistance is 0.82%, meaning the value of REXT may range between REXT_MIN
56.96 kΩ and REXT_MAX = 57.90 kΩ.
Using these value of REXT, the digitized timer intervals calculated with Equation 4 are respectively TADC_MIN
=
586.85 s and TADC_MAX = 611.3 s, giving an error range of –1.88% / +2.19%. The asymmetry of the error range is
due to the quadratic transfer function of the resistance digitizer.
Copyright © 2016, Texas Instruments Incorporated
15
TPL5010-Q1
ZHCSFH0 –SEPTEMBER 2016
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
In battery-powered applications, one design constraint is the need for low current consumption. The TPL5010-Q1
is ideal for applications where there is a need to monitor environmental conditions at a fixed time interval. Often
in these applications, a watchdog or other internal timer in a µC is used to implement a wakeup function. Using
the TPL5010-Q1 to implement the watchdog function will consume only tens of nA, significantly improving the
power consumption of the system.
9.2 Typical Application
The TPL5010-Q1 can be used in conjunction with environment sensors to build a low-power environment data-
logger, such as an air quality data-logger. In this application, due to the monitored phenomena, the µC and the
front end of the sensor spend most of the time in the idle state, waiting for the next logging interval, usually a few
hundred of milliseconds. Figure 13 illustrates a data logging application based on a µC, and a front end for a gas
sensor based on the LMP91000.
VOLTAGE
REFERENCE
VIN
VOUT
GND
µC
LMP91000
Rp
100k
VOUT
VIN
Rp
100k
Rp
100k
TPL5010-Q1
VDD
SDA
VDD
SCL
SDA
VREF
CE
+
VDD
RSTn
WAKE
DONE
RST
Lithium
ion battery
CE
POWER MANAGEMENT
GND
GND
GPIO
GPIO
SCL
RE
RE
WE
-
DELAY/
M_RST
ADC
GND
GPIO
GPIO
VOUT
GND
WE
GAS
SENSOR
MENB
w9óÇ
GPIO
GPIO
Button
Temp 29°C
CO 0PPM
Button
Button
TIME xx:xx
Date xx/xx/xxxx
DISPLAY
KEYBOARD
Figure 13. Data-Logger
9.2.1 Design Requirements
The design is driven by the low current consumption constraint. The data are usually acquired on a rate that
ranges between 1 s and 10 s. The highest necessity is the maximization of the battery life. The TPL5010-Q1
helps achieve that goal because it allows putting the µC in its lowest power mode. The TPL5010-Q1 will take
care of the watchdog and the timing.
16
Copyright © 2016, Texas Instruments Incorporated
TPL5010-Q1
www.ti.com.cn
ZHCSFH0 –SEPTEMBER 2016
Typical Application (continued)
9.2.2 Detailed Design Procedure
When the main constraint is the battery life, the selection of a low-power voltage reference, µC, and display is
mandatory. The first step in the design is the calculation of the power consumption of the devices in their
different mode of operations. For instance, the LMP91000 burns most of the power when in gas measurement
mode, then according to the connected gas sensor it has 2 idle states: stand-by and deep sleep. The same is
true for the µC, such as one of the MSP430 family, which can be placed in one of its lower power modes, such
as LMP3.5 or LMP4.5. In this case, the TPL5010-Q1 can be used to implement the watchdog and wakeup timing
functions.
After the power budget calculation it is possible to select the appropriate time interval which satisfies the
application constraints and maximize the life of the battery.
9.2.3 Application Curves
Without TPL5010-Q1
With TPL5010-Q1
Time
Figure 14. Effect of TPL5010-Q1 on Current Consumption
Copyright © 2016, Texas Instruments Incorporated
17
TPL5010-Q1
ZHCSFH0 –SEPTEMBER 2016
www.ti.com.cn
10 Power Supply Recommendations
The TPL5010-Q1 requires a voltage supply within 1.8 V and 5.5 V. A multilayer ceramic bypass X7R capacitor of
0.1 μF between VDD and GND pin is recommended.
11 Layout
11.1 Layout Guidelines
The DELAY/M_RST pin is sensitive to parasitic capacitance. It is suggested that the traces connecting the
resistance on this pin to GROUND be kept as short as possible to minimize parasitic capacitance. This
capacitance can affect the initial set up of the time interval. Signal integrity on the WAKE and RSTn pins is also
improved by keeping the trace length between the TPL5010-Q1 and the µC short to reduce the parasitic
capacitance.
11.2 Layout Example
Figure 15. Layout
18
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TPL5010-Q1
www.ti.com.cn
ZHCSFH0 –SEPTEMBER 2016
12 器件和文档支持
12.1 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
18-May-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPL5010QDDCRQ1
TPL5010QDDCTQ1
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
6
6
3000 RoHS & Green
250 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
13VX
13VX
Samples
Samples
NIPDAU | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-May-2022
OTHER QUALIFIED VERSIONS OF TPL5010-Q1 :
Catalog : TPL5010
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OUTLINE
DDC0006A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
C
0 -8 TYP
0.25
GAGE PLANE
SEATING PLANE
0.20
0.12
TYP
0.6
0.3
TYP
4214841/C 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/C 04/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/C 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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