TPL5110 [TI]
具有 MOS 驱动器和手动 MOSFET 加电功能的毫微功耗系统计时器;
| 型号： | TPL5110 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 MOS 驱动器和手动 MOSFET 加电功能的毫微功耗系统计时器 驱动 驱动器 |
| 文件： | 总27页 (文件大小：1395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPL5110
ZHCSEK5A –JANUARY 2015–REVISED SEPTEMBER 2018
用于电源门控的 TPL5110 毫微功耗系统计时器
1 特性
3 说明
1
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电源电压范围为 1.8V 至 5.5V
TPL5110 是一款低功耗计时器，具有集成 MOSFET
驱动器，专为占空比或电池供电型应用中的电源门控而
设计。TPL5110 的电流消耗仅为 35nA，可用于支持电
源线路，并可大幅降低睡眠期间的总系统待机电流。这
一节能特性可以大幅减小能量采集或无线传感器应用中
所使用的电池 尺寸。TPL5110 提供 100ms 至 7200s
的可选计时间隔，适合用于电源门控 应用。此
外，TPL5110 还具有独特的单次触发功能，可使计时
器仅为 MOSFET 供电一个周期。TPL5110 采用 6 引
脚 SOT23 封装。
电压为 2.5V 时，电流消耗为 35nA（典型值）
可选计时间隔：100ms 至 7200s
计时器精度：1%（典型值）
可通过电阻选择时间间隔
手动为 MOSFET 上电
单次触发功能
2 应用
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电池供电系统
物联网 (IoT)
出入探测
器件信息(1)
器件编号
TPL5110
封装
SOT23 (6)
封装尺寸（标称值）
篡改检测
3.00mm x 3.00mm
家庭自动化传感器
温度调节装置
消费类电子产品
远程传感器
白色家电
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
简化应用电路原理图
µC
VOUT
VIN
TPL5110
VDD
EN/
ONE_SHOT
VDD
GND
Battery
POWER MANAGEMENT
GND
DRV
DELAY/
M_DRV
DONE
GPIO
REXT
GND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNAS650
TPL5110
ZHCSEK5A –JANUARY 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
目录
7.4 Device Functional Modes.......................................... 9
7.5 Programming .......................................................... 10
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 16
Power Supply Recommendations...................... 17
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Ratings ........................... 4
6.4 Thermal Information ................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements ............................................... 6
6.7 Typical Characteristics.............................................. 7
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
8
9
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 18
11 器件和文档支持 ..................................................... 19
11.1 接收文档更新通知 ................................................. 19
11.2 社区资源................................................................ 19
11.3 商标....................................................................... 19
11.4 静电放电警告......................................................... 19
11.5 术语表 ................................................................... 19
12 机械、封装和可订购信息....................................... 19
7
4 修订历史记录
Changes from Original (January 2015) to Revision A
Page
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已更改 说明文本...................................................................................................................................................................... 1
Changed max IDD ................................................................................................................................................................. 5
Changed TPL5110 Timing labels ........................................................................................................................................... 6
Changed Circuitry text .......................................................................................................................................................... 12
Changed TADC and RD equations in the Quantization Error section..................................................................................... 14
添加了接收文档更新通知 部分.............................................................................................................................................. 19
2
Copyright © 2015–2018, Texas Instruments Incorporated
TPL5110
www.ti.com.cn
ZHCSEK5A –JANUARY 2015–REVISED SEPTEMBER 2018
5 Pin Configuration and Functions
DDC Package
6-Lead SOT-23
Top View
TPL5110
EN/
ONE_ SHOT
1
2
3
VDD
GND
6
5
4
DRV
DELAY/
M_DRV
DONE
Pin Functions
PIN
TYPE(1)
DESCRIPTION
APPLICATION INFORMATION
NO.
1
NAME
VDD
P
G
I
Supply voltage
Ground
2
GND
3
DELAY/
M_DRV
Time interval set and manual
MOSFET Power ON
Resistance between this pin and GND is used to
select the time interval. The manual MOSFET power
ON switch is also connected to this pin.
4
5
6
DONE
DRV
I
O
I
Logic Input for watchdog
functionality
Digital signal driven by the µC to indicate successful
processing.
Power Gating output signal
generated every tIP
The Gate of the MOSFET is connected to this pin.
When DRV = LOW, the MOSFET is ON.
EN/
ONE_SHOT
Selector of mode of operation
When EN/ONE_SHOT = HIGH, the TPL5110 works
as a TIMER. When EN/ONE_SHOT = LOW, the
TPL5110 turns on the MOSFET one time for the
programmed time interval. The next power on of the
MOSFET is enabled by the manual power ON.
(1) G= Ground, P= Power, O= Output, I= Input.
Copyright © 2015–2018, Texas Instruments Incorporated
3
TPL5110
ZHCSEK5A –JANUARY 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
–0.3
–0.3
–5
MAX
6
UNIT
V
Supply Voltage (VDD-GND)
Input Voltage at any pin(2)
Input Current on any pin
Junction Temperature, TJ(3)
Storage Temperature, Tstg
VDD + 0.3
+5
V
mA
°C
150
–65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The voltage between any two pins should not exceed 6 V.
(3) The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a
printed-circuit board (PCB).
6.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human Body Model, per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Ratings
MIN
MAX
5.5
UNIT
V
Supply Voltage (VDD-GND)
Temperature
1.8
–40
105
°C
6.4 Thermal Information
TPL5110
THERMAL METRIC(1)
DDC (SOT-23)
UNIT
6 PINS
163
26
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
57
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7.5
ψJB
57
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
4
Copyright © 2015–2018, Texas Instruments Incorporated
TPL5110
www.ti.com.cn
ZHCSEK5A –JANUARY 2015–REVISED SEPTEMBER 2018
6.5 Electrical Characteristics(1)
Specifications are for TA= 25°C, VDD-GND = 2.5 V, unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN(2)
TYP(3)
MAX(2) UNIT
POWER SUPPLY
IDD
Supply current(4)
Operation mode
35
50
nA
µA
Digital conversion of external
resistance (Rext)
200
400
TIMER
tIP
Time interval Period
1650 selectable
Time intervals
Minimum time
interval
100
ms
s
Maximum time
interval
7200
Time interval Setting Accuracy(5)
Excluding the precision of Rext
±0.6%
±25
Time interval Setting Accuracy over 1.8 V ≤ VDD ≤ 5.5 V
ppm/V
supply voltage
tOSC
Oscillator Accuracy
–0.5%
0.5%
Oscillator Accuracy over
temperature(6)
–40°C ≤ TA≤ 105°C
1.8 V ≤ VDD ≤ 5.5 V
±100
±0.4
±400 ppm/°C
Oscillator Accuracy over supply
voltage
%/V
Oscillator Accuracy over life time(7)
±0.24%
(6)
tDONE
tDRV
DONE Pulse width
100
ns
DRV Pulse width
DONE signal not received
tIP-50
ms
t_Rext
Time to convert Rext
100
120
ms
DIGITAL LOGIC LEVELS
VIH
VIL
Logic High Threshold DONE pin
0.7 × VDD
V
V
Logic Low Threshold DONE pin
0.3 ×
VDD
Iout = 100 µA
Iout = 1 mA
VDD – 0.3
VDD – 0.7
V
V
V
V
V
VOH
Logic output High Level DRV pin
Logic output Low Level DRV pin
Iout = -100 µA
Iout = –1 mA
0.3
0.7
VOL
VIHM_DRV
Logic High Threshold
DELAY/M_DRV pin
1.5
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which
the device may be permanently degraded, either mechanically or electrically.
(2) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through
correlations using statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
(4) The supply current excludes load and pullup resistor current. Input pins are at GND or VDD.
(5) The accuracy for time interval settings below 1 second is ±100 ms.
(6) This parameter is specified by design and/or characterization and is not tested in production.
(7) Operational life time test procedure equivalent to 10 years.
Copyright © 2015–2018, Texas Instruments Incorporated
5
TPL5110
ZHCSEK5A –JANUARY 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
6.6 Timing Requirements
MIN(1)
NOM(2)
50
MAX(1) UNIT
trDRV
tfDRV
Rise Time DRV(3)
Fall Time DRV(3)
Capacitive load 50 pF
Capacitive load 50 pF
Minimum delay(4)
ns
ns
ns
50
100
tDRV
tDDONE
DONE to DRV delay
(4)
Maximum delay
tM_DRV
tDB
Valid manual MOSFET Power ON
Observation time 30 ms
20
ms
ms
De-bounce manual MOSFET Power
ON
20
(1) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through
correlations using statistical quality control (SQC) method.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
(3) This parameter is specified by design and/or characterization and is not tested in production.
(4) From DRV falling edge.
VDD
EN/
ONE_SHOT
ttDDONE
t
tDONE
DONE
t tDRV
t
t tDRV + tDBt
trDRV
t tIPt
DRV
tfDRV
t tIPt
tR_EXT
DELAY/
M_DRV
ttM_DRV
Figure 1. TPL5110 Timing
6
Copyright © 2015–2018, Texas Instruments Incorporated
TPL5110
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ZHCSEK5A –JANUARY 2015–REVISED SEPTEMBER 2018
6.7 Typical Characteristics
80
80
70
60
50
40
30
20
TA= -40°C
TA= 25°C
TA= 70°C
VDD= 1.8V
VDD= 2.5V
VDD= 3.3V
VDD= 5.5V
70
60
50
40
30
20
TA= 105°C
1.5
1.9
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
5.5
1
-40
-25
-10
5
20
35
50
65
80
95
110
Supply Voltage (V)
Temperature (°C)
Figure 2. IDD vs. VDD
Figure 3. IDD vs. Temperature
2
1.5
1
2
1.5
1
TA= -40°C
TA= 25°C
TA= 70°C
TA= 105°C
VDD= 1.8V
VDD= 2.5V
VDD= 3.3V
VDD= 5.5V
0.5
0
0.5
0
-0.5
-1
-0.5
-1
1.5
1.9
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
-40
-25
-10
5
20
35
50
65
80
95
110
Supply Voltage (V)
Temperature (°C)
Figure 4. Oscillator Accuracy vs. VDD
Figure 5. Oscillator Accuracy vs. Temperature
1000
100
10
40%
POR
REXT READING
35%
30%
25%
20%
15%
10%
5%
1
TIMER MODE
0.1
0.01
0
0
0.1
0.2
0.3
0.4
0.5
Time (s)
0.6
0.7
0.8
0.9
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
Accuracy (%)
number of
1s < tIP ≤ 7200s
observations
>20000
Figure 7. Time interval Setting Accuracy
Figure 6. IDD vs. Time
Copyright © 2015–2018, Texas Instruments Incorporated
7
TPL5110
ZHCSEK5A –JANUARY 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPL5110 is a timer with power gating feature. It is ideal for use in power-cycled applications and provides
selectable timing from 100 ms to 7200 s.
Once configured in timer mode (EN/ONE_SHOT= HIGH) the TPL5110 periodically sends out a DRV signal to a
MOSFET to turn on the µC. If the µC replies with a DONE signal within the programmed time interval (tDRV) the
TPL5110 turns off the µC, otherwise the TPL5110 keeps the µC in the on state for a time equal to tDRV
.
The TPL5110 can work also in a one-shot mode (EN/ONE_SHOT= LOW). In this mode the DRV signal is sent
out just one time at the power on of the TPL5110 to turn on the µC. If the µC replies with a DONE signal within
the programmed time interval (tDRV) the TPL5110 turns off the µC, otherwise the TPL5110 keeps the µC in the
on state for a time equal to tDRV
.
7.2 Functional Block Diagram
VDD
EN/
ONE_SHOT
LOW FREQUENCY
OSCILLATOR
FREQUENCY
DIVIDER
LOGIC
CONTROL
DRV
DONE
DELAY/
M_DRV
DECODER
&
MANUAL RESET
DETECTOR
GND
7.3 Feature Description
The TPL5110 implements a periodical power gating feature or one shot power gating according to the
EN/ONE_SHOT voltage. A manual MOSFET Power ON function is realized by momentarily pulling the
DELAY/M_DRV pin to VDD.
7.3.1 DRV
The gate of the MOSFET is connected to the DRV pin. When DRV=LOW, the MOSFET is turned ON. The pulse
generated at DRV is equal to the selected time interval period, minus 50 ms. It is shorter in the case of a DONE
signal received from the µC. If the DONE signal is not received within the programmed time interval (minus 50
ms), the DRV signal will be high for the last 50 ms of the time interval to turn off the MOSFET before the next
cycle starts.
The default value (after resistance reading) is HIGH. The signal is sent out from the TPL5110 when the
programmed time interval starts. When the DRV is LOW, the manual power ON signal is ignored.
7.3.2 DONE
The DONE pin is driven by a µC to signal that the µC is working properly. The TPL5110 recognizes a valid
DONE signal as a low to high transition. If two or more DONE signals are received within the time interval, only
the first DONE signal is processed. The minimum DONE signal pulse length is 100 ns. When the TPL5110
receives the DONE signal it asserts DRV logic HIGH.
8
Copyright © 2015–2018, Texas Instruments Incorporated
TPL5110
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ZHCSEK5A –JANUARY 2015–REVISED SEPTEMBER 2018
7.4 Device Functional Modes
7.4.1 Start-Up
During start-up, after POR, the TPL5110 executes a one-time measurement of the resistance attached to the
DELAY/M_DRV pin in order to determine the desired time interval for DRV. This measurement interval is tR_EXT
During this measurement a constant current is temporarily flowing into REXT
.
.
Once the reading of the external resistance is complete, the TPL5110 enters automatically in one of the two
modes according to the EN/ONE_SHOT value. The EN/ONE_SHOT pin needs to be hard wired to GND or VDD
according to the required mode of operation.
ttIPt
ttIPt
ttDRV
t
FORCED
DRV
DRV RISING
MISSED
DONE
DONE
EN/
ONE_SHOT
DELAY/
M_DRV
RESISTANCE
READING
POR
Figure 8. Start-Up - Timer Mode
7.4.2 Timer Mode
During timer mode (EN/ONE_SHOT = HIGH), the TPL5110 asserts periodic DRV pulses according to the
programmed time interval. The length of the DRV pulses is set by the receiving of a DONE pulse from the µC.
See Figure 8.
7.4.3 One-Shot Mode
During one-shot mode (EN/ONE_SHOT = LOW), the TPL5110 generates just one pulse at the DRV pin which
lasts according to the programmed time interval. In one-shot mode, other DRV pulses can be triggered using the
DELAY/M_DRV pin. If a valid manual power ON occurs when EN/ONE_SHOT is LOW, the TPL5110 generates
just one pulse at the DRV pin. The duration of the pulse is set by the programmed time interval. Also in this case,
if a DONE signal is received within the programmed time interval (minus 50 ms), the MOSFET connected to the
DRV pin is turned off. See Figure 9 and Figure 10.
ttIP
t
DRV
DONE
EN/
ONE_SHOT
DELAY/
M_DRV
RESISTANCE
READING
POR
Figure 9. Start-Up One-Shot Mode (DONE Received Within tIP)
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TPL5110
ZHCSEK5A –JANUARY 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
Device Functional Modes (continued)
ttIPt
ttDRV
t
FORCED
DRV
DRV RISING
MISSED
DONE
DONE
EN/
ONE_SHOT
DELAY/
M_DRV
RESISTANCE
READING
POR
Figure 10. Start-Up One-Shot Mode (No DONE Received Within tIP)
7.5 Programming
7.5.1 Configuring the Time Interval With the DELAY/M_DRV Pin
The time interval between two adjacent DRV pulses (falling edges, in timer mode) is selectable through an
external resistance (REXT) between the DELAY/M_DRV pin and ground. The resistance (REXT) must be in the
range between 500 Ω and 170 kΩ. At least a 1% precision resistance is recommended. See section Selection of
the External Resistance on how to set the time interval using REXT
.
7.5.2 Manual MOSFET Power ON Applied to the DELAY/M_DRV Pin
If VDD is connected to the DELAY/M_DRV pin, the TPL5110 recognizes this as a manual MOSFET Power ON
condition. In this case the time interval is not set. If the manual MOSFET Power ON is asserted during the POR
or during the reading procedure, the reading procedure is aborted and is restarted as soon as the manual
MOSFET Power ON switch is released. A pulse on the DELAY/M_DRV pin is recognized as a valid manual
MOSFET Power ON only if it lasts at least 20 ms (observation time is 30 ms). The manual MOSFET Power ON
may be implemented using a switch (momentary mechanical action).
If the DRV is already LOW (MOSFET ON) the manual MOSFET Power ON is ignored.
ttIPt
ttIPt
DRV
DONE
EN/
ONE_SHOT
ttM_DRV
t
ttM_DRV
t
ttDB
t
ttM_DRVt
DELAY/
M_DRV
IGNORED M_DRV
DRV ALREADY LOW
VALID M_DRV
NOT VALID M_DRV
Figure 11. Manual MOSFET Power ON in Timer Mode
10
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TPL5110
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ZHCSEK5A –JANUARY 2015–REVISED SEPTEMBER 2018
Programming (continued)
ttIPt
DRV
DONE
EN/
ONE_SHOT
ttM_DRV
t
ttDB
t
ttM_DRVt
DELAY/
M_DRV
VALID M_DRV
NOT VALID M_DRV
Figure 12. Manual MOSFET Power ON in One-Shot Mode
7.5.2.1 DELAY/M_DRV
A resistance in the range between 500 Ω and 170 kΩ must to be connected to the DELAY/M_DRV pin to select a
valid time interval. At the POR and during the reading of the resistance, the DELAY/M_DRV is connected to an
analog signal chain through a mux. After the reading of the resistance, the analog circuit is switched off and the
DELAY/M_DRV is connected to a digital circuit.
In this state, a logic HIGH applied to the DELAY/M_DRV pin is interpreted by the TPL5110 as a manual power
ON. The manual power ON detection is provided with a de-bounce feature (on both edges) which makes the
TPL5110 insensitive to the glitches on the DELAY/M_DRV.
The M_DRV must stay high for at least 20 ms to be valid. Once a valid signal at DELAY/M_DRV is understood
as a manual power on, the DRV signal will be asserted in the next 10 ms. Its duration will be according to the
programmed time interval (minus 50 ms), or less if the DONE is received.
A manual power ON signal resets all the counters. The counters will restart as soon as a valid manual power ON
signal is recognized and the signal at DELAY/M_DRV pin is asserted LOW. Due to the asynchronous nature of
the manual power ON signal and its arbitrary duration, the LOW status of the DRV signal may be affected by an
uncertainty of about ±5 ms.
An extended assertion of a logic HIGH at the DELAY/M_DRV pin will turn on the MOSFET for a time longer than
the programmed time interval. DONE signals received while the DELAY/M_DRV is HIGH are ignored. If the DRV
is already LOW (MOSFET ON) the manual power ON is ignored.
7.5.2.2 Circuitry
The manual Power ON may be implemented using a switch (momentary mechanical action). The TPL5110 offers
two possible approaches according to the power consumption constraints of the application.
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TPL5110
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www.ti.com.cn
Programming (continued)
µC
VOUT
VIN
TPL5110
VDD
EN/
ONE_SHOT
VDD
GND
Battery
POWER MANAGEMENT
DRV
DELAY/
M_DRV
DONE
GPIO
REXT
GND
GND
Figure 13. Manual MOSFET Power ON With SPST Switch
For use cases that do not require the lowest power consumption, using a single-pole single-throw switch may
offer a lower-cost solution. The DELAY/M_DRV pin may be directly connected to VDD with REXT in the circuit.
The current drawn from the supply voltage during the manual power ON is given by VDD/REXT
.
µC
VOUT
TPL5110
VIN
VDD
EN/
ONE_SHOT
VDD
GND
Battery
POWER MANAGEMENT
GND
DRV
DELAY/
M_DRV
DONE
GPIO
REXT
GND
Figure 14. Manual MOSFET Power ON With SPDT Switch
The manual MOSFET Power ON function may also be asserted by switching DELAY/M_DRV from REXT to VDD
using a single-pole double-throw switch, which will provide a lower power solution for the manual power ON,
because no current flows.
7.5.3 Selection of the External Resistance
To set the time interval, the external resistance REXT is selected according to Equation 1:
2
≈
∆
’
÷
- b + b - 4a
2a
(
c -100 T
)
REXT =100
∆
«
÷
◊
where
•
•
•
T is the desired time interval in seconds.
REXT is the resistance value to use in Ω.
a, b, c are coefficients depending on the range of the time interval.
(1)
12
Copyright © 2015–2018, Texas Instruments Incorporated
TPL5110
www.ti.com.cn
ZHCSEK5A –JANUARY 2015–REVISED SEPTEMBER 2018
Programming (continued)
Table 1. Coefficients for Equation 1
Time Interval
Range (s)
SET
a
b
c
1
2
3
4
5
1 <T≤ 5
0.2253
-0.1284
0.1972
0.2617
0.3177
-20.7654
46.9861
570.5679
-2651.8889
692.1201
5 <T≤ 10
10 <T≤ 100
100 <T≤ 1000
T> 1000
-19.3450
-56.2407
-136.2571
5957.7934
34522.4680
EXAMPLE
Required time interval: 8 s
The coefficient set to be selected is the number 2. The formula becomes Equation 2.
2
≈
’
46.9861- 46.9861 +4*0.1284
(
-2561.8889-100*8
)
∆
÷
REXT =100
∆
«
÷
◊
2*0.1284
(2)
The resistance value is 10.18 kΩ.
Table 2 and Table 3 contain example values of tIP and their corresponding value of REXT
.
Table 2. First 9 Time Intervals
Parallel of two 1% tolerance resistors,
tIP (ms)
Resistance (Ω)
Closest real value (Ω)
(kΩ)
100
200
300
400
500
600
700
800
900
500
500
1.0 // 1.0
-
1000
1500
2000
2500
3000
3500
4000
4500
1000
1500
2000
2500
3000
3500
4000
4501
2.43 // 3.92
-
4.42 // 5.76
5.36 // 6.81
4.75 // 13.5
6.19 // 11.3
6.19 // 16.5
Table 3. Most Common Time Intervals Between 1s to 2h
Closest Real Value
Parallel of Two 1% Tolerance
tIP
Calculated Resistance (kΩ)
(kΩ)
Resistors,(kΩ)
7.15 // 19.1
12.4 // 15.0
12.7// 19.1
14.7 // 19.1
16.5 // 19.1
18.2 // 18.7
19.1 // 19.6
11.5 // 8.87
17.8 // 26.7
15.0 // 44.2
16.9 // 97.6
32.4 // 34.8
22.6 // 110.0
28.7 // 66.5
1s
2s
5.20
6.79
5.202
6.788
3s
7.64
7.628
4s
8.30
8.306
5s
8.85
8.852
6s
9.27
9.223
7s
9.71
9.673
8s
10.18
10.68
11.20
14.41
16.78
18.75
20.047
10.180
10.68
9s
10s
20s
30s
40s
50s
11.199
14.405
16.778
18.748
20.047
Copyright © 2015–2018, Texas Instruments Incorporated
13
TPL5110
ZHCSEK5A –JANUARY 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
Table 3. Most Common Time Intervals Between 1s to 2h (continued)
Closest Real Value
Parallel of Two 1% Tolerance
tIP
Calculated Resistance (kΩ)
(kΩ)
Resistors,(kΩ)
1min
2min
3min
4min
5min
6min
7min
8min
9min
10min
20min
30min
40min
50min
1h
22.02
29.35
34.73
39.11
42.90
46.29
49.38
52.24
54.92
57.44
77.57
92.43
104.67
115.33
124.91
149.39
170.00
22.021
29.349
34.729
39.097
42.887
46.301
49.392
52.224
54.902
57.437
77.579
92.233
104.625
115.331
124.856
149.398
170.00
40.2 // 48.7
35.7 // 165.0
63.4 // 76.8
63.4 // 102.0
54.9 // 196.0
75.0 // 121.0
97.6 // 100.0
88.7 // 127.0
86.6 // 150.0
107.0 // 124.0
140.0 // 174.0
182.0 // 187.0
130.0 // 536.00
150.0 // 499.00
221.0 // 287.00
165.0 // 1580.0
340.0 // 340.0
1h30min
2h
7.5.4 Quantization Error
The TPL5110 can generate 1650 discrete timer intervals in the range of 100 ms to 7200 s. The first 9 intervals
are multiples of 100 ms. The remaining 1641 intervals cover the range between 1 s to 7200 s. Because they are
discrete intervals, there is a quantization error associated with each value.
The quantization error can be evaluated according to Equation 3:
(
TDESIRED -TADC
)
Err =100
TDESIRED
where
1
é
ù
TADC = INT
aR2 + bR + c
(
)
D
D
ê
ú
100
ë
û
•
•
REXT
100
RD
=
(3)
REXT is the resistance calculated with Equation 1 and a, b, c are the coefficients of the equation listed in Table 1.
7.5.5 Error Due to Real External Resistance
REXT is a theoretical value and may not be available in standard commercial resistor values. It is possible to
closely approach the theoretical REXT using two or more standard values in parallel. However, standard values
are characterized by a certain tolerance. This tolerance will affect the accuracy of the time interval.
The accuracy can be evaluated using the following procedure:
1. Evaluate the min and max values of REXT (REXT_MIN, REXT_MAX with Equation 1 using the selected commercial
resistance values and their tolerances.
2. Evaluate the time intervals (TADC_MIN[REXT_MIN], TADC_MAX[REXT_MAX]) with the TADC equation mentioned in
Equation 3.
3. Find the errors using Equation 3 with TADC_MIN, TADC_MAX
.
The results of the formula indicate the accuracy of the time interval.
14
Copyright © 2015–2018, Texas Instruments Incorporated
TPL5110
www.ti.com.cn
ZHCSEK5A –JANUARY 2015–REVISED SEPTEMBER 2018
The example below illustrates the procedure.
•
•
Desired time interval, T_desired = 600 s,
Required REXT from Equation 1, REXT= 57.44 kΩ.
From Table 3, REXT can be built with a parallel combination of two commercial values with 1% tolerance: R1 =1
07 kΩ, R2 = 124 kΩ. The uncertainty of the equivalent parallel resistance can be found using Equation 4:
2
2
u
u
R2
≈
∆
R1 ’ ≈
’
÷
uR =R//
+
÷ ∆
//
R1
R2
«
◊ «
◊
where
•
uRn (n=1,2) represent the uncertainty of a resistance (see Equation 5)
(4)
(5)
SPACER
Tolerance
uR =Rn
n
3
The uncertainty of the parallel resistance is 0.82%, which means the value of REXT may range between REXT_MIN
= 56.96 kΩ and REXT_MAX = 57.90 kΩ.
Using these value of REXT, the digitized timer intervals calculated by TADC equation mentioned in Equation 3 are
respectively TADC_MIN = 586.85 s and TADC_MAX = 611.3 s, giving an error range of –1.88% / +2.19%. The
asymmetry of the error range is due to the quadratic transfer function of the resistance digitizer.
Copyright © 2015–2018, Texas Instruments Incorporated
15
TPL5110
ZHCSEK5A –JANUARY 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
In battery-powered applications, one design constraint is the need for low current consumption. The TPL5110 is
designed for applications where there is a need to monitor environmental conditions at a fixed time interval. Often
in these applications a watchdog or other internal timer in a µC is used to implement a wake-up function.
Typically, the power consumption of these functions is not optimized. Using the TPL5110 to implement a
periodical power gating of the µC or of the entire system the current consumption will be only tens of nA.
8.2 Typical Application
The TPL5110 can be used in environment sensor nodes such as humidity and temperature sensor node. The
sensor node has to measure the humidity and the temperature and transmit the data through a low power RF
micro such as the CC2531. The temperature and the humidity in home application do not change so fast, so the
measurement and the transmission of the data can be done at very low rate, such as every 30 seconds. The RF
micro should spend most of the time in counting the elapsed time, but using the TPL5110 it is possible to
complete turn off the RF micro and extend the battery life. The TPL5110 will turn on the RF micro when the
programmed time interval elapses or for debug purpose with the manual MOSFET Power ON switch.
DC-DC
BOOST
VIN
VOUT
ENB
GND
CC2531
Rp
100k
Rp
100k
RF
TPL5110
HDC1000
VDD
EN/
ONE_SHOT
VDD
GND
VDD
DRV
SCL
SDA
GND
SCL
+
DELAY/
M_DRV
Lithium
ion battery
DONE
GPIO
SDA
GND
-
Figure 15. Sensor Node
8.2.1 Design Requirements
The design is driven by the low current consumption constraint. The data are usually acquired on a rate which is
in the range between 30 s and 60 s. The highest necessity is the maximization of the battery life. The TPL5110
helps achieve this goal because it allows turning off the RF micro.
8.2.2 Detailed Design Procedure
When the focal constraint is the battery life, the selection of a low power voltage regulator and low leakage
MOSFET to power gate the µC is mandatory. The first step in the design is the calculation of the power
consumption of each device in the different mode of operations. An example is the HDC1000, in measurement
mode the RF micro is in normal operation and transmission. The different modes offer the possibility to select the
appropriate time interval which respect the application constraint and maximize the life of the battery.
16
Copyright © 2015–2018, Texas Instruments Incorporated
TPL5110
www.ti.com.cn
ZHCSEK5A –JANUARY 2015–REVISED SEPTEMBER 2018
Typical Application (continued)
8.2.3 Application Curve
Without TPL5110
With TPL5110
Time
Figure 16. Effect of TPL5110 on Current Consumption
9 Power Supply Recommendations
The TPL5110 requires a voltage supply within 1.8 V and 5.5 V. A multilayer ceramic bypass X7R capacitor of 0.1
μF between VDD and GND pin is recommended.
10 Layout
10.1 Layout Guidelines
The DELAY/M_DRV pin is sensitive to parasitic capacitance. TI suggests that the traces connecting the
resistance on this pin to GROUND be kept as short as possible to minimize parasitic capacitance. This
capacitance can affect the initial set up of the time interval. Signal integrity on the DRV pin is also improved by
keeping the trace length between the TPL5110 and the gate of the MOSFET short to reduce the parasitic
capacitance. The EN/ONE_SHOT needs to be tied to GND or VDD with short traces.
版权 © 2015–2018, Texas Instruments Incorporated
17
TPL5110
ZHCSEK5A –JANUARY 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
10.2 Layout Example
Figure 17. Layout
18
版权 © 2015–2018, Texas Instruments Incorporated
TPL5110
www.ti.com.cn
ZHCSEK5A –JANUARY 2015–REVISED SEPTEMBER 2018
11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015–2018, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPL5110DDCR
TPL5110DDCT
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
6
6
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 105
-40 to 105
ZALX
ZALX
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPL5110DDCR
TPL5110DDCT
SOT-
23-THIN
DDC
DDC
6
6
3000
250
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SOT-
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
23-THIN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPL5110DDCR
TPL5110DDCT
SOT-23-THIN
SOT-23-THIN
DDC
DDC
6
6
3000
250
208.0
208.0
191.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DDC0006A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
C
0 -8 TYP
0.25
GAGE PLANE
SEATING PLANE
0.20
0.12
TYP
0.6
0.3
TYP
4214841/C 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/C 04/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/C 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2022，德州仪器 (TI) 公司
相关型号：
TPL5110-Q1
具有手动复位功能和 MOS 驱动器的汽车 AEC-Q100 毫微功耗系统计时器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPL5110QDDCRQ1
具有手动复位功能和 MOS 驱动器的汽车 AEC-Q100 毫微功耗系统计时器
| DDC | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPL5110QDDCTQ1
具有手动复位功能和 MOS 驱动器的汽车 AEC-Q100 毫微功耗系统计时器
| DDC | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPL5111
用于占空比应用电源门控的超低功耗系统计时器 (35nA)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPL5111DDCR
用于占空比应用电源门控的超低功耗系统计时器 (35nA) | DDC | 6 | -40 to 105Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPL5111DDCT
用于占空比应用电源门控的超低功耗系统计时器 (35nA) | DDC | 6 | -40 to 105Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPL521-2XGRSMT&R
Transistor Output Optocoupler,Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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ISOCOM
TPL521-4XGB
Transistor Output Optocoupler,Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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ISOCOM
TPL7407LA
30V、7 通道 NMOS 阵列低侧驱动器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPL7407LA-Q1
30V、7 通道汽车类 NMOS 阵列低侧驱动器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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