TPS2020DRG4 [TI]
POWER-DISTRIBUTION SWITCHES; 配电开关
| 型号： | TPS2020DRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | POWER-DISTRIBUTION SWITCHES |
| 文件： | 总29页 (文件大小：812K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2020, TPS2021
TPS2022, TPS2023, TPS2024
www.ti.com
SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
POWER-DISTRIBUTION SWITCHES
1
FEATURES
•
UL Listed - File No. E169910
•
33-mΩ (5-V Input) High-Side MOSFET Switch
Short-Circuit and Thermal Protection
Overcurrent Logic Output
D OR P PACKAGE
(TOP VIEW)
•
•
•
•
•
•
•
•
•
•
•
GND
IN
OUT
OUT
OUT
OC
1
2
3
4
8
7
6
5
Operating Range . . . 2.7 V to 5.5 V
Logic-Level Enable Input
IN
Typical Rise Time . . . 6.1 ms
EN
Undervoltage Lockout
Maximum Standby Supply Current . . . 10 μA
No Drain-Source Back-Gate Diode
Available in 8-Pin SOIC and PDIP Packages
Ambient Temperature Range, –40°C to 85°C
2-kV Human-Body-Model, 200-V
Machine-Model ESD Protection
DESCRIPTION
The TPS202x family of power distribution switches is intended for applications where heavy capacitive loads and
short circuits are likely to be encountered. These devices are 50-mΩ N-channel MOSFET high-side power
switches. The switch is controlled by a logic enable compatible with 5-V logic and 3-V logic. Gate drive is
provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize
current surges during switching. The charge pump requires no external components and allows operation from
supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS202x limits the output
current to a safe level by switching into a constant-current mode, pulling the overcurrent (OC) logic output low.
When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the
junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a
thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch
remains off until valid input voltage is present.
The TPS202x devices differ only in short-circuit current threshold. The TPS2020 limits at 0.3-A load, the
TPS2021 at 0.9-A load, the TPS2022 at 1.5-A load, the TPS2023 at 2.2-A load, and the TPS2024 at 3-A load
(see Available Options). The TPS202x is available in an 8-pin small-outline integrated-circuit (SOIC) package
and in an 8-pin dual in-line package (DIP) and operates over a junction temperature range of –40°C to 125°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1998–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS2020, TPS2021
TPS2022, TPS2023, TPS2024
www.ti.com
SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
Table 1. AVAILABLE OPTIONS
PACKAGED DEVICES
RECOMMENDED MAXIMUM
CONTINUOUS LOAD
CURRENT (A)
TYPICAL SHORT-CIRCUIT
CURRENT LIMIT AT 25°C
(A)
TA
ENABLE
SMALL OUTLINE
(D)(1)
PLASTIC DIP
(P)
0.2
0.6
1
0.3
0.9
1.5
2.2
3
TPS2020D
TPS2021D
TPS2022D
TPS2023D
TPS2024D
TPS2020P
TPS2021P
TPS2022P
TPS2023P
TPS2024P
–40°C to 85°C
Active low
1.5
2
(1) The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2020DR)
TPS2020 FUNCTIONAL BLOCK DIAGRAM
Power Switch
†
CS
IN
OUT
Charge
Pump
Current
Limit
EN
Driver
OC
UVLO
Thermal
Sense
GND
†
Current Sense
TERMINAL FUNCTIONS
TERMINAL
NO.
I/O
DESCRIPTION
NAME
D OR P
EN
4
1
I
I
Enable input. Logic-low turns on power switch.
Ground
GND
IN
2, 3
5
I
Input voltage
OC
O
O
Overcurrent. Logic output, active-low
Power-switch output
OUT
6, 7, 8
2
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Copyright © 1998–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS2020 TPS2021 TPS2022 TPS2023 TPS2024
TPS2020, TPS2021
TPS2022, TPS2023, TPS2024
www.ti.com
SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
DETAILED DESCRIPTION
POWER SWITCH
The power switch is an N-channel MOSFET with a maximum on-state resistance of 50 mΩ (VI(IN) = 5 V).
Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when
disabled.
CHARGE PUMP
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
DRIVER
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall
times of the output voltage. The rise and fall times are typically in the 2-ms to 9-ms range.
ENABLE (EN)
The logic enable disables the power switch, the bias for the charge pump, driver, and other circuitry to reduce the
supply current to less than 10 μA when a logic-high is present on EN. A logic-zero input on EN restores bias to
the drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOS
logic levels.
OVERCURRENT (OC)
The OC open drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output remains asserted until the overcurrent or overtemperature condition is removed.
CURRENT SENSE
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver, in turn, reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant-current mode and holds the current constant while
varying the voltage on the load.
THERMAL SENSE
An internal thermal-sense circuit shuts off the power switch when the junction temperature rises to approximately
140°C. Hysteresis is built into the thermal sense circuit. After the device has cooled approximately 20°C, the
switch turns back on. The switch continues to cycle off and on until the fault is removed.
UNDERVOLTAGE LOCKOUT
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
Copyright © 1998–2007, Texas Instruments Incorporated
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Product Folder Link(s): TPS2020 TPS2021 TPS2022 TPS2023 TPS2024
TPS2020, TPS2021
TPS2022, TPS2023, TPS2024
www.ti.com
SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
(2)
VI(IN)
Input voltage range
–0.3 V to 6 V
(2)
VO(OUT)
VI(EN)
Output voltage range
–0.3 V to VI(IN) + 0.3 V
–0.3 V to 6 V
Internally limited
See Dissipation Rating Table
–40°C to 125°C
–65°C to 150°C
260°C
Input voltage range
IO(OUT)
Continuous output current
Continuous total power dissipation
Operating virtual junction temperature range
Storage temperature range
TJ
Tstg
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds
Electrostatic discharge (ESD) protection:
Human body model
2 kV
Machine model
200 V
Charged device model (CDM)
750 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
DISSIPATION RATING TABLE
T
A ≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
POWER RATING
D
P
725 mW
5.8 mW/°C
9.4 mW/°C
464 mW
752 mW
377 mW
611 mW
1175 mW
RECOMMENDED OPERATING CONDITIONS
MIN
2.7
0
MAX UNIT
VI(IN)
5.5
5.5
0.2
0.6
1
V
V
Input voltage
VI(EN)
TPS2020
0
TPS2021
TPS2022
TPS2023
TPS2024
0
IO
Continuous output current
0
A
0
1.5
2
0
TJ
Operating virtual junction temperature
–40
125
°C
4
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Copyright © 1998–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS2020 TPS2021 TPS2022 TPS2023 TPS2024
TPS2020, TPS2021
TPS2022, TPS2023, TPS2024
www.ti.com
SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = rated current, EN = 0 V (unless otherwise noted)
PARAMETER
POWER SWITCH
TEST CONDITIONS(1)
MIN
TYP MAX
UNIT
VI(IN) = 5 V, TJ = 25°C, IO = 1.8 A
33
38
44
37
43
51
30
35
39
33
39
44
6.1
8.6
3.4
3
36
46
50
41
52
61
34
41
47
37
46
56
VI(IN) = 5 V, TJ = 85°C, IO = 1.8 A
VI(IN) = 5 V, TJ = 125°C, IO = 1.8 A
VI(IN) = 3.3 V, TJ = 25°C, IO = 1.8 A
VI(IN) = 3.3 V, TJ = 85°C, IO = 1.8 A
VI(IN) = 3.3 V, TJ = 125°C, IO = 1.8 A
VI(IN) = 5 V, TJ = 25°C, IO = 0.18 A
Static drain-source on-state
resistance
rDS(on)
mΩ
VI(IN) = 5 V, TJ = 85°C, IO = 0.18 A
VI(IN) = 5 V, TJ = 125°C, IO = 0.18 A
VI(IN) = 3.3 V, TJ = 25°C, IO = 0.18 A
VI(IN) = 3.3 V, TJ = 85°C, IO = 0.18 A
VI(IN) = 3.3 V, TJ = 125°C, IO = 0.18 A
VI(IN) = 5.5 V, CL = 1 μF, TJ = 25°C, RL = 10 Ω
VI(IN) = 2.7 V, CL = 1 μF, TJ = 25°C, RL = 10 Ω
VI(IN) = 5.5 V, CL = 1 μF, TJ = 25°C, RL = 10 Ω
VI(IN) = 2.7 V, CL = 1 μF, TJ = 25°C, RL = 10 Ω
tr
tf
Rise time, output
Fall time, output
ms
ms
ENABLE INPUT (EN)
VIH
High-level input voltage
2.7 V≤ VI(IN) ≤ 5.5 V
4.5 V ≤ VI(IN) ≤ 5.5 V
2.7 V ≤ VI(IN) ≤ 4.5 V
EN= 0 V or EN = VI(IN)
CL = 100 μF, RL= 10 Ω
CL = 100 μF, RL= 10 Ω
2
V
V
0.8
0.5
0.5
20
VIL
Low-level input voltage
II
Input current
Turnon time
Turnoff time
–0.5
μA
ms
ton
toff
40
CURRENT LIMIT
TPS2020
0.22
0.66
1.1
0.3
0.9
1.5
2.2
3
0.4
1.1
1.8
2.7
3.8
TPS2021
TJ = 25°C, VI = 5.5 V,
IOS
Short-circuit output current
OUT connected to GND,
TPS2022
TPS2023
TPS2024
A
Device enabled into short circuit
1.65
2.2
SUPPLY CURRENT
TJ = 25°C
0.3
1
10
Supply current, low-level output
No load on OUT EN = VI(IN)
No load on OUT EN = 0 V
μA
–40°C ≤ TJ ≤
125°C
TJ = 25°C
58
75
75
Supply current, high-level output
Leakage current
μA
μA
–40°C ≤ TJ ≤
125°C
100
OUT connected
EN = VI(IN)
–40°C ≤ TJ ≤
125°C
10
to ground
UNDERVOLTAGE LOCKOUT
Low-level input voltage
Hysteresis
2
2.5
V
TJ = 25°C
100
mV
OVERCURRENT (OC)
Output low voltage
Off-state current(2)
IO = 10 mA, VOL(OC)
VO = 5 V, VO = 3.3 V
0.4
1
V
μA
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
(2) Specified by design, not production tested.
Copyright © 1998–2007, Texas Instruments Incorporated
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Product Folder Link(s): TPS2020 TPS2021 TPS2022 TPS2023 TPS2024
TPS2020, TPS2021
TPS2022, TPS2023, TPS2024
www.ti.com
SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
PARAMETER MEASURMENT INFORMATION
OUT
t
f
t
r
RL
CL
V
90%
10%
O(OUT)
90%
10%
TEST CIRCUIT
50%
90%
50%
V
I(EN)
t
off
t
on
V
O(OUT)
10%
VOLTAGE WAVEFORMS
Figure 1. Test Circuit and Voltage Waveforms
6
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Copyright © 1998–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS2020 TPS2021 TPS2022 TPS2023 TPS2024
TPS2020, TPS2021
TPS2022, TPS2023, TPS2024
www.ti.com
SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
PARAMETER MEASURMENT INFORMATION (continued)
TABLE OF TIMING DIAGRAMS
FIGURE
Turnon Delay and Rise TIme
2
Turnoff Delay and Fall Time
3
Turnon Delay and Rise TIme with 1-μF Load
Turnoff Delay and Rise TIme with 1-μF Load
Device Enabled into Short
4
5
6
7, 8, 9, 10,
TPS2020, TPS2021, TPS2022, TPS2023, and TPS2024, Ramped Load on Enabled Device
11
12
13
14
15
16
17
18
19
20
21
22
TPS2024, Inrush Current
7.9-Ω Load Connected to an Enabled TPS2020 Device
3.7-Ω Load Connected to an Enabled TPS2020 Device
3.7-Ω Load Connected to an Enabled TPS2021 Device
2.6-Ω Load Connected to an Enabled TPS2021 Device
2.6-Ω Load Connected to an Enabled TPS2022 Device
1.2-Ω Load Connected to an Enabled TPS2022 Device
1.2-Ω Load Connected to an Enabled TPS2023 Device
0.9-Ω Load Connected to an Enabled TPS2023 Device
0.9-Ω Load Connected to an Enabled TPS2024 Device
0.5-Ω Load Connected to an Enabled TPS2024 Device
V
I(EN)
(5 V/div)
V
I(EN)
(5 V/div)
V
I(EN)
V
I(EN)
V
R
T
A
= 5 V
= 27 Ω
= 25°C
I(IN)
L
V
(2 V/div)
V
(2 V/div)
O(OUT)
O(OUT)
V
R
T
A
= 5 V
= 27 Ω
= 25°C
IN
V
V
L
O(OUT)
O(OUT)
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18
t − Time − ms
Figure 2. Turnon Delay and Rise Time
20
t − Time − ms
Figure 3. Turnoff Delay and Fall Time
Copyright © 1998–2007, Texas Instruments Incorporated
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Product Folder Link(s): TPS2020 TPS2021 TPS2022 TPS2023 TPS2024
TPS2020, TPS2021
TPS2022, TPS2023, TPS2024
www.ti.com
SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
V
I(EN)
(5 V/div)
V
I(EN)
(5 V/div)
V
I(EN)
V
I(EN)
V
(2 V/div)
V
(2 V/div)
V
O(OUT)
O(OUT)
V
= 5 V
= 1 µF
= 27 Ω
= 25°C
= 5 V
I(IN)
I(IN)
C
R
T
C
L
= 1 µF
L
L
R = 27 Ω
V
V
L
O(OUT)
O(OUT)
T
A
= 25°C
A
0
2
0
2
4
6
8
t − Time − ms
Figure 4. Turnon Delay and Rise Time with 1-μF Load
10 12 14 16 18
20
4
6
8
10 12 14 16 18
t − Time − ms
Figure 5. Turnoff Delay and Fall Time with 1-μF Load
20
V
O(OC)
(5 V/div)
V
I(EN)
V
I(EN)
(5 V/div)
V
O(OC)
V
T
= 5 V
= 25°C
V
T
A
= 5 V
= 25°C
I(IN)
I(IN)
A
TPS2024
TPS2023
TPS2022
I
(500 mA/div)
O(OUT)
TPS2021
TPS2020
I
I
O(OUT)
O(OUT)
I
(1 A/div)
O(OUT)
0
20 40 60 80 100 120 140 160 180 200
t − Time − ms
0
1
2
3
4
5
6
7
8
9
10
t − Time − ms
Figure 6. Device Enabled Into Short
Figure 7. TPS2020, Ramped Load on Enabled Device
8
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Product Folder Link(s): TPS2020 TPS2021 TPS2022 TPS2023 TPS2024
TPS2020, TPS2021
TPS2022, TPS2023, TPS2024
www.ti.com
SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
V
O(OC)
(5 V/div)
V
O(OC)
(5 V/div)
V
O(OC)
V
O(OC)
V
T
A
= 5 V
= 25°C
V
T
= 5 V
= 25°C
I(IN)
I(IN)
A
I
(1 A/div)
O(OUT)
I
(1 A/div)
O(OUT)
I
I
O(OUT)
O(OUT)
0
20 40 60 80 100 120 140 160 180 200
t − Time − ms
0
20 40 60 80 100 120 140 160 180 200
t − Time − ms
Figure 8. TPS2021, Ramped Load on Enabled Device
Figure 9. TPS2022, Ramped Load on Enabled Device
V
O(OC)
(5 V/div)
V
O(OC)
(5 V/div)
V
O(OC)
V
O(OC)
V
T
A
= 5 V
= 25°C
I(IN)
V
T
A
= 5 V
= 25°C
I(IN)
I
(1 A/div)
I
(1 A/div)
O(OUT)
O(OUT)
I
I
O(OUT)
O(OUT)
0
20 40 60 80 100 120 140 160 180 200
t − Time − ms
0
20 40 60 80 100 120 140 160 180 200
t − Time − ms
Figure 10. TPS2023, Ramped Load on Enabled Device
Figure 11. TPS2024, Ramped Load on Enabled Device
Copyright © 1998–2007, Texas Instruments Incorporated
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TPS2020, TPS2021
TPS2022, TPS2023, TPS2024
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SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
V
I(EN)
V
O(OC)
(5 V/div)
V
I(EN)
(5 V/div)
V
O(OC)
I
(200 mA/div)
O(OUT)
470 µF
150 µF
I
(500 mA/div)
I(IN)
V
I(IN)
= 5 V
R
T
A
= 7.9 Ω
= 25°C
I
I
L
I(IN)
O(OUT)
R = 10 Ω
L
47 µF
T
= 25°C
A
0
1
2
3
4
5
6
7
8
9
10
0
200 400 600 800 1000 1200 1400 1600 1800 2000
t − Time − ms
Figure 12. TPS2024, Inrush Current
t − Time − µs
Figure 13. 7.9-Ω Load Connected to an Enabled TPS2020
Device
V
O(OC)
(5 V/div)
V
O(OC)
(5 V/div)
V
O(OC)
V
O(OC)
V
R
T
= 5 V
= 3.7 Ω
= 25°C
V
= 5 V
= 3.7 Ω
= 25°C
I(IN)
I(IN)
R
T
L
L
A
A
I
(500 mA/div)
O(OUT)
I
(1 A/div)
O(OUT)
I
I
O(OUT)
O(OUT)
0
50 100 150 200 250 300 350 400 450 500
0
200 400 600 800 1000 1200 1400 1600 1800 2000
t − Time − µs
t − Time − µs
Figure 14. 3.7-Ω Load Connected to an Enabled TPS2020
Figure 15. 3.7-Ω Load Connected to an Enabled TPS2021
Device
Device
10
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Product Folder Link(s): TPS2020 TPS2021 TPS2022 TPS2023 TPS2024
TPS2020, TPS2021
TPS2022, TPS2023, TPS2024
www.ti.com
SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
V
O(OC)
V
O(OC)
(5 V/div)
V
O(OC)
(5 V/div)
V
O(OC)
V
= 5 V
= 2.6 Ω
= 25°C
V
= 5 V
= 2.6 Ω
= 25°C
I(IN)
I(IN)
R
T
R
T
L
L
A
A
I
(1 A/div)
I
(1 A/div)
O(OUT)
O(OUT)
I
I
O(OUT)
O(OUT)
0
50 100 150 200 250 300 350 400 450 500
0
200 400 600 800 1000 1200 1400 1600 1800 2000
t − Time − µs
t − Time − µs
Figure 16. 2.6-Ω Load Connected to an Enabled TPS2021
Figure 17. 2.6-Ω Load Connected to an Enabled TPS2022
Device
Device
V
O(OC)
(5 V/div)
V
O(OC)
(5 V/div)
V
O(OC)
V
O(OC)
V
R
T
A
= 5 V
= 1.2 Ω
= 25°C
I(IN)
L
I
(1 A/div)
O(OUT)
I
(2 A/div)
O(OUT)
V
R
T
A
= 5 V
= 1.2 Ω
= 25°C
I(IN)
I
I
O(OUT)
O(OUT)
L
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
t − Time − µs
Figure 18. 1.2-Ω Load Connected to an Enabled TPS2022
Figure 19. 1.2-Ω Load Connected to an Enabled TPS2023
Device
Device
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TPS2020, TPS2021
TPS2022, TPS2023, TPS2024
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SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
V
O(OC)
(5 V/div)
V
O(OC)
(5 V/div)
V
O(OC)
V
O(OC)
V
= 5 V
= 0.9 Ω
= 25°C
V
R
T
= 5 V
= 0.9 Ω
= 25°C
I(IN)
I(IN)
R
T
L
L
A
A
I
(2 A/div)
O(OUT)
I
(5 A/div)
O(OUT)
I
I
O(OUT)
O(OUT)
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
t − Time − µs
Figure 20. 0.9-Ω Load Connected to an Enabled TPS2023
Figure 21. 0.9-Ω Load Connected to an Enabled TPS2024
Device
Device
V
O(OC)
(5 V/div)
V
O(OC)
V
R
T
A
= 5 V
= 0.5 Ω
= 25°C
I(IN)
L
I
(5 A/div)
O(OUT)
I
O(OUT)
0
50 100 150 200 250 300 350 400 450 500
t − Time − µs
Figure 22. 0.5-Ω Load Connected to an Enabled TPS2024
Device
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TPS2022, TPS2023, TPS2024
www.ti.com
SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
23
td(on)
td(off)
tr
Turnon delay time
vs Output voltage
Turnoff delay time
Rise time
vs Input voltage
24
vs Load current
25
tf
Fall time
vs Load current
26
Supply current (enabled)
Supply current (disabled)
Supply current (enabled)
Supply current (disabled)
vs Junction temperature
vs Junction temperature
vs Input voltage
27
28
29
vs Input voltage
30
vs Input voltage
31
IOS
Short-circuit current limit
vs Junction temperature
vs Input voltage
32
33
vs Junction temperature
vs Input voltage
34
rDS(on)
Static drain-source on-state resistance
Input voltage
35
vs Junction temperature
Undervoltage lockout
36
VI
37
TURNON DELAY TIME
vs
OUTPUT VOLTAGE
TURNOFF DELAY TIME
vs
INPUT VOLTAGE
7.5
7
18
T
C
= 25°C
= 1 µF
A
T
C
= 25°C
= 1 µF
A
L
L
6.5
6
17.5
17
5.5
5
4.5
16.5
16
4
3.5
2.5
3
3.5
4
4.5
5
5.5
6
2.5
3
3.5
4
4.5
5
5.5
6
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 23.
Figure 24.
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TPS2022, TPS2023, TPS2024
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SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
RISE TIME
vs
LOAD CURRENT
FALL TIME
vs
LOAD CURRENT
6.5
3.5
T
C
= 25°C
= 1 µF
A
T
C
= 25°C
= 1 µF
A
L
L
3.25
3
6
5.5
2.75
2.5
5
0
0.5
1
1.5
2
0
0.5
1
1.5
2
I − Load Current − A
L
I − Load Current − A
L
Figure 25.
Figure 26.
SUPPLY CURRENT (ENABLED)
vs
JUNCTION TEMPERATURE
SUPPLY CURRENT (DISABLED)
vs
JUNCTION TEMPERATURE
75
65
5
4
3
2
V
= 5.5 V
I(IN)
V
= 5 V
I(IN)
V
= 5.5 V
I(IN)
V
I(IN)
= 5 V
55
1
V
I(IN)
= 4 V
V
= 4 V
45
35
I(IN)
V
= 3.3 V
I(IN)
V
= 3.3 V
I(IN)
0
V
= 2.7 V
I(IN)
V
= 2.7 V
I(IN)
−1
−50 −25
0
25
50
75
100 125 150
−50 −25
0
25
50
75
100
150
125
T − Junction Temperature − °C
J
T − Junction Temperature − °C
J
Figure 27.
Figure 28.
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TPS2020, TPS2021
TPS2022, TPS2023, TPS2024
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SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
SUPPLY CURRENT (ENABLED)
SUPPLY CURRENT (DISABLED)
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
75
65
5
4
3
2
T = 125°C
J
T = 125°C
J
T = 85°C
J
T = 85°C
J
55
45
1
T = 25°C
J
T = 25°C
J
0
T = 0°C
J
T = 0°C
J
T = −40°C
J
T = −40°C
J
35
−1
2.5
3
3.5
4
4.5
5
5.5
6
2.5
3
3.5
4
4.5
5
5.5
6
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 29.
Figure 30.
SHORT-CIRCUIT CURRENT LIMIT
SHORT-CIRCUIT CURRENT LIMIT
vs
vs
INPUT VOLTAGE
JUNCTION TEMPERATURE
3.5
3.5
T
A
= 25°C
TPS2024
TPS2024
3
3
2.5
2.5
TPS2023
TPS2022
TPS2023
TPS2022
2
1.5
1
2
1.5
1
TPS2021
TPS2020
TPS2021
TPS2020
0.5
0.5
0
0
2
3
4
5
6
−50
−25
0
25
50
75
100
V − Input Voltage − V
I
T − Junction Temperature − °C
J
Figure 31.
Figure 32.
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TPS2022, TPS2023, TPS2024
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SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
vs
INPUT VOLTAGE
JUNCTION TEMPERATURE
60
60
I
O
= 0.18 A
I
O
= 0.18 A
50
40
50
40
V = 2.7 V
I
T = 125°C
J
V = 3.3 V
I
T = 25°C
J
30
20
V = 5.5 V
30
20
I
T = −40°C
J
−50 −25
0
25
50
75 100 125 150
2.5
3
3.5
4
4.5
5
5.5
6
T − Junction Temperature − °C
J
V − Input Voltage − V
I
Figure 33.
Figure 34.
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
vs
INPUT VOLTAGE
JUNCTION TEMPERATURE
60
50
40
60
I
O
= 1.8 A
I
O
= 1.8 A
50
40
T = 125°C
J
V = 3.3 V
I
V = 4 V
I
V = 5.5 V
I
T = 25°C
J
T = −40°C
J
30
20
30
20
3
3.5
4
4.5
5
5.5
6
−50 −25
0
25
50
75 100 125 150
V − Input Voltage − V
I
T − Junction Temperature − °C
J
Figure 35.
Figure 36.
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TPS2020, TPS2021
TPS2022, TPS2023, TPS2024
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SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
UNDERVOLTAGE LOCKOUT
2.5
2.4
2.3
Start Threshold
Stop Threshold
2.2
2.1
2
−50
0
50
100
150
T − Temperature − °C
J
Figure 37.
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TPS2022, TPS2023, TPS2024
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SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
APPLICATION INFORMATION
TPS2024
2,3
0.1 µF
Power Supply
2.7 V to 5.5 V
IN
6,7,8
Load
OUT
10 kΩ
0.1 µF
22 µF
5
4
OC
EN
GND
1
Figure 38. Typical Application
POWER SUPPLY CONSIDERATIONS
A 0.01-μF to 0.1-μF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output and input pins is recommended when the output load is
heavy. This precaution reduces power supply transients that may cause ringing on the input. Additionally,
bypassing the output with a 0.01-μF to 0.1-μF ceramic capacitor improves the immunity of the device to
short-circuit transients.
OVERCURRENT
A sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the
series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant
output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present
long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied, see Figure 6. The TPS202x senses the short and
immediately switches into a constant-current output.
In the second condition, the excessive load occurs while the device is enabled. At the instant the excessive load
occurs, very high currents may flow for a short time before the current-limit circuit can react (see Figures 13–22).
After the current-limit circuit has tripped (reached the overcurrent trip threshhold) the device switches into
constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figures 7–11). The TPS202x is capable of delivering current up to the current-limit threshold
without damaging the device. Once the threshold has been reached, the device switches into its constant-current
mode.
OC RESPONSE
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output remains asserted until the overcurrent or overtemperature condition is removed.
Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from
the inrush current flowing through the device, charging the downstream capacitor. An RC filter can be connected
to the OC pin to reduce false overcurrent reporting. Using low-ESR electrolytic capacitors on the output lowers
the inrush current flow through the device during hot-plug events by providing a low impedance energy source,
thereby reducing erroneous overcurrent reporting.
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TPS2020, TPS2021
TPS2022, TPS2023, TPS2024
www.ti.com
SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
TPS202x
GND
TPS202x
V+
V+
OUT
OUT
OUT
OC
GND
OUT
OUT
OUT
OC
R
pullup
IN
IN
R
pullup
IN
IN
R
filter
EN
EN
C
filter
Figure 39. Typical Circuit for OC Pin and RC Filter for Damping Inrush OC Responses
POWER DISSIPATION AND JUNCTION TEMPERATURE
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to those of power packages; it is
good design practice to check power dissipation and junction temperature. The first step is to find rDS(on) at the
input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of
interest and read rDS(on) from Figures 33–36. Next, calculate the power dissipation using:
PD = rDS(on) × I2
Finally, calculate the junction temperature:
TJ = PD × RθJA + TA
where:
TA = Ambient temperature °C
RθJA = Thermal resistance—SOIC = 172°C/W, PDIP = 106°C/W
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get an acceptable answer.
THERMAL PROTECTION
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS202x into constant current mode, which causes the voltage
across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal to
the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The protection
circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal sense
circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continues
to cycle in this manner until the load fault or input power is removed.
UNDERVOLTAGE LOCKOUT (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at powerup. Whenever the input voltage
falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of hot-insertion
systems where it is not possible to turn off the power switch before input power is removed. The UVLO also
keeps the switch from being turned on until the power supply has reached at least 2 V, even if the switch is
enabled. Upon reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and voltage
overshoots.
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SLVS175C–DECEMBER 1998–REVISED SEPTEMBER 2007
GENERIC HOT-PLUG APPLICATIONS (See Figure 40)
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen by
the main power supply and the card being inserted. The most effective way to control these surges is to limit and
slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Because of the controlled rise times and fall times of the TPS202x series, these devices can
be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of
the TPS202x also ensures the switch is off after the card has been removed, and the switch remains off during
the next insertion. The UVLO feature ensures a soft start with a controlled rise time for every insertion of the card
or module.
PC Board
TPS2024
Power
Supply
Block of
Circuitry
GND
OUT
OUT
OUT
OC
IN
2.7 V to 5.5 V
0.1 µF
1000 µF
Optimum
IN
EN
Overcurrent Response
Figure 40. Typical Hot-Plug Implementation
By placing the TPS202x between the VCC input and the rest of the circuitry, the input power reaches this device
first after insertion. The typical rise time of the switch is approximately 9 ms, providing a slow voltage ramp at the
output of the device. This implementation controls system surge currents and provides a hot-plugging
mechanism for any device.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS2020D
TPS2020DG4
TPS2020DR
TPS2020DRG4
TPS2021D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
8
8
8
8
8
8
8
8
75
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
Purchase Samples
Purchase Samples
Request Free Samples
Request Free Samples
Purchase Samples
Purchase Samples
2500
2500
75
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TPS2021DG4
TPS2021DR
TPS2021DRG4
75
Green (RoHS
& no Sb/Br)
2500
2500
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TPS2021P
TPS2021PE4
TPS2022D
ACTIVE
ACTIVE
ACTIVE
PDIP
PDIP
SOIC
P
P
D
8
8
8
50
50
75
Pb-Free (RoHS)
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
Purchase Samples
Green (RoHS
& no Sb/Br)
Request Free Samples
TPS2022DG4
TPS2022DR
TPS2022DRG4
TPS2023D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
8
8
8
8
8
8
8
75
2500
2500
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
Purchase Samples
Purchase Samples
Request Free Samples
Request Free Samples
Purchase Samples
Purchase Samples
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TPS2023DG4
TPS2023DR
TPS2023DRG4
75
Green (RoHS
& no Sb/Br)
2500
2500
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2010
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
Purchase Samples
Purchase Samples
Purchase Samples
TPS2023P
TPS2023PE4
TPS2024D
ACTIVE
ACTIVE
ACTIVE
PDIP
PDIP
SOIC
P
P
D
8
8
8
50
50
75
Pb-Free (RoHS)
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
TPS2024DG4
TPS2024DR
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
D
D
D
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
Request Free Samples
Request Free Samples
2500
2500
Green (RoHS
& no Sb/Br)
TPS2024DRG4
Green (RoHS
& no Sb/Br)
TPS2024P
ACTIVE
ACTIVE
PDIP
PDIP
P
P
8
8
50
50
Pb-Free (RoHS)
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
Purchase Samples
Purchase Samples
TPS2024PE4
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2010
OTHER QUALIFIED VERSIONS OF TPS2020, TPS2021, TPS2022, TPS2024 :
Automotive: TPS2020-Q1, TPS2021-Q1, TPS2022-Q1, TPS2024-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS2020DR
TPS2021DR
TPS2022DR
TPS2023DR
TPS2024DR
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
8
8
8
8
8
2500
2500
2500
2500
2500
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
6.4
6.4
6.4
6.4
6.4
5.2
5.2
5.2
5.2
5.2
2.1
2.1
2.1
2.1
2.1
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2020DR
TPS2021DR
TPS2022DR
TPS2023DR
TPS2024DR
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
8
8
8
8
8
2500
2500
2500
2500
2500
340.5
340.5
340.5
340.5
340.5
338.1
338.1
338.1
338.1
338.1
20.6
20.6
20.6
20.6
20.6
Pack Materials-Page 2
IMPORTANT NOTICE
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