TPS2115ADRBRG4 [TI]
AUTOSWITCHING POWER MUX; 自动开关MUX
| 型号： | TPS2115ADRBRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AUTOSWITCHING POWER MUX |
| 文件： | 总27页 (文件大小：878K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2114A
TPS2115A
www.ti.com
SBVS044F –MARCH 2004–REVISED MAY 2012
AUTOSWITCHING POWER MUX
Check for Samples: TPS2114A, TPS2115A
1
FEATURES
APPLICATIONS
2
•
Two-Input, One-Output Power Multiplexer with
Low rDS(on) Switches:
•
•
•
•
•
•
•
PCs
PDAs
–
–
120 mΩ Typ (TPS2114A)
84 mΩ Typ (TPS2115A)
Digital Cameras
Modems
•
•
•
•
•
•
Reverse and Cross-Conduction Blocking
Wide Operating Voltage Range: 2.8 V to 5.5 V
Low Standby Current: 0.5-μA Typ
Low Operating Current: 55-μA Typ
Adjustable Current Limit
Cell Phones
Digital Radios
MP3 Players
DESCRIPTION
The TPS211xA family of power multiplexers enables
seamless transition between two power supplies
(such as a battery and a wall adapter), each
operating at 2.8 V to 5.5 V and delivering up to 2 A,
depending on package. The TPS211xA family
includes extensive protection circuitry, including user-
programmable current limiting, thermal protection,
inrush current control, seamless supply transition,
cross-conduction blocking, and reverse-conduction
blocking. These features greatly simplify designing
power multiplexer applications.
Controlled Output Voltage Transition Times
Limit Inrush Current and Minimize Output
Voltage Hold-Up Capacitance
•
•
•
•
CMOS- and TTL-Compatible Control Inputs
Manual and Auto-Switching Operating Modes
Thermal Shutdown
Available in TSSOP-8 and 3-mm × 3-mm SON-8
Packages
TYPICAL APPLICATION
Switch Status
IN1: 2.8 - 5.5V
TPS2115APW
R1
0.1 mF
1
8
IN1
STAT
D0
2
3
4
7
6
5
OUT
IN2
D1
R
L
C
L
ILIM
GND
R
ILIM
IN2: 2.8 - 5.5V
0.1 mF
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2012, Texas Instruments Incorporated
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DEVICE INFORMATION(1)
TA
PACKAGE
TSSOP-8 (PW)
SON-8 (DRB)
IOUT
0.75
1.25
2
ORDERING NUMBER
MARKING
2114A
2115A
CGF
TPS2114APW
–40°C to 85°C
TPS2115APW
TPS2115ADRB
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over recommended junction temperature range (unless otherwise noted).
VALUE
MIN
–0.3
–0.3
MAX
6
UNIT
V
IN1, IN2, D0, D1, ILIM(2)
Voltage
Current
(2)
VO(OUT), VO(STAT)
6
V
Output sink, IO(STAT)
5
mA
A
Continuous output, IO (TPS2114APW)
Continuous output, IO (TPS2115APW)
0.9
1.5
A
Continuous output, IO (TPS2115ADRB),
TJ ≤ 105°C
2.5
A
Power dissipation
Temperature
Continuous total
See Power Dissipation Ratings table
Operating virtual junction, TJ
Human body model, HBM
Charge device model, CDM
–40
125
2
°C
kV
V
ESD ratings
500
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-
maximum rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
AVAILABLE OPTIONS
FEATURE
Current limit adjustment range
TPS2114A
TPS2115A
0.63 A to 2 A
Yes
0.31 A to 0.75 A
Manual
Yes
Yes
Yes
Switching modes
Switch status output
Package
Automatic
Yes
Yes
TSSOP-8
SON-8
TSSOP-8
2
Copyright © 2004–2012, Texas Instruments Incorporated
TPS2114A
TPS2115A
www.ti.com
SBVS044F –MARCH 2004–REVISED MAY 2012
PACKAGE DISSIPATION RATINGS
DERATING FACTOR
ABOVE TA = 25°C
T
A ≤ 25°C POWER
TA = 70°C POWER
TA = 85°C POWER
RATING
PACKAGE
TSSOP-8 (PW)
SON-8 (DRB)
RATING
RATING
213 mW
1.38 W
3.9 mW/°C
387 mW
2.50 W
155 mW
1.0 W
25.0 mW/°C
RECOMMENDED OPERATING CONDITIONS
MIN
1.5
NOM
MAX
5.5
5.5
5.5
5.5
5.5
0.75
1.25
2
UNIT
V
V
I(IN2) ≥ 2.8 V
VI(IN2) < 2.8 V
I(IN1) ≥ 2.8 V
Input voltage at IN1, VI(IN1)
2.8
V
V
1.5
V
Input voltage at IN2, VI(IN2)
Input voltage, VI(DO), VI(D1)
VI(IN1) < 2.8 V
2.8
V
0
V
TPS2114APW
0.31
0.63
0.63
–40
A
Nominal current limit adjustment range,
TPS2115APW
A
(1)
IO(OUT)
TPS2115ADRB, TJ ≤ 105°C
A
Operating virtual junction temperature, TJ
125
°C
(1) Minimum recommended current is based on accuracy considerations.
ELECTRICAL CHARACTERISTICS: POWER SWITCH
Over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, and RILIM = 400 Ω, unless otherwise noted.
TPS2114A
TYP
TPS2115A
PARAMETER
TEST CONDITIONS
MIN
MAX
140
140
140
220
220
220
MIN
TYP
84
MAX UNIT
TJ = 25°C, IL = 500 mA, VI(IN1) = VI(IN2) = 5.0 V
TJ = 25°C, IL = 500 mA, VI(IN1) = VI(IN2) = 3.3 V
TJ = 25°C, IL = 500 mA, VI(IN1) = VI(IN2) = 2.8 V
TJ = 125°C, IL = 500 mA, VI(IN1) = VI(IN2) = 5.0 V
TJ = 125°C, IL = 500 mA, VI(IN1) = VI(IN2) = 3.3 V
TJ = 125°C, IL = 500 mA, VI(IN1) = VI(IN2) = 2.8 V
120
110
110
110
150
150
150
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
120
84
120
84
Drain-source on-state
resistance (INx−OUT)
(1)
rDS(on)
(1) The TPS211xA can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In this
specific case, the lower supply voltage has no effect on the IN1 and IN2 switch on-resistances.
Copyright © 2004–2012, Texas Instruments Incorporated
3
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS: GENERAL
Over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, and RILIM = 400 Ω, unless otherwise noted.
TPS2114A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC INPUTS (D0 AND D1)
VIH
VIL
High-level input voltage
2
V
V
Low-level input voltage
0.7
1
D0 or D1 = high, sink current
µA
μA
Input current at D0 or D1
D0 or D1 = low, source current
0.5
1.4
5
SUPPLY AND LEAKAGE CURRENTS
D1 = high, D0 = low (IN1 active), VI(IN1) = 5.5 V,
VI(IN2) = 3.3 V, IO(OUT) = 0 A
55
1
90
12
75
1
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
D1 = high, D0 = low (IN1 active), VI(IN1) = 3.3 V,
VI(IN2) = 5.5 V, IO(OUT) = 0 A
Supply current from IN1
(operating)
D0 = D1 = low (IN2 active), VI(IN1) = 5.5 V,
VI(IN2) = 3.3 V, IO(OUT) = 0 A
D0 = D1 = low (IN2 active), VI(IN1) = 3.3 V,
VI(IN2) = 5.5 V, IO(OUT) = 0 A
D1 = high, D0 = low (IN1 active), VI(IN1) = 5.5 V,
VI(IN2) = 3.3 V, IO(OUT) = 0 A
1
D1 = high, D0 = low (IN1 active), VI(IN1) = 3.3 V,
VI(IN2) = 5.5 V, IO(OUT) = 0 A
75
12
90
2
Supply current from IN2
(operating)
D0 = D1 = low (IN2 active), VI(IN1) = 5.5 V,
VI(IN2) = 3.3 V, IO(OUT) = 0 A
1
55
D0 = D1 = low (IN2 active), VI(IN1) = 3.3 V,
VI(IN2) = 5.5 V, IO(OUT) = 0 A
D0 = D1 = high (inactive), VI(IN1) = 5.5 V,
VI(IN2) = 3.3 V, IO(OUT) = 0 A
0.5
Quiescent current from IN1
(STANDBY)
D0 = D1 = high (inactive), VI(IN1) = 3.3 V,
VI(IN2) = 5.5 V, IO(OUT) = 0 A
1
D0 = D1 = high (inactive), VI(IN1) = 5.5 V,
VI(IN2) = 3.3 V, IO(OUT) = 0 A
1
Quiescent current from IN2
(STANDBY)
D0 = D1 = high (inactive), VI(IN1) = 3.3 V,
VI(IN2) = 5.5 V, IO(OUT) = 0 A
0.5
0.1
0.1
0.3
2
Forward leakage current from IN1 D0 = D1 = high (inactive), VI(IN1) = 5.5 V, IN2 open,
(measured from OUT to GND) VO(OUT) = 0 V (shorted), TJ = 25°C
5
Forward leakage current from IN2 D0 = D1= high (inactive), VI(IN2) = 5.5 V, IN1 open, VO(OUT)
5
(measured from OUT to GND)
= 0 V (shorted), TJ = 25°C
Reverse leakage current to INx
(measured from INx to GND)
D0 = D1 = high (inactive), VI(INx) = 0 V, VO(OUT) = 5.5 V,
TJ = 25°C
5
CURRENT LIMIT CIRCUIT
RILIM = 400 Ω
RILIM = 700 Ω
RILIM = 400 Ω
RILIM = 700 Ω
0.51
0.30
0.95
0.47
0.63
0.36
1.25
0.71
0.80
0.50
1.56
0.99
A
A
A
A
Current limit accuracy, TPS2114A
Current limit accuracy, TPS2115A
Time for short-circuit output current to settle within 10% of
its steady state value.
td
Current limit settling time
Input current at ILIM
1
ms
VI(ILIM) = 0 V, IO(OUT) = 0 A
–15
0
μA
UVLO
Falling edge
Rising edge
1.15
1.25
1.30
57
V
V
IN1 and IN2 UVLO
1.35
65
IN1 and IN2 UVLO hysteresis
30
mV
V
Falling edge
Rising edge
2.4
2.53
2.58
50
Internal VDD UVLO (the higher of
IN1 and IN2)
2.8
75
V
Internal VDD UVLO hysteresis
UVLO deglitch for IN1, IN2
30
mV
μs
Falling edge
110
4
Copyright © 2004–2012, Texas Instruments Incorporated
TPS2114A
TPS2115A
www.ti.com
SBVS044F –MARCH 2004–REVISED MAY 2012
ELECTRICAL CHARACTERISTICS: GENERAL (continued)
Over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, and RILIM = 400 Ω, unless otherwise noted.
TPS2114A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REVERSE CONDUCTION BLOCKING
D0 = D1 = high, VI(INx) = 3.3 V
Minimum input-to-output voltage
ΔVO(I_block)
Connect OUT to a 5-V supply through a series 1-kΩ
resistor. Let D0 = low. Slowly decrease the supply voltage
until OUT connects to IN1.
80
100
120
mV
difference to block switching
THERMAL SHUTDOWN
Thermal shutdown threshold
Recovery from thermal shutdown
Hysteresis
TPS211xA is in current limit
TPS211xA is in current limit
135
125
°C
°C
°C
10
20
IN2−IN1 COMPARATORS
Hysteresis of IN2−IN1 comparator
0.1
10
0.2
50
V
Deglitch of IN2−IN1 comparator
(both ↑↓)
μs
STAT OUTPUT
Leakage current
VO(STAT) = 5.5 V
0.01
0.13
150
1
μA
V
Saturation voltage
II(STAT) = 2 mA, IN1 switch is on
0.4
Deglitch time (falling edge only)
μs
SWITCHING CHARACTERISTICS
Over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, and RILIM = 400 Ω, unless otherwise noted.
TPS2114A
TPS2115A
PARAMETER
POWER SWITCH
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX UNIT
Output rise time from
an enable
VI(IN1) = VI(IN2) = 5 V, TJ = 25°C, CL = 1 μF, IL = 500 mA
(see Figure 1a)
tr
tf
0.5
1.0
0.5
1.5
0.7
1
1.8
1
3
2
ms
ms
Output fall time from a VI(IN1) = VI(IN2) = 5 V, TJ = 25°C, CL = 1 μF, IL = 500 mA
disable
0.35
0.5
(see Figure 1a)
IN1 to IN2 transition, VI(IN1) = 3.3 V, VI(IN2) = 5 V,
TJ = 125°C, CL = 10 μF, IL = 500 mA
Measure transition time as 10−90% rise time or from
3.4 V to 4.8 V on VO(OUT) (see Figure 1b).
40
40
60
60
40
40
60
60
μs
μs
tt
Transition time
IN2 to IN1 transition, VI(IN1) = 5 V, VI(IN2) = 3.3 V,
TJ = 125°C, CL = 10 μF, IL = 500 mA
Measure transition time as 10−90% rise time or from
3.4 V to 4.8 V on VO(OUT) (see Figure 1b).
VI(IN1) = VI(IN2) = 5 V, measured from enable to 10% of
VO(OUT), TJ = 25°C, CL = 10 μF, IL = 500 mA
(see Figure 1a)
Turn-on propagation
delay from enable
tPLH1
0.5
3
1
5
ms
ms
VI(IN1) = VI(IN2) = 5 V, measured from disable to 90% of
VO(OUT), TJ = 25°C, CL = 10 μF, IL = 500 mA
(see Figure 1a)
Turn-off propagation
delay from a disable
tPHL1
Logic 1 to Logic 0 transition on D1, VI(IN1) = 1.5 V,
VI(IN2) = 5 V, VI(D0) = 0 V, measured from D1 to 10% of
VO(OUT), TJ = 25°C, CL = 10 μF, IL = 500 mA
(see Figure 1c)
Switch-over rising
propagation delay
tPLH2
40
3
100
10
40
5
100
10
μs
Logic 0 to Logic 1 transition on D1, VI(IN1) = 1.5V,
VI(IN2) = 5V, VI(D0) = 0 V, measured from D1 to 90% of
VO(OUT), TJ = 25°C, CL = 10 μF, IL = 500 mA
(see Figure 1c)
Switch-over falling
propagation delay
tPHL2
2
2
ms
Copyright © 2004–2012, Texas Instruments Incorporated
5
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012
www.ti.com
Table 1. Truth Table
D1
0
D0
0
VI(IN2) > VI(IN1)
STAT
Hi-Z
0
OUT(1)
IN2
X(2)
No
Yes
X
0
1
IN1
0
1
Hi-Z
0
IN2
1
0
IN1
1
1
X
0
Hi-Z
(1) The under-voltage lockout circuit causes the output OUT to go Hi-Z if the selected power supply does not exceed the IN1/IN2 UVLO, or
if neither of the supplies exceeds the internal VDD UVLO.
(2) X = Don’t care.
PIN CONFIGURATIONS
PW PACKAGE
DRB PACKAGE
TSSOP-8
3mm × 3mm SON-8
(TOP VIEW)
(TOP VIEW)
1
2
3
4
8
7
6
5
STAT
D0
IN1
STAT
D0
1
2
3
4
8
7
6
5
IN1
OUT
IN2
OUT
IN2
GND
D1
D1
ILIM
GND
ILIM
GND
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
TTL- and CMOS-compatible input pins. Each pin has a 1-μA pull-up. Table 1 illustrates the
functionality of D0 and D1.
D0
2
I
TTL- and CMOS-compatible input pins. Each pin has a 1-μA pull-up. Table 1 illustrates the
functionality of D0 and D1.
D1
3
5
8
I
I
I
GND
IN1
Ground
Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above
the UVLO threshold and at least one supply exceeds the internal VDD UVLO.
Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is
above the UVLO threshold and at least one supply exceeds the internal VDD UVLO.
IN2
6
I
A resistor RILIM from ILIM to GND sets the current limit IL to 250/RILIM and 500/RILIM for the
TPS2114A and TPS2115A, respectively.
ILIM
4
7
I
OUT
STAT
PAD
O
O
I
Power switch output
STAT is an open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1
switch is ON or if OUT is Hi-Z (i.e., EN is equal to logic 0).
1
—
Tie to GND. Connect to internal planes for improved heatsinking with multiple vias.
6
Copyright © 2004–2012, Texas Instruments Incorporated
TPS2114A
TPS2115A
www.ti.com
SBVS044F –MARCH 2004–REVISED MAY 2012
FUNCTIONAL BLOCK DIAGRAM
Internal V
DD
1 mA
1 mA
V = 0 V
f
V = 0 V
f
I
O(OUT)
Q1
8
6
7
IN1
IN2
OUT
Q2
Charge
Pump
k* I
O(OUT)
TPS2114A: k = 0.2%
TPS2115A: k = 0.1%
V
DD
ULVO
4
_
+
ILIM
0.5 V
IN2
ULVO
Cross-Conduction
Detector
+
IN1
ULVO
+
0.6 V
+
_
_
EN2
EN1
Q1 is ON
Q2 is ON
UVLO (V
100 mV
+
)
DD
V
> V
I(INx)
O(OUT)
+
_
UVLO (IN2)
UVLO (IN1)
D0
EN1
2
3
D0
D1
Thermal
Sense
Control
Logic
D1
IN2
+
_
5
GND
IN1
1
STAT
Q2 is ON
Copyright © 2004–2012, Texas Instruments Incorporated
7
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION
90%
10%
90%
10%
V
O(OUT)
0 V
t
r
t
f
t
t
PHL1
PLH1
DO-D1
Switch Off
Switch Off
Switch Enabled
(a)
5 V
4.8 V
V
O(OUT)
3.4 V
3.3 V
t
t
DO-D1
Switch #2 Enabled
(b)
Switch #1 Enabled
5 V
1.85 V
4.65 V
V
O(OUT)
1.5 V
t
t
PLH2
PHL2
DO-D1
Switch #1 Enabled
Switch #2 Enabled
(c)
Switch #1 Enabled
Figure 1. Propagation Delays and Transition Timing Waveforms
8
Copyright © 2004–2012, Texas Instruments Incorporated
TPS2114A
TPS2115A
www.ti.com
SBVS044F –MARCH 2004–REVISED MAY 2012
TYPICAL CHARACTERISTICS
space
OUTPUT SWITCHOVER RESPONSE
V
I(DO)
5 V
2V/Div
TPS2115APW
0.1 mF
1
2
8
NC
IN1
STAT
D0
7
6
5
f = 28 Hz
78% Duty Cycle
OUT
IN2
V
I(D1)
3
4
D1
50 W
1
mF
2V/Div
ILIM
GND
400 W
3.3 V
V
O(OUT)
0.1 mF
2V/Div
Output Switchover Response Test Circuit
t - Time - 1 ms/div
Figure 2.
OUTPUT TURN-ON RESPONSE
V
I(DO)
5 V
2V/Div
TPS2115APW
0.1 mF
1
2
8
7
IN1
STAT
D0
NC
f = 28 Hz
78% Duty Cycle
V
OUT
IN2
I(D1)
3
4
6
5
2V/Div
D1
50 W
1
mF
ILIM
GND
400 W
3.3 V
V
O(OUT)
2V/Div
0.1 mF
Output Turn-On Response Test Circuit
t - Time - 2 ms/div
Figure 3.
Copyright © 2004–2012, Texas Instruments Incorporated
9
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
space
OUTPUT SWITCHOVER VOLTAGE DROOP
V
I(DO)
5 V
2V/Div
TPS2115APW
0.1 mF
1
2
8
7
IN1
STAT
D0
NC
V
f = 580 Hz
90% Duty Cycle
OUT
IN2
I(D1)
C
L
= 1 mF
3
4
6
5
2V/Div
D1
50 W
C
L
ILIM
GND
400 W
V
O(OUT)
2V/Div
0.1 mF
C
L
= 0 mF
Output Switchover Voltage Droop Test Circuit
t - Time - 40 ms/div
Figure 4.
10
Copyright © 2004–2012, Texas Instruments Incorporated
TPS2114A
TPS2115A
www.ti.com
SBVS044F –MARCH 2004–REVISED MAY 2012
TYPICAL CHARACTERISTICS (continued)
space
OUTPUT SWITCHOVER VOLTAGE DROOP
vs
LOAD CAPACITANCE
5
V
I
= 5 V
4.5
4
3.5
3
R = 10 W
L
2.5
2
1.5
1
0.5
0
R
L
= 50 W
0.1
1
10
100
C
L
- Load Capacitance -mF
V
I
TPS2115APW
0.1 mF
8
7
6
5
1
2
3
4
IN1
NC
STAT
f = 28 Hz
50% Duty Cycle
OUT
IN2
D0
D1
ILIM
GND
400 W
50 W
10 W
0.1 mF
0.1 mF
1 mF
10 mF
47 mF
100 mF
Output Switchover Voltage Droop Test Circuit
Figure 5.
Copyright © 2004–2012, Texas Instruments Incorporated
11
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
space
AUTO SWITCHOVER VOLTAGE DROOP
V
I(IN1)
2V/Div
5V
TPS2115A
W
1k
m
0.1
F
1
2
8
7
IN1
STAT
VOUT
D0
OUT
IN2
f = 220 Hz
20% Duty Cycle
3
4
6
5
3.3V
D1
W
50
m
10
F
ILIM
GND
0.1mF
W
400
V
O(OUT)
2V/Div
75% less output voltage
droop compared to TPS2115
Auto Switchover Voltage Droop Test Circuit
t - Time - 250 ms/div
Figure 6.
12
Copyright © 2004–2012, Texas Instruments Incorporated
TPS2114A
TPS2115A
www.ti.com
SBVS044F –MARCH 2004–REVISED MAY 2012
TYPICAL CHARACTERISTICS (continued)
space
INRUSH CURRENT
vs
LOAD CAPACITANCE
300
250
200
150
100
50
V = 5 V
I
V = 3.3 V
I
0
0
20
40
60
80
100
C
L
- Load Capacitance -µF
V
I
TPS2115APW
0.1 mF
8
7
6
5
To Oscilloscope
1
2
3
4
NC
NC
IN1
OUT
IN2
STAT
D0
f = 28 Hz
90% Duty Cycle
D1
50 W
ILIM
GND
400 W
0.1 mF
0.1 mF
1 mF
10 mF
47 mF
100 mF
Output Capacitor Inrush Current Test Circuit
Figure 7.
Copyright © 2004–2012, Texas Instruments Incorporated
13
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
space
SWITCH ON-RESISTANCE
vs
SWITCH ON-RESISTANCE
vs
JUNCTION TEMPERATURE
SUPPLY VOLTAGE
180
160
140
120
115
110
105
100
95
TPS2114A
TPS2114A
TPS2115A
120
100
90
80
60
TPS2115A
85
80
-50
0
50
100
150
2
3
4
5
6
T
J
- Junction Temperature -°C
V
I(INx)
- Supply Voltage - V
Figure 8.
Figure 9.
IN1 SUPPLY CURRENT
vs
IN1 SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
0.96
0.94
0.92
0.90
0.88
0.86
60
IN1 Switch is ON
Device Disabled
= 0 V
V
I(IN2)
I
= 0 V
58
56
54
52
50
48
46
44
V
I(IN2)
O(OUT)
= 0 A
O(OUT)
I
= 0 A
0.84
0.82
42
40
2
3
4
5
6
2
3
4
5
- Supply Voltage - V
6
V
I(IN1)
V
- IN1 Supply Voltage - V
I(IN1)
Figure 10.
Figure 11.
14
Copyright © 2004–2012, Texas Instruments Incorporated
TPS2114A
TPS2115A
www.ti.com
SBVS044F –MARCH 2004–REVISED MAY 2012
TYPICAL CHARACTERISTICS (continued)
space
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
1.2
1
80
70
IN1 Switch is ON
Device Disabled
V
I(IN1)
V
I(IN2)
= 5.5 V
= 3.3 V
= 0 A
V
I(IN1)
V
I(IN2)
= 5.5 V
= 3.3 V
= 0 A
I
O(OUT)
I
O(OUT)
60
50
I
I(IN1)
I
= 5.5 V
I(IN1)
0.8
40
30
20
0.6
0.4
0.2
0
10
0
I
I(IN2)
I
3.3 V
I(IN2) =
-50
0
50
100
150
-50
0
50
100
150
T
J
- Junction Temperature - °C
T
J
- Junction Temperature - °C
Figure 12.
Figure 13.
Copyright © 2004–2012, Texas Instruments Incorporated
15
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012
www.ti.com
APPLICATION INFORMATION
Some applications have two energy sources, one of which should be used in preference to another. Figure 14
shows a circuit that will connect IN1 to OUT until the voltage at IN1 falls below a user-specified value. Once the
voltage on IN1 falls below this value, the TPS2114A/5A will select the higher of the two supplies. This usually
means that the TPS2114A/5A will swap to IN2.
Switch Status
IN1: 2.8 - 5.5V
TPS2115APW
R1
0.1 mF
1
2
3
4
8
7
6
5
IN1
OUT
IN2
STAT
D0
NC
D1
R
L
C
L
ILIM
GND
R
ILIM
IN2: 2.8 - 5.5V
C2
0.1 mF
Figure 14. Auto-Selecting for a Dual Power Supply Application
In Figure 15, the multiplexer selects between two power supplies based upon the D1 logic signal. OUT connects
to IN1 if D1 is logic 1; otherwise, OUT connects to IN2. The logic thresholds for the D1 terminal are compatible
with both TTL and CMOS logic.
Switch Status
IN1: 2.8 - 5.5V
TPS2115APW
R1
0.1 mF
1
2
3
4
8
7
6
5
IN1
OUT
IN2
STAT
D0
D1
R
L
C
L
ILIM
GND
R
ILIM
IN2: 2.8 - 5.5 V
0.1 mF
Figure 15. Manually Switching Power Sources
16
Copyright © 2004–2012, Texas Instruments Incorporated
TPS2114A
TPS2115A
www.ti.com
SBVS044F –MARCH 2004–REVISED MAY 2012
DETAILED DESCRIPTION
AUTO-SWITCHING MODE
D0 equal to logic 1 and D1 equal to logic 0 selects the auto-switching mode. In this mode, OUT connects to the
higher of IN1 and IN2.
MANUAL SWITCHING MODE
D0 equal to logic 0 selects the manual-switching mode. In this mode, OUT connects to IN1 if D1 is equal to logic
1, otherwise OUT connects to IN2.
N-CHANNEL MOSFETs
Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic
selects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so output-to-
input current cannot flow when the FET is off. An integrated comparator prevents turn-on of a FET switch if the
output voltage is greater than the input voltage.
CROSS-CONDUCTION BLOCKING
The switching circuitry ensures that both power switches will never conduct at the same time. A comparator
monitors the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source
voltage of the other FET is below the turn-on threshold voltage.
REVERSE-CONDUCTION BLOCKING
When the TPS211xA switches from a higher-voltage supply to a lower-voltage supply, current can potentially
flow back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the
TPS211xA will not connect a supply to the output until the output voltage has fallen to within 100 mV of the
supply voltage. Once a supply has been connected to the output, it will remain connected regardless of output
voltage.
CHARGE PUMP
The higher of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power to the
current limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply voltages.
A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET.
CURRENT LIMITING
A resistor RILIM from ILIM to GND sets the current limit to 250/RILIM and 500/RILIM for the TPS2114A and
TPS2115A, respectively. Setting resistor RILIM equal to zero is not recommended as that disables current limiting.
OUTPUT VOLTAGE SLEW-RATE CONTROL
The TPS2114A/5A slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the Hi-Z state
(see Table 1). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can glitch
the voltage bus and cause a system to hang up or reset. It can also cause reliability issues—like pit the
connector power contacts, when hot-plugging a load such as a PCI card. The TPS2114A/5A slews the output
voltage at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the output
voltage droop and reduces the output voltage hold-up capacitance requirement.
Copyright © 2004–2012, Texas Instruments Incorporated
17
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (April 2011) to Revision F
Page
•
•
•
•
Changed description of power supplies in Description section ............................................................................................ 1
Added IOUT column to Device Information table .................................................................................................................... 2
Changed conditions of Absolute Maximum Ratings table .................................................................................................... 2
Added PW to end of device name in first two continuous output rows in Current parameter of Absolute Maximum
Ratings table ......................................................................................................................................................................... 2
•
•
•
•
•
Added last continuous output row to Current parameter in Absolute Maximum Ratings table ............................................ 2
Deleted storage temperature row from Absolute Maximum Ratings table ........................................................................... 2
Changed Current limit adjustment range parameter, TPS2115A specification in Available Options table .......................... 2
Changed Nominal current limit adjustment range parameter in Recommended Operating Conditions table ...................... 3
Added footnote 1 to Recommended Operating Conditions table ......................................................................................... 3
Changes from Revision D (July 2006) to Revision E
Page
•
•
•
•
•
Updated document to current format .................................................................................................................................... 1
Changed title, footnote, and CGF marking in Device Information table ............................................................................... 2
Deleted footnote 1 (not tested in production) from Electrical Characteristics: General table ............................................... 4
Deleted footnote 1 (not tested in production) from Switching Characteristics table ............................................................. 5
Added PAD row to Terminal Functions table ........................................................................................................................ 6
18
Copyright © 2004–2012, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
TPS2114APW
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
SON
PW
8
8
8
8
8
8
8
8
8
8
8
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
2114A
TPS2114APWG4
TPS2114APWR
TPS2114APWRG4
TPS2115ADRBR
TPS2115ADRBRG4
TPS2115ADRBT
TPS2115ADRBTG4
TPS2115APW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PW
PW
150
2000
2000
3000
3000
250
Green (RoHS
& no Sb/Br)
2114A
2114A
2114A
CGF
Green (RoHS
& no Sb/Br)
PW
Green (RoHS
& no Sb/Br)
DRB
DRB
DRB
DRB
PW
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
CGF
SON
Green (RoHS
& no Sb/Br)
CGF
SON
250
Green (RoHS
& no Sb/Br)
CGF
TSSOP
TSSOP
TSSOP
TSSOP
150
Green (RoHS
& no Sb/Br)
2115A
2115A
2115A
2115A
TPS2115APWG4
TPS2115APWR
TPS2115APWRG4
PW
150
Green (RoHS
& no Sb/Br)
PW
2000
2000
Green (RoHS
& no Sb/Br)
PW
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS2115A :
Automotive: TPS2115A-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jun-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2114APWR
TPS2115ADRBT
TPS2115APWR
TSSOP
SON
PW
DRB
PW
8
8
8
2000
250
330.0
180.0
330.0
12.4
12.4
12.4
7.0
3.3
7.0
3.6
3.3
3.6
1.6
1.1
1.6
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q2
Q1
TSSOP
2000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jun-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2114APWR
TPS2115ADRBT
TPS2115APWR
TSSOP
SON
PW
DRB
PW
8
8
8
2000
250
367.0
210.0
367.0
367.0
185.0
367.0
35.0
35.0
35.0
TSSOP
2000
Pack Materials-Page 2
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