TPS2115AIPWRQ1 [TI]
AUTO-SWITCHING POWER MULTIPLEXER; 自动切换电源多路复用器
| 型号： | TPS2115AIPWRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AUTO-SWITCHING POWER MULTIPLEXER |
| 文件： | 总20页 (文件大小：402K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2115A-Q1
www.ti.com ........................................................................................................................................................................................... SBVS124–NOVEMBER 2008
AUTO-SWITCHING POWER MULTIPLEXER
1
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
PCs
PDAs
•
Qualified for Automotive Applications
•
Two-Input One-Output Power Multiplexer With
Low rDS(on) Switch...84 mΩ (Typ)
Digital Cameras
Modems
Cell Phones
Digital Radios
MP3 Players
•
•
•
•
•
•
Reverse and Cross-Conduction Blocking
Wide Operating Voltage Range...2.8 V to 5.5 V
Low Standby Current...0.5 µA (Typ)
Low Operating Current...55 µA (Typ)
Adjustable Current Limit
PW PACKAGE
(TOP VIEW)
Controlled Output Voltage Transition Times
Limit Inrush Current and Minimize Output
Voltage Hold-Up Capacitance
1
2
3
4
8
7
6
5
STAT
D0
IN1
OUT
IN2
•
•
•
•
CMOS- and TTL-Compatible Control Inputs
Manual and Auto-Switching Operating Modes
Thermal Shutdown
D1
ILIM
GND
Available in TSSOP-8 (PW) Package
DESCRIPTION/ORDERING INFORMATION
The TPS2115A power multiplexer enables seamless transition between two power supplies, such as a battery
and a wall adapter, each operating at 2.8 V to 5.5 V and delivering up to 1 A. The TPS2115A includes extensive
protection circuitry including user-programmable current limiting, thermal protection, inrush current control,
seamless supply transition, cross-conduction blocking, and reverse-conduction blocking. These features greatly
simplify designing power multiplexer applications.
Switch Status
IN1
2.8 V to 5.5 V
TPS2115A
R1
0.1 µF
1
2
3
4
8
7
6
5
IN1
OUT
IN2
STAT
D0
NC
D1
R
L
C
L
ILIM
GND
R
ILIM
IN2
2.8 V to 5.5 V
C2
0.1 µF
Figure 1. Typical Application
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TPS2115A-Q1
SBVS124–NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
2115AQ
–40°C to 85°C
TSSOP – PW
Reel of 2000
TPS2115AIPWRQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
TRUTH TABLE
(1)
D0
0
D1
0
VI(IN2) > VI(IN1)
STAT
Hi-Z
0
OUT(2)
IN2
X
No
Yes
X
0
1
IN1
0
1
Hi-Z
0
IN2
1
0
IN1
1
1
X
0
Hi-Z
(1) X = don’t care
(2) The undervoltage lockout circuit causes the output OUT to go Hi-Z if
the selected power supply does not exceed the IN1/IN2 UVLO, or if
neither of the supplies exceeds the internal VDD UVLO.
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
2
D0
I
I
I
TTL- and CMOS-compatible input pins. Each pin has a 1-µA pullup. The Truth Table shows the functionality
of D0 and D1.
D1
3
GND
5
Ground
Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above the UVLO
threshold and at least one supply exceeds the internal VDD UVLO.
IN1
IN2
8
6
I
I
Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is above the UVLO
threshold and at least one supply exceeds the internal VDD UVLO.
ILIM
OUT
4
7
I
A resistor RILIM from ILIM to GND sets the current limit IL to 500/RILIM
.
O
Power switch output
Open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1 switch is ON or if OUT is Hi-Z
(i.e., EN is equal to logic 0).
STAT
1
O
2
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FUNCTIONAL BLOCK DIAGRAM
Internal V
DD
1 µA
1 µA
V = 0 V
f
V = 0 V
f
I
O(OUT)
Q1
8
6
7
4
IN1
IN2
OUT
ILIM
Q2
Charge
Pump
k* I
O(OUT)
TPS2114A: k = 0.2%
TPS2115A: k = 0.1%
V
DD
_
+
ULVO
0.5 V
IN2
ULVO
Cross-Conduction
IN1
Detector
+
+
0.6 V
ULVO
+
_
_
EN2
EN1
Q1 is ON
Q2 is ON
UVLO (V
100 mV
+
)
DD
V
> V
I(INx)
O(OUT)
+
_
UVLO (IN2)
UVLO (IN1)
D0
EN1
2
3
D0
D1
Thermal
Sense
Control
Logic
D1
IN2
+
_
5
GND
IN1
1
STAT
Q2 is ON
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ABSOLUTE MAXIMUM RATINGS(1)(2)
over operating free-air temperature range unless otherwise noted
VI
Input voltage range
Output voltage range
IN1, IN2, D0, D1, ILIM
OUT, STAT
–0.3 V to 6 V
–0.3 V to 6 V
5 mA
VO
IO(sink) Output sink current
STAT
IO
Continuous output current
1.5 mA
PD
TA
Continuous total power dissipation
Operating free-air temperature range
Operating virtual-junction temperature range
Storage temperature range
See Dissipation Ratings
–40°C to 85°C
–40°C to 125°C
–65°C to 150°C
260°C
TJ
Tstg
Tlead
Lead temperature soldering
1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MAX UNIT
Human-Body Model (HBM)
2000
500
ESD
Electrostatic discharge protection
V
Charged-Device Model (CDM)
DISSIPATION RATINGS
DERATING FACTOR
ABOVE TA = 25°C
T
A ≤ 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
POWER RATING
TSSOP (PW)
3.9 mW/°C
387 mW
213 mW
155 mW
RECOMMENDED OPERATING CONDITIONS
MIN
1.5
2.8
1.5
2.8
0
MAX UNIT
V
I(IN2) ≥ 2.8 V
VI(IN2) < 2.8 V
I(IN1) ≥ 2.8 V
VI(IN1) < 2.8 V
5.5
5.5
IN1
VI
Input voltage
V
5.5
5.5
5.5
V
IN2
D0, D1
D0, D1
D0, D1
OUT
VIH
VIL
IO
High-level input voltage
2
V
V
Low-level input voltage
0.7
1.25
85
Current limit adjustment range
Operating free-air temperature
0.63
–40
–40
A
TA
TJ
°C
°C
Operating virtual-junction temperature range
125
4
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
(1)
Power Switch
VI(IN1) = VI(IN2) = 5.0 V
84
84
84
110
110
TA = 25°C, IL = 500 mA
TA = 85°C, IL = 500 mA
VI(IN1) = VI(IN2) = 3.3 V
VI(IN1) = VI(IN2) = 2.8 V
VI(IN1) = VI(IN2) = 5.0 V
VI(IN1) = VI(IN2) = 3.3 V
VI(IN1) = VI(IN2) = 2.8 V
110
mΩ
150
Drain-source on-state
resistance (INx to OUT)
rDS(on)
150
150
Logic Inputs (D0 and D1)
D0 or D1 = high, sink current
D0 or D1 = low, source current
1
II
Input current at D0 or D1
µA
5
0.5
1.4
Supply and Leakage Currents
D1 = high, D0 = low (IN1 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A
D1 = high, D0 = low (IN1 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A
D0 = D1 = low (IN2 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A
D0 = D1 = low (IN2 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A
D1 = high, D0 = low (IN1 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A
D1 = high, D0 = low (IN1 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A
D0 = D1 = low (IN2 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A
D0 = D1 = low (IN2 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A
55
1
90
12
µA
75
Supply current from IN1 (operating)
Supply current from IN2 (operating)
1
1
75
µA
12
1
55
90
VI(IN1) = 5.5 V, VI(IN2) = 3.3 V
D0 = D1 = high (inactive), IO(OUT) = 0 A
0.5
2
Quiescent current from IN1 (standby)
Quiescent current from IN2 (standby)
µA
1
VI(IN1) = 3.3 V, VI(IN2) = 5.5 V
VI(IN1) = 5.5 V, VI(IN2) = 3.3 V
D0 = D1 = high (inactive), IO(OUT) = 0 A
1
µA
2
VI(IN1) = 3.3 V, VI(IN2) = 5.5 V
0.5
0.1
Forward leakage current from IN1
(measured from OUT to GND)
D0 = D1 = high (inactive), VI(IN1) = 5.5 V, IN2 open, VO(OUT) = 0 V (shorted),
TA = 25°C
5
5
5
µA
µA
µA
Forward leakage current from IN2
(measured from OUT to GND)
D0 = D1= high (inactive), VI(IN2) = 5.5 V, IN1 open, VO(OUT) = 0 V (shorted),
TA = 25°C
0.1
0.3
Reverse leakage current to INx
(measured from INx to GND)
D0 = D1 = high (inactive), VI(INx) = 0 V, VO(OUT) = 5.5 V, TA = 25°C
Current Limit Circuit
RILIM = 400 Ω
0.95
0.47
1.25
0.71
1
1.56
0.99
Current limit accuracy
A
RILIM = 700 Ω
td
Current limit settling time
Input current at ILIM
Time for short-circuit output current to settle within 10% of its steady state value
VI(ILIM) = 0 V, IO(OUT) = 0 A
ms
II
–15
0
µA
UVLO
Falling edge
Rising edge
1.15
1.25
1.30
57
IN1 and IN2 UVLO
V
mV
V
1.35
65
IN1 and IN2 UVLO hysteresis
30
Falling edge
Rising edge
2.4
2.53
2.58
50
Internal VDD UVLO (the higher of IN1
and IN2)
2.8
75
Internal VDD UVLO hysteresis
UVLO deglitch for IN1, IN2
30
mV
Falling edge
110
µs
Reverse Conduction Blocking
Minimum input-to-output
ΔVIO(blk) voltage difference to block
switching
D0 = D1 = high, VI(INx) = 3.3 V. Connect OUT to a 5-V supply through a series
1-kΩ resistor. Set D0 = low. Slowly decrease the supply voltage until OUT
connects to IN1.
80
100
120
mV
(1) The TPS2115A can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In this
specific case, the lower supply voltage has no effect on the IN1 and IN2 switch on-resistances.
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted)
PARAMETER
Thermal Shutdown
TEST CONDITIONS
MIN
TYP
MAX UNIT
Thermal shutdown threshold
Recovery from thermal shutdown
Hysteresis
TPS2115A is in current limit.
TPS2115A is in current limit.
135
125
°C
°C
°C
10
20
IN2-IN1 Comparators
Hysteresis of IN2-IN1 comparator
0.1
10
0.2
50
V
Deglitch of IN2-IN1 comparator
(both ↑↓)
µs
STAT Output
Ileak
Vsat
Leakage current
VO(STAT) = 5.5 V
0.01
0.13
1
µA
Saturation voltage
II(STAT) = 2 mA, IN1 switch is on
0.4
V
Deglitch time
(falling edge only)
td
150
µs
SWITCHING CHARACTERISTICS
over operating free-air temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted)
PARAMETER
Power Switch
TEST CONDITIONS
MIN
TYP
MAX UNIT
Output rise time from an
enable
TA = 25°C, CL = 1 µF, IL = 500 mA,
See Figure 2(a)
tr
tf
VI(IN1) = VI(IN2) = 5 V
VI(IN1) = VI(IN2) = 5 V
1
1.8
1
3
2
ms
ms
Output fall time from a
disable
TA = 25°C, CL = 1 µF, IL = 500 mA,
See Figure 2(a)
0.5
IN1 to IN2 transition, VI(IN1) = 3.3 V,
VI(IN2) = 5 V
TA = 85°C, CL = 10 µF, IL = 500 mA
[Measure transition time as
10%-90% rise time or from 3.4 V to
4.8 V on VO(OUT)], See Figure 2(b)
40
40
1
60
60
tt
Transition time
µs
IN2 to IN1 transition, VI(IN1) = 5 V,
VI(IN2) = 3.3 V
Turn-on propagation delay
from enable
VI(IN1) = VI(IN2) = 5 V, Measured from
enable to 10% of VO(OUT)
TA = 25°C, CL = 10 µF, IL = 500 mA,
See Figure 2(a)
tPLH1
tPHL1
ms
ms
Turn-off propagation delay
from a disable
VI(IN1) = VI(IN2) = 5 V, Measured from
disable to 90% of VO(OUT)
TA = 25°C, CL = 10 µF, IL = 500 mA,
See Figure 2(a)
5
Logic 1 to Logic 0 transition on D1,
VI(IN1) = 1.5 V, VI(IN2) = 5 V, VI(D0) = 0 V,
Measured from D1 to 10% of VO(OUT)
Switch-over rising
propagation delay
TA = 25°C, CL = 10 µF, IL = 500 mA,
See Figure 2(c)
tPLH2
40
5
100
10
µs
Logic 0 to Logic 1 transition on D1,
VI(IN1) = 1.5 V, VI(IN2) = 5 V, VI(D0) = 0 V,
Measured from D1 to 90% of VO(OUT)
Switch-over falling
propagation delay
TA = 25°C, CL = 10 µF, IL = 500 mA,
See Figure 2(c)
tPHL2
2
ms
6
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PARAMETER MEASUREMENT INFORMATION
90%
10%
90%
10%
V
O(OUT)
0 V
t
r
t
f
t
t
PHL1
PLH1
DO-D1
Switch Off
Switch Off
Switch Enabled
(a)
5 V
4.8 V
V
O(OUT)
3.4 V
3.3 V
t
t
DO-D1
Switch #1 Enabled
Switch #2 Enabled
(b)
5 V
1.85 V
4.65 V
V
O(OUT)
1.5 V
t
t
PHL2
PLH2
DO-D1
Switch #1 Enabled
Switch #2 Enabled
(c)
Switch #1 Enabled
Figure 2. Propagation Delays and Transition Timing Waveforms
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TYPICAL CHARACTERISTICS
OUTPUT SWITCHOVER RESPONSE
5 V
TPS2115A
0.1 µF
VI(D0)
1
2
8
7
2 V/div
NC
IN1
STAT
D0
f = 28 Hz
78% Duty Cycle
OUT
IN2
VI(D1)
3
4
6
5
2 V/div
D1
50 W
1 µF
VO(OUT)
ILIM
GND
2 V/div
400 W
3.3 V
0.1 µF
Output Switchover Response Test Circuit
t - Time - 1 ms/div
Figure 3.
OUTPUT TURN-ON RESPONSE
VI(D0)
5 V
2 V/div
TPS2115A
0.1 µF
VI(D1)
1
2
8
7
IN1
STAT
D0
2 V/div
NC
f = 28 Hz
78% Duty Cycle
OUT
IN2
3
4
6
5
D1
50 W
1 µF
ILIM
GND
400 W
3.3 V
VO(OUT)
0.1 µF
2 V/div
Output Turn-On Response Test Circuit
t - Time - 2 ms/div
Figure 4.
8
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TYPICAL CHARACTERISTICS (continued)
OUTPUT SWITCHOVER VOLTAGE DROOP
V
I(DO)
5 V
2 V/div
TPS2115A
0.1 µF
1
2
8
7
IN1
STAT
NC
D0
V
f = 580 Hz
90% Duty Cycle
I(D1)
OUT
IN2
C
L
= 1 µF
3
4
6
5
2 V/div
D1
50 W
C
L
ILIM
GND
400 W
V
O(OUT)
0.1 µF
2 V/div
C
L
= 0 µF
Output Switchover Voltage Droop Test Circuit
t - Time - 40 µs/div
Figure 5.
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TYPICAL CHARACTERISTICS (continued)
OUTPUT SWITCHOVER VOLTAGE DROOP
vs
LOAD CAPACITANCE
5
V
I
= 5 V
4.5
4
3.5
3
R = 10 W
L
2.5
2
1.5
1
0.5
0
R
L
= 50 W
0.1
1
10
100
C
L
- Load Capacitance - µF
V
I
TPS2115A
0.1 µF
8
7
6
5
1
2
3
4
IN1
OUT
NC
STAT
D0
f = 28 Hz
50% Duty Cycle
D1
IN2
ILIM
GND
400 W
50 W
10 W
0.1 µF
0.1 µF
1 µF
10 µF
47 µF
100 µF
Output Switchover Voltage Droop Test Circuit
Figure 6.
10
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TYPICAL CHARACTERISTICS (continued)
AUTO SWITCHOVER VOLTAGE DROOP
V
I(IN1)
2V/Div
5 V
TPS2115A
1 kW
0.1 µF
1
2
8
7
IN1
STAT
VOUT
D0
OUT
IN2
f = 220 Hz
20% Duty Cycle
3
4
6
5
3.3 V
D1
50 W
10 µF
ILIM
GND
400 W
0.1 µF
V
O(OUT)
75% less output voltage
2V/Div
droop compared to TPS2115
Auto Switchover Voltage Droop Test Circuit
t - Time - 250 µs/div
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
INRUSH CURRENT
vs
LOAD CAPACITANCE
300
250
200
V = 5 V
I
150
100
50
V = 3.3 V
I
0
0
20
40
60
80
100
C
L
- Load Capacitance - µF
V
I
TPS2115A
0.1 µF
8
7
6
5
To Oscilloscope
1
2
3
4
NC
NC
IN1
STAT
D0
f = 28 Hz
90% Duty Cycle
OUT
IN2
D1
50 W
ILIM
GND
400 W
0.1 µF
0.1 µF
1 µF
10 µF
47 µF
100 µF
Output Capacitor Inrush Current Test Circuit
Figure 8.
12
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TYPICAL CHARACTERISTICS (continued)
SWITCH ON-RESISTANCE
vs
JUNCTION TEMPERATURE
SWITCH ON-RESISTANCE
vs
SUPPLY VOLTAGE
120
115
110
105
100
95
180
160
140
120
100
90
80
60
85
80
2
3
4
5
6
-50
0
50
100
150
T - J unction Temperature - °C
J
V
I(INx)
- Suppl y Voltage - V
Figure 9.
Figure 10.
IN1 SUPPLY CURRENT
vs
SUPPLY VOLTAGE
IN1 SUPPLY CURRENT
vs
SUPPLY VOLTAGE
0.96
0.94
0.92
0.90
0.88
0.86
60
IN1 Switch is ON
Device Disabled
V
I(IN2)
= 0 V
= 0 A
58
56
54
52
50
48
46
44
V
I(IN2)
= 0 V
= 0 A
I
O(OUT)
I
O(OUT)
0.84
0.82
42
40
2
3
4
5
6
2
3
4
5
- Suppl y Voltage - V
6
V
I(IN1)
V
- IN1 Supply Voltage - V
I(IN1)
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
1.2
1
80
IN1 Switch is ON
Device Disabled
V
V
= 5.5 V
= 3.3 V
I(IN1)
V
V
= 5.5 V
= 3.3 V
I(IN1)
70
60
50
I(IN2)
I(IN2)
I
= 0 A
O(OUT)
I
= 0 A
O(OUT)
I
= 5.5 V
I
I(IN1)
I(IN1)
0.8
0.6
0.4
0.2
0
40
30
20
10
0
I
=
I
3.3 V
I(IN2)
I(IN2)
-50
0
50
100
150
-50
0
50
100
150
T - J unction Temperature - °C
J
T - J unction Temperature - °C
J
Figure 13.
Figure 14.
14
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APPLICATION INFORMATION
Some applications have two energy sources, one of which should be used in preference to another. Figure 15
shows a circuit that will connect IN1 to OUT until the voltage at IN1 falls below a user-specified value. Once the
voltage on IN1 falls below this value, the TPS2115A will select the higher of the two supplies. This usually means
that the TPS2115A will swap to IN2.
Switch Status
IN1
2.8 V to 5.5 V
TPS2115A
R1
0.1 µF
1
2
3
4
8
7
6
5
IN1
OUT
IN2
STAT
D0
NC
D1
R
L
C
L
ILIM
GND
R
ILIM
IN2
2.8 V to 5.5 V
C2
0.1 µF
Figure 15. Auto-Selecting for a Dual Power Supply Application
In Figure 16, the multiplexer selects between two power supplies based upon the D1 logic signal. OUT connects
to IN1 if D1 is logic 1; otherwise, OUT connects to IN2. The logic thresholds for the D1 terminal are compatible
with both TTL and CMOS logic.
Switch Status
IN1
2.8 V to 5.5 V
TPS2115A
R1
0.1 µF
1
2
3
4
8
7
6
5
IN1
OUT
IN2
STAT
D0
D1
R
L
C
L
ILIM
GND
R
ILIM
IN2
2.8 V to 5.5 V
0.1 µF
Figure 16. Manually Switching Power Sources
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DETAILED DESCRIPTION
Auto-Switching Mode
D0 equal to logic 1 and D1 equal to logic 0 selects the auto-switching mode. In this mode, OUT connects to the
higher of IN1 and IN2.
Manual Switching Mode
D0 equal to logic 0 selects the manual-switching mode. In this mode, OUT connects to IN1 if D1 is equal to
logic 1, otherwise OUT connects to IN2.
N-Channel MOSFETs
Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic
selects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so
output-to-input current cannot flow when the FET is off. An integrated comparator prevents turn-on of a FET
switch if the output voltage is greater than the input voltage.
Cross-Conduction Blocking
The switching circuitry ensures that both power switches will never conduct at the same time. A comparator
monitors the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source
voltage of the other FET is below the turn-on threshold voltage.
Reverse-Conduction Blocking
When the TPS2115A switches from a higher-voltage supply to a lower-voltage supply, current can potentially
flow back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the
TPS2115A will not connect a supply to the output until the output voltage has fallen to within 100 mV of the
supply voltage. Once a supply has been connected to the output, it will remain connected regardless of output
voltage.
Charge Pump
The higher of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power to the
current limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply voltages.
A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET.
Current Limiting
A resistor RILIM from ILIM to GND sets the current limit to 500/RILIM. Setting resistor RILIM equal to zero is not
recommended as that disables current limiting.
Output Voltage Slew-Rate Control
The TPS2115A slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the Hi-Z state
(see Truth Table). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can
glitch the voltage bus and cause a system to hang up or reset. It can also cause reliability issues such as pitting
the connector power contacts when hot-plugging a load such as a PCI card. The TPS2115A slews the output
voltage at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the output
voltage droop and reduces the output voltage hold-up capacitance requirement.
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Jan-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TPS2115AIPWRQ1
ACTIVE
TSSOP
PW
8
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS2115A-Q1 :
Catalog: TPS2115A
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
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