TPS2157IDGQ [TI]
3.3-V LDO AND DUAL SWITCH FOR USB BUS-POWERED HUB POWER MANAGEMENT; 3.3 -V LDO和双开关， USB总线供电集线器电源管理
| 型号： | TPS2157IDGQ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V LDO AND DUAL SWITCH FOR USB BUS-POWERED HUB POWER MANAGEMENT |
| 文件： | 总19页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2149
TPS2159
SLVS401 – AUGUST 2001
3.3-V LDO AND DUAL SWITCH
FOR USB BUS-POWERED HUB POWER MANAGEMENT
FEATURES
DESCRIPTION
Complete Power Management Solution for
USB Bus-Powered Hubs
The TPS2149 incorporates two power distribution
switches and an LDO in one small package, providing
a USB bus-powered hub power management solution
that saves up to 60% in board space over typical
implementations.
3.3-V 200 mA Low-Dropout Voltage Regulator
Two 5-V 340-mΩ (Typ) High-Side MOSFETs
Independent Thermal- and Short-Circuit
Protection for LDO and Each Switch
The TPS2149 meets USB 2.0 bus-powered hub
requirements. An integrated LDO regulates the 5-V bus
power down to 3.3 V for the USB controller. The two
MOSFET switches provide power to the downstream
ports. With independent enables, the downstream ports
remain unpowered until the hub completes
enumeration.
Overcurrent Indicator With Transient Filter
2.9-V to 5.5-V Operating Range
CMOS- and TTL-Compatible Enable Inputs
75-µA (Typ) Supply Current
Available in 8-Pin MSOP (PowerPAD )
–40°C to 85°C Ambient Temperature Range
Each power-distribution switch is capable of supplying
200 mA of continuous current, and the independent
logic enables are compatible with 5-V logic and 3-V
logic. The switches and the LDO are designed with
controlled rise times and fall times to minimize current
surges.
APPLICATIONS
USB Bus-Powered Hubs
– Keyboards
– Monitors
The TPS2149 has active-low enables while the
TPS2159 has active-high enables.
– Hub Boxes
LDO and dual switch family selection guide and schematics
TPS2149/59
MSOP–8
TPS2148/58
MSOP–8
TPS2145/55
TSSOP–14
TPS2147/57
MSOP–10
LDO_OUT
LDO_ADJ
V
IN/SW1
VIN/SW1
LDO_OUT
VIN
LDO
VIN/SW1
LDO_EN
LDO_OUT
OUT2
LDO
LDO_OUT
LDO
LDO
LDO_EN
EN2
OC1
OC1
OUT1
OC
OUT1
OUT1
EN1
OUT1
EN1
EN1
OUT2
OUT2
OC2
OUT2
OC2
SW2
EN2
GND
SW2
EN2
GND
EN1
GND
EN2
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2001, Texas Instruments Incorporated
1
www.ti.com
TPS2149
TPS2159
SLVS401 – AUGUST 2001
AVAILABLE OPTIONS
PACKAGED DEVICES
PACKAGE
AND PIN
COUNT
T
A
DESCRIPTION
ACTIVE LOW
ACTIVE HIGH
(SWITCH)
(SWITCH)
TPS2145IPWP
TPS2147IDGQ
Adjustable LDO with LDO enable
3.3-V fixed LDO
TSSOP-14
MSOP-10
TPS2155IPWP
TPS2157IDGQ
–40°C to 85°C
3.3-V Fixed LDO with LDO enable and LDO output
switch
MSOP-8
MSOP-8
TPS2148IDGN
TPS2149IDGN
TPS2158IDGN
TPS2159IDGN
3.3-V Fixed LDO, shared input with switches
NOTE: All options available taped and reeled. Add an R suffix (e.g. TPS2145IPWPR)
TPS2149, TPS2159
MSOP (DGN) PACKAGE
(TOP VIEW)
†
†
EN1
EN2
OC
OUT1
VIN
8
7
6
5
1
2
3
4
LDO_OUT
OUT2
GND
†
Pins 7 and 8 are active high for TPS2159.
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Input voltage range: V
Output voltage range: V
Maximum output current, I
Continuous output current, I
,V
, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
I(VIN) I(ENx)
, V
, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
O(OUTx) O(LDO_OUT) O(OC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
O(OC)
O(OUT) O(LDO_OUT)
, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual-junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 110°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Electrostatic discharge (ESD) protection: Human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
Charged device model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND.
‡
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
MSOP8
1455.5 mW
17.1 mW/°C
684.9 mW 428.08 mW
2
www.ti.com
TPS2149
TPS2159
SLVS401 – AUGUST 2001
recommended operating conditions
MIN
2.9
0
MAX
5.5
UNIT
V
V
I(VIN)
Input voltage
V
5.5
I(ENx)
LDO_OUT
200
150
450
400
100
Continuous output current, I
mA
O
OUT1, OUT2
LDO_OUT
250
200
–40
Output current limit, I
mA
O(LMT)
OUT1, OUT2
Operating virtual-junction temperature range, T
°C
J
electrical characteristics over recommended operating junction-temperature range,
2.9 V ≤ V
≤ 5.5 V, T = –40°C to 100°C (unless otherwise noted)
I(VIN)
J
general
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
= 5 V (inactive),
I(ENx)
Off-state supply current
= no load,
= no load
100
µA
O(LDO_OUT)
O(OUTx)
V
V
V
= 5 V (inactive),
I(ENx)
V
V
= 5 V
= 5 V,
I(VIN)
= no load,
= 0 V
O(LDO_OUT)
Forward leakage current (power
switches only)
1
µA
O(OUTx)
(measured from outputs to
ground)
I(VIN)
ENx = on (active)
ENx = off (inactive)
150
100
µA
µA
No load on OUTx,
No load on LDO_OUT
I
I
Total input current at VIN
power switches
PARAMETER
TEST CONDITIONS
= 200 mA,
MIN
TYP
MAX
UNIT
I
O(LDO_OUT)
IOUT1 and IOUT2 = 150 mA, T = –40°C to 100°C
680
Static drain-source
on-state resistance,
VIN to OUTx
J
r
mΩ
DS(on)
I
= 200 mA,
O(LDO_OUT)
IOUT1 and IOUT2 = 150 mA, T = 25°C
340
J
V
V
= 5 V, V
= 5 V
= 0 V,
= 0 V,
= 0 V,
I(ENx)
I(VIN)
I(ENx)
I(ENx)
I(ENx)
10
10
V
V
= 5 V, V
= 2.9 V
I(ENx)
I(VIN)
I
I
Reverse leakage current at OUTx
Short circuit output current
V
= 5 V
µA
lkg(R)
O(OUTx)
V
V
= 5 V, V
= 0 V
I(ENx)
I(VIN)
10
OUTx connected to GND, device enabled into short
circuit
0.2
0.4
A
OS
Delay time for asserting OC flag
Delay time for deasserting OC flag
From IOUTx at 95% of current limit level to 50% OC.
From IOUTx at 95% of current limit level to 50% OC.
5.5
ms
ms
10.5
NOTE 1: Specified by design, not tested in production.
3
www.ti.com
TPS2149
TPS2159
SLVS401 – AUGUST 2001
electrical characteristics over recommended operating junction-temperature range,
2.9 V ≤ V
≤ 5.5 V, T = –40°C to 100°C (unless otherwise noted)
I(VIN)
J
timing parameters, power switches
PARAMETER
TEST CONDITIONS
MIN
0.5
TYP
MAX
6
UNIT
C
C
C
C
C
C
C
C
= 100 µF
= 1 µF
L
L
L
L
L
L
L
L
t
t
t
t
Turnon time, OUTx switch, (see Note 1)
Turnoff time, OUTx switch (see Note 1)
Rise time, OUTx switch (see Note 1)
Fall time, OUTx switch (see Note 1)
R
R
R
R
= 33 Ω
= 33 Ω
= 33 Ω
= 33 Ω
on
off
r
L
L
L
L
0.1
3
= 100 µF
= 1 µF
5.5
10
2
ms
0.05
0.5
= 100 µF
= 1 µF
5
0.1
2
= 100 µF
= 1 µF
5.5
9
f
0.05
1.2
NOTE 1. Specified by design, not tested in production.
undervoltage lockout at VIN
PARAMETER
UVLO Threshold
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
2.2
2.85
Hysteresis (see Note 1)
260
mV
µs
Deglitch (see Note 1)
50
NOTE 1. Specified by design, not tested in production.
electrical characteristics over recommended operating junction-temperature range,
2.9 V ≤ V
(unless otherwise noted)
≤ 5.5 V, V
= 0 V, V
= 5 V, C
= 10 µF, T = –40°C to 100°C
I(VIN)
I(ENx)
I(LDO_EN)
L(LDO_OUT) J
3.3 V LDO
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
= 4.25 V to 5.25 V,
I(VIN)
V
O
Output voltage, dc
Dropout voltage
3.20
3.3
3.40
V
I
= 0.5 mA to 200 mA
O(LDO_OUT)
V
= 3.2 V, I
= 150 mA,
I(VIN)
O(OUT1)
= 200 mA
0.35
V
I
O(LDO_OUT)
Line regulation voltage (see Note 1)
Load regulation voltage (see Note 1)
Short-circuit current limit
V
V
V
V
V
= 4.25 V to 5.25 V, I
= 5 mA
0.1
1%
%/V
I(VIN)
O(LDO_OUT)
= 5 mA to 200 mA
= 4.25 V, I
O(LDO_OUT)
= 4.25 V, LDO_OUT connected to GND
0.4
0.33
10
I(VIN)
I
I
0.275
0.55
A
OS
I(VIN)
= 3.3 V, V
= 5.5 V, V
= 0 V
= 0 V
µA
µA
Reverse leakage current into
LDO_OUT
O(LDO_OUT)
O(LDO_OUT)
I(IN)
I(IN)
lkg(R)
10
f = 1 kHz, C
L(LDO_OUT)
= 4.7 µF, ESR = 0.25 Ω,
= 5 mA, V = 100 mV
Power supply rejection
50
dB
ms
I
O
INp–p
V
R
ramping up from 10% to 90% in 0.1 ms,
IN
= 16 Ω, C
Ramp-up time, LDO_OUT (0% to 90%)
0.1
1
= 10 µF
L(LDO_OUT)
L
†
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
NOTES: 1. Specified by design, not tested in production.
4
www.ti.com
TPS2149
TPS2159
SLVS401 – AUGUST 2001
electrical characteristics over recommended operating junction-temperature range,
2.9 V ≤ V ≤ 5.5 V, V = 0 V, T = –40°C to 100°C (unless otherwise noted)
I(VIN)
I(ENx)
J
enable input, ENx (active low)
PARAMETER
TEST CONDITIONS
MIN
TYP
TYP
MAX
UNIT
V
V
V
High-level input voltage
Low-level input voltage
Input current, pullup (source)
2
IH
0.8
5
V
IL
I
I
V
= 0 V
µA
I(ENx)
I(ENx)
enable input, ENx (active high)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
V
High-level input voltage
Low-level input voltage
Input current, pulldown (sink)
2
IH
0.8
5
V
IL
I
I
V
= 5 V
µA
logic output, OC
PARAMETER
TEST CONDITIONS
MIN
TYP
TYP
MAX
MAX
UNIT
Current sinking at V = 0.4 V
O
1
mA
thermal shutdown characteristics
PARAMETER
TEST CONDITIONS
MIN
120
110
155
UNIT
First thermal shutdown (shuts down switch or regulator
in overcurrent)
Occurs at or above specified temperature
when overcurrent is present.
Recovery from thermal shutdown
°C
Second thermal shutdown (shuts down all switches and Occurs on rising temperature, irrespective of
regulator)
overcurrent.
Second thermal shutdown hysteresis
10
5
www.ti.com
TPS2149
TPS2159
SLVS401 – AUGUST 2001
TPS2149 functional block diagram
3.3 V / 200 mA
LDO
LDO_OUT
OUT1
VIN
CS
Charge
Pump
Current
Limit
Driver
OC
EN1
Thermal
Sense
OUT2
CS
Current
Limit
Driver
EN2
Thermal
Sense
GND
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME
TPS2149 TPS2159
EN1
EN1
EN2
EN2
GND
8
I
I
Logic level enable to transfer power to OUT1
Logic level enable to transfer power to OUT2
8
7
7
5
3
6
1
4
2
5
3
6
1
4
2
Ground
LDO_OUT
OC
O
O
O
LDO output
Overcurrent status flag for OUT1 and OUT2. Open drain output.
Switch 1 output
OUT1
OUT2
VIN
Switch 2 output
I
Input for LDO switch 1 and switch 2; device supply voltage
6
www.ti.com
TPS2149
TPS2159
SLVS401 – AUGUST 2001
detailed description
VIN
The VIN serves as the input to the internal LDO and as the input to both N-channel MOSFETs. The 3.3-V LDO
hasadropoutvoltageof0.35Vandisratedfor200mAofcontinuouscurrent. ThepowerswitchesareN-channel
MOSFETs with a maximum on-state resistance of 580 mΩ per switch. Configured as high-side switches, the
powerswitchespreventcurrentflowfromOUTtoINandINtoOUTwhendisabled. Thepowerswitchesarerated
at 150 mA, continuous current.
OUTx
OUT1 and OUT2 are the outputs from the internal power-distribution switches.
LDO_OUT
LDO_OUT is the output of the internal 200-mA LDO.
enable (ENx, ENx)
The logic enable disables the power switch. Both switches have independent enables and are compatible with
both TTL and CMOS logic.
overcurrent (OC)
The OC open drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
current sense
A sense FET monitors the current supplied to the load. Current is measured more efficiently by the sense FET
than by conventional resistance methods. When an overload or short circuit is encountered, the current-sense
circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power
FET into its saturation region, which switches the output into a constant-current mode and holds the current
constant while varying the voltage on the load.
thermal sense
A dual-threshold thermal trip is implemented to allow fully independent operation of the power distribution
switches. In an overcurrent or short-circuit condition, the junction temperature rises. When the die temperature
rises to approximately 120°C, the internal thermal sense circuitry determines which power switch is in an
overcurrent condition and turns off that switch, thus isolating the fault without interrupting operation of the
adjacent power switch. Because hysteresis is built into the thermal sense, the switch turns back on after the
device has cooled approximately 10 degrees. The switch continues to cycle off and on until the fault is removed.
undervoltage lockout
Avoltagesensecircuitmonitorstheinputvoltage. Whentheinputvoltageisbelowapproximately2.5V, acontrol
signal turns off the power switch.
7
www.ti.com
TPS2149
TPS2159
SLVS401 – AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
50%
50%
V
I(ENx)
t
t
pd(off)
on
pd(on)
t
t
off
90%
10%
90%
10%
V
V
O(OUTx)
t
t
f
r
90%
10%
90%
10%
O(OUTx)
TIMING
Figure 1. Timing and Internal Voltage Regulator Transition Waveforms
TYPICAL CHARACTERISTICS
SWITCH TURNON DELAY AND RISE TIME
SWITCH TURNOFF DELAY AND FALL TIME
WITH 1-µF LOAD
WITH 1-µF LOAD
V
I(EN)
(5 V/div)
V
I(EN)
(5 V/div)
V
O(OUT)
(2 V/div)
V
O(OUT)
(2 V/div)
V = 5 V
V = 5 V
I
T
= 25°C
= 1 µF
= 25 Ω
T
= 25°C
= 1 µF
= 25 Ω
A
L
L
C
R
0
0.4 0.8 1.2 1.6
t – Time – ms
0
0.4 0.8 1.2 1.6
t – Time – ms
2
2.4 2.8 3.2 3.6 4.2
2
2.4 2.8 3.2 3.6 4.2
Figure 2
Figure 3
8
www.ti.com
TPS2149
TPS2159
SLVS401 – AUGUST 2001
TYPICAL CHARACTERISTICS
SWITCH TURNOFF DELAY AND FALL TIME
SWITCH TURNON DELAY AND RISE TIME
WITH 120-µF LOAD
WITH 120-µF LOAD
V
I(EN)
(5 V/div)
V
I(EN)
(5 V/div)
V
O(OUT)
(2 V/div)
V
O(OUT)
(2 V/div)
V = 5 V
V = 5 V
I
T
= 25°C
= 120 µF
= 25 Ω
T
= 25°C
= 120 µF
= 25 Ω
A
L
L
C
R
0
4
8
12 16 20 24 28 32 36 40
t – Time – ms
0
2
4
6
8
10 12 14 16 18 20
t – Time – ms
Figure 4
Figure 5
SHORT-CIRCUIT CURRENT, SWITCH
ENABLED INTO A SHORT
LDO TURNON DELAY AND RISE TIME
WITH 4.7-µF LOAD
V = 5 V
I
A
T
= 25°C
= 4.7 µF
= 13.2 Ω
C
R
L
L
V
I(EN)
(5 V/div)
V
I(LDO_EN)
(5 V/div)
V
O(LDO_OUT)
(1 V/div
I
O(OUT)
(100 mA/div)
0
1
2
3
4
5
6
7
8
9
10
0
0.4 0.8 1.2 1.6
t – Time – ms
2
2.4 2.8 3.2 3.6 4.2
t – Time – ms
Figure 6
Figure 7
9
www.ti.com
TPS2149
TPS2159
SLVS401 – AUGUST 2001
TYPICAL CHARACTERISTICS
LOAD TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
I
O(LDO_OUT)
(200 mA/div)
5.25 V
V
I(VIN)
4.25 V
∆V
O(LDO_OUT)
∆V
O(LDO_OUT)
(0.05 V/div)
(100 mV/div)
T
C
= 25°C
T
C
= 25°C
= 4.7 µF
L(LDO_OUT)
A
A
= 4.7 µF
L(LDO_OUT)
ESR = 1 Ω
ESR = 1 Ω
I
= 200 mA
O(LDO_OUT)
0
100 200 300 400
500 600 700 800 900 1000
0
100 200 300 400
500 600 700 800 900 1000
t – Time – µs
t – Time – µs
Figure 9
Figure 8
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
SUPPLY VOLTAGE
140
120
100
80
140
120
100
80
60
60
40
20
0
40
20
0
–40
–20
0
T
20
40
60
80
100
2.5
3
3.5
– Supply Voltage – V
CC
4
4.5
5
5.5
– Temperature – °C
V
J
Figure 10
Figure 11
10
www.ti.com
TPS2149
TPS2159
SLVS401 – AUGUST 2001
TYPICAL CHARACTERISTICS
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
vs
JUNCTION TEMPERATURE
SUPPLY VOLTAGE
0.6
0.38
0.55
0.5
0.37
0.36
0.35
0.34
0.33
0.32
0.45
0.4
SW1
SW1
SW2
0.35
0.3
SW2
0.25
0.2
0.31
0.3
0.15
0.1
–40 –20
0
20
40
60
80
100
2.5
3
3.5
CC
4
4.5
5
5.5
T
J
– Junction Temperature – °C
V
– Supply Voltage
Figure 12
Figure 13
SHORT CIRCUIT CURRENT
vs
SHORT CIRCUIT CURRENT
vs
JUNCTION TEMPERATURE
SUPPLY VOLTAGE
400
400
380
360
340
320
300
280
260
240
380
360
340
320
300
280
260
240
SW1
SW2
SW1
SW2
220
200
220
200
–40
–20
0
20
40
60
80
100
2.5
3
3.5
V – Supply Voltage
CC
4
4.5
5
5.5
T
J
– Free-Air Temperature – °C
Figure 14
Figure 15
11
www.ti.com
TPS2149
TPS2159
SLVS401 – AUGUST 2001
TYPICAL CHARACTERISTICS
UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
Rising
Falling
–40 –25 –10
5
20 35 50 65 80 95 110
T
J
– Junction Temperature – °C
Figure 16
APPLICATION INFORMATION
external capacitor requirements on power lines
A ceramic bypass capacitor (0.01-µF to 0.1-µF) between VIN and GND, close to the device, is recommended
to improve load transient response and noise rejection.
A bulk capacitor (4.7-µF ) between VIN and GND is also recommended, especially if load transients in the
hundreds of milliamps with fast rise times are anticipated.
A 66-µF bulk capacitor is recommended from OUTx to ground, especially when the output load is heavy. This
precaution helps reduce transients seen on the power rails. Additionally, bypassing the outputs with a 0.1-µF
ceramic capacitor improves the immunity of the device to short-circuit transients.
LDO output capacitor requirements
Stabilizing the internal control loop requires an output capacitor connected between LDO_OUT and GND. The
minimum recommended capacitance is a 4.7 µF with an ESR value between 200 mΩ and 10 Ω. Solid tantalum
electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the
ESR requirements.
overcurrent
A sense FET is used to measure current through the device. Unlike current-sense resistors, sense FETs do not
increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current. Complete shut down occurs only if the fault is present long enough to
activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output is shorted before the device is
enabledorbeforeVINhasbeenapplied. TheTPS2149andTPS2159sensetheshortandimmediatelyswitches
to a constant-current output.
12
www.ti.com
TPS2149
TPS2159
SLVS401 – AUGUST 2001
APPLICATION INFORMATION
overcurrent (continued)
In the second condition, the short occurs while the device is enabled. At the instant the short occurs, very high
currents may flow for a very short time before the current-limit circuit can react. After the current-limit circuit has
tripped (reached the overcurrent trip threshold), the device switches into constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded. TheTPS2149andTPS2159arecapableofdeliveringcurrentuptothecurrent-limitthresholdwithout
damagingthedevice. Oncethethresholdhasbeenreached, thedeviceswitchesintoitsconstant-currentmode.
OC response
The OC open-drain output is asserted (active low) when an overcurrent condition is encountered. The output
will remain asserted until the overcurrent condition is removed. Connecting a heavy capacitive load to an
enabled device can cause momentary false overcurrent reporting from the inrush current flowing through the
device, charging the downstream capacitor. The TPS2149 and TPS2159 are designed to reduce false
overcurrent reporting. An internal overcurrent transient filter eliminates the need for external components to
removeunwantedpulses. Usinglow-ESRelectrolyticcapacitorsonOUTxlowerstheinrushcurrentflowthrough
the device during hot-plug events by providing a low-impedance energy source, also reducing erroneous
overcurrent reporting.
power dissipation and junction temperature
The main source of power dissipation for the TPS2149 and TPS2159 comes from the internal voltage regulator
and the N-channel MOSFETs. Checking the power dissipation and junction temperature is always a good
designpracticeanditstartswithdeterminingther
oftheN-channelMOSFETaccordingtotheinputvoltage
(on)
DS
and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and
read r from the graphs shown in the Typical Characteristics section of this data sheet. Using this value,
(on)
DS
the power dissipation per switch can be calculated using:
2
P
r
I
D
DS(on)
(1)
(2)
Multiply this number by two to get the total power dissipation coming from the N-channel MOSFETs.
The power dissipation for the internal voltage regulator is calculated using:
P
V –V
I
D
I
O(min)
O
The total power dissipation for the device becomes:
P
P
2
P
D(total)
D(voltage regulator)
Finally, calculate the junction temperature:
D(switch)
(3)
(4)
T
P
R
T
J
D
JA
A
Where:
T = Ambient temperature °C
A
R
= Thermal resistance °C/W, equal to inverting the derating factor found on the power dissipation
θJA
table in this datasheet.
13
www.ti.com
TPS2149
TPS2159
SLVS401 – AUGUST 2001
APPLICATION INFORMATION
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
thermal protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS2149 and TPS2159 into constant-current mode at first, which
causes the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across
the switch is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high
levels.
The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the
thermal sense circuit, and after the device has cooled approximately 10 degrees, the switch turns back on. The
switch continues to cycle in this manner until the load fault or input power is removed.
The TPS2149 and TPS2159 implement a dual thermal trip to allow fully independent operation of the power
distribution switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die
temperature rises to approximately 120°C, the internal thermal sense circuitry checks which power switch is
in an overcurrent condition and turns that power switch off, thus isolating the fault without interrupting operation
of the adjacent power switch. Should the die temperature exceed the first thermal trip point of 120°C and reach
155°C, the device will turn off.
undervoltage lockout (UVLO)
An undervoltage lockout ensures that the device (LDO and switches) is in the off state at power up. The UVLO
will also keep the device from being turned on until the power supply has reached the start threshold (see
undervoltage lockout table), even if the switches are enabled. The UVLO will also be activated whenever the
input voltage falls below the stop threshold as defined in the undervoltage lockout table. This facilitates the
design of hot-insertion systems where it is not possible to turn off the power switches before input power is
removed. Upon reinsertion, the power switches will be turned on with a controlled rise time to reduce EMI and
voltage overshoots.
universal serial bus (USB) applications
The universal serial bus (USB) interface is a multiplexed serial bus operating at either 12 Mb/s, or 1.5 Mb/s for
USB 1.1, or 480 Mb/s for USB 2.0. The USB interface is designed to accommodate the bandwidth required by
PC peripherals such as keyboards, printers, scanners, and mice. The four-wire USB interface was conceived
for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two
lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub or across long cables. Each function must provide its own regulated
3.3 V from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
•
•
•
•
•
Hosts/self-powered hubs (SPH)
Bus-powered hubs (BPH)
Low-power, bus-powered functions
High-power, bus-powered functions
Self-powered functions
14
www.ti.com
TPS2149
TPS2159
SLVS401 – AUGUST 2001
APPLICATION INFORMATION
universal serial bus (USB) applications (continued)
The TPS2149 and TPS2159 are well suited for USB bus-powered hub applications. The internal LDO can be
used to provide the 3.3 V power needed by the controller while the dual switches distribute power to the
downstream functions.
USB power distribution requirements
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
•
Hosts/self-powered hubs must:
–
–
Current-limit downstream ports
Report overcurrent conditions on USB V
BUS
Bus-powered hubs must:
–
–
–
Enable/disable power to downstream ports
Power up at <100 mA
Limit inrush current (<44 Ω and 10 µF)
Functions must:
–
–
Limit inrush currents
Power up at <100 mA
The feature set of the TPS2149 and TPS2159 is designed to help USB bus-powered hubs meet the
requirements. The integrated current-limiting and overcurrent reporting is required by hosts and self-powered
hubs. The logic-level enable and controlled rise times meet the need of both input and output ports on
bus-powered hubs, as well as the input ports for bus-powered functions.
USB applications
Figure 17 shows the TPS2149 being used in a USB bus-powered two-port hub design. The internal 3.3-V LDO
is used to provide power for the USB function controller as well as to the 1.5-kΩ pullup resistor.
Switches 1 and 2 provide power to the downstream ports. Both are separately enabled to control power being
sent downstream. They are also disabled during enumeration to satisfy the 100 mA requirement.
Figure 18 shows the TPS2149 being used in a USB bus-powered four-port hub design. The internal 3.3-V LDO
is used to provide power for the USB function controller as well as to the 1.5 kΩ pullup resistor.
15
www.ti.com
TPS2149
TPS2159
SLVS401 – AUGUST 2001
APPLICATION INFORMATION
Upstream Port
USB Hub Controller
Downstream Port
D+
D–
D+
D–
DP0
DM0
DP1
DM1
GND
GND
SN75240
SN75240
C
D
C
D
A
B
A
B
5 V
5 V
68 µF
VCC_3.3 V
D+
D–
DP2
DM2
0.1 µF
DP3
DM3
GND
0.1 µF
10 µF
SN75240
XTAL1
XTAL2
33 pF
5 V
C
D
A
B
6 MHz
1.5 kΩ
68 µF
DP4
DM4
D+
D–
33 pF
1.5 kΩ
TPS2149
GND
GND
GND
EN1
OUT1
OUT2
PWRON1
PWRON2
OVRCUR
EN2
OC
5 V
68 µF
D+
D–
3.3 V_OUT
VIN
0.1 µF
10 µF
GND
5 V
68 µF
Figure 17. Example of a Two Port Hub Design With TPS2149
16
www.ti.com
TPS2149
TPS2159
SLVS401 – AUGUST 2001
APPLICATION INFORMATION
Upstream Port
D+
USB Hub Controller
Downstream Port
D+
DP0
DM0
DP1
DM1
D–
D–
SN75240
SN75240
GND
GND
C
D
C
D
A
B
A
B
5 V
5 V
68 µF
VCC_3.3 V
D+
DP1
DM1
0.1 µF
D–
0.1 µF
XTAL1
XTAL2
33 pF
GND
6 MHz
1.5 kΩ
TPS2149
5 V
EN1
OUT1
OUT2
PWRON1
PWRON2
OVRCUR
10 µF
33 pF
68 µF
GND
GND
EN2
OC
1.5 kΩ
3.3 V_OUT
VIN
10 µF
0.1 µF
Figure 18. Example of a 4 Port Hub Design With TPS2149
17
www.ti.com
TPS2149
TPS2159
SLVS401 – AUGUST 2001
DGN (S-PDSO-G8)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
0,65
M
0,25
8
5
Thermal Pad
(See Note D)
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
0°–6°
1
4
0,69
0,41
3,05
2,95
Seating Plane
0,10
0,15
0,05
1,07 MAX
4073271/A 04/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusions.
D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments.
18
www.ti.com
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its products to the specifications applicable at the time of sale in accordance with
TI’sstandardwarranty. TestingandotherqualitycontroltechniquesareutilizedtotheextentTIdeemsnecessary
to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except
those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
products or services might be or are used. TI’s publication of information regarding any third party’s products
or services does not constitute TI’s approval, license, warranty or endorsement thereof.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation
or reproduction of this information with alteration voids all warranties provided for an associated TI product or
service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.
Resale of TI’s products or services with statements different from or beyond the parameters stated by TI for
that product or service voids all express and any implied warranties for the associated TI product or service,
is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.
Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2001, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明