TPS22810DBVR [TI]
具备可调节上升和可调节输出放电的 18V、3A、79mΩ 负载开关 | DBV | 6 | -40 to 105;
| 型号： | TPS22810DBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具备可调节上升和可调节输出放电的 18V、3A、79mΩ 负载开关 | DBV | 6 | -40 to 105 开关 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总37页 (文件大小：2554K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS22810
ZHCSFR6C –DECEMBER 2016–REVISED JANUARY 2018
TPS22810，具有热保护的 2.7V-18V、79mΩ 导通电阻负载开关
1 特性
3 说明
1
•
集成单通道负载开关
TPS22810 是一款单通道负载开关，其具有可配置的
上升时间并集成有快速输出放电 (QOD) 功能。此外，
该器件还 具有 热关断保护，可防止器件结温过高，借
此从内部确保器件处于安全工作区域。该器件包括一个
N 通道金属氧化物半导体场效应晶体管 (MOSFET)，
可在 2.7V 至 18V 的输入电压范围内运行。SOT23-5
(DBV) 封装可支持 2A 的最大电流。WSON (DRV) 封
装可支持 3A 的最大电流。此开关由一个开关输入控
制，能够直接连接低电压控制信号。
•
运行环境温度范围：
–40°C 至 +105°C
–
–
SOT23-6 (DBV)：2A 最大持续工作电流1
WSON (DRV)：3A 最大持续电流 1
•
•
•
输入电压范围：2.7V 至 18V
绝对最大输入电压：20V
导通电阻 (RON
RON = 79mΩ（VIN = 12V 时的典型值）
静态电流
62µA（VIN = 12V 时的典型值）
关断电流
)
–
•
•
该器件的可配置上升时间可大幅降低大容量负载电容所
产生的浪涌电流，从而降低或消除电源压降。欠压闭锁
用于在 VIN 电压降至阈值以下时关闭器件，以确保下
游电路不会因为供电电压低于预期值而损坏。可配置的
快速输出放电 (QOD) 引脚控制器件的下降时间，以便
针对掉电进行灵活设计。
–
–
500nA（VIN = 12V 时的典型值）
•
•
•
•
•
热关断
欠压闭锁 (UVLO)
可调节快速输出放电 (QOD)
可通过 CT 引脚配置的上升时间
小外形尺寸晶体管 (SOT) 23-6 封装
TPS22810 采用方便目测检查焊点的带引线 SOT-23
封装 (DBV) 以及 WSON 封装 (DRV)。该器件在自然
通风环境下的额定运行温度范围为 -40˚C 至 +105˚C。
删除的 IMAX 和 IPLS
–
2.9mm × 2.8mm，0.95mm 间距，
1.45mm 高 (DBV)
•
WSON 封装
2mm × 2mm，0.65mm 间距，
0.75mm 高 (DRV)
静电放电 (ESD) 性能经测试符合 JESD 22 规范
Device Information(1)
–
PART NUMBER
PACKAGE
SOT-23 (6)
WSON (6)
BODY SIZE (NOM)
2.90mm x 2.80mm
2.00mm × 2.00mm
TPS22810
•
–
±2kV 人体模型 (HBM) 和 ±1kV 带电器件模型
(CDM)
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
(1)
必须考虑热性能
简化原理图
VIN
VOUT
QOD
CT
Power
Supply
2 应用
CIN
RL
CL
•
•
•
•
高清电视
GND
工业系统
机顶盒
ON
监控系统
EN/
UVLO
OFF
TPS22810
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDH0
TPS22810
ZHCSFR6C –DECEMBER 2016–REVISED JANUARY 2018
www.ti.com.cn
目录
9.4 Device Functional Modes........................................ 17
10 Application and Implementation........................ 18
10.1 Application Information.......................................... 18
10.2 ON and OFF Control............................................. 18
10.3 Input Capacitor (Optional)..................................... 18
10.4 Output Capacitor (Optional).................................. 18
10.5 Typical Application ............................................... 18
11 Power Supply Recommendations ..................... 23
12 Layout................................................................... 24
12.1 Layout Guidelines ................................................. 24
12.2 Layout Example .................................................... 24
12.3 Thermal Considerations........................................ 24
13 器件和文档支持 ..................................................... 25
13.1 器件支持................................................................ 25
13.2 Documentation Support ........................................ 25
13.3 接收文档更新通知 ................................................. 25
13.4 Community Resources.......................................... 25
13.5 商标....................................................................... 25
13.6 静电放电警告......................................................... 25
13.7 Glossary................................................................ 25
14 机械、封装和可订购信息....................................... 25
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings ............................................................ 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Switching Characteristics.......................................... 7
7.7 Typical DC Characteristics ....................................... 8
7.8 Typical AC Characteristics........................................ 9
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 13
9.3 Feature Description................................................. 13
8
9
4 修订历史记录
Changes from Revision B (May 2017) to Revision C
Page
•
Changed Rise time can be calculated by multiplying to Rise time can be calculated by dividing in the Feature
Description Section 9.3.4 Adjustable Rise Time (CT) .......................................................................................................... 17
Changes from Revision A (December2016) to Revision B
Page
•
•
将 WSON (DRV) 的当前信息添加至特性 , 说明部分和建议运行条件表中.............................................................................. 1
已添加 WSON (DRV) 封装 ..................................................................................................................................................... 1
Changes from Original (December 2016) to Revision A
Page
•
•
•
•
从绝对最大额定值表中............................................................................................................................................................ 1
Deleted IMAX and IPLS from the Absolute Maximum Ratings table .......................................................................................... 4
Changed the Quiescent current MAX value From: 70 µA To: 80 µA in the Electrical Characteristics table ......................... 5
Changed the Quiescent current MAX value for VIN = 2.7 V From: 60 µA To: 70 µA in the Electrical Characteristics
table ....................................................................................................................................................................................... 5
•
Changed the Shutdown current MAX value From: 2.25 µA To: 2.3 µA in the Electrical Characteristics table...................... 5
2
Copyright © 2016–2018, Texas Instruments Incorporated
TPS22810
www.ti.com.cn
ZHCSFR6C –DECEMBER 2016–REVISED JANUARY 2018
5 Device Comparison Table
MAXIMUM
OUTPUT
CURRENT
QUICK OUTPUT
DISCHARGE
DEVICE
RON at 12 V
Package
TA
ENABLE
TPS22810
TPS22810
79 mΩ
79 mΩ
DBV
DRV
Configurable
Configurable
105°C
105°C
2 A
3 A
Active High
Active High
6 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
DRV Package
6-Pin WSON
Top View
VOUT
QOD
CT
1
6
VIN
VOUT
QOD
CT
VIN
GND
1
6
2
3
5
4
EN/UVLO
GND
5
2
3
4
EN/UVLO
Pin Functions
PIN
NO,
I/O
DESCRIPTION
NAME
SOT23
WSON
CT
4
3
O
I
Switch slew rate control. Can be left floating
Active high switch control input and UVLO adjustment. Do not leave
floating
EN/UVLO
GND
3
2
5
4
—
Device ground
Quick Output Discharge pin. This functionality can be enabled in one
of three ways.
•
•
Placing an external resistor between VOUT and QOD
QOD
5
2
O
Tying QOD directly to VOUT and using the internal resistor value
(RPD
)
•
Disabling QOD by leaving pin floating
See the Quick Output Discharge (QOD) for more information
VIN
1
6
6
1
I
Switch input. Place ceramic bypass capacitor(s) between this pin and
GND
VOUT
O
Switch output
Copyright © 2016–2018, Texas Instruments Incorporated
3
TPS22810
ZHCSFR6C –DECEMBER 2016–REVISED JANUARY 2018
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
V
VIN
Input voltage
20
VOUT
VEN/UVLO
TJ
Output voltage
min(VIN + 0.3, 20)
V
EN/UVLO voltage
Maximum junction temperature
Storage temperature
20
V
150
150
°C
°C
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
±2000
±1000
UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Charged-device model (CDM), per JEDEC specification JESD22-C101
Electrostatic
discharge
V(ESD)
V
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
2.7
0
MAX UNIT
VIN
Input voltage
18
18
VIN
2
V
V
V
VEN/UVLO
VOUT
EN/UVLO voltage
Output voltage
IMAX
Maximum continuous switch current, TA = 65°C (DBV)
A
Maximum continuous switch current, TA = 65°C (DRV)
3
(1)
TA
Operating free-air temperature
–40
1(2)
105
°C
µF
CIN
Input capacitor
(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(MAX)], the
maximum power dissipation of the device in the application [PD(MAX)], and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(MAX) = TJ(MAX) – (θJA × PD(MAX)).
(2) See the Detailed Description section.
7.4 Thermal Information
TPS22810
(1)
THERMAL METRIC
DBV (SOT23)
6 PINS
182
DRV (WSON)
6 PINS
74.6
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
127.2
80.3
16.9
44.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
26.4
3.2
ψJB
36.3
44.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2016–2018, Texas Instruments Incorporated
TPS22810
www.ti.com.cn
ZHCSFR6C –DECEMBER 2016–REVISED JANUARY 2018
7.5 Electrical Characteristics
Unless otherwise noted, the specification in the following table applies over the following ambient operating temperature
–40°C ≤ TA ≤ +105°C. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
80
UNIT
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +105°C
62
VIN = 18 V
85
62
59
80
VIN = 12 V
85
80
Quiescent
current
IQ, VIN
V = 18 V, I = 0 A
VIN = 5 V
VIN = 3.3 V
µA
85
53
80
85
49
70
VIN = 2.7 V
85
0.5
0.5
0.5
0.5
0.5
2.3
3.8
2.3
3.8
2.3
3.8
2.3
3.8
2.3
3.8
VIN = 18 V
VIN = 12 V
Shutdown
current
ISD, VIN
VON = 0 V, VOUT = 0 V VIN = 5 V
µA
VIN = 3.3 V
VIN = 2.7 V
EN/UVLO pin
IEN/UVLO input leakage
current
VIN = 18 V, IOUT = 0 A
–40°C to +105°C
0.1
µA
V
VIN UVLO
VUVR
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
2
2.54
5%
2.62
threshold, rising
VIN UVLO
VUVhyst
hysteresis
EN threshold
VENR
1.13
1.08
1.23
1.13
1.3
V
V
voltage, rising
EN threshold
VENF
1.18
voltage, falling
EN threshold
VSHUTF voltage for low
IQ shutdown
–40°C to +105°C
0.5
0.75
0.9
V
Copyright © 2016–2018, Texas Instruments Incorporated
5
TPS22810
ZHCSFR6C –DECEMBER 2016–REVISED JANUARY 2018
www.ti.com.cn
Electrical Characteristics (continued)
Unless otherwise noted, the specification in the following table applies over the following ambient operating temperature
–40°C ≤ TA ≤ +105°C. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
86
UNIT
25°C
79
VIN = 18 V, IOUT = –200 mA
–40°C to +85°C
–40°C to +105°C
25°C
105
115
86
79
79
79
83
86
VIN = 12 V, IOUT = –200 mA
VIN = 9 V, IOUT = –200 mA
VIN = 5 V, IOUT = –200 mA
VIN = 3.3 V, IOUT = –200 mA
VIN = 2.7 V, IOUT = –200 mA
–40°C to +85°C
–40°C to +105°C
25°C
105
115
86
–40°C to +85°C
–40°C to +105°C
25°C
105
115
86
RON
On-resistance
mΩ
–40°C to +85°C
–40°C to +105°C
25°C
105
115
92
–40°C to +85°C
–40°C to +105°C
25°C
115
125
95
–40°C to +85°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
120
130
350
350
400
VIN = VOUT = 18 V, VEN/UVLO = 0 V
VIN = VOUT = 12 V, VEN/UVLO = 0 V
VIN = VOUT = 5 V, VEN/UVLO = 0 V
290
265
250
Output pull
down resistance
RPD
TS
Ω
Thermal
shutdown
Threshold, VIN = 18 V
–40°C to +105°C
160
°C
°C
Thermal
shutdown
hysteresis
TSHDN
Hyst
TSD hysteresis, VIN = 18 V
–40°C to +105°C
30
6
Copyright © 2016–2018, Texas Instruments Incorporated
TPS22810
www.ti.com.cn
ZHCSFR6C –DECEMBER 2016–REVISED JANUARY 2018
7.6 Switching Characteristics
Refer to the timing test circuit in Figure 16 (unless otherwise noted) for references to external components used for the test
condition in the switching characteristics table. Switching characteristics shown below are only valid for the power-up
sequence where VIN is already in steady state condition before the EN/UVLO pin is asserted high.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN = 18 V, VEN/UVLO = 5 V, TA = 25 °C (unless otherwise noted)
tON
tOFF
tR
Turnon time
Turnoff time
VOUT rise time
VOUT fall time
Delay time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
520
3.3
700
2
µs
tF
tD
180
VIN = 12 V, VEN/UVLO = 5 V, TA = 25 °C (unless otherwise noted)
tON
tOFF
tR
Turnon time
Turnoff time
VOUT rise time
VOUT fall time
ON delay time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
380
3.3
460
2
µs
tF
tD
150
VIN = 3.3 V, VEN/UVLO = 5 V, TA = 25 °C (unless otherwise noted)
tON
tOFF
tR
Turnon time
Turnoff time
VOUT rise time
VOUT fall time
ON delay time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
185
3.3
120
2
µs
tF
tD
130
Copyright © 2016–2018, Texas Instruments Incorporated
7
TPS22810
ZHCSFR6C –DECEMBER 2016–REVISED JANUARY 2018
www.ti.com.cn
7.7 Typical DC Characteristics
90
80
70
60
50
40
30
1.8
1.6
1.4
1.2
1
-40èC
25èC
85èC
105èC
0.8
0.6
0.4
0.2
0
-40èC
25èC
85èC
105èC
20
10
0
2.7
4.7
6.7
8.7
10.7
12.7
14.7
16.7 18
2.7
4.7
6.7
8.7
10.7
12.7
14.7
16.7 18
Input Voltage (V)
Input Voltage (V)
D001
D002
VEN/UVLO = 5 V
IOUT = 0 A
VEN/UVLO = 0 V
IOUT = 0 A
Figure 1. Quiescent Current vs Input Voltage
Figure 2. Shutdown Current vs Input Voltage
140
130
120
110
100
90
160
140
120
100
80
VIN = 2.7 V
VIN = 3.3 V
VIN í 5 V
80
60
70
40
-40èC
25èC
85èC
105èC
60
20
50
40
0
-40
-20
0
20
40
60
80
100
2.7
4.7
6.7
8.7
10.7
12.7
14.7
16.7 18
Temperature (èC)
Input Voltage (V)
D003
D004
VEN/UVLO = 5 V
IOUT = –200 mA
VEN/UVLO = 5 V
IOUT = –200 mA
Figure 3. On-Resistance vs Temperature
Figure 4. On-Resistance vs Input Voltage
450
400
350
300
250
200
150
100
50
1.155
1.15
1.145
1.14
1.135
1.13
1.125
1.12
-40èC
25èC
1.115
1.11
-40 èC
25èC
85èC
105èC
85èC
105èC
1.105
2.7
4.7
6.7
8.7
10.7
12.7
14.7
16.7 18
2.7
4.7
6.7
8.7
10.7
12.7
14.7
16.7 18
Input Voltage (V)
Input Voltage (V)
D006
D007
IOUT = 0 A
Figure 5. EN VIL vs Input Voltage
VIN = VOUT
VEN/UVLO = 0 V
Figure 6. Output Pull-Down Resistance vs Input Voltage
8
Copyright © 2016–2018, Texas Instruments Incorporated
TPS22810
www.ti.com.cn
ZHCSFR6C –DECEMBER 2016–REVISED JANUARY 2018
7.8 Typical AC Characteristics
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
200
180
160
140
120
100
80
60
-40èC
25èC
85èC
105èC
-40èC
25èC
85èC
105èC
40
20
0
2.7
4.7
6.7
8.7
10.7
12.7
14.7
16.7 18
2.7
4.7
6.7
8.7
10.7
12.7
14.7
16.7 18
Input Voltage (V)
Input Voltage (V)
D008
D009
CIN = 1 µF
RL = 10 Ω
CL = 0.1 µF
CIN = 1 µF
RL = 10 Ω
CL = 0.1 µF
CT = 2200 pF
CT = 2200 pF
Figure 7. VOUT Rise Time (tR) vs Input Voltage
Figure 8. Delay Time (tD) vs Input Voltage
1.8
1.6
1.4
1.2
1
5
4.5
4
3.5
3
2.5
2
0.8
0.6
0.4
0.2
0
1.5
1
-40èC
25èC
85èC
105èC
-40èC
25èC
85èC
105èC
0.5
0
2.7
4.7
6.7
8.7
10.7
12.7
14.7
16.7 18
2.7
4.7
6.7
8.7
10.7
12.7
14.7
16.7 18
Input Voltage (V)
Input Voltage (V)
D010
D011
CIN = 1 µF
RL = 10 Ω
CL = 0.1 µF
CIN = 1 µF
RL = 10 Ω
CL = 0.1 µF
Figure 9. VOUT Fall Time (tF) vs Input Voltage
Figure 10. Turnoff Time (tOFF) vs Input Voltage
600
550
500
450
400
350
300
250
200
150
100
VIN
VON
VOUT
-40èC
25èC
85èC
105èC
IIN
2.7
4.7
6.7
8.7
10.7
12.7
14.7
16.7 18
Input Voltage (V)
D012
CIN = 1 µF
RL = 10 Ω
CL = 0.1 µF
CT = 2200 pF
Figure 11. Turnon Time (tON) vs Input Voltage
VIN = 5 V
CIN = 1 µF
CL = 0.1 µF
RL = 10 Ω
CT = 2200 pF
Figure 12. Rise Time tR at VIN = 5 V
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Typical AC Characteristics (continued)
VIN
VIN
VON
VON
VOUT
VOUT
IIN
IIN
VIN = 5 V
CIN = 1 µF
CL = 0.1 µF
VIN = 12 V
CIN = 1 µF
CL = 0.1 µF
RL = 10 Ω
QOD = Open
RL = 10 Ω
CT = 2200 pF
Figure 13. Fall Time tF at VIN = 5 V
Figure 14. Rise Time tR at VIN = 12 V
VIN
VON
VOUT
IIN
VIN = 12 V
CIN = 1 µF
QOD = Open
CL = 0.1 µF
RL = 10 Ω
Figure 15. Fall Time tF at VIN = 12 V
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8 Parameter Measurement Information
VIN
VOUT
CIN = 1 µF
+
-
CL
ON
(A)
RL
EN/UVLO
GND
OFF
TPS22810
GND
GND
A. Rise and fall times of the control signal are 100 ns
Figure 16. Test Circuit
VON
50%
50%
tF
tR
tOFF
tOUT
90%
90%
VOUT
VOUT
50%
50%
10%
10%
100%
tD
Figure 17. Timing Waveforms
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9 Detailed Description
9.1 Overview
The TPS22810 is a 6-pin, 2.7-18-V load switch with thermal protection in two separate package options. To
reduce voltage drop for low voltage and high current rails, the device implements a low resistance N-channel
MOSFET which reduces the drop out voltage across the device.
The device starts its operation by monitoring the VIN bus. When VIN exceeds the undervoltage-lockout threshold
(VUVR), the device samples the EN/UVLO pin. A high level on this pin enables the internal MOSFET. As VIN
rises, the internal MOSFET of the device starts conducting and allow current to flow from VIN to VOUT. When
EN/UVLO is held low (below VENF), internal MOSFET is turned off.
A voltage V(EN/UVLO) < V(ENF) on this pin turns off the internal FET, thus disconnecting VIN from VOUT, while
voltage below V(SHUTF) takes the device into shutdown mode, with IQ less than 1 μA to ensure minimal power
loss.
The device has a configurable slew rate which helps reduce or eliminate power supply droop because of large
inrush currents. The device also features an internal RPD resistor, which discharges VOUT once the switch is
disabled.
During shutdown, the device has very low leakage currents, thereby reducing unnecessary leakages for
downstream modules during standby. Integrated control logic, driver, charge pump, and output discharge FET
eliminates the need for any external components which reduces solution size and bill of materials (BOM) count.
The device also features a QOD pin, which allows the configuration of the discharge rate of VOUT once the
switch is disabled.
The device has a thermal protection feature. Due to this device protects itself against thermal damage due to
over-temperature and over-current conditions. Safe Operating Area (SoA) requirements are thus inherently met
without any special design consideration by the board designer.
12
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9.2 Functional Block Diagram
VIN
Charge Pump
EN/UVLO
Control Logic
CT
VOUT
QOD
2.54 V
2.4 V
1.23 V
1.13 V
Thermal
Shutdown
GND
Copyright © 2016, Texas Instruments Incorporated
9.3 Feature Description
9.3.1 On and Off Control
TThe EN/UVLO pin controls the state of the switch. EN/UVLO is active high and has a low threshold, making it
capable of interfacing with low-voltage signals. The EN/UVLO pin is compatible with standard GPIO logic
threshold. It can be used with any microcontroller with 1.2 V or higher GPIO voltage. This pin cannot be left
floating and must be driven either high or low for proper functionality.
9.3.2 Quick Output Discharge (QOD)
The TPS22810 includes a QOD feature. The QOD pin can be configured in one of three ways:
•
QOD pin shorted to VOUT pin. Using this method, the discharge rate after the switch becomes disabled is
controlled with the value of the internal resistance RPD. The value of this resistance is listed in the Electrical
Characteristics table.
•
QOD pin connected to VOUT pin using an external resistor REXT. After the switch becomes disabled, the
discharge rate is controlled by the value of the total resistance of the QOD. To adjust the total QOD
resistance, Equation 1 can be used.
RQOD = RPD + REXT
where
•
•
•
RQOD is the total output discharge resistance
RPD is the internal pulldown resistance
REXT is the external resistance placed between the VOUT and QOD pin.
(1)
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Feature Description (continued)
•
QOD pin is unused and left floating. Using this method, there is no quick output discharge functionality, and
the output remains floating after the switch is disabled.
Note that during thermal shutdown, the QOD functionality is not available. The device does not discharge the
load as RPD does not become engaged.
The fall times of the device depend on many factors including the total resistance of the QOD, VIN, and the
output capacitance. When QOD is connected to VOUT, the fall time changes over VIN as the internal RPD varies
over VIN. To calculate the approximate fall time of VOUT for a given RQOD, use Equation 2 and Table 1.
VCAP = VIN × e-t/τ
where
•
•
•
VCAP is the voltage across the capacitor (V)
t is the time since power supply removal (s)
τ is the time constant equal to RQOD × CL
(2)
The fall times' dependency on VIN becomes minimal as the QOD value increases with additional external
resistance. See Table 1 for QOD fall times.
Table 1. QOD Fall Times
FALL TIME (μs) 90% - 10%, CIN = 1 μF, IOUT = 0 A , VIN = 0 V, ON = 0 V(1)
VIN (V)
TA = 25°C
CL = 10 μF
4700
TA = 85°C
CL = 10 μF
4700
CL = 1 μF
470
CL = 100 μF
47000
CL = 1 μF
470
CL = 100 μF
47000
18
12
9
450
4500
45000
450
4500
45000
440
4400
44000
440
4400
44000
5
500
5000
50000
480
4800
48000
3.3
600
6000
60000
570
5700
57000
(1) TYPICAL VALUES WITH QOD SHORTED TO VOUT
9.3.2.1 QOD when System Power is Removed
The adjustable QOD can be used to control the power down sequencing of a system even when the system
power supply is removed. When the power is removed, the input capacitor, CIN, discharges at VIN. Past the set
UVLO level, the pull-down resistance RPD becomes disabled and the output no longer becomes discharged. If
there is still remaining charge on the output capacitor, this results in longer fall times. Care must be taken such
that CIN is large enough to meet the device UVLO settings.
9.3.2.2 Internal QOD Considerations
Special considerations must be taken when using the internal RPD by shorting the QOD pin to the VOUT pin. The
internal RPD is a pulldown resistance designed to quickly discharge a load after the switch has been disabled.
Care must be used to ensure that excessive current does not flow through RPD during discharge so that the
maximum TJ of 125°C is not exceeded. When using only the internal RPD to discharge a load, the total capacitive
load must not exceed 200 uF. Otherwise, an external resistor, REXT, must be used to ensure the amount of
current flowing through RPD is properly limited and the maximum TJ is not exceeded. To ensure the device is not
damaged, the remaining charge from CL needs to decay naturally through the internal QOD resistance and must
not be driven.
9.3.3 EN/UVLO
As an input pin, EN/UVLO controls the ON and OFF state of the internal MOSFET. In its high state, the internal
MOSFET is enabled. A low on this pin turns off the internal MOSFET. High and Low levels are specified in the
parametric table of the datasheet
A voltage V(EN/UVLO < V(ENF) on this pin turns off the internal FET, thus disconnecting VIN from VOUT, while
voltage below V(SHUTF) takes the device into shutdown mode, with IQ less than 1 μA to ensure minimal power
loss.
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The EN/UVLO pin can be directly driven by a 1.8 V, 3.3 V or 5 V general purpose output pin.
The internal de-glitch delay on EN/UVLO falling edge is intentionally kept low (2.5 μs typical) for quick detection
of power failure. For applications where a higher de-glitch delay on EN/UVLO is desired, or when the supply is
particularly noisy, it is recommended to use an external bypass capacitor from EN/UVLO to GND.
The undervoltage lock out can be programmed by using an external resistor divider from supply VIN terminal to
EN/UVLO terminal to GND as shown in Figure 18. When an undervoltage or input power fail event is detected,
the internal FET is quickly turned off. If the Under-Voltage Lock-Out function is not needed, the EN/UVLO
terminal must be connected to the VIN terminal. EN/UVLO terminal must not be left floating.
The device also implements internal undervoltage-lockout (UVLO) circuitry on the VIN terminal. The device
disables when the VIN terminal voltage falls below internal UVLO Threshold V(UVF). The internal UVLO
threshold has a hysteresis of 125 mV (5% of V(UVR)). See Figure 19 and Figure 20.
VIN
CIN
VOUT
CL
VIN
2.54 V
2.4 V
GATE
R1
CONTROL
EN/
UVLO
1.23 V
1.13 V
Thermal
Shutdown
R2
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 18. Configuring UVLO with External Resistor Network
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VIN
VOUT
CL
VIN
CIN
2.54 V
2.4 V
GATE
CONTROL
EN/
UVLO
GPIO
1.23 V
1.13 V
Thermal
Shutdown
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 19. Using 1.8 V/3.3 V GPIO Signal Directly from Processor
VIN
CIN
VOUT
CL
VIN
2.54 V
2.4 V
GATE
CONTROL
EN/
UVLO
1.23 V
1.13 V
Thermal
Shutdown
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 20. Default UVLO Threshold V(UVR) Using No Additional External Components
9.3.4 Adjustable Rise Time (CT)
A capacitor to GND on the CT pin sets the slew rate. The voltage on the CT pin can be as high as 2.5 V. An
approximate formula for the relationship between CT and slew rate is shown in Equation 3. This equation
accounts for 10% to 90% measurement on VOUT and does NOT apply for CT < 1 nF.
Use Table 2 to determine rise times for when Ct ≥ 1 nF.
SR = 46.62 / Ct
where
•
SR is the slew rate (in V/µs)
16
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•
•
CT is the the capacitance value on the CT pin (in pF)
The units for the constant a are µs/V. The units for the constant b are µs/(V × pF).
(3)
Rise time can be calculated by dividing the input voltage by the slew rate. Table 2 contains rise time values
measured on a typical device. Rise times shown below are only valid for the power-up sequence where VIN is
already in steady state condition before the EN/UVLO pin is asserted high.
Table 2. Rise Time Table
RISE TIME (µs) 10% - 90%, CL = 0.1 µF, CIN = 1 µF, RL = 10 Ω
CT (pF)
VIN = 18 V
115
VIN = 12 V
91
VIN = 9 V
78
VIN = 5 V
60
VIN = 3.3 V
98
0
470
136
94
80
63
98
1000
2200
4700
10000
27000
310
209
158
91
102
688
464
345
198
135
1430
3115
8230
957
704
397
265
2085
5460
1540
4010
864
550
2245
1430
9.3.5 Thermal Shutdown
The switch disables when the junction temperature (TJ) rises above the thermal shutdown threshold, TSD. The
switch re-enables once the temperature drops below the TSD – TSD,HYS value.
9.4 Device Functional Modes
The features of the TPS22810 depend on the operating mode. Table 3 summarizes the Device Functional
Modes.
Table 3. Function Table
EN/UVLO
Device State
Disabled
L
H
Enabled
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
This section highlights some of the design considerations when implementing this device in various applications.
A PSPICE model for this device is also available in the product page of this device on www.ti.com (See the 器件
支持 section for more information).
10.2 ON and OFF Control
The EN/UVLO pin controls the state of the switch. Asserting EN/UVLO high enables the switch. EN/UVLO is
active high and has a low threshold, making it capable of interfacing with low-voltage signals. The EN/UVLO pin
is compatible with standard GPIO logic thresholds. It can be used with any microcontroller with 1.2 V or higher
GPIO voltage. This pin cannot be left floating and must be driven either high or low for proper functionality.
10.3 Input Capacitor (Optional)
To limit the voltage drop on the input supply caused by transient inrush currents when the switch turns on into a
discharged load capacitor, a capacitor needs to be placed between VIN and GND. A 1-μF ceramic capacitor, CIN,
placed close to the pins, is usually sufficient. Higher values of CIN can be used to further reduce the voltage drop
during high current applications. When switching heavy loads, it is recommended to have an input capacitor
about 10 times higher than the output capacitor to avoid excessive voltage drop.
10.4 Output Capacitor (Optional)
Due to the integrated body diode in the NMOS switch, a CIN greater than CL is highly recommended. A CL
greater than CIN can cause VOUT to exceed VIN when the system supply is removed. This can result in current
flow through the body diode from VOUT to VIN. A CIN to CL ratio of 10 to 1 is recommended for minimizing VIN
dip caused by inrush currents during startup; however, a 10 to 1 ratio for capacitance is not required for proper
functionality of the device. A ratio smaller than 10 to 1 (such as 1 to 1) can cause slightly more VIN dip upon
turnon due to inrush currents.
This can be mitigated by increasing the capacitance on the CT pin for a longer rise time.
10.5 Typical Application
This typical application demonstrates how the TPS22810 can be used to power downstream modules.
VIN
VOUT
QOD
CT
Power
Supply
CIN
RL
CL
GND
ON
EN/
OFF
UVLO
TPS22810
Copyright © 2016, Texas Instruments Incorporated
Figure 21. Typical Application Schematic
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Typical Application (continued)
10.5.1 Design Requirements
For this design example, use the values listed in Table 4 as the design parameters:
Table 4. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VIN
Load current
12 V
2 A
CL
22 µF
20 ms
400 mA
Desired fall time
Maximum acceptable inrush current
10.5.2 Detailed Design Procedure
10.5.2.1 Shutdown Sequencing During Unexpected Power Loss
Using the adjustable Quick Output Discharge function of the TPS22810, adding a load switch to each power rail
can be used to manage the power down sequencing in the event of an unexpected power loss (that is battery
removal). To determine the QOD values for each load switch, first confirm the power down order of the device
you wish to power sequence. Be sure to check if there are voltage or timing margins that must be maintained
during power down. Next, consult Table 1 to determine appropriate CL and RQOD values for each power rail's
load switch so that the load switches' fall times correspond to the order in which they need to be powered down.
In the above example, we must have this power rail's fall time to be 4 ms. Using Equation 2, we can determine
the appropriate RQOD to achieve our desired fall time.
Since fall times are measured from 90% of VOUT to 10% of VOUT, using Equation 2, we get Equation 4 and
Equation 5.
1.2V = 10.8V ìe-(20ms)/(RQODì(22mF))
(4)
RQOD = 413.7 Ω
(5)
Consulting Figure 6, RPD at VIN = 12 V is approximately 250 Ω. Using Equation 1, the required external QOD
resistance can be calculated as shown in Equation 6 and Equation 7.
413.7 Ω = 250 Ω + REXT
REXT = 163.7 Ω
(6)
(7)
Figure 22 through Figure 25 are scope shots demonstrating an example of the QOD functionality when power is
removed from the device (both ON and VIN are disconnected simultaneously). In the scope shots, the VIN = 12 V
and correspond to when RQOD = 1000 Ω, RQOD= 500 Ω, and QOD = VOUT with two values of CL = 10 µF and 22
µF.
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VIN
VIN
VON
VON
VOUT
VOUT
VIN = 12 V
CIN = 1 µF
CL = 10 µF
VIN = 12 V
CIN = 1 µF
CL = 10 µF
Figure 22. Fall Time tF at VIN = 12 V, RQOD = 1000 Ω
Figure 23. Fall Time tF at VIN = 12 V, RQOD = 500 Ω
VIN
VIN
VON
VON
VOUT
VOUT
VIN = 12 V
CIN = 1 µF
CL = 10 µF
VIN = 12 V
CIN = 1 µF
CL = 22 µF
Figure 24. tF at VIN = 12 V , QOD = VOUT
Figure 25. tF at VIN = 12 V, RQOD = 1000 Ω
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VIN
VIN
VON
VON
VOUT
VOUT
VIN = 12 V
CIN = 1 µF
CL = 22 µF
VIN = 12 V
CIN = 1 µF
CL = 22 µF
Figure 26. tF at VIN = 12 V, RQOD = 500 Ω
Figure 27. tF at VIN = 12 V, QOD = VOUT
10.5.2.2 VIN to VOUT Voltage Drop
The VIN to VOUT voltage drop in the device is determined by the RON of the device and the load current. The
RON of the device depends upon the VIN conditions of the device. Refer to the RON specification of the device in
the Electrical Characteristics table of this datasheet. Once the RON of the device is determined based upon the
VIN conditions, use Equation 8 to calculate the VIN to VOUT voltage drop.
∆V = ILOAD × RON
where
•
•
•
ΔV is the voltage drop from VIN to VOUT
ILOAD is the load current
RON is the On-resistance of the device for a specific VIN
(8)
An appropriate ILOAD must be chosen such that the IMAX specification of the device is not violated.
10.5.2.3 Inrush Current
To determine how much inrush current is caused by the CL capacitor, use Equation 9.
dVOUT
I
= CL ´
INRUSH
dt
where
•
•
•
•
IINRUSH is the amount of inrush caused by CL
CL is the capacitance on VOUT
dt is the Output Voltage rise time during the ramp up of VOUT when the device is enabled
dVOUT is the change in VOUT during the ramp up of VOUT when the device is enabled
(9)
The appropriate rise time can be calculated using the design requirements and the inrush current equation. As
we calculate the rise time (measured from 10% to 90% of VOUT), we account for this in our dVOUT parameter
(80% of VOUT = 9.6 V) as shown in Equation 10 and Equation 11.
400 mA = 22 µF × 9.6 V/dt
dt = 528 µs
(10)
(11)
To ensure an inrush current of less than 400 mA, choose a CT value that yields a rise time of more than 528 μs.
Consulting Table 2 at VIN = 12 V, CT = 4700 pF provides a typical rise time of 957 μs. Using this rise time and
voltage into Equation 9, yields Equation 12 and Equation 13.
IInrush = 22 µF × 9.6 V/ 957 µs
Inrush = 220 mA
(12)
(13)
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An appropriate CL value must be placed on VOUT such that the IMAX and IPLS specifications of the device are not
violated.
10.5.3 Application Curves
See the oscilloscope captures below for an example of how the CT capacitor can be used to reduce inrush
current for VIN = 12 V. See the Adjustable Rise Time (CT) section for rise times for corresponding CT values.
VIN
VIN
VON
VON
VOUT
VOUT
IIN
IIN
Figure 28. TPS22810 Inrush Current With
CL = 22 µF, CT = 0 pF
Figure 29. TPS22810 Inrush Current
with CL = 22 µF, CT = 4700 pF
VIN
VIN
VON
VON
VOUT
VOUT
IIN
IIN
Figure 31. TPS22810 Inrush Current
With CL = 100 µF, CT = 0 pF
Figure 30. TPS22810 Inrush Current
With CL = 22 µF, CT = 27000 pF
22
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VIN
VIN
VON
VON
VOUT
VOUT
IIN
IIN
Figure 32. TPS22810 Inrush Current
With CL = 100 µF, CT = 4700 pF
Figure 33. TPS22810 Inrush Current
With CL = 100 µF, CT = 27000 pF
11 Power Supply Recommendations
The device is designed to operate from a VIN range of 2.7 V to 18 V. This supply must be well regulated and
placed as close to the device terminal as possible with the recommended 1-µF bypass capacitor. If the supply is
located more than a few inches from the device terminals, additional bulk capacitance may be required in
addition to the ceramic bypass capacitors. If additional bulk capacitance is required, an electrolytic, tantalum, or
ceramic capacitor of 1 µF may be sufficient.
The TPS22810 operates regardless of power sequencing order. The order in which voltages are applied to VIN
and ON does not damage the device as long as the voltages do not exceed the absolute maximum operating
conditions.
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12 Layout
12.1 Layout Guidelines
1. VIN and VOUT traces must be as short and wide as possible to accommodate for high current.
2. The VIN pin must be bypassed to ground with low ESR ceramic bypass capacitors. The typical
recommended bypass capacitance is 1-μF ceramic with X5R or X7R dielectric. This capacitor must be
placed as close to the device pins as possible.
12.2 Layout Example
1 VIN
VOUT 6
QOD 5
2 GND
EN/UVLO
CT
3
4
VIA to Power Ground Plane
Figure 34. Recommended Board Layout
12.3 Thermal Considerations
For best performance, all traces must be as short as possible. To be most effective, the input and output
capacitors must be placed close to the device to minimize the effects that parasitic trace inductances may have
on normal and short-circuit operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic
electrical effects along with minimizing the case to ambient thermal impedance.
The maximum IC junction temperature must be restricted to 150°C under normal operating conditions. To
calculate the maximum allowable dissipation, PD(max) for a given output current and ambient temperature, use
Equation 14.
TJ(MAX) - TA
PD(MAX)
=
qJA
where
•
•
•
•
PD(MAX) is the maximum allowable power dissipation
TJ(MAX) is the maximum allowable junction temperature (150°C for the TPS22810)
TA is the ambient temperature of the device
θJA is the junction to air thermal impedance. Refer to the Thermal Information table. This parameter is highly
dependent upon board layout.
(14)
24
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13 器件和文档支持
13.1 器件支持
13.1.1 开发支持
关于 TPS22810 PSpice 瞬态模型，请参见 《TPS22810 PSpice 瞬态模型》
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
•
•
•
TPS22810 负载开关评估模块
选择一个负载开关以代替分立式解决方案
负载开关的计时
13.3 接收文档更新通知
要接收文档更新通知（包括芯片勘误表），请转至 ti.com.cn 上您的器件对应的产品文件夹。单击右上角的“提醒我”
(Alert me) 按钮。点击后，您将每周定期收到已更改的产品信息（如果有的话）。有关更改的详细信息，请查看任
意已修订文档的修订历史记录。
13.4 Community Resources
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
13.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2016–2018, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS22810DBVR
TPS22810DBVT
TPS22810DRVR
TPS22810DRVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
WSON
WSON
DBV
DBV
DRV
DRV
6
6
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 105
-40 to 105
-40 to 105
-40 to 105
19HF
19HF
1CRH
1CRH
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS22810 :
Automotive : TPS22810-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS22810DBVR
TPS22810DBVT
TPS22810DRVR
TPS22810DRVT
SOT-23
SOT-23
WSON
WSON
DBV
DBV
DRV
DRV
6
6
6
6
3000
250
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
3.2
3.2
2.3
2.3
3.2
3.2
2.3
2.3
1.4
1.4
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q2
Q2
3000
250
1.15
1.15
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS22810DBVR
TPS22810DBVT
TPS22810DRVR
TPS22810DRVT
SOT-23
SOT-23
WSON
WSON
DBV
DBV
DRV
DRV
6
6
6
6
3000
250
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A
C
B
0.05
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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