TPS22918DBVR [TI]
具有可调节上升时间和可调节输出放电功能的 5.5V、2A、52mΩ 负载开关 | DBV | 6 | -40 to 105;
| 型号： | TPS22918DBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可调节上升时间和可调节输出放电功能的 5.5V、2A、52mΩ 负载开关 | DBV | 6 | -40 to 105 开关 |
| 文件： | 总28页 (文件大小：1178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS22918
ZHCSEX3A –FEBRUARY 2016–REVISED MARCH 2016
TPS22918 5.5V、2A、导通电阻为 52mΩ 的负载开关
1 特性
3 说明
1
•
•
•
•
集成单通道负载开关
TPS22918 是一款单通道负载开关，可对上升时间和
快速输出放电进行配置。此器件包括一个 N 沟道金属
氧化物半导体场效应晶体管 (MOSFET)，可在 1V 至
5.5V 的输入电压范围内运行并可支持 2A 的最大持续
电流。此开关由一个开关输入控制，能够直接连接低电
压控制信号。
环境工作温度范围：-40°C 至 +105°C
输入电压范围：1V 至 5.5V
导通电阻 (RON
)
–
–
RON = 52mΩ（VIN = 5V 时的典型值）
RON = 53mΩ（VIN = 3.3V 时的典型值）
•
•
2A 最大持续开关电流
该器件的可配置上升时间可大幅降低大容量负载电容所
产生的浪涌电流，从而降低或消除电源压降。
TPS22918 具有 一个可配置的快速输出放电 (QOD) 引
脚，用于控制器件的下降时间，以便针对掉电或排序进
行灵活设计。
低静态电流
–
8.3µA（VIN = 3.3V 时的典型值）
•
低控制输入阈值，允许使用 1V 或电压更高的
GPIO
•
•
•
可调节快速输出放电 (QOD)
TPS22918 采用小型、带引线的 SOT-23 封装
可通过 CT 引脚配置的上升时间
小外形尺寸晶体管 (SOT-23)-6 封装 (DBV)
(DBV)，方便对焊接点进行外观检查。该器件在自然通
风环境下的额定运行温度范围为 –40°C 至 +105°C。
–
2.90mm × 2.80mm，间距为 0.95mm，
高度为 1.45mm（带引线）
器件信息 (1)
•
静电放电 (ESD) 性能经测试符合 JESD 22 规范
部件号
TPS22918
封装
SOT-23 (6)
封装尺寸（标称值）
–
±2kV 人体模型 (HBM) 和 ±1kV 带电器件模型
2.90mm x 1.60mm
(CDM)
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
2 应用
•
•
•
•
工业系统
机顶盒
血糖仪
电子销售终端
RON 与 VIN 间的关系 (IOUT = –200mA)
典型值
简化电路原理图
100
VIN
VOUT
QOD
Power
Supply
-40èC
CIN
25èC
90
REXT
85èC
GND
105èC
RL
80
CL
ON
OFF
ON
70
60
50
40
30
CT
TPS22918
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSD76
TPS22918
ZHCSEX3A –FEBRUARY 2016–REVISED MARCH 2016
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics.............................................. 7
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 13
9
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 21
11.3 Thermal Considerations........................................ 21
12 器件和文档支持 ..................................................... 22
12.1 器件支持................................................................ 22
12.2 文档支持................................................................ 22
12.3 社区资源................................................................ 22
12.4 商标....................................................................... 22
12.5 静电放电警告......................................................... 22
12.6 Glossary................................................................ 22
13 机械、封装和可订购信息....................................... 22
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (February 2016) to Revision A
Page
•
已将器件状态由“产品预览”更改为“量产数据” .......................................................................................................................... 1
2
Copyright © 2016, Texas Instruments Incorporated
TPS22918
www.ti.com.cn
ZHCSEX3A –FEBRUARY 2016–REVISED MARCH 2016
5 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
VIN
GND
ON
1
2
3
6
5
4
VOUT
QOD
CT
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
Switch input. Place ceramic bypass capacitor(s) between this pin and GND. See the
Detailed Description section for more information.
1
VIN
I
2
3
GND
ON
—
I
Device ground.
Active high switch control input. Do not leave floating.
Switch slew rate control. Can be left floating. See the Feature Description section for
more information.
4
CT
O
Quick Output Discharge pin. This functionality can be enabled in one of three ways.
•
•
•
Placing an external resistor between VOUT and QOD
Tying QOD directly to VOUT and using the internal resistor value (RPD
Disabling QOD by leaving pin floating
5
6
QOD
O
O
)
See the Quick Output Discharge (QOD) section for more information.
VOUT
Switch output.
Copyright © 2016, Texas Instruments Incorporated
3
TPS22918
ZHCSEX3A –FEBRUARY 2016–REVISED MARCH 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
–0.3
–0.3
–0.3
MAX
6
UNIT
V
VIN
Input voltage
Output voltage
ON voltage
VOUT
VON
IMAX
IPLS
TJ
6
V
6
V
Maximum continuous switch current, ambient temperature = 70°C
Maximum pulsed switch current, pulse < 300 µs, 2% duty cycle
Maximum junction temperature
2
A
2.5
125
150
A
°C
°C
Tstg
Storage temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Charged-device model (CDM), per JEDEC specification JESD22-C101
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
V(ESD)
Electrostatic discharge
V
(2)
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
0
MAX UNIT
VIN
Input voltage
5.5
5.5
VIN
5.5
0.5
105
V
V
VON
ON voltage
0
VOUT
VIH, ON
VIL, ON
TA
Output voltage
V
High-level input voltage, ON
Low-level input voltage, ON
Operating free-air temperature range
Input Capacitor
VIN = 1 V to 5.5 V
VIN = 1 V to 5.5 V
1
0
V
V
(1)
–40
°C
µF
(2)
CIN
1
(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(MAX)], the
maximum power dissipation of the device in the application [PD(MAX)], and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(MAX) = TJ(MAX) – (θJA × PD(MAX)).
(2) Refer to Application and Implementation section
6.4 Thermal Information
TPS22918
(1)
THERMAL METRIC
DBV (SOT-23)
6 PINS
183.2
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
151.6
34.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
37.2
ψJB
33.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2016, Texas Instruments Incorporated
TPS22918
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ZHCSEX3A –FEBRUARY 2016–REVISED MARCH 2016
6.5 Electrical Characteristics
Unless otherwise noted, the specification in the following table applies over the full ambient operating temperature
–40°C ≤ TA ≤ +105°C. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
VIN = 5.5 V
TA
MIN
TYP
9.2
8.7
8.3
10.2
9.3
8.9
0.5
0.5
0.5
0.5
0.4
0.4
MAX
16
16
15
17
16
15
5
UNIT
VIN = 5 V
VIN = 3.3 V
VIN = 1.8 V
VIN = 1.2 V
VIN = 1 V
IQ, VIN
Quiescent current VON = 5 V, IOUT = 0 A
–40°C to +105°C
µA
VIN = 5.5 V
VIN = 5 V
4.5
3.5
2.5
2
VIN = 3.3 V
VIN = 1.8 V
VIN = 1.2 V
VIN = 1 V
ISD, VIN
Shutdown current VON = 0 V, VOUT = 0 V
–40°C to +105°C
–40°C to +105°C
µA
2
ON pin input
ION
VIN = 5.5 V, IOUT = 0 A
leakage current
0.1
µA
25°C
51
52
52
53
53
55
64
71
59
71
78
59
71
79
59
71
79
59
71
80
61
75
80
65
79
88
77
88
104
85
100
116
VIN = 5.5 V, IOUT = –200 mA
VIN = 5.0 V, IOUT = –200 mA
VIN = 4.2 V, IOUT = –200 mA
VIN = 3.3 V, IOUT = –200 mA
VIN = 2.5 V, IOUT = –200 mA
VIN = 1.8 V, IOUT = –200 mA
VIN = 1.2 V, IOUT = –200 mA
VIN = 1.0 V, IOUT = –200 mA
–40°C to +85°C
–40°C to +105°C
25°C
mΩ
–40°C to +85°C
–40°C to +105°C
25°C
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
–40°C to +85°C
–40°C to +105°C
25°C
–40°C to +85°C
–40°C to +105°C
25°C
RON
On-Resistance
–40°C to +85°C
–40°C to +105°C
25°C
–40°C to +85°C
–40°C to +105°C
25°C
–40°C to +85°C
–40°C to +105°C
25°C
–40°C to +85°C
–40°C to +105°C
–40°C to +105°C
25°C
mΩ
VHYS
ON pin hysteresis VIN = 1 V to 5.5 V
VIN = 5.0 V, VON = 0 V
107
24
mV
–40°C to +105°C
25°C
30
35
60
25
45
Output pull down
VIN = 3.3 V, VON = 0 V
resistance(1)
RPD
Ω
–40°C to +105°C
25°C
VIN = 1.8 V, VON = 0 V
–40°C to +105°C
(1) Output pull down resistance varies with input voltage. Please see Figure 7 for more information.
Copyright © 2016, Texas Instruments Incorporated
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6.6 Switching Characteristics
Refer to the timing test circuit in Figure 21 (unless otherwise noted) for references to external components used for the test
condition in the switching characteristics table. Switching characteristics shown below are only valid for the power-up
sequence where VIN is already in steady state condition before the ON pin is asserted high. VON = 5 V, TA = 25 °C, QOD =
Open.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN = 5 V
tON
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
Delay time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
1950
2
tOFF
tR
2540
2
µs
tF
tD
690
VIN = 3.3 V
tON
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
Delay time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
1430
2
tOFF
tR
1680
2
µs
µs
µs
tF
tD
590
VIN = 1.8 V
tON
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
Delay time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
965
2
tOFF
tR
960
2
tF
tD
480
VIN = 1 V
tON
tOFF
tR
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
Delay time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 1000 pF
725
3
560
2
tF
tD
430
6
Copyright © 2016, Texas Instruments Incorporated
TPS22918
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ZHCSEX3A –FEBRUARY 2016–REVISED MARCH 2016
6.7 Typical Characteristics
6.7.1 DC Characteristics
11
10.5
10
3
2.5
2
-40èC
25èC
85èC
105èC
9.5
9
8.5
8
1.5
1
7.5
-40èC
7
25èC
0.5
0
85èC
105èC
6.5
6
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
1
1.5
2
2.5
3
3.5
4
4.5
4.5
4.5
5
5.5
Input Voltage (V)
Input Voltage (V)
D002
D003
VON = 5 V
IOUT = 0 A
Figure 1. IQ vs VIN
VON = 0 V
IOUT = 0 A
Figure 2. ISD vs VIN
100
100
-40èC
25èC
85èC
105èC
90
80
70
60
50
40
30
20
90
80
70
60
50
40
30
VIN= 1 V
VIN = 1.05 V
VIN = 1.2 V
VIN = 1.8 V
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5 V
VIN = 5.5 V
-40
-20
0
20
40
60
80
100
1
1.5
2
2.5
3
3.5
4
5
5.5
Temperature (èC)
Input Voltage (V)
D004
D001
VON = 5 V
IOUT = –200 mA
VON = 5 V
IOUT = –200 mA
Figure 3. RON vs TJ
Figure 4. RON vs VIN
100
140
90
80
70
60
50
40
30
20
10
0
120
100
80
60
40
20
0
-40èC
VIN= 1 V
VIN = 1.2 V
VIN = 1.5 V
VIN = 1.8 V
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5 V
VIN = 5.5 V
25èC
85èC
105èC
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
1
1.5
2
2.5
3
3.5
4
5 5.5
Output Current (A)
Input Voltage (V)
D005
D008
VON = 5 V
TA = 25°C
IOUT = 0 A
Figure 5. RON vs IOUT
Figure 6. VHYS vs VIN
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DC Characteristics (continued)
275
250
225
200
175
150
125
100
75
-40èC
25èC
85èC
105èC
50
25
0
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
D009
VIN = VOUT
VON = 0 V
Figure 7. RPD vs VIN
6.7.2 AC Characteristics
3000
2500
2000
1500
1000
500
800
700
600
500
400
300
-40èC
25èC
85èC
105èC
-40èC
25èC
85èC
105èC
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
Input Voltage (V)
D010
D011
CIN = 1 µF
RL = 10 Ω
CL = 0.1 µF
CIN = 1 µF
RL = 10 Ω
Figure 9. tD vs VIN
CL = 0.1 µF
CT = 1000pF
Figure 8. tR vs VIN
5
4
3
2
1
0
5
4
3
2
1
0
-40èC
-40èC
25èC
85èC
105èC
25èC
85èC
105èC
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
Input Voltage (V)
D012
D013
CIN = 1 µF
RL = 10 Ω
CL = 0.1 µF
QOD = Open
CIN = 1 µF
RL = 10 Ω
Figure 11. tOFF vs VIN
CL = 0.1 µF
Figure 10. tF vs VIN
8
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ZHCSEX3A –FEBRUARY 2016–REVISED MARCH 2016
AC Characteristics (continued)
2150
1850
1550
1250
950
-40èC
25èC
85èC
105èC
650
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
D014
CIN = 1 µF
CT = 1000 pF
RL = 10 Ω
CL = 0.1 µF
Figure 12. tON vs VIN
VIN = 5 V
CIN = 1 µF
CL = 0.1 µF
VIN = 5 V
CIN = 1 µF
CL = 0.1 µF
RL = 10 Ω
CT = 1000 pF
RL = 10 Ω
QOD = Open
Figure 14. tF at VIN = 5 V
Figure 13. tR at VIN = 5 V
VIN = 3.3 V
CIN = 1 µF
CL = 0.1 µF
VIN = 3.3 V
CIN = 1 µF
CL = 0.1 µF
RL = 10 Ω
CT = 1000 pF
RL = 10 Ω
QOD = Open
Figure 15. tR at VIN = 3.3 V
Figure 16. tF at VIN = 3.3 V
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AC Characteristics (continued)
VIN = 1.8 V
CIN = 1 µF
CL = 0.1 µF
VIN = 1.8 V
CIN = 1 µF
CL = 0.1 µF
RL = 10 Ω
CT = 1000 pF
RL = 10 Ω
QOD = Open
Figure 17. tR at VIN = 1.8 V
Figure 18. tF at VIN = 1.8 V
VIN = 1.0 V
CIN = 1 µF
CL = 0.1 µF
VIN = 1.0 V
CIN = 1 µF
CL = 0.1 µF
RL = 10 Ω
CT = 1000 pF
RL = 10 Ω
QOD = Open
Figure 19. tR at VIN = 1.0 V
Figure 20. tF at VIN = 1.0 V
10
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ZHCSEX3A –FEBRUARY 2016–REVISED MARCH 2016
7 Parameter Measurement Information
(1) Rise and fall times of the control signal are 100 ns
(2) Turn-off times and fall times are dependent on the time constant at the load. For TPS22918, the internal pull-down
resistance RPD is enabled when the switch is disabled. The time constant is (RQOD || RL) × CL.
Figure 21. Test Circuit
VON
50%
50%
tF
tOFF
tR
tON
90%
90%
VOUT
VOUT
50%
10%
50%
10%
10%
tD
Figure 22. Timing Waveforms
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8 Detailed Description
8.1 Overview
The TPS22918 is a 5.5 V, 2 A load switch in a 6-pin SOT-23 package. To reduce voltage drop for low voltage
and high current rails, the device implements a low resistance N-channel MOSFET which reduces the drop out
voltage across the device.
The device has a configurable slew rate which helps reduce or eliminate power supply droop because of large
inrush currents. Furthermore, the device features a QOD pin, which allows the configuration of the discharge rate
of VOUT once the switch is disabled. During shutdown, the device has very low leakage currents, thereby
reducing unnecessary leakages for downstream modules during standby. Integrated control logic, driver, charge
pump, and output discharge FET eliminates the need for any external components which reduces solution size
and bill of materials (BOM) count.
8.2 Functional Block Diagram
VIN
Charge Pump
Control
Logic
ON
CT
VOUT
QOD
GND
12
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8.3 Feature Description
8.3.1 On and Off Control
The ON pin controls the state of the switch. ON is active high and has a low threshold, making it capable of
interfacing with low-voltage signals. The ON pin is compatible with standard GPIO logic threshold. It can be used
with any microcontroller with 1 V or higher GPIO voltage. This pin cannot be left floating and must be driven
either high or low for proper functionality.
8.3.2 Quick Output Discharge (QOD)
The TPS22918 includes a QOD feature. The QOD pin can be configured in one of three ways:
•
QOD pin shorted to VOUT pin. Using this method, the discharge rate after the switch becomes disabled is
controlled with the value of the internal resistance RPD. The value of this resistance is listed in the Electrical
Characteristics table.
•
QOD pin connected to VOUT pin using an external resistor REXT. After the switch becomes disabled, the
discharge rate is controlled by the value of the total resistance of the QOD. To adjust the total QOD
resistance, Equation 1 can be used:
RQOD = RPD + REXT
Where:
•
•
•
RQOD = Total output discharge resistance
RPD = Internal pulldown resistance
REXT = External resistance placed between the VOUT and QOD pin.
(1)
•
QOD pin is unused and left floating. Using this method, there will be no quick output discharge functionality,
and the output will remain floating after the switch is disabled.
The fall times of the device depend on many factors including the total resistance of the QOD, VIN, and the
output capacitance. When QOD is shorted to VOUT, the fall time will change over VIN as the internal RPD varies
over VIN. To calculate the approximate fall time of VOUT for a given RQOD, use Equation 2 and Table 1.
VCAP = VIN × e-t/τ
Where:
•
•
•
VCAP = Voltage across the capacitor (V)
t = Time since power supply removal (s)
τ = Time constant equal to RQOD × CL
(2)
The fall times' dependency on VIN becomes minimal as the QOD value increases with additional external
resistance. See Table 1 for QOD fall times.
Table 1. QOD Fall Times
(1)FALL TIME (μs) 90% - 10%, CIN = 1 μF, IOUT = 0 A , VON = 0 V
VIN (V)
TA = 25°C
CL = 10 μF
190
TA = 85°C
CL = 10 μF
210
CL = 1 μF
42
CL = 100 μF
1880
CL = 1 μF
40
CL = 100 μF
2150
5.5
5
43
200
1905
45
220
2200
3.3
2.5
1.8
1.2
1
47
230
2150
50
260
2515
58
300
2790
60
345
3290
75
430
4165
80
490
4950
135
230
955
9910
135
210
1035
10980
19270
1830
19625
1800
(1) TYPICAL VALUES WITH QOD SHORTED TO VOUT
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8.3.2.1 QOD when System Power is Removed
The adjustable QOD can be used to control the power down sequencing of a system even when the system
power supply is removed. When the power is removed, the input capacitor discharges at VIN. Past a certain VIN
level, the strength of the RPD will be reduced. If there is still remaining charge on the output capacitor, this will
result in longer fall times. For further information regarding this condition, refer to Shutdown Sequencing During
Unexpected System Power Loss.
8.3.2.2 Internal QOD Considerations
Special considerations must be taken when using the internal RPD by shorting the QOD pin to the VOUT pin. The
internal RPD is a pulldown resistance designed to quickly discharge a load after the switch has been disabled.
Care must be used to ensure that excessive current does not flow through RPD during discharge so that the
maximum TJ of 125°C is not exceeded. When using only the internal RPD to discharge a load, the total capacitive
load must not exceed 200 µF. Otherwise, an external resistor, REXT, must be used to ensure the amount of
current flowing through RPD is properly limited and the maximum TJ is not exceeded. To ensure the device is not
damaged, the remaining charge from CL must decay naturally through the internal QOD resistance and should
not be driven.
8.3.3 Adjustable Rise Time (CT)
A capacitor to GND on the CT pin sets the slew rate of VOUT. The CT capacitor will charge up until shortly after
the switch is turned on and VOUT becomes stable. Once VOUT become stable, the capactior will discharge to
ground. An approximate formula for the relationship between CT and the slew rate is shown in Equation 3:
SR = 0.55× CT + 30
where
•
•
•
SR = slew rate (in µs/V)
CT = the capacitance value on the CT pin (in pF)
The units for the constant 30 are µs/V. The units for the constant 0.52 are µs/(V × pF).
(3)
This equation accounts for 10% to 90% measurement on VOUT and does not apply for CT = 0 pF. Use Table 2 to
determine rise times for when CT = 0 pF.
Rise time can be calculated by multiplying the input voltage by the slew rate. Table 2 contains rise time values
measured on a typical device.
Table 2. Rise Time Table
RISE TIME (µs) 10% - 90%, CL = 0.1 µF, CIN = 1 µF, RL = 10 Ω
(1)
CT× (pF)
VIN = 5 V VIN = 3.3 V VIN = 2.5 V VIN = 1.8 V VIN = 1.5 V VIN = 1.2 V VIN = 1.0 V
0
135
650
95
455
75
350
60
50
45
40
220
260
220
185
160
470
1260
2540
5435
12050
26550
850
655
480
415
340
300
1000
2200
4700
10000
1680
3580
7980
17505
1300
2760
6135
13460
960
810
660
560
2020
4485
9790
1715
3790
8320
1390
3120
6815
1220
2735
5950
(1) Typical values at 25°C with a 25 V X7R 10% ceramic capacitor on CT.
As the voltage across the capacitor approaches the capacitor rated voltage, the effective capacitance reduces.
Depending on the dielectric material used, the voltage coefficient changes. See Table 3 for the recommended
minimum voltage rating for the CT capacitor. If using VIN = 1.2 V or 4 V, it is recommended to use the higher of
the two CT Voltage ratings specified.
14
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Table 3. Recommended CT Capacitor Voltage Rating
RECOMMENDED CT CAPACITOR VOLTAGE
VIN (V)
RATING (V)
1 V to 1.2 V
1.2 V to 4 V
4 V to 5.5 V
10
16
20
8.4 Device Functional Modes
Table 4 describes the connection of the VOUT pin depending on the state of the ON pin.
Table 4. VOUT Connection
QOD
CONFIGURATION
ON
TPS22918 VOUT
QOD pin connected to
VOUT with REXT
L
GND (via REXT+RPD)
QOD pin tied to VOUT
directly
L
L
GND (via RPD
Open
)
QOD pin left open
Any valid QOD
configuration
H
VIN
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This section highlights some of the design considerations when implementing this device in various applications.
A PSPICE model for this device is also available in the product page of this device on www.ti.com (See the 器件
支持 section for more information).
9.2 Typical Application
This typical application demonstrates how the TPS22918 can be used to power downstream modules.
Figure 23. Typical Application Schematic
9.2.1 Design Requirements
For this design example, use the values listed in Table 5 as the design parameters:
Table 5. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VIN
Load Current
5 V
2 A
CL
22 µF
4 ms
Desired Fall Time
Maximum Acceptable Inrush Current
400 mA
16
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9.2.2 Detailed Design Procedure
9.2.2.1 Input Capacitor (CIN)
To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a
discharged load capacitor or short-circuit, a capacitor needs to be placed between VIN and GND. A 1 µF ceramic
capacitor, CIN, placed close to the pins, is usually sufficient. Higher values of CIN can be used to further reduce
the voltage drop during high-current application. When switching heavy loads, it is recommended to have an
input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop.
9.2.2.2 Output Capacitor (CL) (Optional)
Becuase of the integrated body diode in the MOSFET, a CIN greater than CL is highly recommended. A CL
greater than CIN can cause VOUT to exceed VIN when the system supply is removed. This could result in current
flow through the body diode from VOUT to VIN. A CIN to CL ratio of 10 to 1 is recommended for minimizing VIN
dip caused by inrush currents during startup.
9.2.2.3 Shutdown Sequencing During Unexpected System Power Loss
Microcontrollers and processors often have a specific shutdown sequence in which power needs to be removed.
Using the adjustable Quick Output Discharge function of the TPS22918, adding a load switch to each power rail
can be used to manage the power down sequencing in the event of an unexpected system power loss (i.e.
battery removal). To determine the QOD values for each load switch, first confirm the power down order of the
device you wish to power sequence. Be sure to check if there are voltage or timing margins that must be
maintained during power down. Next, consult QOD Fall Time Table in the Quick Output Discharge (QOD) feature
description to determine appropriate COUT and RQOD values for each power rail's load switch so that the load
switches' fall times correspond to the order in which they need to be powered down. In the above example, we
would like this power rail's fall time to be 4 ms. Using Equation 2, to determine the appropriate RQOD to achieve
our desired fall time.
Because fall times are measured from 90% of VOUT to 10% of VOUT, the equation becomes:
.5 V = 4.5 V × e-(4 ms) / (R × (22 µF))
(4)
(5)
RQOD = 83.333 Ω
Refer to Figure 7, RPD at VIN = 5 V is approximately 25 Ω. Using Equation 1, the required external QOD
resistance can be calculated:
83.333 Ω = 25 Ω + REXT
REXT = 58.333 Ω
(6)
(7)
Figure 24 through Figure 29 are scope shots demonstrating an example of the QOD functionality when power is
removed from the device (both ON and VIN are disconnected simultaneously). The input voltage is decaying in
all scope shots below.
•
•
•
•
Initial VIN = 3.3 V
QOD = Open, 500 Ω, or shorted to VOUT
CL = 1 μF, 10 μF
VOUT is left floating
NOTE: VIN may appear constant in some figures. This is because the time scale of the scope shot is too small to
show the decay of CIN.
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VIN = 3.3 V
VIN = 3.3 V
VIN = 3.3 V
CIN = 1 µF
CL = 1 µF
CL = 1 µF
CL = 10 µF
VIN = 3.3 V
VIN = 3.3 V
VIN = 3.3 V
CIN = 1 µF
CL = 1 µF
QOD = Open
QOD = 500 Ω
Figure 24. tF at VIN = 3.3 V
Figure 25. tF at VIN = 3.3 V
CIN = 1 µF
CIN = 1 µF
CL = 10 µF
QOD = VOUT
QOD = Open
Figure 26. tF at VIN = 3.3 V
Figure 27. tF at VIN = 3.3 V
CIN = 1 µF
CIN = 1 µF
CL = 10 µF
QOD = 500 Ω
QOD = VOUT
Figure 28. tF at VIN = 3.3 V
Figure 29. tF at VIN = 3.3 V
18
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9.2.2.4 VIN to VOUT Voltage Drop
The VIN to VOUT voltage drop in the device is determined by the RON of the device and the load current. The
RON of the device depends upon the VIN conditions of the device. Refer to the RON specification of the device in
the Electrical Characteristics table of this data sheet. When the RON of the device is determined based upon the
VIN conditions, use 公式 8 to calculate the VIN to VOUT voltage drop:
∆V = ILOAD × RON
where
•
•
•
ΔV = voltage drop from VIN to VOUT
ILOAD = load current
RON = On-resistance of the device for a specific VIN
An appropriate ILOAD must be chosen such that the IMAX specification of the device is not violated.
(8)
9.2.2.5 Inrush Current
Use 公式 9 to determine how much inrush current will be caused by the CL capacitor:
dVOUT
I
= CL ´
INRUSH
dt
where
•
•
•
•
IINRUSH = amount of inrush caused by CL
CL = capacitance on VOUT
dt = Output Voltage rise time during the ramp up of VOUT when the device is enabled
dVOUT = change in VOUT during the ramp up of VOUT when the device is enabled
(9)
The appropriate rise time can be calculated using the design requirements and the inrush current equation. As
we are calculating the rise time (measured from 10% to 90% of VOUT), we will account for this in our dVOUT
parameter (80% of VOUT = 4 V).
400 mA = 22 μF × 4 V/dt
dt = 220 μs
(10)
(11)
To ensure an inrush current of less than 400 mA, choose a CT value that will yield a rise time of more than 220
μs. Consulting Table 2 at VIN = 5 V, CT = 220 μF will provide a typical rise time of 650 μs. Inputting this rise time
and voltage into 公式 9, yields:
IInrush = 22 μF × 4 V / 650 μs
(12)
(13)
IInrush = 135 mA
This inrush current can be seen in the Application Curves below. An appropriate CL value should be placed on
VOUT such that the IMAX and IPLS specifications of the device are not violated.
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www.ti.com.cn
9.2.3 Application Curves
VIN = 5 V
CL = 22 µF
CT = 0 µF
VIN = 5 V
CL = 22 µF
CT = 220 µF
图 30. TPS22918 Inrush Current
图 31. TPS22918 Inrush Current
10 Power Supply Recommendations
The device is designed to operate from a VIN range of 1 V to 5.5 V. This supply must be well regulated and
placed as close to the device terminal as possible with the recommended 1-µF bypass capacitor. If the supply is
located more than a few inches from the device terminals, additional bulk capacitance may be required in
addition to the ceramic bypass capacitors. If additional bulk capacitance is required, an electrolytic, tantalum, or
ceramic capacitor of 1 µF may be sufficient.
The TPS22918 operates regardless of power sequencing order. The order in which voltages are applied to VIN
and ON will not damage the device as long as the voltages do not exceed the absolute maximum operating
conditions. If voltage is applied to ON before VIN, the slew rate of VOUT will not be controlled.
11 Layout
11.1 Layout Guidelines
VIN and VOUT traces should be as short and wide as possible to accommodate for high current.
The VIN pin should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended
bypass capacitance is 1-µF ceramic with X5R or X7R dielectric. This capacitor should be placed as close to the
device pins as possible.
20
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TPS22918
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ZHCSEX3A –FEBRUARY 2016–REVISED MARCH 2016
11.2 Layout Example
1
2
3
6
5
4
VIN VOUT
GND QOD
ON
CT
ëL! to ꢀower Dround ꢀlane
图 32. Recommended Board Layout
11.3 Thermal Considerations
For best performance, all traces should be as short as possible. To be most effective, the input and output
capacitors should be placed close to the device to minimize the effects that parasitic trace inductances may have
on normal and short-circuit operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic
electrical effects along with minimizing the case to ambient thermal impedance.
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. To
calculate the maximum allowable dissipation, PD(max) for a given output current and ambient temperature, use 公
式 14:
TJ(MAX) - TA
PD(MAX)
=
qJA
where
•
•
•
•
PD(MAX) = maximum allowable power dissipation
TJ(MAX) = maximum allowable junction temperature (125°C for the TPS22918)
TA = ambient temperature of the device
θJA = junction to air thermal impedance. Refer to the Thermal Information table. This parameter is highly
dependent upon board layout.
(14)
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12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
关于 TPS22918 PSpice 瞬态模型，请参见 SLVMBI6。
12.2 文档支持
12.2.1 相关文档ꢀ
相关文档如下：
《TPS22918 5.5V、2A、导通电阻为 50mΩ 的负载开关评估模块》，SLVUAP0。
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
22
版权 © 2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS22918DBVR
TPS22918DBVT
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
6
6
3000 RoHS & Green
250 RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
13MW
13MW
NIPDAU | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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