TPS2350PWG4_技术文档

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SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003

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FEATURES

DESCRIPTION

D

Replaces OR-ing Diodes

The TPS2350 is a hot swap power manager

optimized for replacing OR-ing diodes in

redundant power −48-V systems. The TPS2350

operates with supply voltages from −12 V to

−80 V, and withstands spikes to −100 V.

Operating Supply Range of −12 V to −80 V

Withstands Transients to –100 V

Programmable Current Limit

Programmable Linear Inrush Slew Rate

Programmable UV/OV Thresholds

Programmable UV and OV Hysteresis

Fault Timer to Eliminate Nuisance Trips

Power Good and Fault Outputs

The TPS2350 uses two power FETs as low

voltage drop diodes to efficiently select between

two redundant power supplies. This minimizes

system power dissipation and also minimizes

voltage drop through the power management

chain.

14-Pin SOIC and TSSOP Package

The TPS2350 also uses a third power FET to

provide load current slew rate control and peak

current limiting that is programmed by one resistor

and one capacitor. The device also provides a

power good output to enable down-stream power

converters and a fault output to indicate load

problems.

APPLICATIONS

D

−48-V Distributed Power Systems

Central Office Switching

ONET

Base Stations

TYPICAL APPLICATION DIAGRAM

R

LOAD

1

C

LOAD

RTN

3

12

2

UV

PG

FLT

Q1

11

10

7

GAT

R

SENSE

Power Good

Fault

0.01 Ω

TPS2350

SENSE

SOURCE

GATA

9

4

OV

GATB

8

FLTTIM RAMP

−VINA −VINB

14 13

5

6

−VINB

−VINA

C

RAMP

FLT

UDG−03125

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Copyright  2003, Texas Instruments Incorporated

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ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ

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1

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SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature (unless otherwise noted)

(1)

PARAMETER

TPS2350

−0.3 to 100

−100 to 100

−0.3 to 15

−0.3 to 100

10

UNIT

V

(2)

Input voltage range, RTN

Input voltage range, −VINA to –VINB

(2)

Input voltage range, FLTTIM, RAMP, SENSE, OV, UV

(2)(3)

Output voltage range, FLT, PG

Continuous output current, FLT, PG

Continuous total power dissipation

Operating junction temperature range, T

mA

°C

TBD

−55 to 125

−65 to 150

260

J

Storage temperature range, T

stg

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”

is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

All voltages are with respect to the more negative of –VINA and −VINB (unless otherwise noted).

(2)

(3)

With 10 kΩ minimum series resistance. Range limited to –0.3V to 80V from low impedance source.

SOIC/TSSOP-14 PACKAGE

(TOP VIEW)

RTN

FLT

UV

1

2

3

4

5

6

7

14

13

12

11

10

9

−VINA

−VINB

PG

OV

GAT

FLTTIM

RAMP

SOURCE

SENSE

GATA

GATB

8

ELECTROSTATIC DISCHARGE

(ESD) PROTECTION

AVAILABLE OPTIONS

T

PACKAGE

(4)

PART NUMBER

TPS2350D

A

MIN

UNIT

SOIC−14

−40°C to 85°C

Human body model (HBM)

2

kV

(4)

TSSOP−14

TPS2350PW

(4)

Charged device model (CDM)

1.5

The D and PW packages are also available taped and reeled.

Add an R suffix to the device type (i.e. TPS2350DR).

RECOMMENDED OPERATING CONDITIONS

MIN

−80

−40

NOM

MAX

−12

85

UNIT

V

Input supply, −VINA, −VINB to RTN

Operating junction temperature range

−48

_C

DISSIPATION RATING TABLE

PACKAGE

T

< 25 _C

DERATING FACTOR

T

= 85 _C

A

POWER RATING

ABOVE T = 25 _C

POWER RATING

A

SOIC−14

750 mW

7.5 mW/C

300 mW

TSSOP−14

750 mW

300 mW

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SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003

ELECTRICAL CHARACTERISTICS

−VINA = −48 V, −VINB = 0 V, UV = 2.5 V, OV = 0.5 V, SENSE = 0 V, RAMP = 0 V, SOURCE = more negative of –VINA

and –VINB, all outputs unloaded, T = −40 _C to 85 _C (unless otherwise noted)†‡

A

Input Supply

PARAMETER

Supply current

TEST CONDITIONS

−VINA = −48 V, −VINB = 0 V

−VINA = −80 V, −VINB = 0 V

−VINB = −48 V, −VINA = 0 V

−VINB = −80 V, −VINA = 0 V

To GAT pull up

MIN

TYP

MAX

1500

2000

1500

2000

−8.0

500

UNIT

I

1000

CC1A

CC2A

CC1B

CC2B

Supply current

µA

Supply current

1000

Supply current

V

Internal UVLO threshold voltage

Internal UVLO hysteresis voltage

−11.8

50

−10

240

V

UVLO_I

V

mV

HYST

Overvoltage and Undervoltage Inputs (OV and UV)

PARAMETER

TEST CONDITIONS

MIN

1.391

1.387

1.384

−11

TYP

1.400

−10

MAX

1.409

1.413

1.419

−9

UNIT

To GAT pull up, 25 _C

To GAT pull up, 0 to 70 _C

To GAT pull up, −40 to 85 _C

UV = −45.5 V

V

UV threshold voltage, UV rising, to –VINA

V

THUV

I

UV hysteresis

HYSUV

µA

UV low−level input current

OV threshold voltage, OV rising, to −VINA

OV hysteresis

UV = −47 V

−1

1

ILUV

V

To GAT pull up

1.376

−11.1

−1

1.400

−10

1.426

−8.6

1

V

THOV

HYSOV

ILOV

I

OV = −45.5 V

µA

OV low−level input current

OV = −47 V

Linear Curent Amplifier (LCA)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

High level output, GAT−SOURCE

GAT sink current in fault

SENSE = SOURCE

11

14

17

V

OH

SENSE – SOURCE = 80 mV, GAT = −43

V, FLTTIME = 5 V

I

30

75

5

SINK_f

mA

SENSE – SOURCE = 80 mV, GAT =

−43 V, FLTTIME = 2 V

I

GAT sink current in linear mode

SENSE input current

10

1

SINK_l

0.0 V < SENSE – SOURCE < 0.2 V

RAMP – SOURCE = 6 V

−1

34

−7

µA

IN

Reference clamp voltage, SENSE −

SOURCE

V

42

50

9

REF_K

mV

V

IO

Input offset voltage, SENSE − SOURCE

RAMP – SOURCE = 0 V

Ramp Generator

PARAMETER

TEST CONDITIONS

RAMP − SOURCE = 0.25 V

RAMP − SOURCE = 1 V and 3 V

UV = SOURCE

MIN

−800

−11.3

TYP

−550

−10

MAX

−300

−8.5

5

UNIT

nA

I

RAMP source current, slow turn-on rate

RAMP source current, normal rate

Low-level output voltage

SRC1

µA

SRC2

V

OL

mV

A

V

Voltage gain, relative to SENSE

0 V < RAMP − SOURCE < 5 V

9.5

10

10.7

mV/V

†

‡

All voltages are with respect to RTN unless otherwise stated.

Currents are positive into and negative out of the specified terminal.

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SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003

ELECTRICAL CHARACTERISTICS

−VINA = −48 V, −VINB = 0 V, UV = 2.5 V, OV = 0.5 V, SENSE = 0 V, RAMP = 0 V, SOURCE = more negative of –VINA

and –VINB, all outputs unloaded, T = −40 _C to 85 _C (unless otherwise noted)†‡

A

Overload Comparator

PARAMETER

SENSE current overload threshold

Response time

TEST CONDITIONS

MIN

100

TYP

120

MAX

140

UNIT

mV

µs

V

TH_OL

t

SENSE – SOURCE = 200 mV

2

4

7

RSP

Fault Timer

PARAMETER

TEST CONDITIONS

UV = −48 V

MIN

TYP

MAX

5

UNIT

mV

V

OL

FLTTIM low−level output voltage, to −VINA

FLTTIM charging current, current limit mode

FLTTIM fault threshold voltage to SOURCE

Fault reset threshold to SOURCE

I

FLTTIM − SOURCE = 2 V

−54

−50

4.00

0.5

−41

4.25

µA

CHG

V

3.75

FLT

RST

DSG

V

I

FLTTIM Discharge current, retry mode

FLTTIM – SOURCE = 2 V

0.38

0.75

µA

SENSE − SOURCE = 80 mV,

FLTTIM − SOURCE = 2 V

D

Output duty cycle during retry cycles

1.0%

1

1.5%

I

FLTTIM discharge current, timer reset mode

FLTTIM − SOURCE = 2 V, SENSE = V

mA

RST

Logic Outputs (FLT, PG)

PARAMETER

TEST CONDITIONS

UV = −48 V, FLT – SOURCE = 80 V

UV = −45 V, PG – SOURCE = 80 V

MIN

−10

TYP

MAX

10

UNIT

I

FLT high-level output leakage current

PG high-level output leakage current

OHFLT

µA

10

OHPG

SENSE−SOURCE = 80 mV,

FLTTIM−SOURCE = 5 V,

I(FLT) = 1 mA

R

FLT ON resistance

PG ON resistance

50

80

DS(on)

Ω

UV = −48 V, I (PG) = 1 mA

O

Supply Selector

PARAMETER

TEST CONDITIONS

−VINB = −48 V, −VINA falling

−VINA = −48 V, −VINB falling

MIN

TYP

MAX

UNIT

V

Threshold voltage, −VINA falling

Threshold voltage, −VINB falling

−48.45 −48.40 −48.35

THA

V

THB

−VINA = 0 V, −VINB = −48 V,

GATA = −41 V

I

GATA sink current

GATA source current

GATB sink current

GATB source current

30

80

−50

80

mA

µA

SINK

−VINA = −48 V, −VINB = −0 V,

GATA = −41 V

I

−20

SOURCE

−VINA = −48 V, −VINB = −0 V,

GATB = −41 V

I

30

mA

µA

SINK

−VINA = 0 V, −VINB = −48 V,

GATB = −41 V

I

−50

−20

SOURCE

V

GATA low voltage to –VINA

GATA high voltage to –VINA

GATB low voltage to –VINB

GATB high voltage to −VINB

−VINA = 0 V, −VINB = −48 V

−VINA = −48 V, −VINB = 0 V

−VINA = 0 V, −VINB = −48 V

0.1

17

OLA

OLB

V

11

14

V

0.1

17

†

‡

All voltages are with respect to RTN unless otherwise stated.

Currents are positive into and negative out of the specified terminal.

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SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

2

FLT

O

Open-drain, active-low indication that the part is in fault.

Connection for user programming of the fault timeout period.

FLTTIM

5

I/O

Gate drive for external N-channel FET that ramps load current and disconnects in the event of a

fault.

GAT

11

O

GATA

GATB

OV

9

8

O

Gate drive for external N-channel FET that selects –VINA.

Gate drive for external N-channel FET that selects –VINB.

Over voltage sense input.

O

4

I

PG

12

6

O

Open-drain, active-high indication that the power FET is fully enhanced.

Programming input for setting the inrush current slew rate.

Supply return (ground).

RAMP

RTN

I/O

1

I

SENSE

SOURCE

UV

10

7

I

Positive current sense input.

I/O

Negative current sense input.

3

I

Under voltage sense input.

−VINA

−VINB

14

13

Negative supply input A.

Negative supply input B.

PIN DESCRIPTIONS

FLT: Open-drain, active-low indication that TPS2350 has shut down due to a faulted load. This happens if the

load current stays limited by the linear current amplifier for more than the fault time (time to charge the FLTTIM

capacitor). FLT is cleared when both supplies drop below the UV-comparator threshold or one supply exceeds

the OV-comparator threshold. The FLT output is pulled to the lower of –VINA and –VINB. The FLT output is able

to sink 10 mA when in fault, withstand 80 V without leakage when not faulted, and withstand transients as high

as 100 V when limited by a series resistor of at least 10 kΩ.

FLTTIM: Connection for user programming of the fault timeout period. An external capacitor connected from

FLTTIM to SOURCE establishes the timeout period to declare a fault condition. This timeout protects against

indefinite current sourcing into a faulted load, and also provides a filter against nuisance trips from momentary

current spikes or surges. TPS2350 define a fault condition as voltage at the SENSE pin at or greater than the

42-mV fault threshold. When a fault condition exists, the timer is active. The devices manage fault timing by

charging the external capacitor to the 4-V fault threshold, then subsequently discharging it at approximately 1%

the charge rate to establish the duty cycle for retrying the load. Whenever the fault latch is set (timer expired),

GAT and FLT are pulled low.

GAT: Gate drive for an external N-channel protection power MOSFET. When either input supply is above the

UV threshold and both are below the OV threshold, gate drive is enabled and the device begins charging the

external capacitor connected to RAMP. RAMP develops the reference voltage at the non-inverting input of the

internal LCA. The inverting input is connected to the current sense node, SENSE. The LCA acts to slew the pass

FET gate to force the SENSE voltage to track the reference. The reference is internally clamped to 42 mV, so

the maximum current that can be sourced to the load is determined by the sense resistor value as IMAX ≤

42 mV/R

. Once the load voltage has ramped up to the input dc potential and current demand drops off,

SENSE

the LCA drives GAT 14 V above SOURCE to fully enhance the pass FET, completing the low-impedance supply

return path for the load.

GATA: Gate drive for an external N-channel power MOSFET to select −VINA. When –VINA is more negative

than –VINB, GATA is pulled 14 V above –VINA, turning on the –VINA power FET. When –VINB is more negative

than –VINA, GATA is pulled down to –VINB, turning off the –VINA power FET.

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SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003

PIN DESCRIPTIONS (cont.)

GATB: Gate drive for an external N-channel power MOSFET to select −VINB. When –VINB is more negative

than –VINA, GATB is pulled 14 V above –VINB, turning on the –VINB power FET. When –VINA is more negative

than –VINB, GATB is pulled down to –VINA, turning off the –VINB power FET.

PG: Open-drain, active-high indication that load current is below the commanded current and the power FET

is fully enhanced. When commanded load current is more than the actual load current, the linear current

amplifier (LCA) will raise the power MOSFET gate voltage to fully enhance the power MOSFET. At this time,

the PG output will go high. This output can be used to enable a down-stream dc-to-dc converter. The PG output

is pulled to the lower of –VINA and –VINB. The PG output is able to sink 10 mA when in fault, withstand 80 V

without leakage when power is not good, and withstand transients as high as 100 V when limited by a series

resistor of at least 10 kΩ.

OV: Over voltage comparator input. This input is typically connected to a voltage divider between RTN and

SOURCE to sense the magnitude of the more negative input supply. If OV is less than 1.4 V above SOURCE,

UV is more than 1.4 V above SOURCE, and there is no fault, the linear current amp will be enabled. In the event

of a fault, pulling OV high or UV low will reset the fault latch and allow restarting. OV can also be used as an

active-low logic enable input. The over-voltage comparator hysteresis is programmed by the equivalent

resistance seen looking into the divider at the OV input.

RAMP: Programming input for setting inrush current and current slew rate. An external capacitor connected

between RAMP and SOURCE establishes turn-on current slew rate. During turn-on, TPS2350 charges this

capacitor to establish the reference input to the LCA at 1% of the voltage from RAMP to SOURCE. The

closed-loop control of the LCA and the pass FET maintains the current-sense voltage from SENSE to SOURCE

at the reference potential, so the load current slew rate is directly set by the voltage ramp rate at the RAMP pin.

When fully charged, RAMP can exceed SOURCE by 6 V, but the reference is internally clamped to 42 mV,

limiting load current to 42 mV/R

capacitor is discharged and held low to initialize for the next turn on.

. When the output is disabled via OV, UV, or due to a load fault, the RAMP

SENSE

RTN: Positive supply input. For negative voltage systems, this pin connects directly to the return node of the

input power bus.

SENSE: Current sense input. An external low-value resistor connected between SENSE and SOURCE is used

to monitor current magnitude. There are two internal device thresholds associated with the voltage at the

SENSE pin. During ramp-up of the load capacitance or during other periods of excessive demand, the linear

current amp (LCA) will regulate this voltage to 42 mV. Whenever the LCA is in current regulation mode, the

capacitor at FLTTIM is charging and the timer is running. If the LCA is saturated, GAT is pulled 14 V above

SOURCE. At this time, a fast fault such as a short circuit can cause the SENSE voltage to rapidly exceed 120 mV

(the overload threshold). In this case, the GAT pin is pulled low rapidly, bypassing the fault timer.

SOURCE: Connection to the sources of the input supply negative rail selector FETs and the negative terminal

of the current sense resistor. The supply select comparator will turn on the appropriate power FET to connect

SOURCE to the more negative of –VINA and –VINB.

UV: Under voltage comparator input. This input is typically connected to a voltage divider between RTN and

SOURCE to sense the magnitude of the more negative input supply. If UV is more than 1.4 V above SOURCE,

OV is less than 1.4 V above SOURCE, and there is no fault, the linear current amp will be enabled. In the event

of a fault, pulling UV low or OV high will reset the fault latch and allow restarting. UV can also be used as an

active high logic enable input. The under-voltage comparator hysteresis is programmed by the equivalent

resistance seen looking into the divider at the UV input.

−VINA: Negative supply input A. This pin connects directly to the first input supply negative rail.

−VINB: Negative supply input B. This pin connects directly to the second input supply negative rail.

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SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

SUPPLY SELECTOR THRESHOLD VOLTAGE

vs

AMBIENT TEMPERATURE, −VINA FALLING

AMBIENT TEMPERATURE, −VINB FALLING

−0.350

−0.375

−0.400

−0.425

−0.450

−0.350

−0.375

−0.400

−0.425

−0.450

V

= 0 V

V

= 0 V

(RTN)

Relative to −VINA

(RTN)

Relative to −VINB

V

= −48 V

(−VINB)

V

= −48 V

(−VINA)

V

= −20 V

(−VINB)

V

= −20 V

(−VINA)

V

= −80 V

(−VINB)

V

= −80 V

(−VINA)

−40

−15

10

35

60

85

−40

−15

T

10

35

60

85

T

A

− Ambient Temperature − °C

A

Figure 1

Figure 2

GATA HIGH-LEVEL OUTPUT VOLTAGE

GATB HIGH-LEVEL OUTPUT VOLTAGE

vs

AMBIENT TEMPERATURE

16

12

8

16

12

8

V

= −20 V

(−VINA)

V

= −48 V

V

= −20 V

(−VINB)

V

= −48 V

(−VINB)

(−VINA)

V

= −12 V

V

= −12 V

(−VINB)

(−VINA)

4

V

= V

(−VINB)

= 0 V

10

V

= V = 0 V

(−VINA)

(RTN)

Relative to −VINA

(RTN)

Relative to −VINB

0

−40

−15

T

35

60

85

−15

10

35

60

85

− Ambient Temperature − °C

T

A

− Ambient Temperature − °C

A

.

Figure 3

Figure 4

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SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

GATx SINK CURRENT

vs

AMBIENT TEMPERATURE

SUPPLY CURRENT

vs

AMBIENT TEMPERATURE

100

80

1500

1200

V

= V = 0 V

(−VINB)

(RTN)

V

= −80 V

(−VINA)

GATA Output

V

=V

(−VINB)

OUT(GATA)

=0V

= −48 V

= −41 V

(RTN) (−VINA)

V

60

40

20

V

900

600

300

0

GATB Output

=V

V

=0V

(RTN) (−VINB)

V

= −48 V

(−VINA)

OUT(GATB)

= −41 V

V

= −48 V

(−VINA)

V

= −20 V

(−VINA)

V

= −12 V

(−VINA)

0

−40

−15

10

35

60

85

−15

10

35

60

85

T

A

− Ambient Temperature − °C

T

A

− Ambient Temperature − °C

Figure 5

Figure 6

UNDERVOLTAGE PULL-UP CURRENT

VOLTAGE COMPARATOR THRESHOLDS

vs

AMBIENT TEMPERATURE

1.42

1.41

1.40

1.39

1.38

−9.0

−9.4

V

= V = 0 V

(RTN) (−VINB)

V

= V

(−VINA)

−V

= 0 V

≤ −20 V

(RTN)

(−VINB)

Relative to −VINA

−48 V ≤ V

V

=2.5V

IN(UV) IN(SOURCE)

OV Comparator

= −80 V

V

(−VINA)

−9.8

−10.2

−−10.6

−11.0

UV Comparator

−48 V≤ V ≤ −20 V

(−VINA)

−40

−15

T

10

35

60

85

−40

−15

T

10

35

60

85

− Ambient Temperature − °C

A

Figure 7

Figure 8

8

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ꢀꢁ ꢂ ꢃꢄ ꢅꢆ

SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

RAMP OUTPUT CURRENT

GAT HIGH-LEVEL OUTPUT VOLTAGE

vs

AMBIENT TEMPERATURE, REDUCED RATE MODE

AMBIENT TEMPERATURE

−460

16

12

8

V

= V

= 0 V

(RTN)

(−VINB)

−V

=0.25V

OUT(RAMP) IN(SOURCE)

−480

−500

V

= −48 V

(−VINA)

V

= −20 V

(−VINA)

V

= −12 V

(−VINA)

−520

−540

V

= −12 V

(−VINA)

V

= −48 V

(−VINA)

4

V

= −36 V

(−VINA)

−560

V

= V = 0 V

(−VINB)

(RTN)

−V

=0V

35

IN(SENSE) IN(SOURCE)

I

= −10 µA

OUT(GAT)

−580

0

−40

−15

10

35

60

85

−15

10

60

85

T

A

− Ambient Temperature − °C

T

A

− Ambient Temperature − °C

Figure 9

Figure 10

TIMER CHARGING CURRENT

vs

AMBIENT TEMPERATURE

RAMP OUTPUT CURRENT

vs

AMBIENT TEMPERATURE, NORMAL RATE MODE

−8.5

−46

−48

V

= V

(−VINB)

= 0 V

Average for V

−V

=1V, 3 V

(RTN)

OUT(RAMP) IN(SOURCE)

− V

= 2 V

V

= V

= 0 V

OUT(FLTTIM)

IN(SOURCE)

(RTN)

−80 V ≤ V

(−VINB)

−80 V ≤ V

≤ −20 V

≤ −12 V

(−VINA)

−9.1

−9.7

−52

−54

−10.3

−10.9

−11.5

0

−40

−15

10

35

60

85

−40

−15

10

35

60

85

T

A

− Ambient Temperature − °C

T

A

− Ambient Temperature − °C

Figure 11

Figure 12

9

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SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

TIMER DISCHARGE CURRENT

FAULT LATCH THRESHOLD VOLTAGE

vs

AMBIENT TEMPERATURE

0.50

0.45

4.25

4.15

V

= V

(−VINA)

= 0 V

≤ −20 V

V

= V

= −48 V

= 0 V

(RTN)

(−VINB)

(RTN) (−VINB)

−80 V ≤ V

V

(−VINA)

V

−V

=2V

Relative to SOURCE

OUT(FLTTIM) IN(SOURCE)

0.40

0.35

4.05

3.95

0.30

0.25

3.85

3.75

0.20

−40

−15

T

10

35

60

85

−40

−15

10

35

60

85

− Ambient Temperature − °C

T

A

− Ambient Temperature − °C

A

Figure 13

Figure 14

10

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SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003

FUNCTIONAL BLOCK DIAGRAM

RTN

1

Input UV

Comparator

3

4

UV

OV

+

1.4 V

Input OV

Comparator

Disable

2

FLT

+

1.4 V

Fault Latch

S

Q

120 mV

4 µs

Filter

Retry

Timer

Fault

Timer

+

R

Q

Overload

Comparator

5

FLTTIM

SENSE

+

11

GAT

10

Linear Current

Amp

99R

6

RAMP

Power Good

Detection

Disable

12

PG

42 mV

R

+

7

SOURCE

Supply Select

Comparator

+

9

8

GATA

GATB

400 mV

Hysteresis

14

−VINA

13

−VINB

11

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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ

SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003

APPLICATION INFORMATION

SUPPLY SECTION

The supply selection comparator selects between –VINA and –VINB based on which supply has a larger

magnitude. To prevent chattering between two nearly identical supplies, the supply selection comparator has

400 mV of hysteresis. This prevents supply noise or ripple from tripping the comparator and should be adequate

for most systems. Hysteresis is set to 400 mV to give the highest noise margin without allowing conduction in

the body diodes of the supply selection FETs.

For systems with many cards, high current cards, or long cables between the power and the load, the voltage

loss in the cable can be significant. If the supplies are close to the same magnitude, then the voltage loss in the

cable could cause enough drop to exceed the supply selection comparator hysteresis. In this case, the supply

selection comparator hysteresis must be increased.

TPS2350 allows you to increase the hysteresis of the supply selection comparator with external resistors,

limited to the threshold of the external FETs. Figure 15 shows shows a system with higher hysteresis, set by

R4, R5, R6 and R7. The resistors act as a simple multiplier to increase the voltage differential required to switch

the comparator. For example, for R4 = R5 = 40 kΩ, and R6 = R7 = 20 kΩ, the hysteresis is approximately 1.2 V.

Because of the large hysteresis, the supply selection power FETs are replaced with dual power FETs, configured

so that the body diodes can never conduct. The GATA and GATB outputs are able to switch dual FETs, so no

additional drive or logic circuits are required.

RTN

C

LOAD

R

R1

1

LOAD

RTN

Q1

POWER GOOD

FAULT

12

2

11

10

PG

FLT

UV

GAT

SENSE

TPS2350

R

SENSE

3

7

9

8

SOURCE

GATA

R2

R3

Q2

Q4

4

OV

Q3

GATB

FLTTIM RAMP −VINA −VINB

5

6

14

13

Q5

R6

R7

R4

R5

C

RAMP

FLT

UDG−03121

−VINB

−VINA

Figure 15. Typical Application to Develop Higher Supply Comparator Hysteresis

12

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SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003

APPLICATION INFORMATION

Setting the Sense Resistor Value

Due to the current-limiting action of the internal LCA, the maximum allowable load current for an implementation

is easily programmed by selecting the appropriate sense resistor value. The LCA acts to limit the sense voltage

V

to its internal reference. Once the voltage at the RAMP pin exceeds approximately 4 V, this limit is the

SENSE

clamp voltage, V

. Therefore, a maximum sense resistor value can be determined from equation (1).

REF_K

34 mV

R

v

SENSE

I

IMAX

(1)

where

D

R

is the resistor value

SENSE

I

is the desired current limit

IMAX

When setting the sense resistor value, it is important to consider two factors, the minimum current that may be

imposed by the TPS2350, and the maximum load under normal operation of the module. For the first factor,

the specification minimum clamp value is used, as seen in equation (1). This method accounts for the tolerance

in the sourced current limit below the typical level expected (42 mV/R

). (The clamp measurement includes

SENSE

LCA input offset voltage; therefore, this offset does not have to be factored into the current limit again.) Second,

if the load current varies over a range of values under normal operating conditions, then the maximum load level

must be allowed for by the value of R

. One example of this is when the load is a switching converter, or

SENSE

brick, which draws higher input current, for a given power output, when the distribution bus is at the low end of

its voltage range, with decreasing draw at higher supply voltages. To avoid current limit operation under normal

loading, some margin should be designed in between this maximum anticipated load and the minimum current

limit level, or I

> I

, for equation (1).

IMAX

LOAD(max)

For example, using a 10-mΩ sense resistor for a nominal 2-A load application provides a minimum of 1.4 A of

overhead for load variance/margin. Typical bulk capacitor charging current during turn-on is 4.2 A

(42 mV/10 mΩ).

Setting the Inrush Slew Rate

The TPS2350 device enables user-programming of the maximum current slew rate during load start-up events.

A capacitor tied to the RAMP pin (C

sense resistor value has been established, a value for C

equation (2).

in the typical application diagram) controls the di/dt rate. Once the

RAMP

, in microfarads, can be determined from

RAMP

11.3

C

+

RAMP

di

ǒ Ǔ

100 R

SENSE

dt

(max)

(2)

where

D

R

is the sense resistor value in Ω

SENSE

(di/dt)

is the desired maximum slew rate in A/s

(max)

For example, if the desired slew rate for the typical application shown is 1500 mA/ms, the calculated value for

C

is about 7500 pF. Selecting the next larger standard value of 8200 pF provides some margin for capacitor

RAMP

and sense resistor tolerances.

The TPS2350 initiates ramp capacitor charging, and consequently load current slewing, at a reduced rate. This

reduced rate applies until the voltage on the RAMP pin is about 0.5 V. The maximum di/dt rate, as set by equation

(2), is effective once the device switches to a 10-µA charging source.

13

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SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003

APPLICATION INFORMATION

Setting the Fault Timing Capacitor

The fault timeout period is established by the value of the capacitor connected to the FLTTIM pin, C . The

FLT

timeout period permits riding out spurious current glitches and surges that may occur during operation of the

system, and prevents indefinite sourcing into faulted loads. However, to ensure smooth voltage ramping under

all conditions of load capacitance and input supply potential, the minimum timeout should be set to

accommodate these system variables. To do this, a rough estimate of the maximum voltage ramp time for a

completely discharged plug-in card provides a good basis for setting the minimum timer delay. This section

presents a quick procedure for calculating the timing capacitance requirement. However, for proper operation

of the TPS2350, there is an absolute minimum value of 0.01-µF for C . This minimum requirement overrides

FLT

any smaller results of equations (7) and (8) below.

Due to the three-phase nature of the load current at turn-on, the load voltage ramp has potentially three distinct

phases. This profile depends on the relative values of load capacitance, input DC potential, maximum current

limit and other factors. The first two phases are characterized by the two different slopes of the current ramp;

the third phase, if required to complete load charging, is the constant-current charging at IMAX. Considering

the two current ramp phases to be one period at an average di/dt simplifies calculation of the required timing

capacitor.

For the TPS2350, the typical duration of the soft-start period, t , is given by equation (3)

SS

t

+ 1260 C

RAMP

SS

(3)

where

D

t

is the soft-start period in ms

SS

C

is given in µF

RAMP

During this current ramp period, the load voltage magnitude which is attained is estimated by equation (4).

ǒ_tǓ²

i

AVG

V

+

LSS

SS

2 C

C

100 R

RAMP

SENSE

LOAD

(4)

where

D

V

is the load voltage reached during soft-start

is 3.18 µA for the TPS2350

LSS

i

AVG

C

is the load capacitance in Farads

LOAD

t

is the soft-start period in s

SS

The quantity i

in equation (4) is a weighted average of the two charge currents applied to C

during

RAMP

AVG

turn-on, considering the typical output values.

14

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SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003

APPLICATION INFORMATION

If the result of equation (4) is larger than the maximum input supply value, then the load can be expected to

charge completely during the inrush slewing portion of the insertion event. However, if this voltage is less than

the maximum supply input, V

remaining amount of time required at IMAX is determined from equation (5).

, the HSPM transitions to the constant-current charging of the load. The

IN(MAX)

ǒ_V

_LSSǓ

C

* V

IN(MAX)

LOAD

t

+

CC

V

REF_K(MIN)

R

SENSE

(5)

where

D

t

is the constant-current voltage ramp time, in seconds

CC

V

is the minimum clamp voltage, 34 mV

REF_K(MIN)

With this information, the minimum recommended value timing capacitor C

can be determined. The delay

FLT

time needed will be either a time t

load. The quantity t

or the sum of t

and t , according to the estimated time to charge the

SS2

SS2 CC

is the duration of the normal rate current ramp period, and is given by equation (6).

SS2

t

+ 0.35 C

RAMP

SS2

(6)

where

D

C

is given in µF

RAMP

Since fault timing is generated by the constant-current charging of C , the capacitor value is determined from

FLT

either equation (7) or (8), as appropriate.

54 t

SS2

C

+

FLT(MIN)

3.75

(7)

(8)

₅₄ǒ_t

_CCǓ

) t

SS2

3.75

where

D

C

is the recommended capacitor value, in µ-Farads

FLT(MIN)

t

is the result of equation (6), in seconds

SS2

t

is the result of equation (5), in seconds

CC

Continuing this calculation example, using a 220-µF input capacitor (C

), equations (3) and (4) estimate the

LOAD

load voltage ramping to approximately −45 V during the soft-start period. If the module should operate down

to −72-V input supply, approximately another 1.4 ms of constant-current charging may be required. Therefore,

equations (6) and (8) are used to determine C

, and the result is approximately 0.039-µF.

FLT(MIN)

15

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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ

SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003

APPLICATION INFORMATION

Setting the Undervoltage and Overvoltage Thresholds

The UV and OV pins can be used to set the undervoltage (V ) and overvoltage (V ) thresholds of the hot

UV

OV

swap circuit. When the input supply is below V

or above V , the GAT pin is held low, disconnecting power

UV

from the load, and the PG output is deasserted. When input voltage is within the UV/OV window, the GAT pin

drive is enabled, assuming all other input conditions are valid for turn-on.

Threshold hysteresis is provided via two internal sources which are switched to either pin whenever the

corresponding input level exceeds the internal 1.4-V reference. The additional bias shifts the pin voltage in

proportion to the external resistance connected to it. This small voltage shift at the device pin is gained up by

the external divider to input supply levels.

(a)

(b)

GND

R1

200 kΩ

1 %

1

R1

R2

R8

RTN

3

4

UV

3

4

UV

R2

4.99 kΩ

1 %

TPS2350*

OV

TPS2350*

OV

R3

3.92 kΩ

1 %

SOURCE

7

SOURCE

7

R9

−48V

R1 ) R2 ) R3

R2 ) R3

R1 ) R2

V_{UV_L}

+

V_THUV

V_{UV_L}

+

V_THUV

R2

R1 ) R2 ) R3

R8 ) R9

V_{OV_L}

V_THOV* I_HYSUV R1

V_{OV_L}

V_THOV

UDG−03121

R3

R9

*Additional details omitted for clarity

Figure 16. Programming the Undervoltage and Overvoltage Thresholds

The UV and OV thresholds can be individually programmed with a three-resistor divider connected to the

TPS2350 as shown in the typical application diagram, and again in Figure 16a. When the desired trip voltages

and undervoltage hysteresis have been established for the protected board, the resistor values needed can be

determined from the following equations. Generally, the process is simplest by first selecting the top leg of the

divider (R1 in the diagram) needed to obtain the threshold hysteresis. This value is calculated from equation (9).

V

HYS_UV

R1 +

10 mA

(9)

where

D

V

is the undervoltage hysteresis value

HYS_UV

16

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ꢀꢁ ꢂ ꢃꢄ ꢅꢆ

SLUS574A − JULY 2003 − REVISED SEPTEMBER 2003

APPLICATION INFORMATION

For example, assume the typical application design targets have been set to undervoltage turn-on at 33 V (input

supply rising), turn-off at 31 V (input voltage falling), and overvoltage shutdown at 72 V. Then equation (9) yields

R1 = 200 kΩ for the 2-V hysteresis. Once the value of R1 is selected, it is used to calculate resistors R2 and

R3.

ȱ

Ȳ

ȳ

V

UV_L

1.4 R1

^{R2 +}ǒ_{V * 1.4}Ǔ^{1 *}ǒ_V

_R1Ǔ

ȧ

*5

) 10

OV_L

ȴ

UV_L

(10)

(11)

1.4 R1 V

UV_L

^{R3 +}ǒ_{V * 1.4}Ǔǒ_V

_R1Ǔ

*5

) 10

OV_L

UV_L

where

D

V

is the UVLO threshold when the input supply is low; i.e., less than V , and

UV

UV_L

is the OVLO threshold when the input supply is low; i.e., less than V

OV

OV_L

Again referring to the Figure 17a schematic, equations (10) and (11) produce R2 = 4.909 kΩ (4.99 kΩ selected)

and R3 = 3.951 kΩ (3.92 kΩ selected), as shown. For the selected values, the expected nominal supply

thresholds are V

= 32.8 V, V

= 30.8 V, and V

= 72.6 V. The hysteresis of the overvoltage threshold,

UV_L

UV_H

OV_L

as seen at the supply inputs, is given by the quantity (10 µA) × (R1 + R2). For the majority of applications, this

value is very nearly the same as the UV hysteresis, since typically R1 >> R2.

If more independent control is needed for the OVLO hysteresis, there are several options. One option is to use

separate dividers for both the UV and OV pins, as shown in Figure 16b. In this case, once R1 and R8 have been

selected for the required hysteresis per equation (9), and values for the bottom resistors in the divider (R2 and

R9 in Figure 16b) can be calculated using equation (12).

V

REF

R

(TOP)

⁺ǒ_V

_REFǓ

XVLO

* V

XV_L

(12)

where

D

R

V

is R2 or R9

XVLO

is R1 or R8 as appropriate for the threshold being set

(TOP)

is the under (V

) or overvoltage (V

) threshold at the supply input, and

XV_L

UV_L

OV_L

V

is either V

or V

from the specification table, as required for the resistor being calculated.

REF

THUV

THOV

17

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

19-Jul-2005

PACKAGING INFORMATION

Orderable Device

TPS2350D

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

14

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS2350DR

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS2350PW

TPS2350PWR

TSSOP

PW

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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dsp.ti.com

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Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	TPS2350PWG4
厂家：	TEXAS INSTRUMENTS
描述：	具有 ORing 的 -12V 至 -80V 热插拔控制器 \| PW \| 14 \| -40 to 85 控制器光电二极管电源管理电路电源电路
文件：	总21页 (文件大小：366K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS2350PWG4 [TI]

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